Netlist by FlatLVS :
n 0 /4
n 1 /3
n 2 /2
n 3 /1
; pfet Instance /+1 = auLvs device Q0
d pfet D G S B (p D S)
i 0 pfet 0 1 3 3 " m 1.0 l 240e-9 w 2.58e-6 "
; nfet Instance /+0 = auLvs device Q1
d nfet D G S B (p D S)
i 1 nfet 0 1 2 2 " m 1.0 l 240e-9 w 1.58e-6 "

Netlist by MacroLVS:
n 0 /4
n 1 /5
n 2 /2
n 3 /3
n 4 /1
; v25inv_1 Instance /I2 = auLvs device X0
d v25inv_1 vdd vss op ip
i 0 v25inv_1 2 3 1 0 " lvsName \"v25inv_1\" "

 
1. In order to run MacroLVS, you must first create a cellview called macrolvs for every cell you inserted into your design as macros (except for the digital cells from Cadence's libraries). There are two ways to create this cellview, which are described below. 

Method A:

1. Create a symbol cellview from the schematic of your cell. 
2. Open Library Manager from the CIW window, select the symbol you created and select Edit->Copy... on the Library Manager window. 
3. In the To section of the window that pops up, fill in the same library and cell names as the symbol cellview and type in "macrolvs"under the View field. Click OK and the cellview is created. 
Method B:
1. Use the same procedure of creating a symbol cellview but fill in "macrolvs" under the To View Name field after you select Design->Create Cellview->From Cellview... in the schematic window. 

 
2. Next you should edit the CDF information for the cells you created with a macrolvs cellview. The steps are described below. 
 
1. On the CDF window, select Tools->CDF->Edit... . 
2. On the window that pops up, choose Base instead of Effective under CDF Type. Type in or click on Browse to select the library and cell names you want to edit. Under the Simulation Information section, click Edit . 
3. On the second window that pops up, choose auLvs under Choose Simulator and type in "ansLvsCompPrim" under netlistProcedure and the name of your cell under componentName. Click Apply on the two windows to apply the changes. 
4. Repeat this procedure for every macro cell you created.

 
3. (Tips kindly given by Amir)
   If you want the netlister to descend into the next hierarchial level of a particular cell with macro cellview, you can select the cell in your layout, press 'q' and select Property on the window that pops up. You can then select Add at the bottom of the window. On the next window that pops up, type in ivCellType under Name and graphic under Value. Press OK.
   Note: if you later want to do macro extraction for that cell, simply change graphic to any other words under Value.

 
4. To run MacroLVS, you should do macro extraction for your layout (which will be described in later section). In macro extraction, only the blocks of cells you inserted into your layout and the cells' pin layers are extracted, and all the internal connections and nets of the cells are ignored. Thus when drawing layouts consisted of macro cells, you should make connections right at the pin layers of the macro cells. All the connections made somewhere away from the pins of the macro cells are not recognizable by macro extraction and will cause errors when you run MacroLVS. This is applicable also to digital cell layouts inserted from Cadence's libraries. If you are not sure of their pins' locations, you can first run macro extraction to your layout and you will then see clearly the pins' locations from the extraction (after you press Ctrl+F in the extraction).

 
5. In order to run MacroLVS correctly for the cells with no macro cellview, you should do either one of the two described below for this kind of cells.
1. If the cell contains no pin, before you can do macro extraction, you should insert the cell into a temporary layout and do a flat extraction for it.  If you go directly to the macro extraction, Cadence will output an error saying that your cell cannot be extracted because it has no pins.
2. If the cell contains pins, you can do the same steps as described in Step 3 above to EVERY instance of the cell inserted to your layout.
3. If the cell contains pins, another choice is to do step 4 to the layout with the cell inserted.  Otherwise Cadence will not recognize the connections correctly.

 

 
1. Download the file flatlvs from here if you have run MacroLVS before. Save it in your working directory and rename it as .simrc. If you have never run MacroLVS, you do not need to download this file. 

NOTE: You may find this step similar but actually different from what the online lvs documentation says. Due to different settings for Cadence in different schools (I guess), it happens that only the step described here works for us.
 
2. In your layout window, select Verify->Extract... . Click on flat under Extract Method and OK to create an extracted view for your layout. Also, save and extract your schematic.

 
3. Open up the LVS window by selecting Verify-> LVS... in your layout or extracted window. Fill in the correct info for the schematic and extracted sections. If you have used m-factor in your schematic for CMOSP25 or CMOSP35 technologies, you should refer to News on M-Factor for additional instructions needed. Click on Run and if you have the .simrc file in your home directory, you should see the "File of flatlvs is now being executed." message in your CIW window.

 

 
1. Download the file macrolvs from here . Save it in your working directory and rename it as .simrc. 

NOTE: You may find this step similar but actually different from what the online lvs documentation says. Due to different settings for Cadence in different schools (I guess), it happens that only the step described here works for us.
 
2. In your layout window, select Verify->Extract... . Click on macro cell under Extract Method and OK to create an extracted view for your layout. Also, save and extract your schematic.

 
3. Open up the LVS window by selecting Verify-> LVS... in your layout or extracted window. Fill in the correct info for the schematic and extracted sections. Click on Run and if you have the .simrc file in your home directory, you should see the  "File of macrolvs is now being executed." message In your CIW window.