1. Download the source code of the pcell you want to install:
   1. CMOSP18 technology:
      For nfet-differential pair layout, download diffpairp18_nfet.il
      For pfet-differential pair layout, download diffpairp18_pfet.il
      For nfet layout, download nfetp18.il
      For pfet layout, download pfetp18.il
      
   2. CMOSP25 technology:
      For nfet-differential pair layout, download diffpairp25_nfet.il
      For pfet-differential pair layout, download diffpairp25_pfet.il
      For nfet layout, download nfetp25.il
      For pfet layout, download pfetp25.il
      
   Save it anywhere in your directory.
   
   
2. Create a library called "pcell2_p18" if you are using CMOSP18 technology or "pcell2_p25" if you are using CMOSp25 technology.
   
   
3. Under the CIW window (there is a line of space at the bottom of the window where you can type in your own command), enter the command-- load("< directory path of where you saved the source code>/< filename>"). For example, if I downloaded the source code nfetp25.il under the directory /johns/b/b0/wongann, the command would be load("/johns/b/b0/wongann/nfetp25.il").
   NOTE: It is likely that Cadence will output an error message about illegal declaration of arrays in the source code. In that case you just need to re-enter the command and this time the source code should be executed successfully.
   
   
4. Now the pcell is created and available for use under the library "pcell2_p18" or "pcell2_p25". Unless you modify the source code to create a new pcell, you don't need to execute the source code again next time when you open Cadence.
   
   
5. To add the pcell to your design, select Create->Instance->pcell2_p18/pcell2_p25->pcell_name in your layout window. In the window that pops up, there will be a list of parameters where you can specify you own values for the pcell.
   
   
6. To edit the pcell parameters after you place the pcell on your design, select the pcell, press 'q' and select parameter under the window that pops up. Edit the parameter values and then press okay to modify the pcell.
   
   

This differential pair cell consists of 10 parameters in total. Parameters' default values and descriptions are given below. Try to play around with different parameter values to get a better understanding of their uses.
NOTE: In this pcell, the gates of transistors are connected by metal. The pcell is designed such that you can change the metal layer to poly layer and it still satisfies the DRC rules. However, there is no parameter for that and you need to flatten the pcell before you can modify the layer type.

Parameter Names	Default Values	Descriptions
width	2.0um	Width of each basic transistor. Minimum value is in CMOSP18 and in CMOSP25. Value smaller than this will result in a transistor layout with minimum width.
length	0.5um	Length of each basic transistor. Minimum value is 0.18um in CMOSP18 and 0.25um in CMOSP25. Value smaller than this will result in a transistor layout with minimum length.
finger	2	Finger number of each of the two transistors that form the differential pair. Maximum value is 150. Value specified larger than this will only result in a layout with 150 fingers.
D1D2_connect?	yes	When the value is yes, drains of each transistor are connected by metal.
metal_D1	metal2	Metal type used to connect drains of first transistor. Values can be "metal1", "metal2", "metal3" or "metal4" in both technologies. In CMOSP18 technology, "metal5" is also accepted.
Metal_D2	metal2	Metal type used to connect drains of second transistor. Values can be "metal1", "metal2", "metal3" or "metal4" in both technologies. In CMOSP18 technology, "metal5" is also accepted.
S1S2_connect?	yes	When the value is yes, sources of the transistors are connected together by metal.
Metal_S1S2	metal2	Metal type used to connect sources of the two transistors. Values can be "metal1", "metal2", "metal3" or "metal4" in both technologies. In CMOSP18 technology, "metal5" is also accepted.
via_wanted?	yes	When the value is yes, vias that connect metal1 through metal 4 (or metal5 in CMOSP18)are placed in appropriate locations of transistors' drains and sources.
dummy_wanted?	yes	When the value is yes, dummy poly layers are placed on two sides of the differential pair.

This nfet or pfet cell consists of 8 parameters in total. Parameters' default values and descriptions are given below. Try to play around with different parameter values to get a better understanding of their uses.

Parameter Names	Default Values	Descriptions
width	2.0um	Width of each basic transistor. Minimum value is 0.45um in CMOSP18 and is in CMOSP25. Value smaller than this will result in a transistor layout with minimum width.
length	0.5um	Length of each basic transistor. Minimum value is 0.18um in CMOSP18 and is in CMOSP25. Value smaller than this will result in a transistor layout with minimum length.
Finger	2	Finger number of the transistor. Maximum value is 300. Value specified larger than this will only result in a layout with 300 fingers.
D_connect?	yes	When the value is yes, drains of the transistor are connected by metal.
Metal_D	metal2	Metal type used to connect drains of the transistor. Values can be "metal1", "metal2", "metal3" or "metal4" in both technologies. In CMOSP18 technology, "metal5" is also accepted.
S_connect?	yes	When the value is yes, sources of the transistor are connected together by metal.
Metal_S	metal2	Metal type used to connect sources of the transistor. Values can be "metal1", "metal2", "metal3" or "metal4" in both technologies. In CMOSP18 technology, "metal5" is also accepted.
Via_wanted?	yes	When the value is yes, vias that connect metal1 through metal 4 (or metal5 in CMOSP18)are placed in appropriate locations of transistor's drains and sources.

.

Flatten Your Pcell to Make Specific Changes