I'm a Ph.D. in computer engineering, graduated from the University of Toronto with Prof. Andreas Moshovos as my advisor.

I'm currently working at Jump Trading, enjoying a fast paced environment as a hardware engineer. In the past, I've worked at Altera Corp. both as RTL designer and verification engineer.

In 2005 I finished my undergraduate studies at Sharif University of Technology in Tehran, Iran. Then I moved to Canada and in 2007 finished my M.A.Sc. at the University of Victoria. From 2007 to 2013 I studied for my Ph.D. in soft processor architectures at the University of Toronto.


My current research interests:
  • Computer Architecture
  • Soft Processors
  • Low-Power Designs
  • Again Computer Architecture!


Publications:

High Performance Soft Processors:

  • An Architectural Approach to Characterizing and Eliminating Sources of Inefficiency in a Soft Processor Design
    In the IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM).
    Kaveh Aasaraai, Andreas Moshovos

  • What limits the operating frequency of a soft processor design
    In the International Conference on ReConFigurab le Computing and FPGAs (Reconfig'14), December 2014.
    Kaveh Aasaraai, Andreas Moshovos

  • Low-Cost, High-Performance Branch Predictors for Soft Processors
    In the International Conference on ReConFigurable Computing and FPGAs (Reconfig'13), December 2013.
    Di Wu, Kaveh Aasaraai, Andreas Moshovos

  • SPREX: A Soft Processor with Runahead Execution
    In the International Conference on ReConFigurable Computing and FPGAs (Reconfig'12), December 2012.
    Kaveh Aasaraai, Andreas Moshovos

  • NCOR: An FPGA-Friendly Non-Blocking Data Cache for Soft Processors With Runahead Execution (invited)
    In the Special Issue of the International Journal of Reconfigurable Computing (IJRC), November 2011.
    Kaveh Aasaraai, Andreas Moshovos

  • An Efficient Non-Blocking Data Cache for Soft Processors (pdf)
    In the International Conference on ReConFigurable Computing and FPGAs (Reconfig'10), December 2010.
    Invited for publication in the Special Issue of IJRC.
    Kaveh Aasaraai, Andreas Moshovos

  • Design Space Exploration of Instruction Schedulers for Out-of-Order Soft Processors (pdf)
    In the International Conference on Field-Programmable Technology (FPT'10), December 2010 (Poster presentation).
    Kaveh Aasaraai, Andreas Moshovos

  • Towards a Viable Out-of-Order Soft Core: Copy-Free, Checkpointed Register Renaming (pdf)
    In the 19th International Conference on Field Programmable Logic and Applications (FPL'09), August 2009
    Kaveh Aasaraai, Andreas Moshovos

Low-Power Design and Branch Predictors:

  • Toward Virtualizing Branch Direction Prediction (pdf)
    In the Design, Automation and Test in Europe (DATE), March 2012
    Maryam Sadooghi-Alvandi, Kaveh Aasaraai, Andreas Moshovos

  • A Power-Aware Alternative for the Perceptron Branch Predictor
    The Twelfth Asia-Pacific Computer Systems Architecture Conference (ACSAC), August 2007
    Kaveh Aasaraai, Amirali Baniasadi

  • Computational and Storage Power Optimizations for the O-GEHL Branch Predictor,
    In the ACM International Conference on Computing Frontiers, 2007
    Kaveh Aasaraai, Amirali Baniasadi, Ehsan Atoofian


  • Speculative Supplier Identification for Reducing Power of Interconnects in Snoopy Cache Coherence Protocols,
    In the ACM International Conference on Computing Frontiers, 2007
    Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai

  • Exploiting Speculation Cost Prediction in Power-Aware Applications,
    Journal of Low Power Electronics, Vol. 3, No. 1, 2007
    Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai

  • Low-Power Perceptron Branch Predictor,
    Journal of Low Power Electronics, Vol. 2, No. 3, December 2006
    Kaveh Aasaraai, Amirali Baniasadi

  • Low-Complexity Perceptron Branch Predictor,
    Graduate Innovation Forum, University of Victoria, May 2006.
    Kaveh Aasaraai, Amirali Baniasadi


Tutorials:
  • A quick tutorial I wrote on how to get a gate level power report of your design.