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Amir H. Ashouri

Autotuning — Machine learning — Compiler Optimizations — GPUs

Postdoctoral Researcher @ Electrical and Computer Engineering Dept.

Advised by Tarek Abdelrahman

University of Toronto

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Autotuning addresses automatic code-generation and optimization by using different scenarios and architectures. It constructs techniques for automatic optimization of different parameters in order to maximize or minimize the satisfiability of an objective function.

Machine Learning Applications

Recent optimization problems, i.e. compiler phase-ordering, autotuning problems, selection of right set of optimization from many available optimizations, etc., are too large to exhaustively search. I am looking into ways of adapting applications of machine learning to focus on tuning optimization parameters specially in recent compilers and GPGPUs.

Inference on Mobile Devices

Deep Learning algorithms are nearly used in everyday applications, i.e. image recognition, translation, navigation, etc. However, it has not yet fully exploit the specific DSP and hardware modules available in modern embedded devices such as cellphones. Althought, training a deep learning model is indeed computational intensive, but the inference can be optimized to be mapped and executed on a cellphone's specialized deep learning enabled processors. I am looking into differnt ways of optimizing this proces

Selected Publications

[Full list @ GScholar]

  • [JOURNAL-2017] AH. Ashouri, A. Bignoli, G. Palermo, C, Silvano, S. Kulkarni, J. Cavazos, “MiCOMP: Mitigating the Compiler Phase-ordering Problem using Optimization Sub-sequences and Machine Learning,” ACM Transactions on Architecture and Code Optimization – ACM, 2017.
  • [JOURNAL-2016] AH. Ashouri, G. Mariani, G. Palermo, EJ, Park, J. Cavazos, “COBAYN: Compiler Autotuning Framework Using Bayesian Networks,” ACM Transactions on Architecture and Code Optimization – ACM, 2016. [DOWNLOAD], [DOI], [SOURCE CODE]
  • [WORKSHOP-2016] AH. Ashouri, A. Bignoli, G. Palermo, C. Silvano, “Predictive Modeling Methodology for Compiler Phase-Ordering,” International Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures (PARMA-DITAM) – ACM , 2016. [DOWNLOAD], [DOI]
  • [CONFERENCE-2013] AH. Ashouri, V. Zaccaria, S. Xydis, G. Palermo, C. Silvano, “A Framework for Compiler Level Statistical Analysis over Customized VLIW Architecture,” International Conference on Very Large Scale Integration (VLSI-SoC) – IEEE, 2013. [DOWNLOAD], [DOI]

  • Theses

    • [PHD THESIS] AH. Ashouri, “Compiler Autotuning using Machine Learning Techniques,” Politecnico di Milano – Theses Archive, 2016. [DOI]
    • [M.SC THESIS] AH. Ashouri, “Design Space Exploration Methodology For Compiler Parameters in VLIW Processors,” Politecnico di Milano – Theses Archive, 2012. [DOI]


    DNN Inference on DSP

    This project aims to optimize DNN inference on mobile devices.


    ANTAREX is an EU-FP7 funded project and proposes a holistic approach capable of controlling all the decision layers in order to implement a self-adaptive application optimized for energy efficiency.


    Ph.D. Computer Engineering — December 2016 (cum laude)

    M.Sc. Computer Engineering — December 2012

    B.Sc. Information Technology Engineering — September 2009

    Awards & Grants

    [See the full list @ My CV]

  • [July 2017 - Dec 2017] HiPEAC Junior Postdoc Collaboration Grant
  • [July 2017 - July 2019] Mitacs Elevate Postdoc Fellowship - Advisor: prof. Tarek Abdelrahman - Industrial partner Qualcomm Canada Inc.
  • [April 2017]  Best IEEE (Italy Section) PhD Thesis Award [More Info]
  • [Sep 2014 - April 2015] HiPEAC PhD Collaboration Grant - Visiting scholar of prof. John Cavazos @ University of Delaware, USA [More Info]