Date |
Presenter |
Topic/Reading |
Link |
Presentation |
Oct 13, 2009 |
Andrew Canis |
Alex Papakonstantinou, Karthik Gururaj, John Stratton, Jason Cong, Deming Chen, Wen-mei Hwu. "FCUDA: Enabling Efficient Compilation of CUDA Kernels onto FPGAs". Symposium on Application Specific Processors, July, 2009. |
pdf
| abstract |
pdf |
Oct 20, 2009 |
Mark Aldham |
Lysecky, G. Stitt, F. Vahid. Warp Processors. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 3, pp. 659 - 681, 2006.
|
pdf
| abstract
| ppt |
Oct 27, 2009 |
Jason Luu |
C.H. Ho, C.W. Yu, P.H.W. Leong, W. Luk and S.J.E. Wilton. Floating-Point FPGA: Architecture and Modeling. To appear in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2009.
|
pdf
| abstract
| ppt |
Nov 3, 2009 |
Andrew Canis |
Nitin Chawla. High Performance Signal Processing design using HLS: A
1GSample/sec Frequency Domain Processor Case Study. Tutorial at DAC 2009.
|
N/A |
pdf |
Nov 10, 2009 |
Alex Choong |
A. Ludwin, V. Betz, and K. Padalia, High-quality, deterministic parallel placement for FPGAs on commodity hardware. in Proc. FPGA, 2008, pp. 14-23. |
pdf
| abstract |
ppt |
Nov 24, 2009 |
Nick Ni |
I. Mavroidis and I. Papaefstathiou, Efficient testbench code synthesis for a hardware emulator system in Design, Automation, and Test in Europe (DATA), 2007, pp. 888-893. |
pdf
| abstract |
|
|