Refereed Journal Papers:

[J36] J. Liang*, A. Sheikholeslami, H. Tamura, Y. Ogata, and H. Yamaguchi
Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs
IEEE Journal of Solid-State Circuits, Vol. 53, No. 9, pp. 2696-2708, Sep. 2018.

[J35] J. Liang*, A. Sheikholeslami, H. Tamura,and H. Yamaguchi
On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR
IEEE Journal of Solid-State Circuits, Vol. 53, No. 3, pp. 750-761, Mar. 2018.

[J34] W. Rahman*, D. Yoo, J. Liang, A. Sheikholeslami, H. Tamura, T. Shibasaki, and H. Yamaguchi,
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS
IEEE Journal of Solid-State Circuits, Vol. 52, No. 12, pp. 3517-3531, Dec. 2017.

[J33] S. Karimelahi*, W. Rahman*, M. Parvizi, N. Ben-Hamida, and A. Sheikholeslami,
Optical and electrical trade-offs of rib-to-contact distance in depletion-type ring modulators
Optics Express Vol. 25, No. 17, pp. 20202-20215, Aug. 2017.

[J32] S. Karimelahi* and A. Sheikholeslami,
Ring modulator small-signal response analysis based on pole-zero representation
Optics Express Vol. 24, No. 7, pp. 7585-7599, 2016.

[J31] S. Karimelahi* and A. Sheikholeslami,
Quadrature amplitude modulation (QAM) using binary-driven coupling-modulated rings
Optics Communications Vol. 366, pp. 354-361, May 2016.

[J30] M. S. Jalali*, A. Sheikholeslami, M. Kibune, and H. Tamura,
A Reference-Less Single-Loop Half-Rate Binary CDR
IEEE Journal of Solid-State Circuits, Vol. 50, No. 9, pp. 1-11, Sep. 2015.

[J29] M. S. Jalali*, C. Ting*, J. Liang*, A. Sheikholeslami, M. Kibune, H. Tamura
A 3x blind ADC-based CDR for 20dB loss channel
IEEE Trans. on Circuits and Systems I :Regular Papers, Vol. 62 No. 6, pp. 1658-1667, June 2015.

[J28] A. Vatankhahghadim*, W. Song, and A. Sheikholeslami,
A Variation-Tolerant MRAM-backed-SRAM Cell for Nonvolatile Dynamically Reconfigurable FPGA
IEEE Trans. on Circuits and Systems II : Express Briefs, Vo. 62, No. 6, pp. 573-577, June 2015.

[J27] J. Liang*, M. S. Jalali*, A. Sheikholeslami, M. Kibune, and H. Tamura,
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs
IEEE Journal of Solid-State Circuits, Vol. 50, No. 4, pp. 845-855, Apr. 2015.

[J26] N. Kovacevic*, M. S. Jalali*, J. Liang*, C. Ting*, A. Sheikholeslami, M. Kibune, and H. Tamura,
A 4x, 3-Level, Blind ADC-Based Receiver
Electronics Letters, Vol. 51, No. 7, pp. 551-553, Apr. 2015.

[J25] S. Karimelahi* and A. Sheikholeslami,
PAM-N signaling by coupling modulation in a ring resonator
Optics Letters, Vol. 40, No. 4, pp. 332-335, Feb. 2015.

[J24] Y. Dong, W. Yang, R. Schreier, A. Sheikholeslami, and S. Korrapati,
A Continuous-Time 0.3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS
IEEE Journal of Solid-State Circuits, Vol. 46, No. 12, pp. 2868-2877, Dec. 2014.

[J23] A. Vatankhahghadim*, S. Huda*, and A. Sheikholeslami,
A Survey on Circuit Modeling of Spin-Transfer-Torque Magnetic Tunnel Junctions
IEEE Trans. on Circuits and Systems I :Regular Papers, Vol. 61, No. 9 pp. 2634-2643, Sep. 2014.

[J22] R. Shivnaraine*, M. S. Jalali*, A. Sheikholeslami, M. Kibune, H. Tamura
An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset"
IEEE Trans. on Circuits and Systems I :Regular Papers, Vol. 61 No. 7, pp. 2129-2138, July 2014.

[J21] C. Ting*, J. Liang*, A. Sheikholeslami, M. Kibune, H. Tamura,
A Blind Baud-Rate ADC-Based CDR
IEEE Journal of Solid-State Circuits, Vol. 48, No. 12, pp. 3285-3295, Dec. 2013.

[J20] S. Huda* and A. Sheikholeslami,
A Novel STT-MRAM Cell With Disturbance-Free Read Operation
IEEE Trans. on Circuits and Systems I :Regular Papers, Vol. 60, No. 6, pp. 1534-1547, June 2013.

[J19] B. Abiri*, A. Sheikholeslami, H. Tamura, and M. Kibune,
An Adaptation Engine for a 2x Blind ADC-Basead CDR in 65 nm CMOS
IEEE Journal of Solid-State Circuits, Vol. 46, No. 12, pp. 3140-3149, Dec. 2011.

[J18] O. Tyshchenko*, A. Sheikholeslami, H. Tamura, M. Kibune, H. Yamaguchi, and J. Ogawa,
A 5Gb/s ADC-Based Feed-Forward CDR in 65nm CMOS
IEEE Journal of Solid-State Circuits, Vol. 45, No. 6, pp. 1091-1098, June. 2010.

[J17] O. Tyshchenko* and A. Sheikholeslami,
Match Sensing Using Match-Line Stability in Content-Addressable Memories (CAM),
IEEE Journal of Solid-State Circuits, Vol. 43, No. 9, pp. 1972-1981, Sep. 2008.

[J16] M. van Ierssel*, H. Yamaguchi, A. Sheikholeslami, H. Tamura, and W. W. Walker,
Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI,
IEEE Trans. on Circuits and Systems I :Regular Papers, Vol. 55, No. 5, pp. 1306-1315, June 2008.

[J15] M. van Ierssel*, A. Sheikholeslami, H. Tamura, and W. W. Walker,
A 3.2Gb/s CDR using semi-blind oversampling to achieve high jitter tolerance,
IEEE Journal of Solid-State Circuits, pp. 2224-2234, October 2007.

[J14] D. Nguyen*, D. Halupka*, P. Aarabi, and A. Sheikholeslami,
Real-Time Face Detection and Lip Feature Extraction Using Field-Programmable Gate Arrays,
IEEE Trans. on Systems, Man, and Cybernetics - Part B: Cybernetics, Vol. 36, No. 4, Aug. 2006.

[J13] K. Pagiamtzis* and A. Sheikholeslami,
Content-addressable memory (CAM) circuits and architectures: A tutorial and survey,
IEEE Journal of Solid-State Circuits, pp. 712-727, March 2006.

[J12] Y. Eslami*, A. Sheikholeslami, P. G. Gulak, and S. Masui,
An Area-Efficient Universal Cryptography Processor for Smart Cards,
IEEE Transactions on VLSI Systems, Vol. 14, No. 1, pp. 43-56, Jan. 2006.

[J11] D. Halupka*, N. J. Mathai*, P. Aarabi, and A. Sheikholeslami,
Robust Sound Localization in 0.18µm CMOS,
IEEE Trans. on Signal Processing, Vol. 53, No. 6, pp. 2243-2250, June 2005.

[J10] Y. Eslami*, A. Sheikholeslami, S. Masui, T. Endo, and S. Kawashima,
Circuit implementations for the differential-capacitance read scheme for FeRAMs,
IEEE Journal of Solid-State Circuits, pp. 2024-2031, Nov. 2004.

[J9] K. Pagiamtzis* and A. Sheikholeslami,
A Low-Power Content-Addressable Memory (CAM) Using Pipelined Hierarchical Search Scheme,
IEEE Journal of Solid-State Circuits, pp. 1512-1519, Sep. 2004.

[J8] I.Arsovski* and A. Sheikholeslami,
A Mismatch-Dependent Power Allocation Technique for Match-Line Sensing in Content-Addressable Memories,
IEEE Journal of Solid-State Circuits, Vol. 38, No. 11, pp. 1958-1966, November 2003.

[J7] J. W. Siu*, Y. Eslami*, A. Sheikholeslami, P. G. Gulak, T. Endo, and S. Kawashima,
A Current-Based Reference-Generation Scheme for 1T-1C Ferroelectric Random-Access Memories,
IEEE Journal of Solid-State Circuits, Vol. 38, No. 3, pp. 541-549, March 2003.

[J6] I.Arsovski*, T. Chandler*, and A. Sheikholeslami,
A Ternary Content Addressable Memory (TCAM) based on a 4T Static Storage and including a Current-Race Sensing Scheme,
IEEE Journal of Solid-State Circuits, Vol. 38, No. 1, pp. 155-158, January 2003.

[J5] N. J. Mathai*, D. Kundur, and A. Sheikholeslami,
Hardware Implementation Perspectives of Digital Video Watermarking Algorithms,
IEEE Transactions on Signal Processing, Vol. 51, No. 4, pp. 925-938, April 2003.

[J4] A. Sheikholeslami and P. G. Gulak,
A survey of circuit innovations in Ferroelectric random-access memories,
Proceedings of the IEEE, Vol. 88, No. 3, pp. 667-689, May 2000.

[J3] A. Sheikholeslami, P. G. Gulak, H. Takauchi, H. Tamura, H. Yoshioka, and T. Tamura,
A pulse-based, parallel-element macromodel for ferroelectric capacitors,
IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 47, No. 4, pp. 784-791, July 2000.

[J2] A. Sheikholeslami and P. G. Gulak,
A survey of behavioral modeling of ferroelectric capacitors,
IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 44, No. 4, pp. 917-924, July 1997.

[J1] A. Sheikholeslami and P. G. Gulak,
Transient modeling of ferroelectric capacitors for nonvolatile memories,
IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Vol. 43, No. 3, pp. 450-456, May 1996.

Refereed Conference Papers:

[C46] M. Javad-Kalbasi, K. Dabiri*, S. Valaee, and A. Sheikholeslami
Digitally Annealed Solution for the Vertex Cover Problem with Application in Cyber Security
IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Proceesings, pp. 2642-2646, 2019.

[C45] D. Yoo*, M. Bagherbeik*, W. Rahman*, A. Sheikholeslami, H. Tamura, and T. Shibasaki
A 30Gb/s 2x Half-Baud-Rate CDR
IEEE Custom Integrated Circuit Conference (CICC), Proceedings, pp. 1-4, Apr. 2019.

[C44] D. Yoo*, M. Bagherbeik*, W. Rahman*, A. Sheikholeslami, H. Tamura, and T. Shibasaki
A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS
IEEE International Solid-State Circuits Conference (ISSCC), Dig. of Tech. Papers, pp. 126-128, Feb. 2019.

[C43] A. Sheikholeslami
ADC-based receiver designs: Challenges and opportunities
IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), Proceedings, pp. 1-4, 2017.

[C42] J. Liang*, A. Sheikholeslami, H. Tamura, and H. Yamaguchi
Jitter injection for on-chip jitter measurement in PI-based CDRs
IEEE Custom Integrated Circuit Conference (CICC), Proceedings, pp. 1-4, Apr. 2017.

[C41] W. Rahman*, D. Yoo*, J. Liang*, A. Sheikholeslami, H. Tamura, T. Shibasaki, and H. Yamaguchi,
A 22.5-to-32Gb/s 3.2pJ/b Referenceless Baud-Rate Digital CDR with DFE and CTLE in 28nm CMOS
IEEE International Solid-State Circuits Conference (ISSCC), Dig. of Tech. Papers, pp. 120-121, Feb. 2017.

[C40] J. Liang*, A. Sheikholeslami, H. Tamura, Y. Ogata, and H. Yamaguchi,
A 28Gb/s Digital CDR with Adaptive Loop Gain for Optimum Jitter Tolerance
IEEE International Solid-State Circuits Conference (ISSCC), Dig. of Tech. Papers, pp. 122-123, Feb. 2017.

[C39] S. Sharifymoghaddam* and A. Sheikholeslami,
Low-Swing Signaling for FPGA Power Reduction
24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays Proc. of, pp. 283-283, Feb. 2016.

[C38] A. Vatankhahghadim* and A. Sheikholeslami,
A Multi-level Cell for STT-MRAM with Biaxial Magnetic Tunnel Junction
2015 IEEE International Symposium on Multiple-Valued Logic pp. 158-163, May 2015

[C37] C. Ting*, M. S. Jalali*, A. Sheikholeslami, M. Kibune, H. Tamura,
A Blind ADC-Based CDR with Digital Data Interpolation and Adaptive CTLE and DFE,
IEEE Custom Integrated Circuit Conference (CICC), Proceedings, pp. 1-4, Sep. 2014.

[C36] J. Liang*, M. S. Jalali*, A. Sheikholeslami, M. Kibune, and H. Tamura,
On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs,
IEEE Symposium on VLSI Circuits, Dig. of Tech. Papers, pp. 1-2, June 2014.

[C35] Y. Dong, R. Schreier, W. Yang, S. Korrapati, A. Sheikholeslami,
A 235mW CT 0-3 MASH ADC achieving -167dBFS/Hz NSD with 53MHz BW,
IEEE International Solid-State Circuits Conference (ISSCC), Dig. of Tech. Papers, pp. 480-481, Feb. 2014.

[C34] M. S. Jalali*, C. Ting*, B. Abiri*, A. Sheikholeslami, M. Kibune, H. Tamura,
A 3x Blind ADC-Based Receiver,
IEEE Asian Solid-State Circuits Conference (ASSCC), Dig. Of Tech. Papers, pp. 349-352, Nov. 2013.

[C33] M. S. Jalali*, R. Shivnaraine*, A. Sheikholeslami, M. Kibune, H. Tamura,
An 8mW Frequency Detector for 10Gb/s Half-Rate CDR using Clock Phase Selection,
IEEE Custom Integrated Circuit Conference (CICC), Proceedings, pp. 1-4, Sep. 2013.

[C32] A. Sheikholeslami and H. Tamura,
Design Metrics for Blind ADC-Based Wireline Receivers (Invited Paper),
IEEE Custom Integrated Circuit Conference (CICC), Proceedings, pp. 1-4, Sep. 2013.

[C31] C. Ting*, J. Liang*, A. Sheikholeslami, M. Kibune, H. Tamura,
A Blind Baud-Rate ADC-Based CDR,
IEEE International Solid-State Circuits Conference (ISSCC), Digest of Tech. Papers, pp. 122-123, Feb. 2013.

[C30] B. Abiri*, R. Shivnaraine*, A. Sheikholeslami, H. Tamura, M. Kibune,
A 1-to-6Gb/s Phase-Interpolator-Based Burst-Mode CDR in 65nm CMOS,
IEEE International Solid-State Circuits Conference (ISSCC), Digest of Tech. Papers, pp. 154-155, Feb. 2011.

[C29] B. Abiri*, A. Sheikholeslami, H. Tamura, M. Kibune,
A 5Gb/s Adaptive DFE for 2x Blind ADC-Based CDR in 65nm CMOS,
IEEE International Solid-State Circuits Conference (ISSCC), Digest of Tech. Papers, pp. 436-437, Feb. 2011.

[C28] S. Shahramian*, C. Ting*, A. Sheikholeslami, H. Tamura, M. Kibune,
A Pattern-Guided Adaptive Equalizer in 65nm CMOS
IEEE International Solid-State Circuits Conference (ISSCC), Digest of Tech. Papers, pp. 354-355, Feb. 2011.

[C27] T. Tahmoureszadeh*, S. Sarvari*, A. Sheikholeslami, H. Tamura, Y. Tomita, M. Kibune,
A Combined Anti-Aliasing Filter and 2-tap FFE in 65-nm CMOS for 2x Blind 2-10 Gb/s ADC-Based Receivers
IEEE Custom Integrated Circuit Conference (CICC), Proceedings, pp. 1-4, Sep. 2010.

[C26] S. Sarvari*, T. Tahmoureszadeh*, A. Sheikholeslami, H. Tamura, M. Kibune,
A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS,
IEEE Symposium on VLSI Circuits, Dig. of Tech. Papers, pp. 69-70, June 2010.

[C25] D. Halupka*, S. Huda*, W. Song*, A. Sheikholeslami, K. Tsunoda, C. Yoshida, and M. Aoki,
Negative-Resistance Read and Write Schemes for STT-MRAM in 0.13um CMOS,
IEEE International Solid-State Circuits Conference (ISSCC), Digest of Tech. Papers, pp. 256-257, Feb. 2010.

[C24] O. Tyshchenko*, A. Sheikholeslami, H. Tamura, Y. Tomita, H. Yamaguchi, M. Kibune, T. Yamamoto,
A Fractional-Sampling-Rate ADC-Based CDR with Feed-Forward Architecture in 65nm CMOS,
IEEE International Solid-State Circuits Conference (ISSCC), Digest of Tech. Papers, pp. 166-167, Feb. 2010.

[C23] H. Yamaguchi, H. Tamura, Y. Doi, Y. Tomita, T. Hamada, M. Kibune, S. Ohmoto, K. Tateishi,
O. Tyshchenko*, A. Sheikholeslami, T. Higuchi, J. Ogawa, T. Saito, H. Ishida, K. Gotoh,
A 5-Gb/s Transceiver with an ADC-Based Feed-Forward CDR and CMA Adaptive Equalizer in 65-nm CMOS,
IEEE International Solid-State Circuits Conference (ISSCC), Digest of Tech. Papers, pp. 168-169, Feb. 2010.

[C22] D. Halupka* and A. Sheikholeslami,
Cross-Coupled BL Biasing for 22-nm SRAM,
IEEE International Conference on PhD Research in Microelectronics and Electronics (PRIME 2009), Proceedings, pp. 104-107, July 2009.

[C21] S. McLeod*, A. Sheikholeslami, T. Yamamoto, N. Nedovic, H. Tamura, and W. W. Walker,
A Digital Offset-Compensation Scheme for an LA and CDR in 65-nm CMOS,
IEEE Symposium on VLSI Circuits, Dig. of Tech. Papers, pp. 448-449, June 2009.

[C20] R. Yuen*, M. van Ierssel*, A. Sheikholeslami, H. Tamura, and W. W. Walker,
A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers,
IEEE Custom Integrated Circuit Conference (CICC), Proceedings, pp. 413-416, Sep. 2006.

[C19] M. van Ierssel*, A. Sheikholeslami, H. Tamura, and W. W. Walker,
A 3.2Gb/s Semi-Blind-Oversampling CDR,
IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 334-335, Feb. 2006.

[C18] K. Pagiamtzis* and A. Sheikholeslami,
Using Cache to Reduce Power in Content-Addressable Memories (CAMs),
IEEE Custom Integrated Circuit Conference (CICC), Proceedings, pp. 369-372, Sep. 2005.

[C17] D. Halupka*, S. Rabi*, P. Aarabi, and A. Sheikholeslami,
Real-Time Dual-Microphone Speech Enhancement Using Field-Programmable Gate Arrays,
Proc. IEEE Conf. on Acoustics, Speech, and Signal Processing (ICASSP), Mar. 2005.

[C16] J. Chow*, A. Sheikholeslami, S. Masui, and J. Cross,
A voltage-dependent switching-time (VDST) model of ferroelectric capacitors for low-voltage FeRAM circuits,
IEEE Symposium on VLSI Circuits, Dig. of Tech. Papers, pp. 448-449, June 2004.

[C15] M. van Ierssel*, J. Wong*, and A. Sheikholeslami,
An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling,
Proc. of IEEE System-on-Chip Conference (SOCC), pp. 297-300, Sep. 2004.

[C14] H. Kimura*, K. Pagiamtzis*, A. Sheikholeslami, and T. Hanyu,
A study of multiple-valued Magnetoresistive RAM (MRAM) using binary MTJ devices,
Proc. of the 34th IEEE Int. Symp. on Multiple-Valued Logic (ISMVL), pp. 340-345, 2004.

[C13] K. Pagiamtzis* and A. Sheikholeslami,
Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories,
Proc. of IEEE Custom Integrated Circuits Conference, pp. 383-386, Sep. 2003.

[C12] T. Chandler*, A. Sheikholeslami, S. Masui, and M. Oura,
An Adaptive Reference Generation Scheme for 1T1C FeRAMs,
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 173-174, June 2003.

[C11] I. Arsovski* and A. Sheikholeslami,
A Current-Saving Match-line Sensing Scheme for Content Addressable Memories,
IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, pp. 304-305, Feb. 2003.

[C10] M. van Ierssel*, T. Esmailian*, A. Sheikholeslami, and P. S. Pasupathy,
Signaling capacity of FR4 PCB traces for chip-to-chip communication,
IEEE International Symposium on Circuits and Systems (ISCAS), Proceedings, Vol. 5, pp. 85-88, May 2003.

[C9] N. J. Mathai*, A. Sheikholeslami, and D. Kundur,
VLSI implementation of a real-time video watermark embedder and detector,
IEEE International Symposium on Circuits and Systems (ISCAS), Proceedings, Vol. 2, pp. 772-775, May 2003.

[C8] D. Nguyen*, P. Aarabi, and A. Sheikholeslami,
Real-Time Sound Localization Using Field- Programmable Gate Arrays,
2003 IEEE Conference on Acoustics, Speech, and Signal Processing (ICASSP), Proceedings, pp. 573-576, April 2003.

[C7] Y. Eslami*, A. Sheikholeslami, S. Masui, T. Endo, and S. Kawashima,
Differential-capacitance read scheme for FeRAMs,
IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 298-301, June 2002.

[C6] J. Siu*, Y. Eslami*, A. Sheikholeslami, P. G. Gulak, T. Endo, and S. Kawashima,
A 16kb 1T1C FeRAM Testchip Using Current-Based Reference Scheme,
IEEE Custom Integrated Circuit Conference, pp. 107-110, May 2002.

[C5] Y. Eslami*, J. Siu*, A. Sheikholeslami, P.G. Gulak, T. Endo, and S. Kawashima,
A 2T-2C FeRAM Testchip for Optimum Bitline and Cell Capacitances,
Proc. of the 1st Int'l Meeting on Ferroelectric Random Access Memories, pp. 178-179, Nov. 2001.

[C4] A. Sheikholeslami and P. G. Gulak,
A Survey of Reference Generation Techniques for Ferroelectric Memories,
12th Int. Symp. on Integrated Ferroelectrics (ISIF2000), Abstracts, p. 252, Aachen, Germany, March 12-15, 2000.

[C3] A. Sheikholeslami, R. Yoshimura, and P. G. Gulak,
Look-up tables for multiple-valued, combinational logic,
Proc. of the 28th Int. Symp. on Multiple-Valued Logic (ISMVL), pp. 264-269, May 1998.

[C2] A. Sheikholeslami, P. G. Gulak, and T. Hanyu,
A multiple-valued ferroelectric content-addressable memory,
Proc. of the 26th Int. Symp. on Multiple-Valued Logic (ISMVL), pp. 74-79, May 1996.

[C1] A. Sheikholeslami and P. G. Gulak,
Transient modeling of ferroelectric capacitors for semiconductor memories,
1st European Meeting on Integrated Ferroelectrics, Nijmegen, Netherlands, July 1995.

Patents Granted:

[G7] S. Masui, Y. Eslami*, and A. Sheikholeslami,
Ferroelectric memory supplying predetermined amount of direct-current bias electricity to first and second bitlines upon reading data from memory cell,
Canadian Patent No. 2,430,875, issued on Feb. 5, 2008.
This patent is acquired by Fujitsu Laboratories Limited, Kawasaki, Japan.

[G6] T. Chandler*, A. Sheikholeslami, and S. Masui,
Ferroelectric memory,
US Patent No. 7,266,009, issued on Sep. 4, 2007.
This patent is acquired by Fujitsu Laboratories Limited, Kawasaki, Japan.

[G5] S. Masui, Y. Eslami*, and A. Sheikholeslami,
Plate line non-drive improved reading method for a ferroelectric memory,
European Patent No. 1,369,876, granted on March 14, 2007.
This patent is acquired by Fujitsu Laboratories Limited, Kawasaki, Japan.

[G4] I. Arsovski* and A. Sheikholeslami,
A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories,
US Patent No. 7,006,368, issued on Feb. 28, 2006.
This patent is acquired by Mosaid Technologies Inc., Kanata, Ontario, Canada

[G3] S. Masui, Y. Eslami*, and A. Sheikholeslami,
Ferroelectric memory supplying predetermined amount of direct-current bias electricity to first and second bitlines upon reading data from memory cell,
US Patent No. 6,882,559, issued on Apr. 19, 2005.
This patent is acquired by Fujitsu Laboratories Limited, Kawasaki, Japan.

[G2] A. Sheikholeslami, P. G. Gulak, and T. Hanyu,
Non-Volatile Content Addressable Memory,
US Patent No. 5,930,161, issued on July 27, 1999.
This patent is acquired by Nortel, Ottawa, Canada.

[G1] A. Sheikholeslami, P. Glenn Gulak, T. Hanyu,
Non-Volatile Content Addressable Memory,
US Patent No. 5,808,929, issued on Sep. 15, 1998.
This patent is acquired by Nortel, Ottawa, Canada.