About Me


From 2011 to 2013, I was a MASc student in the department of electrical and computer engineering at the University of Toronto. I was supervised by Prof. Vaughn Betz. My research revolved around FPGA circuit design. That is, how do we go about designing FPGA circuitry, and what are good circuit design practices in advanced process technology? To enable this kind of research, I developed a fully-automated transistor-level design tool for FPGAs called COFFE. The tool is available here. Although I'm graduated now, I'm still actively developping and supporting COFFE while new students take over.


M.A.Sc. at University of Toronto, supervised by Vaughn Betz, 2011 - 2013.
B.Eng. at Université de Moncton, 2006 - 2011.


Email: charlesc (at) eecg.utoronto.ca

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J. Luu, C. McCullough, S. Wang, S. Huda, Y. Bo, C. Chiasson, K. Kent, J. Anderson, J. Rose and V. Betz, "On Hard Adders and Carry Chains in FPGAs", IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 52 - 59. [PDF]

C. Chiasson and V. Betz, "COFFE: Fully-Automated Transistor Sizing for FPGAs", IEEE International Conference on Field-Programmable Technology (FPT), 2013, pp. 34 - 41. [PDF]

C. Chiasson and V. Betz, "Should FPGAs Abandon the Pass-Gate?", IEEE International Conference on Field-Programmable Logic and Applications (FPL), 2013. [PDF]