COFFE is an automated transistor-level design tool for FPGAs. Automated transistor-level design of FPGA architectures is crucial when evaluating many different architectures with tools such as VPR. Different architectures have different transistor-level requirements. For instance, transistor and wire loading greatly depend on the FPGA’s architecture. Thus transistor-level design should be performed for each architecture that is evaluated to ensure a thorough exploration of the design space.

COFFE enables this thorough design space exploration by providing area and delay estimates of properly sized FPGA circuitry for a user specified architecture. These estimates can then be fed into VPR to evaluate the architecture through place and route experiments. The VPR trunk (post 7.0) has been updated to use COFFE's improved area model by default, and its routing delay model has been updated to account for COFFE's circuit design assumptions, making COFFE and VPR fully-compatible. COFFE's transistor sizing algorithm is described in detail in this paper along with its area, delay and wire load models.

News

 
  • COFFE v2.0 is coming soon!
  • COFFE v1.1 is now available! It features a new HSPICE interface that makes COFFE run more reliably with different versions of HSPICE (which was a problem in COFFE v1.0). All the HSPICE versions I have tried so far have been working as expected. Feel free to inform me of any issues.

Download

 
Download COFFE v1.1
Download COFFE v1.0

Documentation

 

COFFE User's Manual (DOCX)
COFFE User's Manual (PDF)

C. Chiasson and V. Betz, "COFFE: Fully-Automated Transistor Sizing for FPGAs", IEEE International Conference on Field-Programmable Technology (FPT), 2013, pp. 34 - 41 [PDF]

How to cite

 

The following paper can be used as a citation for COFFE:

C. Chiasson and V. Betz. "COFFE: Fully-Automated Transistor Sizing for FPGAs", IEEE International Conference on Field-Programmable Technology (FPT), 2013.

Contact

 
Have questions? Ran into a problem? Find bugs?
Feel free to email me at: charlesc(at)eecg.utoronto.ca and I'll do my best to help.