"Should FPGAs Abandon the Pass-Gate?"


The following VPR architecture files all have an identical 22nm architecture which is described in detail in "Should FPGAs Abandon the Pass-Gate?" [PDF]. Briefly, N=10, K=6, W=320, Fcin = 0.2, Fcout = 0.025. See [1] for more details. They differ in terms of the type of switch used (pass-transistor or transmission gate) and in terms of supply voltage and SRAM voltage (i.e. gate boosting). Timing estimates for the logic and routing were obtained with an early version of COFFE. Note that the nominal VDD for this process is 0.8V.

Pass-transistor FPGAs

VDD = 0.8V, VSRAM+ = 0.8V, ArchFile: PT_N10_K6_W320_no_boost.xml

VDD = 0.8V, VSRAM+ = 0.9V, ArchFile: PT_N10_K6_W320_boost_01.xml

VDD = 0.8V, VSRAM+ = 1.0V, ArchFile: PT_N10_K6_W320_boost_02.xml

VDD = 0.7V, VSRAM+ = 0.7V, ArchFile: PT_N10_K6_W320_vdd07_vsram07.xml

VDD = 0.7V, VSRAM+ = 0.8V, ArchFile: PT_N10_K6_W320_vdd07_vsram08.xml

VDD = 0.6V, VSRAM+ = 0.6V, ArchFile: PT_N10_K6_W320_vdd06_vsram06.xml

VDD = 0.6V, VSRAM+ = 0.8V, ArchFile: PT_N10_K6_W320_vdd06_vsram08.xml

Transmission Gate FPGAs

VDD = 0.8V, VSRAM+ = 0.8V, VSRAM- = 0.0V, ArchFile: TG_N10_K6_W320_no_boost.xml

VDD = 0.8V, VSRAM+ = 0.9V, VSRAM- = 0.0V, ArchFile: TG_N10_K6_W320_boost_01.xml

VDD = 0.8V, VSRAM+ = 1.0V, VSRAM- = 0.0V, ArchFile: TG_N10_K6_W320_boost_02.xml

VDD = 0.7V, VSRAM+ = 0.7V, VSRAM- = 0.0V, ArchFile: TG_N10_K6_W320_vdd07_vsram07.xml

VDD = 0.7V, VSRAM+ = 0.8V, VSRAM- = 0.0V, ArchFile: TG_N10_K6_W320_vdd07_vsram08.xml

VDD = 0.6V, VSRAM+ = 0.6V, VSRAM- = 0.0V, ArchFile: TG_N10_K6_W320_vdd06_vsram06.xml

VDD = 0.6V, VSRAM+ = 0.8V, VSRAM- = 0.0V, ArchFile: TG_N10_K6_W320_vdd06_vsram08.xml