Vector Microprocessors: Architectural and Compilation Issues

Advances in VLSI technology will soon be able to provide one billion transistors on a single chip. For this research, we are investigating the challenges of using this unprecedented number of transistors to implement vector architectures on a single chip. One reason for considering vector architectures is that they offer the exciting possibility for architects to target the emerging applications area of multimedia.

Recent developments in general-purpose microprocessors have augmented state-of-the-art superscalar hardware with vector capabilities with the goal of targetting multimedia applications. These industrial developments suggest that they are cost-effective implementations for such applications.

Motivated by these industrial developments, we are exploring not only traditional vector configurations but also combined superscalar vector configurations. Our investigation encompasses compilation algorithms for vectorization, performance and cost analysis of processor design, and exploring new architectures for vector processors and memory systems.

Graduate Students

Mark Stoodley, Ph.D., Performance and Cost Study of Superscalar Vector Processors, in progress.
Paul Hellyar, M.A.Sc., Automatic Compilation for Short Vector Extensions, in progress.
Derek DeVries, M.A.Sc., A Vectorizing SUIF Compiler [abstract], May 1997.

Publications and Presentations

M.G. Stoodley and C.G. Lee. Vector Microprocessors for Desktop Computing. Submitted for publication to the 26th Annual International Symposium on Computer Architecture.
C.G. Lee and M.G. Stoodley. Simple Vector Microprocessors for Multimedia Applications. Accepted for publication in the 31st Annual International Symposium on Microarchitecture.
(Slides: 4-up ps, ps)
C.G. Lee and D.J. DeVries. Initial Results on the Performance and Cost of Vector Microprocessors. In the Proceedings of the 30th Annual International Symposium on Microarchitecture, pp 171-182, December 1997. (Slides: 4-up ps, ps; Data graphs: 4-up ps, ps)
D. DeVries and C.G. Lee. A Vectorizing SUIF Compiler. In Proceedings of the First SUIF Compiler Workshop, pp. 59-67, January 1996. (Slides: 4-up ps)

Research Infrastructure [synopses]

VIVACE: Variable Implementations for Vector Architectural and Compiler Exploration
- VMIPS: a vector extension of the MIPS ISA
- VSUIF: an experimental vectorizing compiler
- vmable: a functional simulator that emulates VMIPS instructions
- vcello: a parameterizable timing simulator that simulates the behavior of a wide variety of vector processors
SVX_SUIF: an extension to VSUIF to target short vector extensions

Related Research [synopses]

Architectures

The Berkeley IRAM Project, University of California, Berkeley, 1997 to present.
Advanced Vector Architectures, Universitat Politecnica de Catalunya, February 1997.
Torrent T0 Vector Microprocessor, University of California, Berkeley, 1992-1995.

Compilation

High-level tools and compiler technology for multimedia instruction sets, University of Bristol, 1998.
Session on "Support for Specialized Instruction Sets" at The SUIF Compiler Workshop, August 1997.
Compilation for SWAR (SIMD Within a Register) Processors, Purdue University, 1997.
NESL: A Parallel Programming Language, Carnegie Mellon University, 1994-96.
Parallel Loop Transformation: Techniques for Vector-Based Multiprocessor Systems, University of Minnesota, May 1994.

References [synopses]

Architectures

Compilation

Architectural Panel Session at PLDI, June 1998.
High Performance Compilers for Parallel Computing, 1998.
National Compiler Infrastructure Project, 1997 to present.
- SUIF, 1994 to present.
- Zephyr, 1994 to present.

Last Updated: 17 Nov 1998
Corinna G. Lee (corinna@eecg.toronto.edu)