

Note that PDF
reprints are provided below within the context of
fair use. Please obtain copies from the respective
publisher, if appropriate.
Publications Submitted to Refereed Journals for Review
Refereed Journal Publications

N. Nikkhoo, P.G. Gulak, K. Maxwell, "Rapid detection of E.Coli bacteria using potassiumsensitive FETs in CMOS", IEEE Transactions on Biomedical Circuits and Systems, Submitted Mar. 2013.b

M. Shabany, D. Patel, P.G. Gulak, "A LowLatency LowPower QRDecomposition ASIC Implementation in 0.13um CMOS", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 60, No. 2, pp. 327340, Feb. 2013. (NSERC)

D. Ho, O. Noor, U. Krull, G. Gulak, and R. Genov, "CMOS TunableWavelength MultiColor Photogate Sensor", IEEE Trans. on Biomedical Circuits and Systems, accepted for publication. (NSERC).

D. Ho, M. O. Noor, U. Krull, P.G. Gulak, R. Genov, "CMOS TunableColor Image Sensor With DualADC ShotNoiseAware Dynamic Range Extension", IEEE Transactions on Circuits and Systems I: Regular Papers, DOI: 10.1109/TCSI.2013.2239115 (Early Access). (NSERC)

D. Ho, M. O. Noor, U. Krull, P.G. Gulak, R. Genov, "CMOS SpectrallyMultiplexed FRETonaChip for DNA Analysis", IEEE Transactions on Biomedical Circuits and Systems, DOI: 10.1109/TBCAS.2012.2230172 (Early Access). (NSERC)

V. Smolyakov, P. G. Gulak, T. Gallager, C. Ling, "FaultTolerant Embedded Memory Strategy for Baseband Signal Processing Systems", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, DOI: 10.1109/TVLSI.2012.2208208 (Early Access). (NSERC)

M. Shabany, A. Youssef, P. G. Gulak, "HighThroughput 0.13um CMOS Lattice Reduction Core Supporting 880Mb/s Detection", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, DOI: 10.1109/TVLSI.2012.2198927 (Early Access). (NSERC)

M. Zargham, P. G. Gulak, "Maximum Achievable Efficiency in NearField Coupled Power Transfer Systems", IEEE Transactions on Biomedical Circuits and Systems, Vol. 6, No. 3, pp. 228245, Mar. 2012. (NSERC)

M. Shabany, P. G. Gulak, "A 675 Mbps, 4x4 64QAM KBest MIMO Detector in 0.13um CMOS", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 1, pp. 135147, Jan. 2012. (NSERC)

R. Singh, D. Ho, A. Nilchi, P. G. Gulak P. Yau, R. Genov, "A CMOS/ThinFilm Fluorescence Contact Imaging Microsystem for DNA Analysis", IEEE Trans. on Circuits and Systems I: Regular Papers, Vol. 57, No. 5, pp. 10291038, May 2010. (NSERC)

M. Shabany and P. G. Gulak, "Efficient Compensation of the Nonlinearity of SolidState Power Amplifiers Using Adaptive Sequential Monte Carlo Methods", IEEE Transactions on Circuits and Systems I, Vol. 55, No. 10, pp. 32703283, 2008. (NSERC)

W. J. Gross, F. R. Kschischang, and P. G. Gulak, "Architecture and Implementation of an Interpolation Processor for SoftDecision ReedSolomon Decoding", IEEE Transactions on VLSI Systems, Vol. 15, No. 3, pp. 309318, March 2007. (NSERC)

W. J. Gross, F. R. Kschischang, R. Koetter, and P. G. Gulak, "Applications of Algebraic SoftDecision Decoding of ReedSolomon Codes", IEEE Transactions on Communications, Vol. 54, No. 7, pp. 12241234, July 2006. (NSERC)

Yadollah Eslami, Ali Sheikholeslami, Glenn Gulak, "An AreaEfficient Universal Cryptography Processor for Smart Cards", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 1, pp. 4356, Jan. 2006. (NSERC, Fujitsu)

D. Gnaedig, E. Boutillon, M. Jezequel, V. Gaudet and P. G. Gulak, "On Multiple Slice Turbo Codes", Annals of Telecommunications, Vol. 60,No.12, January/February 2005, pp.79102.

W. Gross, F. Kschischang, R. Koetter and P. G. Gulak, "Towards a VLSI Architecture for InterpolationBased SoftDecision ReedSoloman Decoders", Journal of VLSI Signal Processing, Vol. 39, No. 12, 2005, pp. 93111.

V. Gaudet and P. G. Gulak, "A 13.3Mbps, 0.35um CMOS Analog Turbo Decoder IC with Configurable Interleaver" (invited), IEEE Journal of SolidState Circuits, Nov. 2003.

T. Esmailian, F.R. Kschischang, and P. G. Gulak, "InBuilding Power Lines as High Speed Communication Channels: Channel Characterization and a Test Channel Ensemble", International Journal of Communication Systems, pp. 381400, May 2003. (NSERC), Motorola.

J. Siu, Y. Eslami, A. Sheikholeslami, P. G. Gu lak, T. Endo, and S. Kawashima, "A CurrentBased ReferenceGeneration Scheme for 1T1C Ferroelectric RandomAccess Memories", IEEE Journal of SolidState Circuits, Vol. 38, No. 3, March 2003, pp. 541549.

E. Boutillon, W. Gross, and P. G. Gulak, "VLSI Architectures for the MAP Algorithm", IEEE Trans. on Communications, Vol. 51, No. 2, Feb. 2003, pp. 175185.

V. Gaudet, R. Gaudet and P. G. Gulak, "Programmable Interleaver Design for Analog Iterative Decoders", IEEE Transactions on Circuits and Systems II  Analog and Digital Signal Processing, Vol. 49, No. 7, pp. 457464, July 2002.

W. Gross, V. Gaudet, and P. G. Gulak, "Difference Metric Softoutput Detection: Architecture and Implementation", IEEE Transactions on Circuits and Systems II"Analog and Digital Signal Processing, Vol. 48, No. 10, pages 904911, October 2001.

Sheikholeslami, A., and P. G. Gulak, Takauchi, H.,
Tamura, H., Yoshioka, H., and Tamura, T., "A PulseBased,
ParallelElement Macromodel for Ferroelectric Capacitors",
IEEE Trans. On Ultrasonics, Ferroelectrics, and
Frequency Control, Vol. 47, No. 4, July 2000, pp.
784791.

Sheikholeslami, A., and P. G. Gulak, "A Survey of
Circuit Innovations in Ferroelectric RandomAccess
Memories", Proceedings of the IEEE. Vol. 88, No.
5, May 2000, pp. 667689.

J. Omidi, P. G. Gulakand S. Pasupathy, "Parallel Structures
for Joint Channel Estimation and Data Detection Over
Fading Channels", IEEE Transactions on Selected Areas
of Communications (special issue on Signal Processing and
Wireless Communications), Vol. 16, No. 9, pp.
16161629, Dec. 1998.

Gaudet, V., and P. G. Gulak, "Implementation Issues
for HighBandwidth FieldProgrammable Analog Arrays",
Journal of Circuits, Systems, and Computers Special Issue
on Analog and Digital Arrays, World Scientific
Publishing, Vol. 8, No. 56, pages 541558, 1998.

W. Gross and P. G. Gulak, "Simplified MAP Algorithm suitable
for implementation of turbo decoders", Electronics
Letters, Aug. 6, 1998, Vol. 34, No. 16, pp. 15771578.

D. R. D"Mello and P. G. Gulak, "Design Approaches to
FieldProgrammable Analog Integrated", (Special Issue
on Programmable Analog Systems), Analog Integrated
Circuits and Signal Processing, Kluwer Academic Publishers,
Vol. 17, No. 12, pp. 734, Sept. 1998.

K. Lowe and P. G. Gulak, "A Joint Gate Sizing and Buffer
Insertion Method for Optimizing Delay and Power in CMOS
and BiCMOS Combinational Logic", IEEE Transactions on
CAD, Vol. 17, No. 5, May 1998, pp. 419434.

K. Schultz and P. G. Gulak, "Physical Performance
Limits for Shared Buffer ATM Switches", IEEE
Transactions on Communications, Vol. 45, No. 8, pp.
9971007, Aug. 1997.

A. Sheikholeslami and P. G. Gulak, "A Survey of
Behavioral Modeling of Ferroelectric Capacitors", IEEE
Transactions on Ultrasonics, Ferroelectrics and Frequency
Control, Vol. 44, No. 4, pp. 917924, July 1997.

K. Schultz and P. G. Gulak, "Multicast Contention
Resolution with SingleCycle Windowing Using Content
Addressable FIFOs", IEEE/ACM Transactions on Networking,
Vol. 4, No. 5, pp. 731742, Oct. 1996.

A. Sheikholeslami and P. G. Gulak, "Transient Modeling of Ferroelectric Capacitors for Semiconductor Memories",
Microelectronic Engineering, Vol. 29, No. 14,
1995, pp. 141144.

A. Sheikholeslami and P. G. Gulak, "Transient Modeling
of Ferroelectric Capacitors for Nonvolatile Memories",
IEEE Transactions on Ultrasonics, Ferroelectrics, and
Frequency Control, Vol. 43, No. 3, 1996, pp. 450456.

K. Schultz and P. G. Gulak, "FullyParallel Integrated
CAM/RAM Using PreClassification to Enable Large
Capacities", IEEE Journal of SolidState Circuits,
Vol. 31, No. 5, pp. 689699, May 1996.

K. Schultz and P. G. Gulak, "Architectures for
LargeCapacity CAMs", Integration, the VLSI Journal,
18, No. 23, pp. 151171, 1995.

K. Schultz and P. G. Gulak,
Throttled Buffer Asynchronous Switch
for ATM, IEICE Transactions on
Communications, (Special Issue on Future Private Networks),Vol.
E77B, No. 3, March 1994, pp. 351358.

G. Feygin, P. G. Gulak and P. Chow,
Minimizing Excess
Code Length and VLSI Complexity in the Multiplication Free
Approximation of Arithmetic Coding, The Journal of
Information Processing and Management (Special Issue on
Data Compression), Vol. 30, No. 6, pp. 805816,
NovDec 1994.

K. C. Smith and P. G. Gulak, Prospects for MultiValued
Integrated Circuits (invited paper), IEICE Transactions
on Electronics, Vol. E76C, No. 3, March 1993, pp.
372382.

E. Lee and P. G. Gulak, CurrentMode Multivalued Dynamic
MOS Memory with Error Correction, IEE Electronics
Letters, Vol. 28, No. 11, May 1992, pp.10671069.

E. Lee and P. G. Gulak, Field Programmable Analog Array
Based on MOSFET Transconductors, IEE Electronics
Letters, Vol. 28, No. 1, Jan. 1992, pp. 2829.

G. Feygin, P. G. Gulak and P. Chow,
A Multiprocessor
Architecture for Viterbi Decoders with Linear Speedup,
IEEE Transactions on Signal Processing, Vol. 41, No.
9, September 1993, pp. 2907  2917.

J. Erfanian, S. Pasupathy, P. G. Gulak,
Reduced
Complexity Symbol Detectors with Parallel Structures for ISI Channels, IEEE Trans. on Communications, Vol.
42; No. 2/3/4, Feb/Mar/April, 1994, pp.16611671.

G. Feygin and P. G. Gulak,
Architectural Tradeoffs for
Survivor Sequence Memory Management in Viterbi Decoders,
IEEE Transactions on Communications, Vol. 41, No.
3, March 1993, pp. 425  429.

E. Lee and P. G. Gulak, A CMOS Field Programmable Analog Array, IEEE J. of Solid State Circuits, Vol. 26,
No. 12, December 1991, pp. 18601867.

E. Lee and P. G. Gulak, Error Correction Technique for Multivalued MOS Memory, IEE Electronics Letters,
Vol. 27, No. 15, July 18, 1991, pp. 13211323.

P. G. Gulak and T. Kailath, Locally Connected VLSI
Architectures for the Viterbi Algorithm, IEEE Journal
on Selected Areas in Communications (Special Issue on VLSI
in Communications), Vol. 6, No. 3, April 1988, pp.
527537.

M. Horowitz, P. Chow, M. Wing, D. Stark, R. Simoni, A. Salz,
S. Przybylski, J. Hennessy, P. G. Gulak, A. Agarwal,
J. Acken, MIPSX: A 20 MIPS Peak, 32Bit Microprocessor
with OnChip Cache, IEEE Journal of Solid State
Circuits, Vol. SC22, No. 5, October 1987, pp.
790799.

H.C. Card, P. G. Gulak, R.D. McLeod and W. Pries,
(lT)
Complexity Measures for VLSI Computations in Constant Chip
Area, IEEE Transactions on Computers, Volume C36,
No. 1, January 1987, pp. 112117.

G.E. Bridges, W. Pries, R.D. McLeod, M. Yunik, P. G. Gulak
and H.C. Card, Dual Systolic Architectures for VLSI
Digital Signal Processing Systems, IEEE Transactions on
Computers, Volume C35, No. 10, October 1986, pp.
916923.

P. G. Gulak and E. Shwedyk, VLSI Structures for Viterbi
Receivers: Part I  General Theory and Applications,
IEEE Journal on Selected Areas in Communications (Special
Issue on VLSI in Communications), Volume SAC4, No. 1,
January 1986, pp. 142154.

P. G. Gulak and E. Shwedyk, VLSI Structures for Viterbi
Receivers: Part II  Encoded MSK Modulation, IEEE
Journal on Selected Areas in Communications (Special Issue
on VLSI in Communications), Volume SAC4, No. 1,
January 1986, pp. 155159.

D.A. Buchanan and P. G. Gulak,
Photocounting Statistics
Associated with Temperature Fluctuations in Semiconductor
Lasers, Journal of Applied Optics, Vol. 22, No. 1,
January 1, 1983, pp. 3748.

P. G. Gulak, E. Shwedyk and D. Card, An Improved
Approximation for the Isolated Transition in Saturated
Magnetic Recording, IEEE Transactions on Magnetics,Vol.MAG18,
No. 5, 1982, pp. 989992.
Refereed Conference Papers

M. Zargham, P.G. Gulak, "A 0.13um CMOS Integrated Wireless Power Receiver for Biomedical Applications", IEEE European Solid State Circuits Conference (ESSCIRC), Submitted May 2013.

N. Nikkhoo, P.G. Gulak, K. Maxwell, "Rapid Detection of E.Coli Bacteria using Potassiumsensitive FETs in CMOS", IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 168171, Nov. 2012. (NSERC) Best Paper Award

D. Ho, M.O Noor, U. Krull, P.G. Gulak, R. Genov "Singlefilter Multicolor CMOS Fluorescent Contact Sensing Microsystem", IEEE Int. Symp. on Circuits and Systems (ISCAS'12), pp. 23932396, 2012. (NSERC)

D. Ho, P.G. Gulak, R. Genov "CMOS 3T Digital Pixel Sensor with Inpixel Shared Comparator", IEEE Int. Symp. on Circuits and Systems (ISCAS'12), pp. 930933, 2012. (NSERC)

M. Zargham, P.G. Gulak, "Fullyintegrated Powerefficient Regulator and Bandgap Circuits for Wirelesspowered Biomedical Applications", IEEE Int. Symp. on Circuits and Systems (ISCAS'12), pp. 28732876, 2012. (NSERC)

M. Zargham, P.G. Gulak, "Highefficiency CMOS Rectifier for Fully Integrated mW Wireless Power Transfer", IEEE Int. Symp. on Circuits and Systems (ISCAS'12), pp. 28692872, 2012. (NSERC)

S. Moradi, R. Doostnejad, P.G. Gulak, "Downlink Beamforming for FDD Systems with Precoding and Beam Steering", IEEE GlobeCOM, pp. 16, 2011. (NSERC)

S. Moradi, P.G. Gulak, "A Robust RAMTHP Architecture for Downlink Multiuser MISO Transmission with User Scheduling", IEEE Signal Processing Systems (SIPS'11), pp. 334339, 2011. (NSERC)

D. Ho, P.G. Gulak, R. Genov "CMOS Field Modulated Color Sensor", IEEE Custom Integrated Circuits Conference (CICC), M22, pp. 14, 2011. (NSERC)

M. Zargham, P.G. Gulak, "Integrated CMOS Wireless Power Transfer for Neural Implants", IEEE Int. Symp. on Circuits and Systems (ISCAS'11), pp. 165168, 2011. (NSERC)

A. Youssef, M. Shabany, P.G. Gulak, "Performance Analysis of LatticeReduction Algorithms for a Novel LRCompatible KBest MIMO Detector", IEEE Int. Symp. on Circuits and Systems (ISCAS'11), pp. 701704, 2011. (NSERC)

D. Patel, V. Smolyakov, M. Shabany, P.G. Gulak, "A WiMAX/LTE Compliant Lowcomplexity 4x4 64QAM Soft MIMO Receiver", IEEE 44th Asilomar Conf. on Signals, Systems and Computers (ASILOMAR), pp. 385389, 2010. (NSERC)

D. Patel, V. Smolyakov, M. Shabany, P.G. Gulak, "VLSI Implementation of a WiMAX/LTE Compliant LowComplexity HighThroughput SoftOutput KBest MIMO Detector", IEEE ISCAS 2010, June 2010. (NSERC)

A. Youssef, M. Shabany, P.G. Gulak, "VLSI Implementation of a HardwareOptimized LatticeReduction Algorithm for WiMAX/LTE MIMO Detection", IEEE Int. Symp. on Circuits and Systems, (ISCAS'10), pp. 35413544, 2010. (NSERC)

R.R. Singh, D. Ho, A. Nilchi, R. Genov, P.G. Gulak, "A Hybrid Thinfilm/CMOS Fluorescence Contact Imager", IEEE Int. Symp. on Circuits and Systems (ISCAS'09), pp. 24372440, 2009. (NSERC)

D. Patel, M. Shabany, P.G. Gulak, "A LowComplexity HighSpeed QR Decomposition Implementation for MIMO Receivers", IEEE Int. Symp. on Circuits and Systems (ISCAS'09), pp. 3336, 2009. (NSERC)

M. Shabany, P.G. Gulak, "A 0.13um CMOS 655Mb/s 64QAM KBest 4x4 MIMO Detector", 2009 IEEE International SolidState Circuits Conference Digest of Technical Papers (ISSCC'09), pp. 256257, Feb. 2009. (NSERC)

N. Nikkhoo, C. Mann, P.G. Gulak and K. Maxwell, "A CMOS Integrated Bacterial Sensor for Rapid Detection of Pseudomonas aeruginosa", IEEE Biomedical Circuits and Systems Conference, (BioCAS), pp. 213216, Nov. 2008. (NSERC, CIHR)

M. Shabany, P.G. Gulak, "A Systolic Architecture of a Sequential Monte Carlobased Equalizer for FrequencySelective MIMO Channels", IEEE Workshop on Signal Processing Systems (SIPS'08), pp. 6772, Oct. 2008. (NSERC)

M. Shabany, P.G. Gulak, "A Scalable VLSI Architecture for KBest Lattice Decoders", IEEE International Symposium on Circuits and Systems (ISCAS'08), pp. 940943, May 2008. (NSERC)

M. Shabany, P.G. Gulak, "The Application of LatticeReduction to the KBest Algorithm for NearOptimal MIMO Detection", IEEE Int. Symp. on Circuits and Systems (ISCAS'08), pp. 316319, May 2008. (NSERC)

M. Shabany, K. Su, P.G. Gulak, "A Pipelined Scalable HighThroughput Implementation of a NearML Complex KBest Complex Lattice Decoders", IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP'08), pp. 31733176, April 2008. (NSERC)

N. Nikkhoo, C. Mann, K. Maxwell, P.G. Gulak, "A 0.18um CMOS Integrated Sensor for the Rapid Identification of Bacteria", 2008 IEEE International SolidState Circuits Conference Digest of Technical Papers (ISSCC'08), pp. 336337, Feb. 2008. (NSERC)

M. Shabany, P.G. Gulak, "Application of Sequential Monte Carlo to MQAM Schemes in the Presence of Nonlinear SolidState Power Amplifiers", IEEE Int. Symp. on Circuits and Systems (ISCAS'07), pp. 22952298, 2007, Best Student Paper Award Nominee. (NSERC)

S. Parikh, P.G. Gulak, P. Chow, "A CMOS Image Sensor for DNA Microarrays", Custom Integrated Circuits Conference (CICC), pp. 821824, Sept. 2007. (NSERC)

K. Kasiri, I. Hosseini, O. Taheri, M.J. Omidi, P.G. Gulak, "A Preprocessing Method for PAPR Reduction in OFDM Systems by Modifying FFT and IFFT Matrices", IEEE Int. Symp. on Personal, Indoor and Mobile Radio Communications (PIMRC'07), pp. 15, 2007.

M. Shabany, P. G. Gulak, "VLSI Implementation of a
Sequential Monte Carlo Receiver", IEEE
International Symposium on Circuits and Systems (ISCAS'06),
Greece, May 2124, 2006.

M. Shabany, P. G. Gulak, "An Efficient Architecture
for Distributed Resampling for HighSpeed Particle
Filtering", IEEE
International Symposium on Circuits and Systems (ISCAS'06),
Greece, May 2124, 2006.

I. Hosseini, M. J. Omidi, K. Kasiri, A. Sadri, P. G.
Gulak, "PAPR Reduction in OFDM Systems Using
Polynomialbased Compressing and Iterative Expanding",
ICASSP 2006, Toulouse, France, May 1419, 2006.

M. Shabany, H. Shojania, J. Zhang, J. Omidi, P. G.
Gulak, "VLSI Architecture of a Wireless Channel
Estimator Using Sequential Monte Carlo Methods", IEEE
Workshop on Signal Processing Advances in Wireless
Communications (SPAWC'05), 2005.

H. ZamiriJafarian and
P.G.Gulak, "Adaptive Channel
SVD Estimation for MIMOOFDM Systems" (Session 5B),
IEEE 61st Semiannual Vehicular Technology Conference, Stockholm, Sweden, May 30June 1,
2005.

H. ZamiriJafarian and P.G.Gulak, "Iterative MIMO
Channel SVD Estimation", IEEE International Conference
on Communications, Seoul, Korea, May 1620, 2005.

W. Gross, F. Kschischang and P. G. Gulak, "An FPGA Interpolation Engine for
SoftDecision ReedSoloman Decoding", Proceedings of
the 2004 Symposium on FieldProgrammable Custom Computing
Machines, April 2004.

D. Gnaedig, E. Boutillon, M.
Jezequel, V. Gaudet, and P. G. Gulak, "On Multiple
Slice Turbo Codes", 3rd Int. Symposium on Turbo Codes
and Related Topics, Brest, France, Sept. 2003, pp.
343346.

V. Gaudet and P. G. Gulak, "A 13.3Mbps, 0.35um CMOS Analog Turbo Decoder IC with a
Configurable Interleaver", 2003 IEEE International
SolidState Circuits Conference Digest of Technical
Papers, pp. 148149, 484, Feb. 2003.

W. Gross, F. Kschischang, R. Koetter, and P. G. Gulak, "A VLSI Architecture for
Interpolation in SoftDecision List Decoding of
ReedSolomon Codes", Proc. of the 2002 IEEE Workshop on
Signal Processing Systems, SIPS'02, San Diego, Oct.
2002, pp. 3944.

T. Fill and P. G. Gulak, "An Assessment of VLSI and Embedded Software
Implementations for Reed Solomon Decoders, IEEE Signal
Processing Systems SIPS"02, Oct. 2002, pp. 99102.

K. Pagiamtzis and P. G. Gulak, "Empirical Performance Prediction for IFFT/FFT
cores for OFDM SystemsonaChip, IEEE Midwest
Symposium on Circuits and Systems, August 2002, Vol.
1, pp. 583586.

W. Gross, F. Kschischang, R.
Koetter, and P. G. Gulak, "Simulation Results for
Algebraic SoftDecision Decoding of ReedSolomon Codes",
Proc. of the 21st Biennial Symposium on Communications,
June 2002, Queen's University, Kingston, Canada, pp.
356360.

J. Siu, Y. Eslami, A.
Sheikholeslami, P. G. Gulak, T. Endo, and S.
Kawashima, "A 16kb 1T1C FeRAM Testchip Using CurrentBased
Reference Scheme", IEEE Custom Integrated Circuit
Conference, pp. 107110, May 2002.

T. Esmailian, F.R.
Kschischang, and P. G. Gulak. "A 32Point
MultiplierFree Approximate FFT," Proceedings of the
21st Biennial Symposium on Communications, Queen's
University, June 2002, pp. 448452.

T. Esmailian, F. R.
Kschischang, and P. G. Gulak, "An InBuilding Power
Line Channel Simulator", Proceedings of the 2002
International Symposium on Power Line Communications and
its Applications, ISPLC2002, pp. 3135, March 2002,
Athens, Greece.

T. Esmailian, F.R.
Kschischang, and P. G. Gulak, "Capacity
Distribution of RadiationLimited InBuilding Power Lines", Proceedings of the 2002 International Symposium
on Power Line Communications and its Applications,
ISPLC2002, pp. 118122, March 2002, Athens, Greece.

Y. Eslami, J. Siu, A.
Sheikholeslami, P. G. Gulak, T. Endo, and S.
Kawashima, "A 2T2C FeRAM Testchip for Optimum Bitline and
Cell Capacitances", Proc. Of the 1^{st} Int'l
Meeting on Ferroelectric Random Access Memories, pp.
178179, Nov. 2001.

A. Ghazel, E. Boutillon,
J.L. Danger, P. G. Gulak, H. Laamari, "Design and
Performance Analysis of a HighSpeed AWGN Communications
Channel Emulator", 2001 IEEE Pacific Rim Conference on
Communications, Computers and Signal Processing, Aug.
2001, Volume 2, pp. 374377.

N. Sohi and P. G. Gulak,
"A MultiStandard SetTop Box Channel Decoder", IEEE
Signal Processing Systems, SIPS"00, Oct. 2000, pp.
295304.

W. Gross, V. Gaudet and
P. G. Gulak, "A VLSI Architecture for Softoutput PR4
Detection", 2000 IEEE Midwest Symposium on Circuits and Systems, August 2000, Vol. 1, pp. 416419.

Boutillon, E., Gross, W., and Gulak, G., "Gestion De La Memoire Pour
L'Algorithme Du Forward Backward", 5eme Workshop AAA
sur 'Adequation Algorithme Architecture, 2628 Jan.
2000, INRIA Rocquencourt, France.

Esmailian,
T., Gulak, G., and Kschischang, F., "A Discrete Multitone
Power Line Communications System", IEEE Int. Conference
on Acoustics, Speech, and Signal Processing, ICASSP
2000, Istanbul, Turkey, Vol. 5, pp. 29532956.

Esmailian,
T., Kschischang, F., and Gulak, G., "Simulation of a
Discrete Multitone System Over InBuilding Power Line",
20^{th} Biennial Symposium on Communications,
Queen"s University, May 2000, pp. 3236.

Esmailian,
T., Kschischang, F., and Gulak, G., "Characteristics of
InBuilding Power Lines at High Frequencies and their
Channel Capacity", Proceedings of 2000 Int. Symposium on PowerLine Communications and its Applications, pp.
5259, ISPLC 2000, Limerick, Ireland.

J. Podaima and P. G.
Gulak, "SelfTimed Fully Parallel Content Addressable
Queue for Switching Applications, CICC, pp. 239242, May 1999, paper
11.4.

A.H. Banihasherni, Frank, R.
Kschischang, P. G. Gulak, "On Tanner Graphs of
Lattices and Codes", Information Theory, Proceedings,
1998 IEEE International Symposium on, pp. 115115,
1998.

P. G. Gulak,
"A Review of MultipleValued Memory Technology", The
TwentyEighth International Symposium of MultipleValued
Logic, Fukuoka, Japan, pp. 222231, May 1998.

A. Sheikholeslami, R.
Yoshimura, and P. G. Gulak, "LookUp Tables (LUTs)
for MultipleValued, Combinational Logic", Proc. 28^{th}
Int. Symposium on MultipleValued Logic, pp. 264269,
May 1998.

J. Omidi, S. Gazor, and
P. G. Gulak, "Differential Kalman Filtering for
Tracking Rayleigh Fading Channels", 1998 IEEE Signal
Processing Workshop on Signal Processing Systems (SiPS
98), pp. 376392, April 1998.

V. Gaudet and P. G. Gulak,
"CMOS Implementation of a Current ConveyorBased
FieldProgrammable Analog Array", 31st Alsilomar
Conference, Signals, and Computers, Pacific Grove, CA,
Nov. 25, 1997.

V. Gaudet and P. G. Gulak,
"Towards a current conveyor
based Field Programmable Analog arrays", ITRC annual
retreat1997.

A. Sheikholeslami and P.
G. Gulak, "Multivalued Ferroelectric Associative
Memory Design", 6th Workshop on PostBinary ULSI
Systems, Nova Scotia, pp. 6869, May 1997.

J. Omidi, P. G. Gulak,
and S. Pasupathy, "Joint Data and Channel Estimation Using
the PerBranch Processing Method", Proceedings of the IEEE Signal Processing Workshop on Wireless
Communications, pp. 389392, April 1997.

B.J. Frey, F.R. Kschischang, and P. G. Gulak,
"Concurrent TurboDecoding", ISIT, Ulm, Germany,
June 1997.

K. Schultz and P. G.
Gulak, "ThrottledBuffer ATM Switch Output Control
Circuitry with CAMBased Multicast Support", ISSCC,
San Francisco, pp. 152153, Feb 1997.

A. Sheikholeslami, P. G.
Gulak, and T. Hanyu, "A MultipleValued Ferroelectric
ContentAddressable Memory", Proceedings, 26^{th}
International Symposium on, pp. 7479, 1996.

P. G. Gulak,
D. D'Mello, "A
Review Field
Programmable Analog Arrays", SPIE Conference, Boston, Oct 1996.

J. Omidi, P. G. Gulak
and S. Pasupathy, "Parallel Structures for Joint Channel
Estimation and Data Detection over Fading Channels", 1996
Workshop on VLSI Signal Processing, pp.325336, Oct
1996.

B. Frey, F. Kschischang and
P. G. Gulak, "Early Detection and Trellis Splicing:
Reducing Complexity of Soft Iterative Decoding", Turbo
Coding Workshop, Lund Institute of Technology, pp.
6573, Aug 1996.

J. Omidi, S. Pasupathy and
P. G. Gulak, "Joint Data and Kalman Estimation of
Fading Channels Using a Generalized Viterbi Algorithm",
1996 IEEE International Communications Conference (ICC),
Dallas, Vol. 2, pp. 11981203, June 1996.

P. G. Gulak,
"FieldProgrammable Analog Arrays: A Status Report"
(Invited Paper), 4th Canadian Workshop on Field
Programmable Devices (FPD"96), Toronto, May 1996.

P. G. Gulak, "FieldProgrammable Analog Arrays: Past, Present and
Future Perspectives" (Invited Paper), TENCON
95, Hong Kong, Nov 1995.

P. Chow, P. Chow and P. G. Gulak, "A FieldProgrammable MixedAnalogDigital Array", FPGA'95.

K. Schultz and P. G. Gulak, "Physical Performance Limits for Shared Buffer ATM Switches to the Year 2005",
International Switching Symposium (ISS), Berlin, April 1995.

E. Lee and P. G. Gulak, "A TransconductorBased Field Programmable Analog Array",
ISSCC, San Francisco, Feb. 1995.

E. Lee and
P. G. Gulak, "MOS TransconductorBased Field Programmable Analog Array",
3rd International Workshop on PostBinary ULSI Systems, Boston,May 1994.

Q. Wang and P. G. Gulak, "Design and Simulation of Data
pathOriented Reconfigurable Architectures",
ASICON, Beijing, China, Oct. 1994.

G. Feygin, P. G. Gulak and P. Chow,
"Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression",
Data Compression Conference DCC'94, Snowbird, Utah, March 1994, pp. 254263.

K. Lowe and
P. G. Gulak, A Unified Discrete Gate Sizing/Cell Library Optimization Method for Design and Analysis of Delay Minimized CMOS and BiCMOS Circuits,
EuroDAC'94, Grenoble, France, October 1994.

K. Lowe and
P. G. Gulak,
A Quick Way to Find the Optimized Performance of a Power Constrained BiCMOS Circuit,
CICC'94, May 1994.

K. Schultz and
P. G. Gulak, Fully
Parallel MultiMegabit Integrated CAM/RAM Design,IEEE International Workshop on Memory Technology, Design and Testing, Santa Clara, CA, August 1994.

K. Schultz and P. G. Gulak, The Telecom Machine: MemoryIntensive Reprogrammable Gigabit Switching,
17th Biennial Symposium on Communications, Kingston, May 1994, pp. 219222.

K. Schultz and P. G. Gulak, Distributed Multicast Contention Resolution Using Content Addressable FIFOsICC '94, April 1994, pp. 14951500.

K. Schultz and P. G. Gulak, CAMBased SingleChip Shared Buffer ATM Switch,ICC '94, April 1994, pp. 11901195.

E. Lee and P. G. Gulak,
A TransconductorBased FieldProgrammable Analog Array,
1994 ACM/SIGDA 2nd International Workshop on Field Programmable Gate Arrays, University of California, Berkeley, February 1994.

K. Schultz and P. G. Gulak,
Architecture for MultiMegabit Integrated CAM/RAM,
CCVLSI, Banff, Alberta, November 1993, pp. 6A16A7. (Best Paper Award).

K. Lowe and
P. G. Gulak,
"Gate Sizing and Buffer Insertion for Optimizing Performance in Power Constrained BiCMOS Circuits",IEEE/ACM International Conference on CAD93, Santa Clara, CA., November 7  10, 1993.

B. Herscovici and
P. G. Gulak,
"Reduced State Viterbi Receivers for Digital Mobile Communications",
Milcom '93, Boston, October 912, 1993.

Q. Wang and
P. G. Gulak, "An Array Architecture for Reconfigurable Datapaths",
Oxford Conference on Field Programmable Systems, University of Oxford, England, September 7  10, 1994.

K. Schultz and
P. G. Gulak, "A LogicEnhanced Memory for Digital Data Recovery Circuits",
ISCAS '93, Chicago, Vol. 3, pp. 20072010.

G. Feygin, P. Chow,
P. G. Gulak, J. Chappel, G. Goodes, O. Hall, A. Sayes, S. Singh, M. Smith, S. Wilton,
"A VLSI Implementation of a Cascade Viterbi Decoder with Traceback",
ISCAS '93, Chicago, Vol. 3, pp. 19451948.

G. Feygin,
P. G. Gulak and P. Chow,
Minimizing Error and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding,
IEEE Data Compression Conference, March 30April 2, 1993, Snowbird, Utah, pp. 118128.

E. Lee and
P. G. Gulak,
Dynamic CurrentMode MultiValued MOS Memory With Error Correction, International Symposium on MultipleValued Logic,
Sendai, Japan, May 1992.

S. Wood, K.C.
Smith and P. G. Gulak, Latched Differential FET Logic,
1991Int. Symposium on Circuits and Systems, Singapore, June 1991, pp. 30113014.

G. Feygin and
P. G. Gulak, Survivor Sequence Memory Management in Viterbi Decoders,
1991 Int. Symposium on Circuits and Systems, Singapore, June 1991, pp. 29672970.

G. Feygin, P. G. Gulak and P. Chow,
Generalized Cascade Viterbi Decoder  A Locally Connected Multiprocessor with Linear Speedup,
ICASSP, Toronto, May 1991, pp. 10971100.

E. Lee and
P. G. Gulak, A CMOS FieldProgrammable Analog Array,IEEE ISSCC'91, San Francisco, February 1991, pp. 186188.

J. Erfanian, S. Pasupathy,
P. G. Gulak, "Reduced Complexity Symbol Detectors with Parallel Structures",
IEEE Global Telecommunications Conference, San Diego, December 1990, pp. 704708.

S. Wood and
P. G. Gulak, "High Speed DRAMs for ASIC Memory Applications",
Canadian Conference on VLSI, Ottawa, October 1990, pp. 5.3.15.3.8.

E. Lee and
P. G. Gulak,
"Prototype Design of a FieldProgrammable Analog Array",
Canadian Conference on VLSI, Ottawa, October 1990, pp. 2.2.12.2.8.

J. Erfanian, J.
Dao, P. G. Gulak and S. Pasupathy,"
Realization of the SPS Detection Algorithm on a Parallel VLSI Architecture",
15th Biennial Symposium on Communications, Kingston, Ontario, June 1990, pp. 4144.

V.P. Roychowdhury,
P. G. Gulak, A. Montalvao and T. Kailath,
Decoding of Ratek/n Convolutional Codes in VLSI,
1987 Princeton Workshop on Algorithm, Architecture and Technology Issues for Models of Concurrent Computation, Princeton, New Jersey, Sept. 30Oct. 1, 1987, pp. 659673.

P. G. Gulak, T. Kailath, A. Montalvo and V.P. Roychowdhury,
Decoding Ratek/n Convolutional Codes in VLSI,
Fifth International Conference on Systems Engineering, Wright State University, Dayton, Ohio, Sept. 1987, pp. 8386.

P. G. Gulak, V.P. Roychowdhury, T. Kailath,
Decoding Convolutional Codes,
in VLSI
Third Joint USSRSwedish International Conference on Information Theory, Sochi, USSR, May 1987.

M. Horowitz, J.L. Hennessy, P. Chow,
P. G. Gulak, J.M. Acken, A. Agarwal, C.Y. Chu, S.A. McFarling, S.A. Przybylski, S.E. Richardson, A. Salz, R.T. Simoni, D. Stark, P.A. Steenkiste, S. Tjiang and M.J. Wing,
A 32b Microprocessor with
onchip 2Kbyte instruction cache, ISSCC 87, Feb. 1987, pp. 3032.

K.D. Mann, P. G. Gulak and E. Shwedyk,
A Shuffle Exchange Implementation of Viterbi's Algorithm using CMOS VLSI,
1985 Canadian Conference on Very Large Scale Integration, Toronto, Ontario, November 45, 1985, pp. 2225.

M. Yunik, W. Pries, R.D. McLeod, G.E. Bridges,
P. G. Gulak and H.C. Card,
Dual Systolic Architectures for Digital Signal Processing in VLSI,
1984 Canadian Conference on Very Large Scale Integration, Edmonton Alberta, October 12, 1984, pp. 6.1886.191.

P. G. Gulak, W. Pries, D. McLeod, H.C. Card,
A GateLevel CMOS Digital Logic Simulator in an EventDriven Environment,
1984 Canadian Conference on Very Large Scale Integration, Edmonton, Alberta, October 12, 1984, pp. 3.903.93.

P. G. Gulak, VLSI Structures for Digital Communication Receivers,
1984 Canadian Conference on Very Large Scale Integration, Edmonton, Alberta, October 12, 1984, pp. 1.261.29.

P. G. Gulak and E. Shwedyk, Block Detection in a Normalized Kolmogorov Metric Space,
Seventh International Conference on Pattern Recognition, Montreal, Canada, August 2, 1984, pp. 709712.

K. Dickson, P. G. Gulak, D. Smith,
PLA Generation Using a Silicon Assembler,
1983 Conference on Very Large Scale Integration, University of Waterloo, Waterloo, Ontario, Canada, October 2425, 1983, pp. 2225.

P. G. Gulak, E. Shwedyk, D. Card, Channel Capacity of a Computer Communication Channel,
Tenth Biennial Symposium on Communications, Queen's University, Kingston, Ontario, Canada, May 2830, 1980.
Patents
 D. Patel, M. Shabany, P.G. Gulak, "Signal Processing Block for a Receiver in Wireless Communication", USPTO No. 12/786,288, filed on May 24, 2010, licensed to MaxLinear Inc.
 D. Patel, M. Shabany, P.G. Gulak, "Method and System for a Lowcomplexity Softoutput MIMO Detection", USPTO No. 13/149,743, filed on May 31, 2011, licensed to MaxLinear Inc.
 C. Ling, V. Smolyakov, T. Gallagher, P.G. Gulak, "Method and Apparatus for Memory Fault Tolerance", USPTO No. 13/269,416, filed on Oct. 7, 2011, Assignee MaxLinear Inc.
 A.
Sheikholeslami, P. G. Gulak, and T. Hanyu,
"MultipleValued Ferroelectric ContentAddressable
Memory", U.S. Patent # 5,808,929, Sept. 15, 1998.
 A.
Sheikholesalmi, P. G. Gulak, and T. Hanyu,
"Nonvolatile Content Addressable Memory", U.S. Patent
#5,930,161, July 27, 1999.
 E.
Boutillon, P. G. Gulak, V. Gaudet and D. Gnaedig,
"Procede de codage et/ou de decodage de codes correcteurs
d'erreurs, dispositifs et systeme correspondants", French
patent #2838581, granted October 17, 2003
Symposia/Colloquia/Unrefereed Conferences
 P. G. Gulak, A VLSI Viterbi Decoder for Galileo (Invited presentation), Algorithms and Parallel VLSI Architectures II, Bonas, France, June 36, 1991.
 E. Lee and P. G. Gulak, A CMOS FieldProgrammable Analog Array for Signal Processing Applications, IEEE VLSI Workshop, Tampa, Florida, Feb. 17, 1990.
 P. G. Gulak, An Undergraduate Course in VLSI Systems, VLSI in Education Conference, Santa Clara, July 1989.
 G. Feygin, P. G. Gulak and F. Pollara, Survivor Sequence Memory Management in Viterbi Decoders, Proceedings of the Third Workshop on ECC, IBM Almaden Research Center, September 18 and 19, 1989.
 P. G. Gulak, VLSI Architectures for Digital Communications (Invited presentation), NATO ASI Workshop on Customized VLSI Architectures for RealTime Signal and Numerical Processing, Belgium, July 2829, 1988.
 T. Kailath, P. G. Gulak, V.P. Roychowdhury and A. Montalvo, Decoding Convolutional Codes in VLSI, 21st Annual Asilomar Conference, Monterey, CA, Oct. 1987.
 P. G. Gulak, V.P. Roychowdhury and T. Kailath, Decoding Convolutional Codes in VLSI, 1986 International Symposium on Information Theory, Ann Arbor, Michigan, October 1986.
 P. G. Gulak and T. Kailath, Locally Connected VLSI Architectures for the Viterbi Algorithm, 2nd Annual IBM Workshop in Coding Theory, IBM Almaden Research Center, San Jose, CA, Sept. 1987.
 P. G. Gulak, V.P. Roychowdhury, A. Montalvo, and T. Kailath, Decoding of Ratek/n Convolutional Codes in VLSI, International Workshop on Information Theory, Como, Italy, July 25, 1987.
 P. G. Gulak, Considerations for Concurrent Decoding of Ratek/n Convolutional Codes, 1st Annual IBM Workshop in Coding Theory, IBM Almaden Research Center, San Jose, CA, August 1986.
Technical Reports
 G. Feygin and P. G. Gulak, Survivor Sequence Memory Management in Viterbi Decoders, Technical Report CSRI252, Computer Systems Research Institute, University of Toronto, Jan. 1991, 24 pages.
 P. G. Gulak, An Undergraduate Course on VLSI Systems  Progress Report, Dept. of Electrical Engineering, University of Toronto, submitted to the Canadian Microelectronics Corporation, June 1990.
 P. G. Gulak, Studies on Convolutional Codes: Theory and Implementation, Technical Report Submitted to Rockwell International, Information Systems Laboratory, Stanford University, Dec. 1986, 86 pages.
 P. G. Gulak, Signal Name Conventions for MIPSX, MIPSX Working Paper #41, Computer Systems Laboratory, Stanford University, Sept. 1985.
 D. Burek and P. G. Gulak, A ThreeDimensional Contour Measurement System using Moire Techniques, A Technical Report Submitted to Diffracto Limited, Windsor, Ontario, 1983, 82 pages.
 D. Burek and P. G. Gulak, Design of an Image Processing Workstation, A Technical Report Submitted to Diffracto Limited, Windsor, Ontario, 1982, 112 pages.
 P. G. Gulak, The Longitudinal Magnetic Recorder as a Digital Communications Channel, A Technical Report Submitted to the Burroughs Corporation, Winnipeg, Manitoba, February 1980, 96 pages.
