Photo - Glenn Gulak   P. Glenn Gulak - Department of Electrical and Computer Engineering
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Silicon Implementations from my Research Group:

 

  • SPARC V8 RISC Microprocessor: (K. Pagiamtzis, P. G. Gulak)
  • 0.18um CMOS

  • 1KB data and instruction cache, 5-stage pipe

  • 1M+transistors

  • In cppperation with European Space Agency

 

 

 

  • 1024-Point FFT Engine for OFDM: (K. Pagiamtzis, P. G. Gulak)
  • 0.18um 6LM CMOS

  • 100 MHz clock

  • 10-stage pipeline

  • Next: 1.5Gbps for 65GHz Radio

 

 

 

  • Cryptoprocessor (ECC, AES, 3DES): (Y. Eslami, A. Sheikholeslami, P. G. Gulak)
  • 0.18um 6LM CMOS

  • Low power, reconfigurable coprocessor for smart card applications

  • ONB representation for algorithms to maximally share hardware

  • Sponsored by Fujitsu

  • Next: 1.5Gbps for 65GHz Radio

 

 

 

  • FeRAM (Fujitsu 0.35um CMOS + FERAM): (Y. Eslami, A. Sheikholeslami, P. G. Gulak)
  • 8Kbit 1T-1C

  • 8Kbit 2T-2C

  • Core Area: 1.4 mm2

  • Sponsored by Fujitsu

 

 

 

 

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