Jason H. Anderson
Dept. of Electrical and Computer Engineering
University of Toronto
Dept. of Electrical and Computer Engineering
University of Toronto
News
April 2012: Prof. Anderson receives the 2012 Gordon R. Slemon Award for Excellence in the Teaching of Design! He also receives a Departmental Teaching Award for Excellence in Undergraduate Teaching in the Fall 2011 Term!
Prof. Anderson is Program Co-Chair for the 2012 IEEE Int'l Conference on Field-Programmable Technology (FPT) to be held Seoul National University, Seoul, Korea in December. Please submit your best work for consideration -- papers are due in early June.
March 2012: Consider submitting a paper to the IEEE Int'l Conf. on Very Large Scale Integration (VLSI-SoC 2012), to be held at Santa Cruz, CA in October 2012. Papers are due April 9 see: PDF.
February 2012: Paper accepted to appear in the 2012 IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)! Congrats James, Andrew and Kevin! "Impact of cache architecture on performance and area of FPGA-based processor/parallel-accelerator systems".
December 2011: New release of LegUp -- our open source high-level synthesis tool. LegUp 2.0 incorporates many enhancements, including more sophisticated resource sharing and scheduling, as well as significant code re-factoring that will make it easier for researchers to modify and experiment with the tool.
December 2011: The 2012 International Symposium on Field-Programmable Custom Computing Machines (FCCM 2012) will be held at Toronto, Canada from April 29-May 1, 2012. Consider submiting a paper!
December 2011: Prof. Anderson is on the program committee for the 2012 Reconfigurable Architectures Workshop to be held at Shanghai, China. Please consider submitting a paper!
November 2011: Several papers accepted to upcoming conferences. Congrats to all of the students involved: Warren, Stefan, Andrew, James, Kevin, Zissis, Jason, Opal!!
Z. Poulous, T. Yang, J.H.
Anderson, A. Veneris, "Leveraging reconfigurability to raise
productivity in FPGA functional debug," to appear in the IEEE
Design Automation and Test of Europe (DATE) Conference, to be held at
Dresden, Germany, March 2012.
W. Shum, J.H. Anderson, "Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power," to appear in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, to be held at Monterey, CA, February 2012.
S. Hadjis, A. Canis, J.H. Anderson, J. Choi, K. Nam, S. Brown. T. Czajkowski, "Impact of FPGA architecture on resource sharing in high-level synthesis," to appear in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, to be held at Monterey, CA, February 2012.
J. Rose, J. Luu, K. Kent, C.-W. Yu, J.H. Anderson, O. Densmore, P. Jamieson, "The VTR project: architecture and CAD for FPGAs from Verilog to Routing," to appear in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, to be held at Monterey, CA, February 2012.
W. Shum, J.H. Anderson, "Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power," to appear in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, to be held at Monterey, CA, February 2012.
S. Hadjis, A. Canis, J.H. Anderson, J. Choi, K. Nam, S. Brown. T. Czajkowski, "Impact of FPGA architecture on resource sharing in high-level synthesis," to appear in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, to be held at Monterey, CA, February 2012.
J. Rose, J. Luu, K. Kent, C.-W. Yu, J.H. Anderson, O. Densmore, P. Jamieson, "The VTR project: architecture and CAD for FPGAs from Verilog to Routing," to appear in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, to be held at Monterey, CA, February 2012.
September 2011: ECE1387: CAD for Digital Circuit Synthesis and Layout will commence on Friday September 16, 4:30-6:30 in BA2135.
September 2011: Best paper award at FPL 2011 for "Reducing FPGA Router Run-Time Through Algorithm and Architecture". Congrats Marcel!
August 2011: Best paper nomination at FPL 2011 for "Reducing FPGA Router Run-Time Through Algorithm and Architecture". Congrats Marcel!
July 2011: Paper accepted to IEEE Transactions on Computer-Aided Design (TCAD) of Integrated Circuits and Systems. Congrats Marcel!
M. Gort, J. Anderson, "Accelerating FPGA Routing Through Parallelization and Engineering Enhancements".
June 2011: Paper accepted to the IEEE Int'l Conference on Application-specific, Systems, Architectures and Processors (ASAP) to be held at Santa Monica, CA in September 2011. This work is part of our LegUp high-level synthesis tool. Congratulations Mark!
M. Aldham, J. Anderson, S. Brown and A. Canis, "Low-Cost Hardware Profiling or Run-time and Energy in FPGA Embedded Processors".
May 2011: Two articles accepted to the IEEE FPL 2011 conference to be held at Crete, Greece in September. Great work Bill and Marcel!
M. Gort and J. Anderson, "Reducing FPGA Router Run-Time Through Algorithm and Architecture" and
B. Teng and J. Anderson, "Latch-Based Performance Optimization for FPGAs".
B. Teng and J. Anderson, "Latch-Based Performance Optimization for FPGAs".
May 2011: Prof. Anderson is the design competition co-chair for the IEEE FPT 2011 conference. Please consider participating!
May 2011: Paper accepted to the IEEE/ACM Int'l Symposium on Low Power Electronics and Design (ISLPED) to be held at Fukuoka, Japan in August 1-3, 2011. Congratulations Warren!
W. Shum and J. Anderson, "FPGA Glitch Power Analysis and Reduction".
May 2011: Prof. Anderson receives departmental teaching award for ECE 241 Digital Systems.
 | LegUp: our open source high-level synthesis framework for FPGA-based processor/accelerator systems. The first official release is planned for March 15, 2011, in conjunction with the publication of our paper in ACM FPGA 2011. Check out the website! |