Jason H. Anderson
Dept. of Electrical and Computer Engineering
University of Toronto

Publications and U.S. Patents


United States Patents:
H. Xu, V. Verma, A. Rahut, J.H. Anderson, S. Kalman, "Patterns for routing nets in a programmable logic device," US Patent #7,797,665, Issued September 2010.

J.H. Anderson, Q. Wang, "Method for technology mapping considering Boolean flexibility, " US Patent #7,725,047, Issued June 2010.

V. Verma, A. Rahut, S.K. Nag, J.H. Anderson, R. Jayaraman, "Method and apparatus for facilitating signal routing within a programmable logic device," US Patent #7,725,868, Issued May 2010.

J.H. Anderson, M. Chirania, S. Gupta, P. Costello, "Method of reducing power of a circuit," US Patent #7,653,891, Issued January 2010.

T. Jang, K. Chung, J.H. Anderson, Q. Wang and S. Gupta, "Method and apparatus for power optimization using don't care conditions of configuration bits in lookup tables," US Patent #7,603,646, Issued October 2009.

Q. Wang, R. Aggarwal and J.H. Anderson, "Processing constraints in computer-aided design for integrated circuits," US Patent #7,555,734, Issued June 2009.

J. Saunders, K. Anandh, G. Stenz, S.K. Nag and J.H. Anderson, "Unified placer infrastructure," US Patent #7,398,496, Issued July 2008.

V. Verma, A. Rahut, S.K. Nag and J.H. Anderson, “Method and apparatus for facilitating signal routing within a programmable logic device,” US Patent #7,306,977, Issued December 2007.

J.H. Anderson, S.K. Nag G. Stenz and S. Dasasathyan, "Method for application of network flow techniques under constraints," US Patent #7,143,380, Issued November 2006.

J.H. Anderson, S. Kalman and V. Verma, "Incremental routing in integrated circuit design," US Patent #7,134,112, Issued November 2006.

J.H. Anderson, S. Kalman and V. Verma, "Post-layout optimization in integrated circuit design," US Patent #7,111,268, Issued September 2006.

R. Kong and J.H. Anderson, "Method for computing and using future costing data in signal routing," US Patent #7,073,155, Issued July 2006.

J.H. Anderson and F.N. Najm, "Leakage power optimization for integrated circuits," US Patent #6,993,737, Issued January 2006.

J. Saunders, K. Anandh, G. Stenz, S.K. Nag and J.H. Anderson, "Unified placer infrastructure," US Patent #6,983,439, Issued January 2006.

G.-J. Nam, S. Kalman, J.H. Anderson, R. Jayaraman, S.K. Nag and J. Zhuang, "Method and apparatus for testing routability," US Patent #6,877,040, Issued April 2005.

J.H. Anderson, "Incremental placement of design objects in an integrated circuit design," US Patent #6,871,336, Issued March 2005.

S. Dasasathyan, G. Stenz, S.K. Nag and J.H. Anderson, "Placement of objects with partial shape restriction," US Patent #6,857,115, Issued February 2005.

R. Kong and J.H. Anderson, "Method for computing and using future costing data in signal routing," US Patent #6,851,101, Issued February 2005.

J.H. Anderson, J. Saunders, M. Chari, S. Nag and R. Jayaraman, "Method and apparatus for placement of input-output design objects into a programmable gate array," US Patent #6,625,795, Issued September 2003.

S. Nag, K. Chaudhary, J.H. Anderson, M. Chari and S. Kalman, "Method and apparatus for timing-driven implementation of a circuit design," US Patent #6,484,298, Issued November 2002.

J.H. Anderson, J. Saunders, M. Chari, S. Nag and R. Jayaraman, "Placement of input-output design objects into a programmable gate array supporting multiple voltage standards," US Patent #6,289,496, Issued September 2001.

Additional U.S. patents pending.

Refereed Conference Publications:

Z. Poulous, T. Yang, J.H. Anderson, A. Veneris, "Leveraging reconfigurability to raise productivity in FPGA functional debug," accepted to appear in the IEEE Design Automation and Test of Europe (DATE) Conference, to be held at Dresden, Germany, March 2012.

W. Shum, J.H. Anderson, "Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power," accepted to appear in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, to be held at Monterey, CA, February 2012.

S. Hadjis, A. Canis, J.H. Anderson, J. Choi, K. Nam, S. Brown. T. Czajkowski, "Impact of FPGA architecture on resource sharing in high-level synthesis," accepted to appear in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, to be held at Monterey, CA, February 2012.

J. Rose, J. Luu, K. Kent, C.-W. Yu, J.H. Anderson, O. Densmore, P. Jamieson, "The VTR project: architecture and CAD for FPGAs from Verilog to Routing," accepted to appear in the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, to be held at Monterey, CA, February 2012.

M. Aldham, J.H. Anderson, S. Brown, A. Canis, "Low-cost hardware profiling of run-time and energy in FPGA embedded processors," IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Santa Monica, CA, September 2011.  (PDF)

B. Teng, J.H. Anderson, "Latch-based performance optimization for FPGAs,"IEEE International Conference on Field Programmable Logic and Applications (FPL), pp. 58-63, Crete, Greece, September 2011. (PDF)

M. Gort, J.H. Anderson, "Reducing FPGA router run-time through algorithm and architecture," IEEE International Conference on Field Programmable Logic and Applications (FPL), pp. 336-342, Crete, Greece, September 2011. (PDF)  (best paper award!)

W. Shum, J.H. Anderson, "FPGA glitch power analysis and reduction," IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 27-32, Fukuoka, Japan, August 2011. (PDF)

A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J.H. Anderson, S. Brown, T. Czajkowski, "LegUp: High-level synthesis for FPGA-based processor/accelerator systems,"ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 33-36, Monterey, CA, February 2011. (PDF)

J. Luu, J.H. Anderson, J. Rose, "Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA),  pp. 227-236, Monterey, CA, February 2011. (PDF)

J.H. Anderson, Q. Wang, "Area-efficient FPGA logic elements: architecture and synthesis,"  IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 369-375, Yokohama, Japan, January 2011.  (best paper nomination!)  (PDF)

A. Rakhshanfar, J.H. Anderson, "An integer programming placement approach for FPGA clock power reduction,"  IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 831-836, Yokohama, Japan, January 2011.  (PDF)

M. Gort, J.H. Anderson, "Deterministic multi-core parallel routing for FPGAs," IEEE International Conference on Field Programmable Technology (FPT), pp. 78-86, Beijing, China, 2010. (PDF)

S. Birk, J.G. Steffan, J.H. Anderson, "Parallelizing FPGA placement using transactional memory," IEEE International Conference on Field Programmable Technology (FPT), pp. 61-69, Beijing, China, 2010. (PDF)  (best paper award!)

J.H. Anderson, C. Ravishankar, "FPGA power reduction by guarded evaluation," ACM/SIGDA International Conference on Field Programmable Gate Arrays (FPGA), pp. 157-166, Monterey, CA, 2010. (PDF)

J.H. Anderson, "A PUF design for secure FPGA-based embedded systems," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 1-6, Taipei, Taiwan, 2010.  (PDF)  (VHDL download)

J.H. Anderson, Q. Wang, "Improving logic density through synthesis-inspired architecture," IEEE International Conference on Field-Programmable Logic and Applications (FPL), pp. 105-111, Prague, Czech Republic, 2009. (PDF)

S. Huda, M. Mallick, J.H. Anderson, "Clock gating architectures for FPGA power reduction,"  IEEE International Conference on Field-Programmable Logic and Applications (FPL), pp. 112-118, Prague, Czech Republic, 2009. (PDF)

Q. Wang, S. Gupta, J.H. Anderson, "Clock power reduction for Virtex-5 FPGAs" ACM/SIGDA International Conference on Field Programmable Gate Arrays (FPGA), pp. 13-22, Monterey, CA, February, 2009. (PDF)  

T. Ahmed, P. Kundarewich, J.H. Anderson, B. Taylor, R. Aggarwal, "Architecture-specific packing for Virtex-5 FPGAs," pp. 5-13, ACM/SIGDA International Conference on Field Programmable Gate Arrays (FPGA), Monterey, CA, February, 2008. (PDF)

S. Gupta, J.H. Anderson, L. Farragher and Q. Wang, "CAD techniques for power optimization in Virtex-5 FPGAs," IEEE Custom Integrated Circuits Conference (CICC), pp. 85-88, San Jose, CA, 2007. (PDF)

J.H. Anderson and F.N. Najm, "Low-power programmable routing circuitry for FPGAs," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 602-609, San Jose, CA, 2004. (PDF)

J.H. Anderson and F.N. Najm, "A novel low-power FPGA routing switch," IEEE Custom Integrated Circuits Conference (CICC), pp. 719-722, Orlando, FL, 2004. (PDF)

J.H. Anderson, S. Nag, K. Chaudhary, S Kalman, C. Madabhushi and P. Cheng, "Run-time-conscious automatic timing-driven FPGA layout synthesis," International Conference on Field-Programmable Logic and Applications (FPL), pp. 168-178, Antwerp, Belgium, 2004. (PDF)

J.H. Anderson, F.N. Najm and T. Tuan, "Active leakage power optimization for FPGAs," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 33-41, Monterey, CA, 2004.

J.H. Anderson and F.N. Najm, "Interconnect capacitance estimation for FPGAs," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 713-718, Yokohama, Japan, 2004.

J.H. Anderson and F.N. Najm, "Switching activity analysis and pre-layout activity prediction for FPGAs," ACM/IEEE International Workshop on System-Level Interconnect Prediction (SLIP), pp. 15-21, Monterey, CA, 2003.

J.H. Anderson and F.N. Najm, "Power-aware technology mapping for LUT-based FPGAs," IEEE International Conference on Field-Programmable Technology (FPT), pp. 211-218, Hong Kong, 2002. (PDF)

J.H. Anderson, J. Saunders, S. Nag, C. Madabhushi and R. Jayaraman, "A placement algorithm for FPGA designs with multiple I/O standards," International Conference on Field-Programmable Logic and Applications (FPL), LNCS 1896, Springer-Verlag, pp. 211-220, Villach, Austria, 2000. (PDF)

J.H. Anderson and S.D. Brown, "Technology mapping for large complex PLDs," ACM/IEEE Design Automation Conference (DAC), pp. 698-703, San Francisco, CA, 1998. (PDF)

J.H. Anderson and S.D. Brown, "An LPGA with foldable logic blocks," ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 244-252, Monterey, CA, 1998. (PDF)
Refereed Journal Publications:

C. Ravishankar, J.H. Anderson, A. Kennings, "FPGA power reduction by guarded evaluation considering logic architecture," submitted to IEEE Transactions on Computer Aided Design for Integrated Circuits and Systems (TCAD), November 2011. (14 page manuscript)

M. Gort, J.H. Anderson, "A combined architecture/algorithm approach to fast FPGA routing," submitted to IEEE Transactions on Very Large Scale Integration (VLSI) Systems, November 2011.

A. Canis, J. Choi, M. Aldham, V. Zhang, A. Kammoona, J.H. Anderson, S. Brown, T. Czajkowski, "LegUp: Open source high-level synthesis for FPGA-based processor/accelerator systems", submitted to ACM Transactions on Embedded Computing Systems (TECS), February 2011. (25 page manuscript in revision)

M. Gort, J.H. Anderson, "Accelerating FPGA routing through parallelization and engineering enhancements", accepted to appear in IEEE Transactions on Computer Aided Design for Integrated Circuits and Systems (TCAD), July 2011. (14 pages).

J. Anderson, Q. Wang, C. Ravishankar, "Raising FPGA logic density through synthesis-inspired architecture," accepted to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, November 2010 (14 pages).  (PDF)

T. Ahmed, P.D. Kundarewich,J.H. Anderson, "Packing techniques for Virtex-5 FPGAs," ACM Transactions on Reconfigurable Technology and Systems (TRETS), Vol 2, No. 3, September 2009. (PDF)

J.H. Anderson and F.N. Najm, "Low-power programmable FPGA routing circuitry," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 8, pp. 1048-1060, 2009. (PDF)

J.H. Anderson and F.N. Najm, "Active leakage power optimization for FPGAs," IEEE Transactions on Computer-Aided Design for Integrated Circuits and Systems (TCAD), Vol. 25, No. 3, pp. 423-437, March 2006. (PDF)

J.H. Anderson and F.N. Najm, "Power estimation techniques for FPGAs," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 10, pp. 1015-1027, October 2004. (PDF)

Magazine Articles:

S. Gupta and J. Anderson, "Optimizing FPGA power with ISE design tools," Issue 60, Second Quarter 2007, pp. 16-19.

Dissertation:

J.H. Anderson, "Power optimization and prediction techniques for FPGAs," Ph.D. Thesis, Department of Electrical and Computer Engineering, University of Toronto, 2005.  (PDF)