Design Tradeoffs for Hard and Soft FPGA-based Networks-on-Chip

Mahamed Abdelfattah and Vaughn Betz

University of Toronto

November, 2012

Abstract: Incorporating Networks-on-Chip (NoC) within FPGAs has the
potential not only to improve the efficiency of the interconnect, but also
to increase designer productivity and  reduce compile time by raising the
abstraction level of communication. By comparing NoC components on FPGAs
and ASICs we quantify the efficiency gap between the two platforms and use
the results to understand the design tradeoffs in that space. We show that
this hard router can be integrated with the soft FPGA interconnect, and
still achieve an area improvement of 22X . A 64-node NoC of hard routers
with soft interconnect utilizes area equivalent to 1.6% of the logic
modules in the latest FPGAs, compared to 33% for a soft NoC.