Mohamed Abdelfattah
University of Toronto
Feb 2014
Integrating networks-on-chip (NoCs) on FPGAs can improve device scalability and facilitate design by abstracting communication and simplifying timing closure, not only between modules in the FPGA fabric but also with large “hard” blocks such as high-speed I/O interfaces. We propose mixed and hard NoCs that add less than 1% area to large FPGAs and run 5-6x faster than the soft NoC equivalent. We then compare the efficiency of embedded NoCs to current application-tailored interconnects. We find that, depending on design choices, hard NoCs consume 4.5-10.4 mJ of energy per GB of data transferred. Surprisingly, this is comparable to the energy efficiency of the simplest traditional interconnect on an FPGA – soft point-to-point links require 4.7 mJ/GB. When compared against custom buses configured into the fabric by commercial system integration tools, embedded NoCs are always more energy efficient, and for most systems they save area as well.