ECE 241 F - Digital Systems Fall 2006 21-Aug-06
Lecture and Lab and Project Schedule
Lect # Monday Date of Week Contents Text Chapter Lab
1 4-Sep Motivation - how this course fits into other ECE courses, Moore's Law/Transistor Exponential Progres & course outline;
Handouts: basic, lab schedule, lab, CAD software, project
1 No Lab
2 11-Sep light switches as logic functions, Variables & Functions,
truth tables; gates; basic AND/ORNOT gates
2.1 - 2.4 No Lab
3 simple boolean expressions; sum of products form,
simple synthesis of logic - from truth tables;†† time-varying signals (timing diagram);
2.4, 2.6, 2.7
4 Lab 1 Discussion; including good practice in labs - bottom up design, careful testing
Voltage, Transistor switch, 7400 seriesBoolean Algebgra, axioms,laws;
3.5.1, 2.5
5 18-Sep Sum of products representation & minterms; product-of-sums & maxterms;
simple algebraic minimization; example;
2.6, 4.1 Lab 1 - Combinational Logic, TTL, Protoboard
6 basic multiplexor; How FPGAs are made 2.8.2, 3.6.5, 10
7 Lab 2 Discussion: Intro to CAD; Intro to Verilog HDL language
Quartus demo;incl Logic Analyzer;
2.9-2.10
8 25-Sep Making circuits better: Optimization 1: 2, 3 & 4 variable Karnaugh maps 4.1 Lab 2 - Introduction to CAD and Quartus Tutorial & Logic Analyzer
9 Optimization 2 - product of sums,
Donít cares
4.3, 4.4
10 Optimization 3 - optimization strategy& 7 segment example
LAB #3 discussion
4.2, 6.4
11 2-Oct Sequential Logic; defn of comb. vs seq
cross-coupled NOR latch
Transparency, RS Latch, D Latch,
timing diagram; desire for edge trig;††
7.1-7.3 Lab 3 - 7 Segment Display and Hierarchical Design
12 master-slave D-type flip flop, timing diagram,
set up & hold time of FF; clock-to-Q;
7.3.1, 7.4
13 Serial Transmission of Data - shift registers, parallel to serial conversion; 7.8
14 9-Oct Coding Registers in Verilog ; 7.8 Midterm!No Lab
15 Registers/Counters
Ripple Counters
Synchronous Counter; BCD Counter;Discuss LAB #4
7.9-7.11
16 Number Representation and Signed Number Representation 5.1-5.2
17 16-Oct Numbers/Arithmetic Representation
Adder - using basic logic, Full Adder, ripple carry adder
5.1-5.2 Lab 4 - Sequential Logic
18 2ís complement addition and Subtraction - Lab 5 Discussion; include LPMs - demo 5.2-5.3
19 State Machine 1
intro; simple recognizer, steps-state diagram
method #1 - 1 one encoding direct method
8.1
20 23-Oct State Machine 2
method #2 - full encoding, State Trans Table, K-map etc.
8.2 Lab 5 - Adders and Registers
21 State Machine 3
Lab 6 discussion - state machine for sequence recognition and control of simple adder unit; LPMs,handshaking big FSMs, FSM review
8.4-8.5
22 Verilog coding of state machines, Project discussion 8.4
23 30-Oct General form of Moore Machine,Example State Machine design ,††   Lab 6 - Finite State Machines and Handshaking;Project will need "uniqueness" signoff this week
24 Introduction to memory (just how to interface to it) 10.1.3
25 Lab 7 Discussion - Hardware of displays, how to interface to to VGA controller for Lab 7  
26 6-Nov RAM - Static RAM; LPMs for SRAM
RAM as organized inside Cyclone FPGA; How to use RAM
10.1.3 Lab 7
VGA Display - Complex State Machine;Project will need "scope" signoff this week
27 Internal working of SRAM - bit, row, column
deocder (for address bus)
tristate gate (for data bus)
10.1.4
28 Debouncing switches
different methods - Debouncing switches
10.3.4
29 13-Nov NMOS transistor,NMOS &CMOS gates - build using transistors 3.2, 3.3 ECE 241/298 Project Period 1
30 transistor operation at process level
real propagation delay, waveform
fanout dependency
3.8.1 - 3.8.5
31 Gate Delay; critical path, maximum clock frequency; hold time violations
Flip flop timing - setup and hold, clock to Q, Demo Quartus Timing Analyzer
7.3.1,5.4
32 20-Nov Reading delays from data sheets
Ring Oscillator
Pg. 438, prob 7.31 ECE 241/298 Project Period 2
33 Fast Addition: Carry-Lookahead Adder 5.4
34 Carry Lookahead Addition, cont'd, Bit Serial Adder 5.4
35 27-Nov Extra time as buffer   ECE 241/298 Project Period 3
36 Multiplexors, Multiplexors as Logic; Lookup Tables (LUTs) and LUT Mapping 6.1, 6.2
37 Shannon's Expansion Theorem; Course Summary, Exam Discussion 6.1