This project consists of 2 sub-projects to
be designed in TSMC 0.18um CMOS at 1.8V power supply.
If you make use of resistors, assume they are ideal
except that the absolute tolerance is +/-15% about the
nominal value.
To get access to the TSMC 0.18um spice models, see:
0.18um spice access
for details on registering with CMC and obtaining
NDAs for CMOSP18. (You have to be on a UofT server).
Please give Jaro (jaro@vrg) the
NDA after you have done the CMC registration and Jaro
will fax it to CMC.
1) Automatic on-chip termination
Design a circuit for on-chip termination of 50 ohms to VDDA.
Assume a bandgap is present on the chip that gives a 1V output
referenced to ground. Use an off-chip resistor of 500 ohms. Assume
a parasitic capacitance of 5pF exists in parallel with the off-chip
resistor. Show the variation in termination resistance over
process, temperature (0 to 125 degrees C) and voltage (1.6V to 2.0V).
Also show the variation in resistance
for a nominal process, temp=50 voltage = 1.8V over the signal level
across the termination of 0 to 500mV. Try to keep variations low.
2) A serial mux with a delay-locked-loop for a 10GB/s system
Assume a 2.5GHz differential clock (400mV peak swing)
with a 50% duty cycle is available. From it, use
a delay-locked-loop to generate 4 clock phases: 0, 90,
180 and 270 degrees). With these 4 clock phases,
multiplex 4 logic signals (full-rail swings) each synchonized at 2.5GHz
to a single serial 10Gb/s signal. Show the resulting jitter
with power supply noise of 200mVpp at various frequencies.
You can do the design assuming a nominal process at
temperature of 50 degrees C and 1.8V power supply (you don't have to vary
process, temp and power supply for this sub-project).
Updated Sept. 22, 2001.