Kevin E. Murray
I am a PhD candidate in the Department of Electrical and Computer Engineering at the Univeristy of Toronto.
I completed a BASc in Engineering Science at the University of Toronto in 2012, and an MASc in 2014.
For 16 months I was an intern at Advanced Micro Devices (AMD) in Sunnyvale California, where I worked on
design flows and methodologies for Static Timing Analysis and developed custom floorplan optimization tools.
My current research interests include CAD algorithms and design methodologies for digital circuits. I'm interested
in elastic circuit design techniques, such as latency insensitive design, that relax the synchronous assumption
governing conventional digital circuits. In particular, I'm interested in investigating what impact these techniques
would have on FPGA CAD tools, and what new avenues for design optimization they enable.
- K. E. Murray, A. Suardi, V. Betz, G. Constantinides, "Quantifying Error: Extending Static Timing Analysis with Probabilistic Transitions", To appear in Design, Automation & Test in Europe (DATE), 2017, 1-6. [Acceptance rate: 24%] (pdf)
- K. E. Murray, and V. Betz, "Hetris: Adaptive Floorplanning for Heterogeneous FPGAs", IEEE Int. Conf. on Field-Programmable Technology, 2015, 1-8. [Acceptance rate: 22%] (pdf)
- K. E. Murray, S. Whitty, S. Liu, J. Luu and V. Betz, "Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap Between Academic and Commercial CAD", ACM Trans. Reconfig. Technol. Syst., April 2015, pp. 10:1 - 10:18. (pdf)
- K. E. Murray and V. Betz, "Quantifying the Cost and Benefit of Latency Insensitive Communication on FPGAs", ACM/SIGDA Int. Symp. on Field-Programmable Gate Arrays, 2014, 223-232. [Acceptance rate: 18%] (pdf)
- K. E. Murray, S. Whitty, S. Liu, J. Luu and V. Betz, "Titan: Enabling Large and Complex Benchmarks in Academic CAD", IEEE Int. Conf. on Field-Programmable Logic and Applications, 2013, 1-8. [Acceptance rate: 23%, Nominated for FPL Community Award] (pdf)
- K. E. Murray, S. Whitty, S. Liu, J. Luu and V. Betz, "From Quartus To VPR: Converting HDL to BLIF with the Titan Flow", IEEE Int. Conf. on Field-Programmable Logic and Applications, 2013, 1-1. [Demo Night Paper] (pdf)
Benchmark, Software and Hardware Releases
Email: k m u r r a y (AT) eecg (DOT) utoronto (DOT) ca [delete spaces and use real @ and .]
Office: D. L. Pratt, Room 372 (PT372)
Dept. of Electrical and Computer Engineering
University of Toronto
10 King's College Road
Toronto, ON, Canada