Quantifying the Cost and Benefit of Latency Insensitive Communication on FPGAs

Latency insensitive communication offers many potential benefits for FPGA designs, including easier timing closure by enabling automatic pipelining, and easier interfacing with embedded NoCs. However, it is important to understand the costs and trade-offs associated with any new design style. This paper presents optimized implementations of latency insensitive communication building blocks, quantifies their overheads in terms of area and frequency, and provides guidance to designers on how to generate high-speed and area-efficient latency insensitive systems.

FPGA 2014 Paper

K. E. Murray and V. Betz, "Quantifying the Cost and Benefit of Latency Insensitive Communication on FPGAs", ACM/SIGDA Int. Symp. on Field Programmable Gate Arrays, 2014, 223-232. (pdf)

Latency Insensitive (LI) Shell Generator and Components

The release includes:

• Parameterized System Verilog components for LI systems
• Scripts to automatically generate a LI shell from a verilog module

The release file is in tar.gz format, it can be extracted on a linux command line as follows: tar -xzvf filename.tar.gz

Version 0.1.0: March 3, 2014

• Initial Release

None