Bibliography
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- [1]
- K. V.
Aadithya, A. Demir, S. Venugopalan, and J. Roychowdhury.
Accurate prediction of random telegraph noise effects in srams and drams.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):73-86, January 2013.
- [2]
- K. V.
Aadithya, E. Keiter, and T. Mei.
DAGSENS: directed acyclic graph based direct and adjoint transient
sensitivity analysis for event-driven objective functions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 155-162, Irvine CA, November 13-16 2017.
- [3]
- K. Aadithya
and J. Roychowdhury.
Dae2fsm: automatic generation of accurate discrete-time logical abstractions
for continuous-time circuit dynamics.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
311-316, San Francisco, CA, June 3-7 2012.
- [4]
- J. Aarestad,
C. Lamech, J. Plusquellic, D. Acharyya, and K. Agarwal.
Characterizing within-die and die-to-die delay variations introduced by process
variations and SOI history effect.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
534-539, San Diego, CA, June 5-9 2011.
- [5]
- C. Ababei and
K. Bazargan.
Placement method targeting predictability robustness and performance.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 81-85, San Jose, CA, November 9-13 2003.
- [6]
- W. Abadeer and
W. Ellis.
Behavior of NBTI under AC dynamic circuit conditions.
In International Reliability Physics Symposium (IRPS), pages 17-22,
Dallas, TX, March 30-April 4 2003.
- [7]
- A. Abbasinasab and M. Marek-Sadowska.
Blech effect in interconnects: applications and design guidelines.
In ACM International Symposium on Physical Design 2015, pages
111-118, Monterey, California, March 29 - April 1 2015.
- [8]
- S. Abbaspour, M. Pedram, A. Ajami, and C. Kashyap.
Fast interconnect and gate timing analysis for performance optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(12):1383-1388, December 2006.
- [9]
- S. Abbaspour, R. Banerji, P. Feldmann, and D. D. Ling.
Efficient variational interconnect modeling for statistical timing analysis by
combined sensitivity analysis and model-order reduction.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 86-91, Austin, Texas,
February 26-27 2007.
- [10]
- S. Abbaspour, H. Fatemi, and M. Pedram.
Parametrized non-gaussian variational gate timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(8):1495-1508, August 2007.
- [11]
- R. A. Abdallah
and N. R. Shanbhag.
Reducing energy at the minimum energy operating point via statistical error
compensation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(6):1328-1337, June 2014.
- [12]
- S. Abdel-Hafeez and A. Gordon-Ross.
A digital CMOS parallel counter architecture based on state look-ahead logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(6):1023-1033, June 2011.
- [13]
- R. Abdel-Khalek and V. Bertacco.
Functional post-silicon diagnosis and debug for networks-on-chip.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 557-563, San Jose, CA, November 5-8 2012.
- [14]
- A. Abdollahi, F. Fallah, and M. Pedram.
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 213-218, Monterey, California, August 12-14 2002.
- [15]
- A. Abdollahi, F. Fallah, and M. Pedram.
Leakage current reduction in sequential circuits by modifying the scan chains.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 49-54, San Jose, CA, March 24-26 2003.
- [16]
- A. Abdollahi, F. Fallah, and M. Pedram.
Leakage current reduction in CMOS VLSI circuits by input vector control.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(2):140-154, February 2004.
- [17]
- A. Abdollahi, F. Fallah, and M. Pedram.
An effective power mode transition technique in MTCMOS circuits.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 37-42,
Anaheim, CA, June 13-17 2005.
- [18]
- A. Abdollahi and
M. Pedram.
A new canonical form for fast boolean matching in logic synthesis and
verification.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
379-384, Anaheim, CA, June 13-17 2005.
- [19]
- A. Abdollahi.
Probabilistic decision diagrams for exact probabilistic analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 266-272, San Jose, CA, November 5-8 2007.
- [20]
- A. Abel and J. Reineke.
MEMIN: SAT-based exact minimization of incompletely specified mealy
machines.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 94-101, Austin, TX, November 2-6 2015.
- [21]
- Abhishek and F. N.
Najm.
Incremental power grid verification.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
151-156, San Francisco, CA, June 3-7 2012.
- [22]
- H. Abou-Kandil, G. Freiling, V. Ionescu, and G. Jank.
Matrix Riccati Equations in Control and Systems Theory.
Birkhauser Verlag, Berlin, 2003.
- [23]
- A. I.
Abou-Seido, B. Nowak, and C. Chu.
Fitted elmore delay: a simple and accurate interconnect delay model.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(7):691-696, July 2004.
- [24]
- J. A. Abraham and
W. K. Fuchs.
Fault and error models for VLSI.
In Proceedings of the IEEE, pages 639-654, May 1986.
- [25]
- J. A. Abraham and H-C.
Shih.
Testing of MOS VLSI circuits.
In International Symposium on Circuits and Systems, Kyoto, Japan, June
5-7 1985.
- [26]
- J. Abraham.
Power calculation and modeling in deep submicron.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 124-126, Monterey, CA, August 10-12 1998.
- [27]
- M. Abramovici, M. A. Breuer, and A. D. Friedman.
Digital Systems Testing and Testable Design.
Computer Science Press, New York, NY, 1990.
- [28]
- H. Abrishami, S. Hatami, and M. Pedram.
Design and multicorner optimization of the energy-delay product of CMOS
flip-flops under the negative bias temperature instability effect.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):869-881, June 2013.
- [29]
- M. H.
Abu-Rahma, K. Chowdhury, J. Wang, Z. Chen, S.-S. Yoon, and M. Anis.
A methodology for statistical estimation of read access yield in srams.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
205-210, Anaheim, CA, June 8-13 2008.
- [30]
- M. H.
Abu-Rahma, M. Anis, and S.-S. Yoon.
Reducing SRAM power using fine-grained wordline pulsewidth control.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(3):356-364, March 2010.
- [31]
- M. H. Abu-Rahma and
M. Anis.
A statistical design-oriented delay variation model accounting for within-die
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(11):1983-1995, November 2008.
- [32]
- Y. Abulafia and
A. Kornfeld.
Estimation of FMAX and ISB in microprocessors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(10):1205-1209, October 2005.
- [33]
- M. Abusultan and
S. P. Khatri.
A flash-based digital circuit design flow.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [34]
- E. Acar, S. Nassif,
Y. Liu, and L. T. Pileggi.
Assessment of true worst case circuit performance under interconnect parameter
variations.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 431-436, San Jose, CA, March 26-28 2001.
- [35]
- E. Acar, F. Dartu,
and L. Pileggi.
TETA: Transistor-level waveform evaluation for timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(5):605-616, May 2002.
- [36]
- E. Acar,
S. Nassif, Y. Liu, and L. T. Pileggi.
Time-domain simulation of variational interconnect models.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 419-424, San Jose, CA, March 18-21 2002.
- [37]
- E. Acar, A. Devgan,
R. Rao, F. Liu, H. Su, S. Nassif, and J. Burns.
Leakage and leakage sensitivity computation for combinational circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 96-99, Seoul, Korea, August 25-27 2003.
- [38]
- V. Acary,
O. Bonnefon, and B. Brogliato.
Time-stepping numerical simulation of switched circuits within the nonsmooth
dynamical systems approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(7):1042-1055, July 2010.
- [39]
- G. Acciani,
D. Congedo, and B. Dilecce.
Improving the computational efficiency of the tree relaxation method for an
iterative solution of linear circuit equations.
IEEE Transactions on Computer-Aided Design, 10(5):668-670, May
1991.
- [40]
- R. Achar, M. S.
Nakhla, H. S. Dhindsa, A. R. Sridhar, D. Paul, and N. M. Nakhla.
Parallel and scalable transient simulator for power grids via waveform
relaxation (PTS-PWR).
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(2):319-332, February 2011.
- [41]
- B. D. Ackland and
R. A. Clark.
Event-EMU : an event driven timing simulator for MOS VLSI circuits.
In IEEE International Conference on Computer-Aided Design, pages
80-83, 1989.
- [42]
- B. Ackland and
C. Nicol.
High performance dsps - what's hot and what's not?
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 1-6, Monterey, CA, August 10-12 1998.
- [43]
- T. Addabbo,
A. Fort, L. Kocarev, S. Rocchi, and V. Vignoli.
Pseudo-chaotic lossy compressors for true random number generation.
IEEE Transactions on Circuits and Systems, 58(8):1897-1909, August
2011.
- [44]
- A. Adir, A. Nahir,
G. Shurek, A. Ziv, C. Meissner, and J. Schumann.
Leveraging pre-silicon verification resources for the post-silicon validation
of the IBM power7 processor.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
569-574, San Diego, CA, June 5-9 2011.
- [45]
- D. Adler.
SIMMOS: a multiple-delay switch-level simulator.
In 23rd ACM/IEEE Design Automation Conference, pages 159-163, Las
Vegas, NV, June 29 - July 2 1986.
- [46]
- D. Adler.
A dynamically-directed switch model for MOS logic simulation.
In 25th ACM/IEEE Design Automation Conference, pages 506-511,
Anaheim, CA, June 12-15 1988.
- [47]
- D. Adler.
Switch-level simulation using dynamic graph algorithms.
IEEE Transactions on Computer-Aided Design, 10(3):346-355, March
1991.
- [48]
- A. Agarwal,
D. Blaauw, and V. Zolotov.
Statistical clock skew analysis considering intra-die process variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 914-921, San Jose, CA, November 9-13 2003.
- [49]
- A. Agarwal,
D. Blaauw, and V. Zolotov.
Statistical timing analysis for intra-die process variations with spatial
correlations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 900-907, San Jose, CA, November 9-13 2003.
- [50]
- A. Agarwal,
D. Blaauw, V. Zolotov, and S. Vrudhula.
Computation and refinement of statistical bounds on circuit delay.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
348-353, Anaheim, CA, June 2-6 2003.
- [51]
- A. Agarwal,
V. Zolotov, and D. T. Blaauw.
Statistical timing analysis using bounds and selective enumeration.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(9):1243-1260, September 2003.
- [52]
- K. Agarwal,
D. Sylvester, and D. Blaauw.
An effective capacitance based driver output model for on-chip RLC
interconnects.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
376-381, Anaheim, CA, June 2-6 2003.
- [53]
- K. Agarwal,
D. Sylvester, and D. Blaauw.
Simple metrics for slew rate of RC circuits based on two circuit moments.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
950-953, Anaheim, CA, June 2-6 2003.
- [54]
- A. Agarwal,
F. Dartu, and D. Blaauw.
Statistical gate delay model considering multiple input switching.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
658-663, San Diego, CA, June 7-11 2004.
- [55]
- A. Agarwal,
C.-H. Kim, S. Mukhopadhyay, and K. Roy.
Leakage in nano-scale technologies: mechanisms, impact and design
considerations.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 6-11,
San Diego, CA, June 7-11 2004.
- [56]
- A. Agarwal,
V. Zolotov, and D. T. Blaauw.
Statistical clock skew analysis considering intradie-process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1231-1242, August 2004.
- [57]
- K. Agarwal,
D. Sylvester, and D. Blaauw.
A library compatible driver output model for on-chip RLC transmission lines.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):128-136, January 2004.
- [58]
- K. Agarwal,
D. Sylvester, and D. Blaauw.
A simple metric for slew rate of RC circuits based on two circuit moments.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1346-1354, September 2004.
- [59]
- K. Agarwal,
D. Sylvester, D. Blaauw, F. Liu, S. Nassif, and S. Vrudhula.
Variational delay metrics for interconnect timing analysis.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
381-384, San Diego, CA, June 7-11 2004.
- [60]
- A. Agarwal,
K. Chopra, D. Blaauw, and V. Zolotov.
Circuit optimization using statistical static timing analysis.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
321-324, Anaheim, CA, June 13-17 2005.
- [61]
- A. Agarwal,
K. Kang, S. K. Bhunia, J. D. Gallagher, and K. Roy.
Effectiveness of low power dual-vt designs in nano-scale technologies under
process parameter variations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 14-19, San Diego, CA, August 8-10 2005.
- [62]
- A. Agarwal,
K. Kang, and K. Roy.
Accurate estimation and modeling of total chip leakage considering inter- &
intra-die process variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 736-741, San Jose, CA, November 6-10 2005.
- [63]
- K. Agarwal,
M. Agarwal, D. Sylvester, and D. Blaauw.
Statistical interconnect metrics for physical-design optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1273-1288, July 2006.
- [64]
- K. Agarwal,
D. Sylvester, and D. Blaauw.
Modeling and analysis of crosstalk noise in coupled RLC interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):892-901, May 2006.
- [65]
- K. Agarwal,
R. Rao, D. Sylvester, and R. Brown.
Parametric yield analysis and optimization in leakage dominated technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(6):613-623, June 2007.
- [66]
- M. Agarwal,
B. C. Paul, M. Zhang, and S. Mitra.
Circuit failure prediction and its application to transistor aging.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 98-105, Austin, Texas,
February 26-27 2007.
- [67]
- M. Agarwal,
V. Balakrishnan, A. Bhuyan, K. Kim, M. Mizuno, B. C. Paul, W. Wang, Y. Cao,
and S. Mitra.
Optimized circuit failure prediction for aging: practicality and promise.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 116-119, Monterey, CA,
February 25-26 2008.
- [68]
- K. Agarwal,
D. Acharyya, and J. Plusquellic.
Characterizing within-die variation from multiple supply port IDDQ
measurements.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 418-424, San Jose, CA, November 2-5 2009.
- [69]
- A. Agarwal and
M. Levy.
The KILL rule for multicore.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
750-753, San Diego, CA, June 4-8 2007.
- [70]
- K. Agarwal and F. Liu.
Efficient computation of current flow in signal wires for reliability analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 741-746, San Jose, CA, November 5-8 2007.
- [71]
- K. Agarwal and
S. Nassif.
Statistical analysis of SRAM cell stability.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 57-62,
San Francisco, CA, July 24-28 2006.
- [72]
- K. Agarwal and
S. Nassif.
Characterizing process variation in nanometer CMOS.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
396-399, San Diego, CA, June 4-8 2007.
- [73]
- K. Agarwal and
S. Nassif.
The impact of random device variation on SRAM cell stability in sub-90nm
CMOS technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(1):86-97, January 2008.
- [74]
- A. Agarwal and K. Roy.
A noise tolerant cache design to reduce gate and sub-threshold leakage in the
nanometer regime.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 18-21, Seoul, Korea, August 25-27 2003.
- [75]
- A. Agarwal and
R. Vermuri.
Hierarchical performance macromodels of feasible regions for synthesis of
analog and RF circuits.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 430-436, San Jose, CA, November 6-10 2005.
- [76]
- B. N.
Agarwala, M. J. Attardo, and P. Ingraham.
Dependence of electromigration-induced failure time on length and width of
aluminum thin-film conductors.
Journal of Applied Physics, 41(10):3954-3960, September 1970.
- [77]
- R. Aggrawal,
R. Murgai, and M. Fujita.
Speeding up technology-independent timing optimization by network partitioning.
In IEEE/ACM International Conference on Computer-Aided Design, pages
83-90, San Jose, CA, November 9-13 1997.
- [78]
- Y. Aghaghiri, F. Fallah, and M. Pedram.
Irredundant address bus encoding for low power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 182-187, Huntington Beach, California, August 6-7
2001.
- [79]
- Y. Aghaghiri, F. Fallah, and M. Pedram.
ALBORZ: address level bus power optimization.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 470-475, San Jose, CA, March 18-21 2002.
- [80]
- Y. Aghaghiri, F. Fallah, and M. Pedram.
Reducing transitions on memory buses using sector-based encoding technique.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 190-195, Monterey, California, August 12-14 2002.
- [81]
- Y. Aghaghiri, F. Fallah, and M. Pedram.
Transition reduction in memory buses using sector-based encoding techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1164-1174, August 2004.
- [82]
- A. Agnihotri, M. C. Yildiz, A. Khatkhate, A. Mathur, S. Ono, and
P. H. Madden.
Fractional cut: improved recursive bisection placement.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 307-310, San Jose, CA, November 9-13 2003.
- [83]
- M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi.
Leakage-delay tradeoff in finfet logic circuits: a comparative analysis with
bulk technology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):232-245, February 2010.
- [84]
- V. D. Agrawal,
K-T Cheng, and P. Agrawal.
CONTEST: a concurrent test generator for sequential circuits.
In 25th ACM/IEEE Design Automation Conference, pages 84-89, Anaheim,
CA, June 12-15 1988.
- [85]
- V. D. Agrawal,
K-T. Cheng, and P. Agrawal.
A directed search method for test generation using a concurrent simulator.
IEEE Transactions on Computer-Aided Design, 8(2):131-138, February
1989.
- [86]
- A. Agrawal,
H. Li, and K. Roy.
DRG-cache: A data retention gated-ground cache for low power.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
473-478, New Orleans, LA, June 10-14 2002.
- [87]
- P. Agrawal and S. M.
Reddy.
Test generation at MOS level.
In IEEE International Conference on Computers, Systems, and Signal
Processing, pages 1116-1119, Bangalore, India, Dec. 10-12 1984.
- [88]
- V. D. Agrawal and S. C.
Seth.
Probabilistic testability.
In IEEE International Conference on Computer Design: VLSI in
Computers, pages 562-565, Port Chester, NY, Oct. 7-10 1985.
- [89]
- V. D. Agrawal.
Information theory in digital testing - a new approach to functional test
pattern generation.
In IEEE International Conference on Circuits and Computers, pages
928-931, Port Chester, NY, Oct. 1-3 1980.
- [90]
- V. D. Agrawal.
An information theoretic approach to digital fault testing.
IEEE Transactions on Computers, C-30(8):582-587, August 1981.
- [91]
- P. Agrawal.
Test generation at switch-level.
In IEEE International Conference on Computer-Aided Design, pages
128-130, Santa Clara, CA, Nov. 12-15 1984.
- [92]
- M. Ahadi and S. Roy.
Sparse linear regression (SPLINER) approach for efficient multidimensional
uncertainty quantification of high-speed circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(10):1640-1652, October 2016.
- [93]
- Lars Valerian Ahlfors.
Complex Analysis.
McGraw-Hill, New York, NY, 1979.
- [94]
- R. Ahmadi and F. N. Najm.
Timing analysis in presence of power supply and ground voltage variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 176-183, San Jose, CA, November 9-13 2003.
- [95]
- F. Ahmed and L. Milor.
Analysis and on-chip monitoring of gate oxide breakdown in SRAM cells.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(5):855-864, May 2012.
- [96]
- E. Ahmed and J. Rose.
The effect of LUT and cluster size on deep-submicron FPGA performance and
density.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(3):288-298, March 2004.
- [97]
- Alfred V. Aho, John E.
Hopcroft, and Jeffrey D. Ullman.
The Design and Analysis of Computer Algorithms.
Addison-Wesley Publishing Company, 1974.
- [98]
- A. V. Aho, B. W.
Kernighan, and P. J. Weinberger.
The Awk Programming Language.
Addison-Wesley, Reading, MA, 1988.
- [99]
- M. Ahrens,
M. Gester, N. Klewinghaus, D. Muller, S. Payer, C. Schulte, and G. Tellez.
Detailed routing algorithms for advanced technology nodes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(4):563-576, April 2015.
- [100]
- R. Aitken and
S. Becker.
Cell library techniques using advanced transistor structures.
In International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 199-204, Austin, TX, May 17-20 2004.
- [101]
- A. A. Ajami,
K. Banerjee, and M. Pedram.
Analysis of substrate thermal gradient effects on optimal buffer insertion.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 44-48, San Jose, CA, November 4-8 2001.
- [102]
- A. H. Ajami,
K. Banerjee, M. Pedram, and L. P.P.P. van Ginneken.
Analysis of non-uniform temperature-dependent interconnect performance in high
performance ics.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
567-572, Las Vegas, NV, June 18-22 2001.
- [103]
- A. H. Ajami,
K. Banerjee, and M. Pedram.
Modeling and analysis of nonuniform substrate temperature effects on global
ULSI interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(6):849-861, June 2005.
- [104]
- S. B. Akers, Jr.
On a theory of boolean functions.
SIAM Journal, 7(4):487-498, December 1959.
- [105]
- S. B. Akers.
Functional testing with binary decision diagrams.
In IEEE 8th International Conference on Fault-Tolerant Computing,
pages 75-82, Tolouse, France, June 21-23 1978.
- [106]
- C. J. Akl and M. A.
Bayoumi.
Reducing interconnect delay uncertainty via hybrid polarity repeater insertion.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(9):1230-1239, September 2008.
- [107]
- C. J. Akl and M. A.
Bayoumi.
Transition skew coding for global on-chip interconnect.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(8):1091-1096, August 2008.
- [108]
- F. Akopyan,
J. Sawada, A. Cassidy, R. Alvarez-Icaza, J. Arthur, P. Merolla, N. Imam,
Y. Nakamura, P. Datta, G.-J. Nam, B. Taba, M. Beakes, B. Brezzo, J. B. Kuang,
R. Manohar, W. P. Risk, B. Jackson, and D. S. Modha.
Truenorth: design and tool flow of a 65 mw 1 million neuron programmable
neurosynaptic chip.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(10):1537-1557, October 2015.
- [109]
- S. A. Al-Arian and
D. P. Agrawal.
Physical failures and fault models of CMOS circuits.
IEEE Transactions on Circuits and Systems, CAS-34(3):269-279, March
1987.
- [110]
- A. H. Al-Mohy and
N. J. Higham.
Computing the action of the matrix exponentinal, with an application to
exponential integrators.
SIAM Journal of Scientific Computing, 33(2):488-511, 2011.
- [111]
- A. A.
Al-Yamani, S. Ramsundar, and D. K. Pradhan.
A defect tolerance scheme for nanotechnology circuits.
IEEE Transactions on Circuits and Systems, 54(11):2402-2409, November
2007.
- [112]
- A. Alaghi,
C. Li, and J. P. Hayes.
Stochastic circuits for real-time image-processing applications.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [113]
- A. Alaghi and J. P.
Hayes.
STRAUSS: spectral transform use in stochastic circuit synthesis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(11):1770-1783, November 2015.
- [114]
- M. R. Alam,
M. E. Salehi Nasab, and S. Mehdi Fakhraie.
Power efficient high-level synthesis by centralized and fine-grained clock
gating.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(12):1954-1963, December 2015.
- [115]
- M. Alawieh,
F. Wang, and X. Li.
Efficient hierarchical performance modeling for integrated circuits via
bayesian co-learning.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [116]
- M. M.
Alaybeyi, J. Y. Lee, and R. A. Rohrer.
Numerical integration algorithms and asymptotic waveform evaluation (AWE).
In IEEE/ACM International Conference on Computer-Aided Design, pages
76-79, Santa Clara, CA, November 8-12 1992.
- [117]
- C. Albea,
F. Gordillo, and C. Canudas de Wit.
High performance control design for dynamic voltage scaling devices.
IEEE Transactions on Circuits and Systems, 58(12):2919-2930, December
2011.
- [118]
- C. Albrecht,
B. Korte, J. Schietke, and J. Vygen.
Cycle time and slack optimization for VLSI chips.
In IEEE/ACM International Conference on Computer-Aided Design, pages
232-238, San Jose, CA, November 7-11 1999.
- [119]
- E. F. M.
Albuquerque and M. M. Silva.
A comparison by simulation and by measurement of the substrate noise generated
by CMOS, CSL, and CBL digital circuits.
IEEE Transactions on Circuits and Systems, 52(4):734-741, April
2005.
- [120]
- M. F. Ali, A. Veneris,
S. Safarpour, R. Drechsler, A. Smith, and M. Abadir.
Debugging sequential circuits using boolean satisfiability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 204-209, San Jose, CA, November 7-11 2004.
- [121]
- M. Alidina,
J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou.
Precomputation-based sequential logic optimization for low power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2(4):426-436, December 1994.
- [122]
- M. Alidina,
J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou.
Precomputation-based sequential logic optimization for low power.
In IEEE/ACM International Conference on Computer-Aided Design, pages
74-81, San Jose, CA, November 6-10 1994.
- [123]
- M. Alidina,
J. Monteiro, A. Ghosh, and M. Papaefthymiou.
Precomputation-based sequential logic optimization for low power.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
57-62, Napa, CA, April 24-27 1994.
- [124]
- A. Alimohammad, S. F. Fard, B. F. Cockburn, and C. Schlegel.
A compact and accurate gaussian variate generator.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(5):517-527, May 2008.
- [125]
- M. Alioto,
G. Palumbo, and M. Poli.
Evaluation of energy consumption in RC ladder circuits driven by a ramp
input.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1094-1107, October 2004.
- [126]
- M. Alioto,
G. Palumbo, and M. Poli.
Energy consumption in RC tree circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(5):452-461, May 2006.
- [127]
- M. Alioto,
G. Palumbo, and M. Poli.
Analysis and modeling of energy consumption in RLC tree circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):278-291, February 2009.
- [128]
- M. Alioto,
E. Consoli, and G. Palumbo.
Flip-flop energy/performance versus clock slope and impact on the clock network
design.
IEEE Transactions on Circuits and Systems, 57(6):1273-1286, June
2010.
- [129]
- M. Alioto,
G. Palumbo, and M. Pennisi.
Understanding the effect of process variations on the delay of static and
domino logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(5):697-710, May 2010.
- [130]
- M. Alioto,
E. Consoli, and G. Palumbo.
Analysis and comparison in the energy-delay-area domain of nanometer CMOS
flip-flops: part I - methodology and design strategies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(5):725-736, May 2011.
- [131]
- M. Alioto,
E. Consoli, and G. Palumbo.
Analysis and comparison in the energy-delay-area domain of nanometer CMOS
flip-flops: part II - results and figures of merit.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(5):737-750, May 2011.
- [132]
- M. Alioto,
G. Scotti, and A. Trifiletti.
A novel framework to estimate the path delay variability on the back of an
envelope via the fan-out-of-4 metric.
IEEE Transactions on Circuits and Systems I: Regular Papers,
64(8):2073-2085, August 2017.
- [133]
- M. Alioto and
G. Palumbo.
Power estimation in adiabatic circuits: a simple and accurate model.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(5):608-615, October 2001.
- [134]
- M. Alioto and
G. Palumbo.
NAND/NOR adiabatic gates: power consumption evaluation and comparion versus
the fan-in.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(9):1253-1262, September 2002.
- [135]
- M. Alioto and
G. Palumbo.
Design strategies for source coupled logic gates.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(5):640-654, May 2003.
- [136]
- M. Alioto and
G. Palumbo.
Impact of supply voltage variations on full adder delay: analysis and
comparison.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(12):1322-1335, December 2006.
- [137]
- M. Alioto.
CAD models of the input admittance of RC wires: comparison and selection
strategies.
In IEEE 20th International Conference on Microelectronics (ICM), pages
154-157, Sharjah, UAE, December 14-17 2008.
- [138]
- M. Alioto.
Ultra-low power VLSI circuit design demystified and explained: a tutorial.
IEEE Transactions on Circuits and Systems, 59(1):3-29, January
2012.
- [139]
- Y. Alkabani1, T. Massey, F. Koushanfar, and M. Potkonjak.
Input vector control for post-silicon leakage current minimization in the
presence of manufacturing variability.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
606-609, Anaheim, CA, June 8-13 2008.
- [140]
- G. A. Allan.
Yield prediction by sampling IC layout.
IEEE Transactions on Computer-Aided Design, 19(3):359-371, March
2000.
- [141]
- N. Allec,
Z. Hassan, L. Shang, R. P. Dick, and R. Yang.
Thermalscope: multi-scale thermal analysis for nanometer-scale integrated
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 603-610, San Jose, CA, November 10-13 2008.
- [142]
- D. Allen,
D. Behrends, and B. Stanisic.
Converting a 64b powerpc processor from CMOS bulk to SOI technology.
In Design Automation Conference, pages 892-897, New Orleans, LA, June
21-25 1999.
- [143]
- J. M. Allred,
S. Roy, and K. Chakraborty.
Dark silicon aware multicore systems: Employing design automation with
architectural insight.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1192-1196, May 2014.
- [144]
- F. A. Aloul,
A. Ramani, I. L. Markov, and K. A. Sakallah.
Generic ILP versus specialized 0-1 ILP: An update.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 450-457, San Jose, CA, November 10-14 2002.
- [145]
- F. A. Aloul, B. D.
Sierawski, and K. A. Sakallah.
Satometer: how much have we searched.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(8):995-1004, August 2003.
- [146]
- E. Alpaslan,
B. Kruseman, A. K. Majhi, W. M. Heuvalman, and J. Dworak.
NIM-X: a noise index model-based X-filling technique to overcome the
power supply switching noise effects on path delay test.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(5):809-813, May 2012.
- [147]
- C. J. Alpert,
A. Devgan, and S. T. Quay.
Buffer insertion for noise and delay optimization.
In IEEE/ACM 35th Design Automation Conference, pages 362-367, San
Francisco, CA, June 15-19 1998.
- [148]
- C. J. Alpert,
A. Devgan, and S. T. Quay.
Is wire tapering worthwhile?
In IEEE/ACM International Conference on Computer-Aided Design, pages
430-435, San Jose, CA, November 7-11 1999.
- [149]
- C. J. Alpert,
A. Devgan, and C. Kashyap.
A two moment RC delay metric for performance optimization.
In International Symposium on Physical Design, pages 69-74, San
Diego, CA, April 9-12 2000.
- [150]
- C. J. Alpert,
A. Devgan, and C. V. Kashyap.
RC delay metrics for performance optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(5):571-582, May 2001.
- [151]
- C. J. Alpert,
F. Liu, C. Kashyap, and A. Devgan.
Delay and slew metrics using the lognormal distribution.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
382-385, Anaheim, CA, June 2-6 2003.
- [152]
- C. J. Alpert,
F.-Y. Liu, C. V. Kashyap, and A. Devgan.
Closed-form delay and slew metrics made easy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(12):1661-1669, December 2004.
- [153]
- C. Alpert,
Z. Li, G.-J. Nam, C.-N. Sze, N. Viswanathan, and S. I. Ward.
Placement: hot or not?
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 283-290, San Jose, CA, November 5-8 2012.
- [154]
- C. J. Alpert.
The ispd98 circuit benchmark suite.
In ACM/IEEE International Symposium on Physical Design, pages 80-85,
Monterey, CA, April 6-8 1998.
- [155]
- M. D. Altman,
J. P. Bardhan, B. Tidor, and J. K. White.
FFTSVD: a fast multiscale boundary-element method solver suitable for
bio-MEMS and biomolecule simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(2):274-284, February 2006.
- [156]
- M. Altun, M. D.
Riedel, and C. Neuhauser.
Nanoscale digital computation through percolation.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
615-616, San Francisco, CA, July 26-31 2009.
- [157]
- M. Altun and M. D.
Riedel.
Lattice-based computation of boolean functions.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
609-612, Anaheim, CA, June 13-18 2010.
- [158]
- A. Alvandpour, P. Larsson-Edefors, and C. Svensson.
Separation and extraction of short-circuit power consumption in digital CMOS
VLSI circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 245-249, Monterey, CA, August 10-12 1998.
- [159]
- H. Amanthan,
C.-H. Kim, and K. Roy.
Larger-than-vdd forward body bias in sub-0.5v nanoscale CMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 8-13, Newport Beach, CA, August 9-11 2004.
- [160]
- S. V. Amari and R. B.
Misra.
Closed-form expressions for distribution of sum of exponential random
variables.
IEEE Transactions on Reliability, 46(4):519-522, December 1997.
- [161]
- L. Amaru, P.-E.
Gaillardon, and G. De Micheli.
Majority-inverter graph: a new paradigm for logic optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(5):806-819, May 2016.
- [162]
- L. Amaru,
E. Testa, M. Couceiro, O. Zografos, G. De Micheli, and M. Soeken.
Majority logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [163]
- B. Amelifard, F. Fallah, and M. Pedram.
Low-power fanout optimization using multiple threshold voltage inverters.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 95-98, San Diego, CA, August 8-10 2005.
- [164]
- B. Amelifard, F. Fallah, and M. Pedarm.
Low-power fanout optimization using MTCMOS and multi-vt techniques.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 334-337, Tegernsee, Germany, October 4-6 2006.
- [165]
- B. Amelifard, F. Fallah, and M. Pedram.
Leakage minimization of SRAM cells in a dual-vt and dual-tox technology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(7):851-860, July 2008.
- [166]
- B. Amelifard, F. Fallah, and M. Pedram.
Low-power fanout optimization using multi-threshold voltages and multi-channel
lengths.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(4):478-489, April 2009.
- [167]
- B. Amelifard
and M. Pedram.
Design of an efficient power delivery network in an soc to enable dynamic power
management.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 328-333, Portland, Oregon, August 27-29 2007.
- [168]
- B. Amelifard and
M. Pedram.
Optimal selection of voltage regulator modules in a power delivery network.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
168-173, San Diego, CA, June 4-8 2007.
- [169]
- B. Amelifard and
M. Pedram.
Optimal design of the power delivery network for multiple voltage-island
system-on-chipst.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(6):888-900, June 2009.
- [170]
- E. A.
Amerasekera and F. N. Najm.
Failure Mechanisms in Semiconductor Devices.
John Wiley & Sons, Inc., Chichester, England, 2nd edition, 1997.
- [171]
- B. W. Amick, C. R.
Gauthier, and D. Liu.
Macro-modeling concepts for the chip electrical interface.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
391-394, New Orleans, LA, June 10-14 2002.
- [172]
- C. S. Amin, M. H.
Chowdhury, and Y. I. Ismail.
Realizable RLCK circuit crunching.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
226-231, Anaheim, CA, June 2-6 2003.
- [173]
- C. S. Amin,
F. Dartu, and Y. I. Ismail.
Weibull based analytical waveform model.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 161-168, San Jose, CA, November 9-13 2003.
- [174]
- C. S. Amin,
F. Dartu, and Y. I. Ismail.
Modeling unbuffered latches for timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 254-260, San Jose, CA, November 7-11 2004.
- [175]
- C. S. Amin, M. H.
Chowdhury, and Y. I. Ismail.
Realizable reduction of interconnect circuits including self and mutual
inductances.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(2):271-277, February 2005.
- [176]
- C. S. Amin,
F. Dartu, and Y. I. Ismail.
Weibull-based analytical waveform model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(8):1156-1168, August 2005.
- [177]
- C. S. Amin, Y. I.
Ismail, and F. Dartu.
Piece-wise approximations of RLCK circuit responses using moment matching.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
927-932, Anaheim, CA, June 13-17 2005.
- [178]
- C. S. Amin,
N. Menezes, K. Killpack, F. Dartu, U. Choudhury, N. Hakim, and Y. I. Ismail.
Statistical static timing analysis: how simple can we get?
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
652-657, Anaheim, CA, June 13-17 2005.
- [179]
- C. Amin, C. Kashyap,
N. Menezes, K. Killpack, and E. Chiprout.
A multi-port current source model for multiple-input switching effects in
CMOS library cells.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
247-252, San Francisco, CA, July 24-28 2006.
- [180]
- A. Amirabadi, A. Afzali-Kusha, Y. Mortazavi, and M. Nourani.
Clock delayed domino logic with efficient variable threshold voltage keeper.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(2):125-134, February 2007.
- [181]
- H. Amrouch,
B. Khaleghi, A. Gerstlauer, and J. Henkel.
Towards aging-induced approximations.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [182]
- H. Amrouch,
V. M. van Santen, and J. Henkel.
Estimating and optimizing BTI aging effects: from physics to CAD.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [183]
- B. S. Amrutur and
M. A. Horowitz.
Speed and power scaling of SRAM's.
IEEE Transactions on Solid-State Circuits, 35(2):175-185, February
2000.
- [184]
- D. Amsallem
and J. Roychowdhury.
Modspec: an open, flexible specification framework for multi-domain device
modelling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 367-374, San Jose, CA, November 7-10 2011.
- [185]
- M. E. Amyeen,
W. K. Fuchs, I. Pomeranz, and V. Boppana.
Fault equivalence identification in combinational circuits using implication
and evaluation techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(7):922-936, July 2003.
- [186]
- H. Ananthan and
K. Roy.
Technology-circuit co-design in width-quantized quasi-planar double-gate
SRAM.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 155-160, Austin, TX, May 9 - 11 2005.
- [187]
- H. Ananthan and
K. Roy.
A fully physical model for leakage distribution under process variations in
nanoscale double-gate CMOS.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
413-418, San Francisco, CA, July 24-28 2006.
- [188]
- D. F.
Anastasakis, N. Gopal, and L. T. Pillage.
On the stability of moment-matching approximations in asumptotic waveform
evaluation.
SRC Technical Report C91905, Journal Preprint, December 1991.
- [189]
- D. F.
Anastasakis, N. Gopal, S. Y. Kim, and L. T. Pillage.
On the stability of moment-matching approximations in assymptotic waveform
evaluation.
In 29th ACM/IEEE Design Automation Conference, pages 207-212,
Anaheim, CA, June 8-12 1992.
- [190]
- J. H.
Anderson, F. N. Najm, and T. Tuan.
Active leakage power optimization for fpgas.
In ACM/SIGDA International Symposium on Field Programmable Gate
Arrays, pages 33-41, Monterey, CA, February 22-24 2004.
- [191]
- J. H. Anderson and
F. N. Najm.
Power-aware technology mapping for LUT-based fpgas.
In IEEE International Conference on Field-Programmable Technology,
pages 211-218, Hong Kong, December 16-18 2002.
- [192]
- J. H. Anderson and
F. N. Najm.
Switching activity analysis and pre-layout activity prediction for fpgas.
In ACM/IEEE International Workshop on System-Level Interconnect
Prediction, pages 15-21, Monterey, CA, April 5-6 2003.
- [193]
- J. H. Anderson and
F. N. Najm.
Interconnect capacitance estimation for fpgas.
In IEEE/ACM Asia and South Pacific Design Automation Conference
(ASP-DAC), pages 713-718, Yokohama, Japan, January 27-30 2004.
- [194]
- J. H. Anderson and
F. N. Najm.
Low-power programmable routing circuitry for fpgas.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 602-609, San Jose, CA, November 7-11 2004.
- [195]
- J. H. Anderson and
F. N. Najm.
A novel low-power FPGA routing switch.
In IEEE Custom Integrated Circuits Conference (CICC), pages 719-722,
Orlando, FL, October 3-6 2004.
- [196]
- J. H. Anderson and
F. N. Najm.
Power estimation techniques for fpgas.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1015-1027, October 2004.
- [197]
- J. H. Anderson and
F. N. Najm.
Active leakage power optimization for fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(3):423-437, March 2006.
- [198]
- J. H. Anderson and
F. N. Najm.
Low-power programmable FPGA routing circuitry.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(8):1048-1060, August 2009.
- [199]
- James A.
Anderson and Edward Rosenfeld.
Neurocomputing: Foundations of Research.
MIT Press, 1988.
- [200]
- J. H. Anderson.
Geometrical approach to reduction of dynamical systems.
In Proceedings of the IEE, pages 1014-1018, July 1967.
- [201]
- C. J. Anderson.
Beyond innovation: dealing with the risks and complexity of processor design in
22nm.
In ACM/IEEE 46th Design Automation Conference (DAC-09), page 103, San
Francisco, CA, July 26-31 2009.
- [202]
- N. Andrikos,
L. Lavagno, D. Pandini, and C. P. Sotiriou.
A fully-automated desynchronization flow for synchronous circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
982-985, San Diego, CA, June 4-8 2007.
- [203]
- C. Angione,
J. Costanza, G. Carapezza, P. Lio, and G. Nicosia.
Pareto epsilon-dominance and identifiable solutions for biocad modeling.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [204]
- M. Anis,
S. Areibi, M. Mahmoud, and M. Elmasry.
Dynamic and leakage power reduction in MTCMOS circuits using an automated
efficient gate clustering technique.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
480-485, New Orleans, LA, June 10-14 2002.
- [205]
- M. H. Anis, M. W.
Allam, and M. I. Elmasry.
Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and
MTCMOS technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(2):71-78, April 2002.
- [206]
- M. Anis, S. Areibi,
and M. Elmasry.
Design and optimization of multithreshold CMOS (MTCMOS) circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(10):1324-1342, October 2003.
- [207]
- A. Ankit,
A. Sengupta, and K. Roy.
Trannsformer: neural network transformation for memristive crossbar based
neuromorphic system design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 533-540, Irvine CA, November 13-16 2017.
- [208]
- M. Anton,
I. Colonescu, E. Macii, and M. Poncino.
Fast characterization of RTL power macromodels.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 1591-1594, St. Julian, Malta, September 2-5 2001.
- [209]
- D. A.
Antonelli, D.-Z. Chen, T. J. Dysart, and X.-S. Hu.
Quantum-dot cellular automata (QCA) circuit partitioning: problem modeling
and solutions.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
363-368, San Diego, CA, June 7-11 2004.
- [210]
- D. A. Antoniadis.
SOI CMOS as a mainstream low-power technology: a critical assessment.
In 1997 International Symposium on Low Power Electronics and Design,
pages 295-300, Monterey, CA, August 18-20 1997.
- [211]
- I. Apostolopoulou, K. Daloukas, N. Evmorfopoulos, and
G. Stamoulis.
Selective inversion of inductance matrix for large-scale sparse RLC
simulation.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [212]
- K. Arabi,
K. Samadi, and Y. Du.
3d VLSI: a schalable integration beyond 2d.
In ACM International Symposium on Physical Design 2015, pages 1-7,
Monterey, California, March 29 - April 1 2015.
- [213]
- N. Arai.
When and how will an AI be smart enough to design?
In 20th Asia and South Pacific Design Automation Conference, page 562,
Chiba/Tokyo, Japan, January 19-22 2015.
- [214]
- E. Arbel,
C. Eisner, and O. Rokhlenko.
Resurrecting infeasible clock-gating functions.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
160-165, San Francisco, CA, July 26-31 2009.
- [215]
- S. Ardalan,
F. Yuan, and K. Raahemifar.
Low power technique for delay reduction in static CMOS circuits.
In The First Annual Northeast Workshop on Circuits and Systems
(NEWCAS-03), pages 165-168, Montreal, Quebec, June 17-20 2003.
- [216]
- L. A. Arledge and
W. T. Lynch.
Scaling and performance implications for power supply and other signal routing
constraints imposed by I/O pad limitations.
In IEEE Symposium on IC/Package Design Integration, 1998.
- [217]
- D. B. Armstrong.
On finding a nearly minimal set of fault detection tests for combinational
logic nets.
IEEE Transactions on Electronic Computers, EC-15(1):66-73, February
1966.
- [218]
- J. V. Arthur and K. A.
Boahen.
Silicon-neuron design: a dynamical systems approach.
IEEE Transactions on Circuits and Systems, 58(5):1034-1043, May
2011.
- [219]
- H. Arts,
M. Berkelaar, and C. A. J. van Eijk.
Polarized observability don't cares.
In IEEE/ACM International Conference on Computer-Aided Design, pages
626-631, San Jose, CA, November 10-14 1996.
- [220]
- H. Arts,
M. Berkelaar, and K. van Eijk.
Computing observability don't cares efficiently through polarization.
IEEE Transactions on Computer-Aided Design, 17(7):573-581, July
1998.
- [221]
- D. Arumi,
R. Rodriguez-Montanes, J. Figueras, S. Eichenberger, C. Hora, and
B. Kruseman.
Gate leakage impact on full open defects in interconnect lines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(12):2209-2220, December 2011.
- [222]
- D. Arumi,
R. Rodriguez-Montanes, J. Figueras, S. Eichenberger, C. Hora, and
B. Kruseman.
Diagnosis of interconnect full open defects in the presence of gate leakage
currents.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(2):301-312, February 2013.
- [223]
- K. S. Arun and V. B. Rao.
New heuristics and lower bounds for graph partitioning.
In IEEE International Symposium on Circuits and Systems, pages
1172-1175, June 1991.
- [224]
- R. Arunachalam, K. Rajagopal, and L. T. Pileggi.
TACO: Timing analysis with coupling.
In Design Automation Conference, pages 266-269, Los Angeles, CA, June
5-9 2000.
- [225]
- R. Arunachalam, R. D. Blanton, and L. T. Pileggi.
False coupling interactions in static timing analysis.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
726-731, Las Vegas, NV, June 18-22 2001.
- [226]
- Arvind, R. S.
Nikhil, D. L. Rosenband, and N. Dave.
High-level synthesis: an essential ingredient for designing complex asics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 775-782, San Jose, CA, November 7-11 2004.
- [227]
- H. Asadi and M. B.
Tahoori.
Soft error derating computation in sequential circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 497-501, San Jose, CA, November 5-9 2006.
- [228]
- F. H. A. Asgari and
M. Sachdev.
A low-power reduced swing global clocking methodology.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):538-545, May 2004.
- [229]
- P. Ashar and S. Malik.
Functional timing analysis using ATPG.
IEEE Transactions on Computer-Aided Design, 14(8):1025-1030, August
1995.
- [230]
- T. Askham and
L. Greengard.
Norm-preserving discretization of integral equations for elliptic pdes with
internal layers I: the one-dimensional case.
SIAM Review, 56(4):625-641, December 2014.
- [231]
- F. Assaderaghi.
Circuit styles and strategies for CMOS VLSI design on SOI.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 282-287, San Diego, CA, August 16-17 1999.
- [232]
- G. Astfalk,
I. Lustig, R. Marsten, and D. Shanno.
The interior-point method for linear programming.
IEEE Software, 9(4):61-68, July 1992.
- [233]
- E. M. Atakov,
T. S. Sriram, D. Dunnell, and S. Pizzanello.
Effect of VLSI interconnect layout on electromigration performance.
In IEEE International Reliability Physics Symposium, pages 348-355,
Reno, NV, 1998.
- [234]
- W. Athas,
L. Youngs, and A. Reinhart.
Compact models for estimating microprocessor frequency and power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 313-318, Monterey, California, August 12-14 2002.
- [235]
- W. Athas.
Practical considerations of clock-powered logic.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 173-178, Italy, July 26-27 2000.
- [236]
- K. Athikulwongse, J.-S. Yang, D.-Z. Pan, and S.-K. Lim.
Impact of mechanical stress on the full chip timing for
through-silicon-via-based 3-C ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):905-917, June 2013.
- [237]
- M. J. Attardo,
R. Rutledge, and R. C. Jack.
Statistical metallurgical model for electromigration failure in aluminum
thin-film conductors.
Journal of Applied Physics, 42(11):4343-4349, October 1971.
- [238]
- M. J. Attardo and
R. Rosenberg.
Electromigration damage in aluminum film conductors.
Journal of Applied Physics, 41(6):2381-2386, May 1970.
- [239]
- L. M. Augustin.
An algebra of waveforms.
In L. J. M. Claesen, editor, Formal VLSI Specification and Synthesis: VLSI
Design Methods, I, pages 309-318. Elsevier Science Publishers B. V.
(North-Holland), New York, NY, 1990.
- [240]
- S. Aur, C. Duvvury,
and W. Hunter.
Setting the trap for hot carriers.
IEEE Circuits and Devices Magazine, 11(4):18-24, July 1995.
- [241]
- T. M. Austin.
Designing robust microarchitectures.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 78-78,
San Diego, CA, June 7-11 2004.
- [242]
- M. Avci and F. N. Najm.
Early P/G grid voltage integrity verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 816-823, San Jose, CA, November 7-11 2010.
- [243]
- M. Avci and F. N. Najm.
Verification of the power and ground grids under general and hierarchical
constraints.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(2):729-742, February 2016.
- [244]
- R. L. Aveyard.
A boolean model for a class of discrete event systems.
IEEE Transactions on Systems, Man, and Cybernetics, SMC-4(3):249-258,
May 1974.
- [245]
- H. Awano and T. Sato.
Efficient transistor-level timing yield estimation via line sampling.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [246]
- M. Aydonat and F. N.
Najm.
Power grid correction using sensitivity analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 808-815, San Jose, CA, November 7-11 2010.
- [247]
- N. Azizi,
A. Moshovos, and F. N. Najm.
Low-leakage asymmetric-cell SRAM.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 48-51, Monterey, California, August 12-14 2002.
- [248]
- N. Azizi, F. N.
Najm, and A. Moshovos.
Low-leakage asymmetric-cell SRAM.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):701-715, August 2003.
- [249]
- N. Azizi, M. M.
Khellah, V. De, and F. N. Najm.
Variations-aware low-power design with voltage scaling.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
529-534, Anaheim, CA, June 13-17 2005.
- [250]
- N. Azizi, M. M.
Khellah, V. K. De, and F. N. Najm.
Variations-aware low-power design and block clustering with voltage scaling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(7):746-757, July 2007.
- [251]
- N. Azizi and F. N. Najm.
An asymmetric SRAM cell to lower gate leakage.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 534-539, San Jose, CA, March 22-24 2004.
- [252]
- N. Azizi and F. N. Najm.
Compensation for within-die variations in dynamic logic by using body-bias.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 167-170, Quebec City, Quebec, June 19-22 2005.
- [253]
- N. Azizi and F. N. Najm.
Look-up table leakage reductions for fpgas.
In IEEE Custom Integrated Circuits Conference (CICC), pages 187-190,
San Jose, CA, September 18-21 2005.
- [254]
- N. Azizi and F. N. Najm.
A family of cells to reduce the soft-error-rate in ternary-CAM.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
779-784, San Francisco, CA, July 24-28 2006.
- [255]
- N. Azizi and F. N. Najm.
Using keeper control and body bias for fine grained threshold voltage
compensation in dynamic logic.
In 20th Canadian Conference on Electrical and Computer Engineering
(CCECE), pages 1639-1644, Vancouver, BC, April 22-26 2007.
- [256]
- P. Babighian, L. Benini, and E. Macii.
A scalable algorithm for RTL insertion of gated clocks based on odcs
computation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):29-42, January 2005.
- [257]
- P. Babighina, L. Benini, A. Macii, and E. Macii.
Post-layout leakage power minimization based on distributed sleep transistor
insertion.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 138-143, Newport Beach, CA, August 9-11 2004.
- [258]
- W. W. Bachmann and
S. A. Huss.
Efficient algorithms for multilevel power estimation of VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(2):238-254, February 2005.
- [259]
- M. Badaroglu, K. Tiri, S. Donnay, P. Wambacq, I. Verbauwhede,
G. Gielen, and H. De Man.
Clock tree optimization in synchronous CMOS digital circuits for substrate
noise reduction using folding of supply current transients.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
399-404, New Orleans, LA, June 10-14 2002.
- [260]
- M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. G. E.
Gielen, and H. J. De Man.
Digital ground bounce reduction by supply current shaping and clock frequency
modulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):65-76, January 2005.
- [261]
- A. Baghbanbehrouzian and N. Masoumi.
Analytical solutions for distributed interconnect models - part II: arbitrary
input response and multicoupled lines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(9):1879-1888, September 2015.
- [262]
- R. I. Bahar, E. A.
Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi.
Algebraic decision diagrams and their applications.
In IEEE/ACM International Conference on Computer-Aided Design, pages
188-191, Santa Clara, CA, November 7-11 1993.
- [263]
- R. I. Bahar,
H. Cho, G. D. Hachtel, and F. Somenzi.
An application of ADD-based timing analysis to combinational low power
re-synthesis.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
39-44, Napa, CA, April 24-27 1994.
- [264]
- R. I. Bahar,
G. D. Hachtel, E. Macii, and F. Somenzi.
A symbolic method to reduce power consumption of circuits containing false
paths.
In IEEE/ACM International Conference on Computer-Aided Design, pages
368-371, San Jose, CA, November 6-10 1994.
- [265]
- R. I. Bahar,
M. Burns, G. D. Hachtel, E. Macii, H. Shin, and F. Somenzi.
Symbolic computation of logic implications for technology-dependent low-power
synthesis.
In International Symposium on Low Power Electronics and Design, pages
163-168, Monterey, CA, August 12-14 1996.
- [266]
- R. Iris Bahar,
H. Cho, G. D. Hachtel, E. Macii, and F. Somenzi.
Symbolic timing analysis and resynthesis for low power of combinational
circuits containing false paths.
IEEE Transactions on Computer-Aided Design of Circuits and Systems,
16(10):1101-1115, October 1997.
- [267]
- R. I. Bahar and
F. Somenzi.
Boolean techniques for low power driven re-synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
428-432, San Jose, CA, November 5-9 1995.
- [268]
- Z. Bai, P. Feldmann,
and R. W. Freund.
How to make theoretically passive reduced-order models passive in practice.
In IEEE Custom Integrated Circuits Conference, pages 207-210, Santa
Clara, CA, May 11-14 1998.
- [269]
- Z. Bai, R. D. Slone,
W. T. Smith, and Q. Ye.
Error bound for reduced system model by pade approximation via the lanczos
process.
IEEE Transactions on Computer-Aided Design, 18(2):133-141, February
1999.
- [270]
- G. Bai, S. Bobba, and
I. N. Hajj.
Power bus maximum voltage drop in digital VLSI circuits.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 263-268, San Jose, CA, March 20-22 2000.
- [271]
- G. Bai, S. Bobba,
and I. N. Hajj.
Simulation and optimization of the power distribution network in VLSI
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 481-486, San Jose, CA, November 5-9 2000.
- [272]
- G. Bai, S. Bobba, and
I. N. Hajj.
RC power bus maximum voltage drop in digital VLSI circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 205-210, San Jose, CA, March 26-28 2001.
- [273]
- G. Bai, S. Bobba,
and I. N. Hajj.
RC power bus maximum voltage drop in digital VLSI circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 257-258, San Jose, CA, March 26-28 2001.
- [274]
- G. Bai, S. Bobba,
and I. N. Hajj.
Static timing analysis including power supply noise effect on propagation delay
in VLSI circuits.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
295-300, Las Vegas, NV, June 18-22 2001.
- [275]
- X. Bai, R. Chandra,
S. Dey, and P. V. Srinivas.
Interconnect coupling-aware driver modeling in static noise analysis for
nanometer circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1256-1263, August 2004.
- [276]
- K. Bai, J. Li,
K. Hamedani, and Y. Yi.
Enabling an new era of brain-inspired computing: energy-efficient spiking
neural network with ring topology.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [277]
- X. Bai and S. Dey.
High-level crosstalk defect simulation methodology for system-on-chip
interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1355-1361, September 2004.
- [278]
- G. Bai and I. N. Hajj.
Simultaneouos switching noise and resonance analysis of on-chip power
distributon network.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 163-168, San Jose, CA, March 18-21 2002.
- [279]
- D. H. Bailey.
Misleading performance claims in parallel computations.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
528-533, San Francisco, CA, July 26-31 2009.
- [280]
- B. S. Bajwa,
N. Schumann, and H. Kojima.
Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit
DSP.
In 1997 International Symposium on Low Power Electronics and Design,
pages 137-142, Monterey, CA, August 18-20 1997.
- [281]
- H. B. Bakoglu.
Circuits, Interconnections, and Packaging for VLSI.
Addison-Wesley Pub. Co., Inc., Reading, MA, 1990.
- [282]
- N. Balabanian
and T. A. Bickart.
Electrical Network Theory.
John Wiley & Sons, Inc., New York, NY, 1969.
- [283]
- S. Balachandran and D. Bhatia.
A priori wirelength and interconnect estimation based on circuit
characteristics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):1054-1065, July 2005.
- [284]
- B. Balaji,
M. A. Al Faruque, N. Dutt, R. Gupta, and Y. Agarwal.
Models, abstractions, and architectures: the missing links in cyber-physical
systems.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [285]
- K. J.
Balakrishnan and N. A. Touba.
Relationship between entropy and test data compression.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(2):386-395, February 2007.
- [286]
- F. Balarin.
Worst-case analysis of discrete systems.
In IEEE/ACM International Conference on Computer-Aided Design, pages
347-352, San Jose, CA, November 7-11 1999.
- [287]
- R. Baldick,
A. B. Kahng, A. Kennings, and I. L. Markov.
Efficient optimization by modifying the objective function: application to
timing-driven VLSI layout.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(8):947-956, August 2001.
- [288]
- H. A. Balef,
M. Kamal, A. Afzali-Kusha, and M. Pedram.
All-region statistical model for delay variation based on log-skew-normal
distribution.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(9):1503-1508, September 2016.
- [289]
- A. Balivada,
D. R. Holberg, and L. T. Pillage.
Calculation and application of time-domain waveform sensitivities in asymptotic
waveform evaluation.
In IEEE Custom Integrated Circuits Conference, pages 8.4.1-8.4.4,
1991.
- [290]
- M. O. Ball and J. S.
Provan.
Disjoint products and efficient computation of reliability.
Operations Research, 36(5):703-715, Sept.-Oct. 1988.
- [291]
- B. Bandali,
E. Gad, and M. Bolic.
Accelerated harmonic-balance analysis using a graphical processing unit
platform.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(7):1017-1030, July 2014.
- [292]
- D. Baneres,
J. Cortadella, and M. Kishinevsky.
A recursive paradigm to solve boolean relations.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
416-421, San Diego, CA, June 7-11 2004.
- [293]
- K. Banerjee,
A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu.
On thermal effects in deep sub-micron VLSI interconnects.
In Design Automation Conference, pages 885-891, New Orleans, LA, June
21-25 1999.
- [294]
- P. Banerjee,
M. Haldar, A. Nayak, V. Kim, V. Saxena, S. Parkes, D. Bagchi, S. Pal,
N. Tripathi, D. Zaretsky, R. Anderson, and J. R. Uribe.
Overview of a compiler for synthesizing MATLAB programs onto fpgas.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(3):312-324, March 2004.
- [295]
- P. Banerjee and
J. A. Abraham.
Generating tests for physical failures in MOS logic circuits.
In IEEE International Test Conference, pages 554-559, Philadelphia,
PA, October 1983.
- [296]
- K. Banerjee and
A. Mehrotra.
Coupled analysis of electromigration reliability and performance in ULSI
signal nets.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 158-164, San Jose, CA, November 4-8 2001.
- [297]
- K. Banerjee and
A. Mehrotra.
Analysis of on-chip inductance effects for distributed RLC interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(8):904-915, August 2002.
- [298]
- K. Banerjee and
N. Srivastava.
Are carbon nanotubes the future of VLSI interconnections.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
809-814, San Francisco, CA, July 24-28 2006.
- [299]
- A. Baniasadi
and A. Moshovos.
SEPAS: a highly accurate energy-efficient branch predictor.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 38-43, Newport Beach, CA, August 9-11 2004.
- [300]
- S. R. Banna,
P. C. H. Chan, M. Chan, and S. K. H. Fung.
Fully depleted CMOS/SOI device design guidelines for low power
applications.
In 1997 International Symposium on Low Power Electronics and Design,
pages 301-306, Monterey, CA, August 18-20 1997.
- [301]
- B. R.
Bannister, D. R. Melton, and G. E. Taylor.
Testability of digital circuits via the spectral domain.
In IEEE International Conference on Computer Design, pages 340-343,
1989.
- [302]
- A. Bansal, R. N.
Singh, R. N. Kanj, S. Mukhopadhyay, J.-F. Lee, E. Acar, A. Singhee, K. Kim,
C.-T. Chuang, S. Nassif, F.-L. Heng, and K. K. Das.
Yield estimation of SRAM circuits using "virtual SRAM fab".
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 631-636, San Jose, CA, November 2-5 2009.
- [303]
- J. P. Bardhan
and A. Hildebrandt.
A fast solver for nonlocal electrostatic theory in biomolecular science and
engineering.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
801-805, San Diego, CA, June 5-9 2011.
- [304]
- T. S. Barnett,
A. D. Singh, and V. P. Nelson.
Extending integrated-circuit yield-models to estimate early-life reliability.
IEEE Transactions on Reliability, 52(3):296-300, September 2003.
- [305]
- M. Barocci,
L. Benini, A. Bogliolo, B. Ricco, and G. De Micheli.
Lookup table power macro-models for behavioral library components.
In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages
173-181, Como, Italy, March 4-5 1999.
- [306]
- A. Bartel and
M. Gunther.
Pdaes in refined electrical network modeling.
SIAM Review, 60(1):56-91, March 2018.
- [307]
- R. Bartels and
G. Stewart.
Solution of the matrix equation AX + XB = C: Algorithm 432.
Communications of the ACM, 15:277-303, 1972.
- [308]
- Z. Barzilai,
J. L. Carter, V. S. Iyengar, I. Nair, B. K. Rosen, J. Rutledge, and G. M.
Silberman.
Efficient fault simulation of CMOS circuits with accurate models.
In IEEE International Test Conference, pages 520-529, Sept. 8-11
1986.
- [309]
- D. Baschiera
and B. Courtois.
Testing CMOS: a challenge.
VLSI Design, pages 58-62, October 1984.
- [310]
- R. Bashirullah, W. Liu, and R. K. Cavin.
Low-power design methodology for an on-chip bus with adaptive bandwidth
capability.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
628-633, Anaheim, CA, June 2-6 2003.
- [311]
- R. Bashirullah, W. Liu, and R. K. Cavin, III.
Current-model signaling in deep submicrometer global interconnects.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):406-417, June 2003.
- [312]
- R. Bashirullah, W. Liu, R. Cavin, and D. Edwards.
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth
capability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(8):876-880, August 2004.
- [313]
- P. Bastani,
N. Callegari, L.-C. Wang, and M. S. Abadir.
Ranking of unmodeled systematic timing effects.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 104-109, Monterey, CA,
February 25-26 2008.
- [314]
- P. Bastani,
N. Callegari, L.-C. Wang, and M. S. Abadir.
Statistical diagnosis of unmodeled systematic timing effects.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
355-360, Anaheim, CA, June 8-13 2008.
- [315]
- P. Bastani,
K. Killpack, L.-C. Wang, and E. Chiprout.
Speedpath prediction based on learning from a small set of examples.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 98-103, Monterey, CA,
February 25-26 2008.
- [316]
- P. Bastani,
K. Killpack, L.-C. Wang, and E. Chiprout.
Speedpath prediction based on learning from a small set of examples.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
217-222, Anaheim, CA, June 8-13 2008.
- [317]
- A. Basu, S.-C. Lin,
V. Wason, A. Mehrotra, and K. Banerjee.
Simultaneous optimization of supply and threshold voltages for low-power and
high-performance circuits in the leakage dominant era.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
884-887, San Diego, CA, June 7-11 2004.
- [318]
- M. J. Batek.
Test-set preserving logic transformations.
In 29th ACM/IEEE Design Automation Conference, pages 454-458,
Anaheim, CA, June 8-12 1992.
- [319]
- J. Bautista.
Tera-scale computing and interconnect challenges.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
665-667, Anaheim, CA, June 8-13 2008.
- [320]
- M. A. Bawiec and
M. Nikodem.
Boolean logic function synthesis for generalised threshold gate circuits.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 83-86,
San Francisco, CA, July 26-31 2009.
- [321]
- A. A.
Bayrakci, A. Demir, and S. Tasiran.
Fast monte carlo estimation of timing yield with importance sampling and
transistor-level circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(9):1328-1341, September 2010.
- [322]
- A. A. Bayrakci.
Accelerated accurate timing yield estimation based on control variates and
importance sampling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(8):2787-2798, August 2016.
- [323]
- K. Bazargan,
S. Kim, and M. Sarrafzadeh.
NOSTRADAMUS: A floorplanner of uncertain designs.
In ACM/IEEE International Symposium on Physical Design, pages 18-23,
Monterey, CA, April 6-8 1998.
- [324]
- K. Bazargan,
S. Kim, and M. Sarrafzadeh.
Nostradamus: A floorplanner of uncertain designs.
IEEE Transactions on Computer-Aided Design, 18(4):389-397, April
1999.
- [325]
- M. Beattie,
S. Gupta, and L. Pileggi.
Hierarchical interconnect circuit models.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 215-221, San Jose, CA, November 5-9 2000.
- [326]
- M. Beattie,
B. Krauter, L. Alatan, and L. Pileggi.
Equipotential shells for efficient inductance extraction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(1):70-79, January 2001.
- [327]
- M. W. Beattie and
L. T. Pileggi.
Error bounds for capacitance extraction via window techniques.
IEEE Transactions on Computer-Aided Design, 18(3):311-321, March
1999.
- [328]
- M. W. Beattie and
L. T. Pileggi.
Inductance 101: Modeling and extraction.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
323-328, Las Vegas, NV, June 18-22 2001.
- [329]
- M. W. Beattie and
L. T. Pileggi.
On-chip induction modeling: basics and advanced methods.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):712-729, December 2002.
- [330]
- M. W. Beattie and
L. T. Pileggi.
Parasitics extraction with multipole refinement.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(2):288-292, February 2004.
- [331]
- D. L. Beatty and R. E.
Bryant.
Fast incremental circuit analysis using extracted hierarchy.
In 25th ACM/IEEE Design Automation Conference, pages 495-500,
Anaheim, CA, June 12-15 1988.
- [332]
- J. Beaumont,
A. Mokhov, D. Sokolov, and A. Yakovlev.
High-level asynchronous concepts at the interface between analog and digital
worlds.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 37(1):61-74, January 2018.
- [333]
- M. R. Becer,
D. Blaauw, R. Panda, and I. N. Hajj.
Pre-route noise estimation in deep submicron integrated circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 413-418, San Jose, CA, March 18-21 2002.
- [334]
- M. R. Becer,
D. Blaauw, I. Algor, R. Panda, C. Oh, V. Zolotov, and I. N. Hajj.
Post-route gate sizing for crosstalk noise reduction.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 171-176, San Jose, CA, March 24-26 2003.
- [335]
- M. R. Becer,
D. Blaauw, R. Panda, and I. N. Hajj.
Early probabilistic noise estimation for capacitively coupled interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(3):337-345, March 2003.
- [336]
- M. R. Becer,
D. Blaauw, H. Algor, R. Panda, C. Oh, V. Zolotov, and I. N. Hajj.
Postroute gate sizing for crossing noise reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(12):1670-1677, December 2004.
- [337]
- M. Becer,
V. Zolotov, R. Panda, A. Grinshpon, I. Algor, R. Levy, and C. Oh.
Pessimism reduction in crosstalk noise aware STA.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 954-961, San Jose, CA, November 6-10 2005.
- [338]
- M. Becer and I. N. Hajj.
An analytical model for delay and crosstalk estimation in interconnects.
In 7th IEEE International Conference on Electronics, Circuits and
Systems, pages 831-835, Beirut, Lebanon, December 17-19 2000.
- [339]
- M. Becer and I. N. Hajj.
An analytical model for delay and crosstalk estimation with application to
decoupling.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 51-57, San Jose, CA, March 20-22 2000.
- [340]
- M. Becker,
A. Masrur, and S. Chakraborty.
Composing real-time applications from communicating black-box components.
In 20th Asia and South Pacific Design Automation Conference, pages
624-629, Chiba/Tokyo, Japan, January 19-22 2015.
- [341]
- P. Beckett.
A low-power reconfigurable logic array based on double-gate transistors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(2):115-123, February 2008.
- [342]
- D. K. Beece,
J. Xiong, C. Visweswariah, V. Zolotov, and Y. Li.
Transistor sizing of custom high-performance digital circuits with parametric
yield considerations.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
781-786, Anaheim, CA, June 13-18 2010.
- [343]
- F. Beeftink,
P. Kudva, D. Kung, and L. Stok.
Gate-size selection for standard cell libraries.
In IEEE/ACM International Conference on Computer-Aided Design, pages
545-550, San Jose, CA, November 8-12 1998.
- [344]
- S. De Beer,
M. du Plessis, and E. Seevinck.
An SRAM array based on a four-transistor CMOS SRAM cell.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(9):1203-1208, September 2003.
- [345]
- P. A. Beerel,
K. Y. Yun, S. M. Nowick, and P-C. Yeh.
Estimation and bounding of energy consumption in burst-mode control circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
26-33, San Jose, CA, November 5-9 1995.
- [346]
- R. Beers.
Pre-RTL formal verification: an intel experience.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
806-811, Anaheim, CA, June 8-13 2008.
- [347]
- C. C. Beh, K. H. Arya,
C. E. Radke, and K. E. Torku.
Do stuck fault models reflect manufacturing defects.
In IEEE International Test Conference, pages 35-42, 1982.
- [348]
- A. R. B. Behrouzian.
Analytical solutions for distributed interconnect models - part I: step input
response of finite and semi-infinite lines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(12):2596-2606, December 2014.
- [349]
- F. Beichelt and
P. Tittmann.
A generalized reduction method for the connectedness probability of stochastic
networks.
IEEE Transactions on Reliability, 40(2):198-203, June 1991.
- [350]
- B. A. Beitman and
A. Ito.
Generation of electromigration ground rules utilizing monte carlo simulation
methods.
IEEE Transactions on Semiconductor Manufacturing, 4(1):63-66,
February 1991.
- [351]
- V. Beiu, S. Aunet,
J. Nyathi, R. R. Rydberg, III, and W. Ibrahim.
Serial addition: locally connected architectures.
IEEE Transactions on Circuits and Systems, 54(11):2564-2579, November
2007.
- [352]
- N. Bellas,
I. N. Hajj, C. D. Polychronopoulos, and G. Stamoulis.
Architectural and compiler techniques for energy reduction in high-performance
microprocessors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):317-326, June 2000.
- [353]
- N. E. Bellas,
I. N. Hajj, and C. D. Polychronopoulos.
Using dynamic cache management techniques to reduce energy in general purpose
processors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(6):693-708, December 2000.
- [354]
- G. Beltrame,
C. Brandolese, W. Fornaciari, F. Salice, D. Sciuto, and V. Trianni.
An assembly-level execution-time model for pipelined architectures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 195-200, San Jose, CA, November 4-8 2001.
- [355]
- G. Beltrame,
L. Fossati, and D. Sciuto.
Decision-theoretic design space exploration of multiporcessor platforms.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(7):1083-1095, July 2010.
- [356]
- L. Bening.
A two-state methodology for RTL logic simulation.
In Design Automation Conference, pages 672-677, New Orleans, LA, June
21-25 1999.
- [357]
- L. Benini,
M. Favalli, P. Olivo, and B. Ricco.
A novel approach to cost-effective estimate of power dissipation in CMOS ics.
In European Design Automation Conference (EDAC), pages 354-360,
1993.
- [358]
- L. Benini,
M. Favalli, and B. Ricco.
Analysis of hazard contributions to power dissipation in CMOS ics.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
27-32, Napa, CA, April 24-27 1994.
- [359]
- L. Benini,
P. Siegel, and G. De Micheli.
Saving power by synthesizing gate clocks for sequential circuits.
IEEE Design and Test of Computers, 11(4):32-40, December 1994.
- [360]
- L. Benini,
G. De Micheli, E. Macii, M. Poncino, and S. Quer.
System-level power optimization of special purpose applications: The beach
solution.
In 1997 International Symposium on Low Power Electronics and Design,
pages 24-29, Monterey, CA, August 18-20 1997.
- [361]
- L. Benini,
G. De Micheli, E. Macii, M. Poncino, and R. Scarsi.
Fast power estimation for deterministic input streams.
In IEEE/ACM International Conference on Computer-Aided Design, pages
494-501, San Jose, CA, November 9-13 1997.
- [362]
- L. Benini,
A. Bogliolo, S. Cavallucci, and B. Ricco.
Monitoring system activity for OS-directed dynamic power management.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 185-190, Monterey, CA, August 10-12 1998.
- [363]
- L. Benini,
A. Bogliolo, and G. De Micheli.
Dynamic power management of electronic systems.
In IEEE/ACM International Conference on Computer-Aided Design, pages
696-702, San Jose, CA, November 8-12 1998.
- [364]
- L. Benini,
R. Hodgson, and P. Siegel.
System-level power estimation and optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 173-178, Monterey, CA, August 10-12 1998.
- [365]
- L. Benini,
G. De Micheli, E. Macii, M. Poncino, and S. Quer.
Power optimization of core-based systems by address bus encoding.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(4):554-562, December 1998.
- [366]
- L. Benini,
A. Macii, E. Macii, M. Poncino, and R. Scarsi.
Synthesis of low-overhead interfaces for power-efficient communication over
wide buses.
In Design Automation Conference, pages 128-133, New Orleans, LA, June
21-25 1999.
- [367]
- L. Benini,
A. Bogliolo, and G. De Micheli.
A survey of design techniques for system-level dynamic power management.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):299-316, June 2000.
- [368]
- L. Benini,
A. Macii, E. Macii, M. Poncino, and R. Scarsi.
Architectures and synthesis algorithms for power efficient bus-interfaces.
IEEE Transactions on Computer-Aided Design, 19(9):969-980, September
2000.
- [369]
- L. Benini,
A. Macii, and M. Poncino.
A recursive algorithm for low-power memory partitioning.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 78-83, Italy, July 26-27 2000.
- [370]
- L. Benini,
G. De Micheli, A. Macii, E. Macii, M. Poncino, and R. Scarsi.
Glitch power minimization by selective gate freezing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):287-298, June 2000.
- [371]
- L. Benini,
G. De Micheli, E. Macii, M. Poncino, and R. Scarsi.
A multilevel engine for fast power simulation of realistic input streams.
IEEE Transactions on Computer-Aided Design, 19(4):459-472, April
2000.
- [372]
- L. Benini,
G. De Micheli, A. Lioy, E. Macii, G. Odasso, and M. Poncino.
Synthesis of power-managed sequential components based on computational kernel
extraction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(9):1118-1131, September 2001.
- [373]
- L. Benini,
G. De Micheli, and E. Macii.
Designing low-power circuits: practical recipes.
IEEE Circuits and Systems Magazine, 1(1):6-25, Q1 2001.
- [374]
- L. Benini,
A. Macii, E. Macii, and M. Poncino.
Minimizing memory acess energy in embedded systems by selective instruction
compression.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):521-531, October 2002.
- [375]
- L. Benini,
A. Galati, and A. Macii.
Energy-efficient data scrambling on memory-processor interfaces.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 26-29, Seoul, Korea, August 25-27 2003.
- [376]
- L. Benini,
D. Bruni, A. Macii, and E. Macii.
Memory energy minimization by data compression: algorithms, architectures and
implementation.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(3):255-268, March 2004.
- [377]
- L. Benini and G. De
Micheli.
State assignment for low power dissipation.
In IEEE 1994 Custom Integrated Circuits Conference, pages 136-139,
San Diego, CA, May 1-4 1994.
- [378]
- L. Benini and G. De
Micheli.
Automatic synthesis of low-power gated-clock finite-state machines.
IEEE Transactions on Computer-Aided Design, 15(6):630-643, June
1996.
- [379]
- L. Benini and G. De
Micheli.
System level power optimization: techniques and tools.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 288-293, San Diego, CA, August 16-17 1999.
- [380]
- J. Benkoski and
A. J. Strojwas.
A new approach to hierarchical and statistical timing simulations.
IEEE Transactions on Computer-Aided Design, CAD-6(6):1039-1052,
November 1987.
- [381]
- J. Benkoski and
A. J. Strojwas.
The role of timing verification in layout synthesis.
In 28th ACM/IEEE Design Automation Conference, pages 612-619, San
Francisco, CA, June 17-21 1991.
- [382]
- P. Benner,
S. Gugercin, and K. Willcox.
A survey or projection-based model reduction methods for parametric dynamical
systems.
SIAM Review, 57(4):483-531, December 2015.
- [383]
- T. R. Bennett,
J. M. Booker, S. Keller-McNulty, and N. D. Singpurwalla.
Testing the untestable: reliability in the 21st century.
IEEE Transactions on Reliability, 52(1):118-124, March 2003.
- [384]
- M. Benoit,
S. Taylor, D. Overhauser, and S. Rochel.
Power distribution in high-performance design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 274-278, Monterey, CA, August 10-12 1998.
- [385]
- D. Bera.
Detection and diagnosis of single faults in quantum circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 37(3):587-600, March 2018.
- [386]
- R. A.
Bergamaschi, D. Brand, L. Stok, M. Berkelaar, and S. Prakash.
Efficient use of large don't cares in high-level and logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
272-278, San Jose, CA, November 5-9 1995.
- [387]
- R. A.
Bergamaschi and Y. W. Jiang.
State-based power analysis for systems-on-chip.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
638-641, Anaheim, CA, June 2-6 2003.
- [388]
- R. A.
Bergamaschi and W. R. Lee.
Designing systems-on-chip using cores.
In Design Automation Conference, pages 420-425, Los Angeles, CA, June
5-9 2000.
- [389]
- R. A. Bergamaschi.
Behavioral network graph unifying the domains of high-level and logic
synthesis.
In Design Automation Conference, pages 213-218, New Orleans, LA, June
21-25 1999.
- [390]
- R. Bergamaschi.
The A to Z of socs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 791-798, San Jose, CA, November 10-14 2002.
- [391]
- J. P. Bergmann
and M. A. Horowitz.
Vex - A CAD toolbox.
In Design Automation Conference, pages 523-528, New Orleans, LA, June
21-25 1999.
- [392]
- M. R.
C. M. Berkelaar, P. H. W. Buurman, and J. A. G. Jess.
Computing the entire active area/power consumption versus delay tradeoff curve
for gate sizing with a piecewise linear simulator.
IEEE Transactions on Computer-Aided Design, 15(11):1423-1434,
November 1996.
- [393]
- D. Berleant and
J. Zhang.
Bounding the times to failure of 2-component systems.
IEEE Transactions on Reliability, 53(4):542-550, December 2004.
- [394]
- A. Berman and R. J.
Plemmons.
Nonnegative Matrices in the Mathematical Sciences.
Number 9 in Classics in applied mathematics. SIAM Publishing, Philadelphia, PA,
1994.
- [395]
- C. Leonard Berman.
Circuit width, register allocation, and ordered binary decision diagrams.
IEEE Transactions on Computer-Aided Design, 10(8):1059-1066, August
1991.
- [396]
- G. Bernacchia and M. C. Papaefthymiou.
Analytical macromodeling for high-level power estimation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
280-283, San Jose, CA, November 7-11 1999.
- [397]
- R. Bernardini and G. Cortelazzo.
Tools for designing chaotic systems for secure random number generation.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(5):552-565, May 2001.
- [398]
- A. Bernasconi, V. Ciriani, F. Luccio, and L. Pagli.
Three-level logic minimization based on function regularities.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(8):1005-1016, August 2003.
- [399]
- K. Bernstein, J. E. Bertsch, W. F. Clark, J. J. Ellis-Monaghan,
L. G. Heller, and E. J. Nowak.
Practical performance/power alternatives within an existing CMOS technology
generation.
In International Symposium on Low Power Electronics and Design, pages
365-370, Monterey, CA, August 12-14 1996.
- [400]
- K. Bernstein, P. Andry, J. Cann, P. Emma, D. Greenberg,
W. Haensch, M. Ignatowski, S. Koester, J. Magerlein, R. Puri, and A. Young.
Interconnects in the third dimension: design and process challenges for 3d ics.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
562-567, San Diego, CA, June 4-8 2007.
- [401]
- G. M.
Bernstein and M. A. Lieberman.
Secure random number generation using chaotic circuits.
IEEE Transactions on Circuits and Systems, 37(9):1157-1164, September
1990.
- [402]
- R. Berryhill and
A. Veneris.
Methodologies for diagnosis of unreachable states via property directed
reachability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 37(6):1298-1311, June 2018.
- [403]
- V. Bertacco and
M. Damiani.
The disjunctive decomposition of logic functions.
In IEEE/ACM International Conference on Computer-Aided Design, pages
78-82, San Jose, CA, November 9-13 1997.
- [404]
- V. Bertacco.
Humans for EDA and EDA for humans.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
729-733, San Francisco, CA, June 3-7 2012.
- [405]
- D. Bertozzi,
L. Benini, and B. Ricco'.
Parametric timing and power macromodels for high level simulation of low-swing
interconnects.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 307-312, Monterey, California, August 12-14 2002.
- [406]
- D. Bertozzi,
L. Benini, and G. De Micheli.
Error control schemes for on-chip communication links: the energy-reliability
tradeoff.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(6):818-831, June 2005.
- [407]
- R. M. Bevensee.
Probabilistic potential theory applied to electrical engineering problems.
In Proceedings of the IEEE, pages 423-437, April 1973.
- [408]
- W. T. Beyene.
Application of artifical neural networks to statistical analysis and nonlinear
modeling of high-speed interconnect systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):166-176, January 2007.
- [409]
- J. Bezanson,
A. Edelman, S. Karpinski, and V. B. Shah.
Julia: a fresh approach to numerical computing.
SIAM Review, 59(1):65-98, March 2017.
- [410]
- D. Bhaduri,
S. K. Shukla, P. S. Graham, and M. B. Gokhale.
Reliability analysis of large circuits using scalable techniques and tools.
IEEE Transactions on Circuits and Systems, 54(11):2447-2460, November
2007.
- [411]
- S. Bhanja and
N. Ranganathan.
Dependency preserving probabilistic modeling of switching activity using
bayesian networks.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
209-214, Las Vegas, NV, June 18-22 2001.
- [412]
- S. Bhanja and
N. Ranganathan.
Switching activity estimation of VLSI circuits using bayesian networks.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):558-567, August 2003.
- [413]
- S. Bhanja and
N. R. Ranganathan.
Cascaded bayesian inferencing for switching activity estimation with correlated
inputs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1360-1370, December 2004.
- [414]
- K. Bharath,
E. Engin, M. Swamminathan, K. Uriu, and T. Yamada.
Computationally efficient power integrity simulation for system-on-package
applications.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
612-617, San Diego, CA, June 4-8 2007.
- [415]
- K. Bharath,
E. Engin, and M. Swaminathan.
Automatic package and board decoupling capacitor placement using genetic
algorithms and M-FDM.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
560-565, Anaheim, CA, June 8-13 2008.
- [416]
- M. Bhardwaj,
R. Min, and A. P. Chandrakasan.
Quantifying and enhancing power awareness of VLSI systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(6):757-772, December 2001.
- [417]
- S. Bhardwaj,
S. B. K. Vrudhula, and D. Blaauw.
Estimation of signal arrival times in the presence of delay noise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 418-422, San Jose, CA, November 10-14 2002.
- [418]
- S. Bhardwaj,
S. B. K. Vrudhula, and D. Blaauw.
TAU: timing analysis under uncertainty.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 615-620, San Jose, CA, November 9-13 2003.
- [419]
- S. Bhardwaj, S. Vrudhula, and D. Blaauw.
Probability distribution of signal arrival times using bayesian networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(11):1784-1794, November 2005.
- [420]
- S. Bhardwaj, P. Ghanta, and S. Vrudhula.
A framework for statistical timing analysis using non-linear delay and slew
models.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 225-230, San Jose, CA, November 5-9 2006.
- [421]
- S. Bhardwaj, S. Vrudhula, P. Ghanta, and Y. Cao.
Modeling of intra-die process variations for accurate analysis and optimization
of nano-scale circuits.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
791-796, San Francisco, CA, July 24-28 2006.
- [422]
- S. Bhardwaj, S. Vrudhula, and A. Goel.
A unified approach for full chip statistical timing and leakage analysis of
nanoscale circuits considering intradie process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1812-1825, October 2008.
- [423]
- S. Bhardwaj and
S. Vrudhula.
Formalizing designer's preferences for multiattribute optimization with
application to leakage-delay tradeoffs.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 713-718, San Jose, CA, November 6-10 2005.
- [424]
- S. Bhardwaj and
S. B. K. Vrudhula.
Leakage minimization of nano-scale circuits in the presence of systematic and
random variations.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
541-546, Anaheim, CA, June 13-17 2005.
- [425]
- S. Bhardwaj and
S. Vrudhula.
Leakage minimization of digital circuits using gate sizing in the presence of
process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(3):445-455, March 2008.
- [426]
- S. Bhattacharjee and D. K. Pradhan.
LPRAM: a novel methodology for low-power high-performance RAM design with
testability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):637-651, May 2004.
- [427]
- M. Bhattacharya and P. Mazumder.
Augmentation of SPICE for simulation of circuits containing resonant
tunneling diodes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(1):39-50, January 2001.
- [428]
- A. J. Bhavnagarwala, B. L. Austin, K. A. Bowman, and J. D.
Meindl.
A minimum total power methodology for projecting limits on CMOS GSI.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):235-251, June 2000.
- [429]
- A. N. Bhoj and N. K. Jha.
Design of logic gates and flip-flops in high-performance finfet technology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(11):1975-1988, November 2013.
- [430]
- P. S.
Bhojwani, J. D. Lee, and R. N. Mahapatra.
SAPP: scalable and adaptable peak power management in nocs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 340-345, Portland, Oregon, August 27-29 2007.
- [431]
- S. Bhunia,
K. Roy, and J. Segura.
A novel wavelet transform based transient current analysis for fault detection
and localization.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
361-366, New Orleans, LA, June 10-14 2002.
- [432]
- S. Bhunia,
N. Banerjee, Q. Chen, H. Mahmoodi, and K. Roy.
A novel synthesis approach for active leakage power reduction using dynamic
supply gating.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
479-484, Anaheim, CA, June 13-17 2005.
- [433]
- S. Bhunia and K. Roy.
A novel wavelet transform-based transient current analysis for fault dectection
and localization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(4):503-507, April 2005.
- [434]
- Y. Bi, K. van der Kolk,
D. Ioan, and N. P. van der Meijs.
Sensitivity computation of interconnect capacitances with respect to geometric
parameters.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 209-212, San Jose, CA, October 27-29 2008.
- [435]
- X. Bi, Z. Sun, and
H. Li.
Probabilistic design methodology to improve run-time stability and performance
of STT-RAM caches.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 88-94, San Jose, CA, November 5-8 2012.
- [436]
- G. Biagetti,
S. Orcioni, L. Signoracci, C. Turchetti, P. Crippa, and M. Alessandrini.
Sisma: A statistical simulator for mismatch analysis of MOS ics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 490-496, San Jose, CA, November 10-14 2002.
- [437]
- G. Biagetti,
S. Orcioni, C. Turchetti, P. Crippa, and M. Alessandrini.
Sisma - a tool for efficient analysis of analog CMOS integrated circuits
affected by device mismatch.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(2):192-207, February 2004.
- [438]
- S. Bigalke,
J. Lienig, G. Jerke, J. Scheible, and R. Jancke.
The need and opportunities of electromigration-aware integrated circuit design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [439]
- S. Bilavarn,
G. Gogniat, J.-L. Philppe, and L. Bossuet.
Design space pruning through early estimations of area/delay tradeoffs for
FPGA implementations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):1950-1968, October 2006.
- [440]
- O. Billoint,
H. Sarhan, I. Rayane, M. Vinet, P. Batude, C. Fenouillet-Beranger, O. Rozeau,
G. Cibrario, F. Deprat, O. Turkyilmaz, S. Thuries, and F. Clermidy.
From 2d to monolithic 3d: design possibilities, expectations and challenges.
In ACM International Symposium on Physical Design 2015, page 127,
Monterey, California, March 29 - April 1 2015.
- [441]
- D. Bindel and A. Hood.
Localization theorems for nonlinear eigenvalue problems.
SIAM Review, 57(4):585-607, December 2015.
- [442]
- G. Bischoff and
R. Razdan.
Static charge delay analysis of MOS circuits.
In IEEE Custom Integrated Circuits Conference, pages 8.5.1-8.5.4,
1991.
- [443]
- L. Bisdounis, O. Koufopavlou, and S. Nikolaidis.
Accurate evaluation of CMOS short-circuit power dissipation for short-channel
devices.
In International Symposium on Low Power Electronics and Design, pages
189-192, Monterey, CA, August 12-14 1996.
- [444]
- L. Bisdounis, S. Nikolaidis, and O. Koufopavlou.
Propagation delay and short-circuit power dissipation modeling of the CMOS
inverter.
IEEE Transactions on Circuits and Systems - I: Fundamental Theory and
Applications, 45(3):259-270, March 1998.
- [445]
- B. Bishop,
V. Lyuboslavsky, N. Vijaykrishnan, and M. J. Irwin.
Design considerations for databus charge recovery.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(1):104-106, February 2001.
- [446]
- D. T. Blaauw,
A. Dharchoudhury, R. Panda, S. Sirichotiyakul, C. Oh, and T. Edwards.
Emerging power management tools for processor design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 143-148, Monterey, CA, August 10-12 1998.
- [447]
- D. Blaauw,
V. Zolotov, S. Sundareswaran, C. Oh, and R. Panda.
Slope propagation in static timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 338-343, San Jose, CA, November 5-9 2000.
- [448]
- D. Blaauw,
V. Zolotov, and S. Sundareswaran.
Slope propagation in static timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(10):1180-1195, October 2002.
- [449]
- D. Blaauw,
S. Sirichotiyakul, and C. Oh.
Driver modeling and alignment for worst-case delay noise.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(2):157-166, April 2003.
- [450]
- D. T. Blaauw,
C. Oh, V. Zolotov, and A. Dasgupta.
Static electromigration analysis for on-chip signal interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(1):39-48, January 2003.
- [451]
- D. Blaauw,
K. Chopra, A. Srivastava, and L. Scheffer.
Statistical timing analysis: from basic principles to state of the art.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(4):589-607, April 2008.
- [452]
- D. Blaauw and
K. Chopra.
CAD tools for variation tolerance.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
766-766, Anaheim, CA, June 13-17 2005.
- [453]
- J. R. Black.
Electromigration failure modes in aluminum metallization for semiconductor
devices.
In Proceedings of the IEEE, pages 1587-1594, September 1969.
- [454]
- R. D. Blanton,
X. Li, K. Mai, D. Marculescu, R. Marculescu, J. Paramesh, J. Schneider, and
D. E. Thomas.
Statistical learning in chip (SLIC).
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 664-669, Austin, TX, November 2-6 2015.
- [455]
- I. A. Blech.
Electromigration in thin aluminum films on titanium nitride.
Journal of Applied Physics, 47(4):1203-1208, April 1976.
- [456]
- K. Blutman,
H. Fatemi, A. Kapoor, A. B. Kahng, J. Li, and J. P. de Gyvez.
Logic design partitioning for stacked power domains.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(11):3045-3056, November 2017.
- [457]
- S. Bobba,
T. Thorp, K. Aingaran, and D. Lin.
IC power distribution challenges.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 643-650, San Jose, CA, November 4-8 2001.
- [458]
- S. Bobba and I. N. Hajj.
Estimation of maximum current envelope for power bus analysis and design.
In ACM/IEEE International Symposium on Physical Design, pages
141-146, Monterey, CA, April 6-8 1998.
- [459]
- S. Bobba and I. N. Hajj.
Maximum leakage power estimation for CMOS circuits.
In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages
116-124, Como, Italy, March 4-5 1999.
- [460]
- S. Bobba and I. N. Hajj.
Maximum voltage variation in the power distribution network of VLSI circuits
with RLC models.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 376-381, Huntington Beach, California, August 6-7
2001.
- [461]
- S. Bodapati and F. N.
Najm.
Pre-layout estimation of individual wire lengths.
In International Workshop on System-Level Interconnect Prediction,
pages 93-98, San Diego, CA, April 8-9 2000.
- [462]
- S. Bodapati and
F. N. Najm.
Frequency-domain supply current macro-model.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 295-298, Huntington Beach, California, August 6-7
2001.
- [463]
- S. Bodapati and
F. N. Najm.
Prelayout estimation of individual wire lengths.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(6):943-958, December 2001.
- [464]
- S. Bodapati and F. N.
Najm.
High-level current macro-model for power-grid analysis.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
385-390, New Orleans, LA, June 10-14 2002.
- [465]
- S. Bodapati and F. N.
Najm.
High-level current macro model for logic blocks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):837-855, May 2006.
- [466]
- P. Bogdan and Y. Xue.
Mathematical models and control algorithms for dynamic optimization of
multicore platforms: a complex dynamics approach.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 170-175, Austin, TX, November 2-6 2015.
- [467]
- A. Bogliolo, L. Benini, G. De Micheli, and B. Ricco.
Gate-level current waveform simulation of CMOS integrated circuits.
In International Symposium on Low Power Electronics and Design, pages
109-112, Monterey, CA, August 12-14 1996.
- [468]
- A. Bogliolo, L. Benini, and B. Ricco.
Power estimation of cell-based CMOS circuits.
In 33rd Design Automation Conference, pages 433-438, Las Vegas, NV,
June 3-7 1996.
- [469]
- A. Bogliolo,
L. Benini, G. De Micheli, and B. Ricco.
Gate-level power and current simulation of CMOS integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
5(4):473-488, December 1997.
- [470]
- A. Bogliolo, L. Benini, B. Ricco, and G. De Micheli.
Efficient switching activity computation during high-level synthesis of
control-dominated designs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 127-132, San Diego, CA, August 16-17 1999.
- [471]
- A. Bogliolo, R. Corgnati, E. Macii, and M. Poncino.
Parametrized RTL power models for combinational soft macros.
In IEEE/ACM International Conference on Computer-Aided Design, pages
284-287, San Jose, CA, November 7-11 1999.
- [472]
- A. Bogliolo, E. Macii, V. Mihailovici, and M. Poncino.
Combinational characterization-based power macro-models for sequential macros.
In Ninth International Workshop on Power and Timing optimization and
Simulation, pages 293-302, Kos, Greece, October 1999.
- [473]
- A. Bogliolo, R. Corgnati, E. Macii, and M. Poncino.
Parametrized RTL power models for soft macros.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(6):880-887, December 2001.
- [474]
- A. Bogliolo and
L. Benini.
Node sampling: a robust RTL power modeling approach.
In IEEE/ACM International Conference on Computer-Aided Design, pages
461-467, San Jose, CA, November 8-12 1998.
- [475]
- A. Bogliolo and
L. Benini.
Robust RTL power macromodels.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(4):578-581, December 1998.
- [476]
- A. Bogliolo.
Encodings for high-performance signaling.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 170-175, Huntington Beach, California, August 6-7
2001.
- [477]
- J. Bokor.
Prospects for emerging nanoelectronics in mainstream information processing
systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 647-648, San Jose, CA, November 5-9 2006.
- [478]
- M. Bolotski and
P. Alvelda.
Low-power miniaturized information display systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 279-281, Monterey, CA, August 10-12 1998.
- [479]
- A. Bona, M. Sami,
D. Sciuto, C. Silvano, V. Zaccaria, and R. Zafalon.
Energy estimation and optimization of embedded VLIW processors based on
instruction clustering.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
886-891, New Orleans, LA, June 10-14 2002.
- [480]
- B. N. Bond,
Z. Mahmood, Y. Li, R. Sredojevgic, A. Megretski, V. Stojanovic, Y. Avniel,
and L. Daniel.
Compact modeling of nonlinear analog circuits using system identification via
semidefinite programming and incremental stability certification.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(8):1149-1162, August 2010.
- [481]
- B. N. Bond and L. Daniel.
A piecewise-linear moment-matching approach to parametrized model-order
reduction for highly nonlinear systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(12):2116-2129, December 2007.
- [482]
- B. N. Bond and L. Daniel.
Stabilizing schemes for piecewise-linear reduced order models via projection
and weighting functions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 860-867, San Jose, CA, November 5-8 2007.
- [483]
- B. N. Bond and L. Daniel.
Guaranteed stable projection-based model reduction for indefinite and unstable
linear systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 728-735, San Jose, CA, November 10-13 2008.
- [484]
- B. N. Bond and L. Daniel.
Automated compact dynamical modeling: An enabling tool for analog designers.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
415-420, Anaheim, CA, June 13-18 2010.
- [485]
- M. Borah, R. M.
Owens, and M. J. Irwin.
Transistor sizing for low power CMOS circuits.
IEEE Transactions on Computer-Aided Design, 15(6):665-671, June
1996.
- [486]
- S. Borkar,
T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De.
Parameter variations and impact on circuits and microarchitecture.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
338-342, Anaheim, CA, June 2-6 2003.
- [487]
- S. Borkar,
T. Karnik, and V. De.
Design and reliability challenges in nanometer technologies.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 75-75,
San Diego, CA, June 7-11 2004.
- [488]
- S. Borkar.
Design challenges of technology scaling.
In IEEE/ACM International Symposium on Microarchitecture (MICRO-32),
pages 23-29, November 16-18 1999.
- [489]
- S. Borkar.
Thousand-core chips - a technology perspective.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
746-749, San Diego, CA, June 4-8 2007.
- [490]
- S. Borkar.
Design perspectives on 22nm CMOS and beyond.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 93-94,
San Francisco, CA, July 26-31 2009.
- [491]
- S. Borkar.
3d integration for energy efficient system design.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
214-219, San Diego, CA, June 5-9 2011.
- [492]
- A. K. Bose,
P. Kozak, C-Y Lo, H. N. Nham, E. Pacas-Skewes, and K. Wu.
A fault simulator for MOS LSI circuits.
In IEEE 19th Design Automation Conference, pages 400-409, June
1982.
- [493]
- G. Boselli,
G. Trucco, and V. Liberali.
Properties of digital switching currents in fully CMOS combinational logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(12):1625-1638, December 2010.
- [494]
- B. E. Boser.
From micro to nano: MEMS as an interface to the nano world.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 824-825, San Jose, CA, November 5-9 2006.
- [495]
- M. J. Bosley and F. P.
Lees.
A survey of simple transfer-function derivations from high-order state-variable
models.
Automata, 8:765-775, 1972.
- [496]
- C. S.
Bouganis, K. Pournara, and P. Y. K. Cheung.
Exploration of heterogeneous fpgas for mapping linear projection designs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(3):436-449, March 2010.
- [497]
- V. Bourenkov, K. G. McCarthy, and A. Mathewson.
MOS table models for circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):352-362, March 2005.
- [498]
- C. Bowen.
Walking a thin line: performance and quality grading vs. yield overcut.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [499]
- W. J. Bowhill and
et al.
Circuit implementation of a 300-mhz 64-bit second-generation CMOS alpha
CPU.
Digital Technical Journal, 7(1):100-118, July 1995.
- [500]
- K. A. Bowman,
B. L. Austin, J. C. Eble, X. Tang, and J. D. Meindl.
A physical alpha-power law MOSFET model.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 218-222, San Diego, CA, August 16-17 1999.
- [501]
- K. A. Bowman,
X. Tang, J. C. Eble, and J. D. Meindl.
Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit
performance.
IEEE Journal of Solid-State Circuits, 35(8):1186-1193, August
2000.
- [502]
- K. A. Bowman,
S. G. Duvall, and J. D. Meindl.
Impact of die-to-die and within-die parameter fluctuations on the maximum clock
frequency distribution.
In IEEE International Solid-State Circuits Conference (ISSCC), pages
278-279, San Francisco, CA, February 4-8 2001.
- [503]
- K. A. Bowman,
S. B. Samaan, and N. Z. Hakim.
Maximum clock frequency distribution model with practical VLSI design
considerations.
In International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 183-191, Austin, TX, May 17-20 2004.
- [504]
- K. Bowman,
J. Tschanz, M. Khellah, M. Ghoneima, Y. I. Ismail, and V. De.
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 79-84, Tegernsee, Germany, October 4-6 2006.
- [505]
- K. A. Bowman,
A. R. Alameldeen, S. T. Srinivasan, and C. B. Wilkerson.
Impact of die-to-die and within-die parameter variations on the throughput
distribution of multi-core processors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 50-55, Portland, Oregon, August 27-29 2007.
- [506]
- K. Bowman,
J. Tschanz, C. Wilkerson, S.-L. Lu, T. Karnik, V. De, and S. Borkar.
Circuit techniques for dynamic variation tolerance.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 4-7,
San Francisco, CA, July 26-31 2009.
- [507]
- K. A. Bowman,
A. R. Alameldeen, S. T. Srinivasan, and C. B. Wilkerson.
Impact of die-to-die and within-die parameter variations on the clock frequency
and throughput of multi-core processors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(12):1679-1690, December 2009.
- [508]
- K. A. Bowman and J. D.
Meindl.
Impact of within-die parameter fluctuations on future maximum clock frequency
distributions.
In IEEE Custom Integrated Circuits Conference (CICC), pages 229-232,
2001.
- [509]
- K. A. Bowman and J. W.
Tschanz.
Resilient microprocessor design for improving performance and energy
efficiency.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 85-88, San Jose, CA, November 7-11 2010.
- [510]
- S. Boyd, L. El
Ghaoui, E. Feron, and V. Balakrishnan.
Linear matrix inequalities in system and control theory.
Society for Industrial and Applied Mathematics (SIAM), Philadelphia, PA,
1994.
- [511]
- S. Boyd,
L. Vandenberghe, A. El Gamal, and S. Yun.
Design of robust global power and ground networks.
In ACM/IEEE International Symposium on Physical Design, pages 60-65,
Sonoma, CA, 2001.
- [512]
- J. P. Boyd.
Finding the zeros of a univariate equation: proxy rootfinders, chebyshev
interpolation, and the companion matrix.
SIAM Review, 55(2):375-396, June 2013.
- [513]
- E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh.
Optimal integer delay budgeting on directed acyclic graphs.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
920-925, Anaheim, CA, June 2-6 2003.
- [514]
- K. Brace, R. L.
Rudell, and R. E. Bryant.
Efficient implementation of a BDD package.
In 27th ACM/IEEE Design Automation Conference, pages 40-45, Orlando,
FL, June 24-28 1990.
- [515]
- H. G. Brachtendorf, R. Melville, P. Feldmann, and S. Lampe.
Homotopy method for finding the steady states of oscillators.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(6):867-878, June 2014.
- [516]
- J. E. Bracken,
V. Raghavan, and R. A. Rohrer.
Extension of the asymptotic waveform evaluation technique with the method of
characteristics.
In IEEE/ACM International Conference on Computer-Aided Design, pages
71-75, Santa Clara, CA, November 8-12 1992.
- [517]
- A. R.
Brahmbhatt, J. Zhang, Q. Wu, and Q. Qiu.
Low-power bus encoding using an adaptive hybrid algorithm.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
987-990, San Francisco, CA, July 24-28 2006.
- [518]
- A. Brambilla, A. Premoli, and G. Storti-Gajani.
Recasting modified nodal analysis to improve reliability in numerical circuit
simulation.
IEEE Transactions on Circuits and Systems, 52(3):522-534, March
2005.
- [519]
- A. Brambilla and
D. D'Amore.
Energy-based control of numerical errors in time-domain simulation of dynamic
circuits.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(5):543-551, May 2001.
- [520]
- A. Brambilla
and P. Maffezzoni.
Statistical method for the analysis of interconnect delay in submicrometer
layouts.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(8):957-966, August 2001.
- [521]
- A. Brambilla and G. Storti-Gajani.
Frequency warping in time-domain circuit simulation.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(7):904-913, July 2003.
- [522]
- D. Brand, R. A.
Bergamaschi, and L. Stok.
Don't cares in synthesis: theoretical pitfalls and practical solutions.
IEEE Transactions on Computer-Aided Design, 17(4):285-304, April
1998.
- [523]
- D. Brand and
C. Visweswariah.
Inaccuracies in power estimation during logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
388-394, San Jose, CA, November 10-14 1996.
- [524]
- D. Brand.
Detecting sneak paths in transistor networks.
IEEE Transactions on Computers, C-35(3):274-278, March 1986.
- [525]
- D. Brand.
Exhaustive simulation need not require an exponential number of tests.
In IEEE/ACM International Conference on Computer-Aided Design, pages
98-101, Santa Clara, CA, November 8-12 1992.
- [526]
- Y. Brandman,
A. Orlitsky, and J. Hennessy.
A spectral lower bound technique for the size of decision trees and two-level
AND/OR circuits.
IEEE Transactions on Computers, 39(2):282-287, February 1990.
- [527]
- C. Brandolese, W. Fomaciani, F. Salice, and D. Suito.
An instruction-level functionality-based energy estimation model for 32-bits
microprocessors.
In Design Automation Conference, pages 346-351, Los Angeles, CA, June
5-9 2000.
- [528]
- C. Brandolese, F. Salice, W. Fornaciari, and D. Sciuto.
Static power modeling of 32-bit microprocessors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(11):1306-1316, November 2002.
- [529]
- C. Brandolese, W. Fornaciari, and F. Salice.
An area estimation methodology for FPGA based designs at systemc-level.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
129-132, San Diego, CA, June 7-11 2004.
- [530]
- F. H. Branin, Jr.
Transient analysis of lossless transmission lines.
In Proceedings of the IEEE, pages 2012-2013, November 1967.
- [531]
- F. H. Branin, Jr.
The analysis and design of power distribution nets on LSI chips.
In IEEE International Conference on Circuits and Computers, pages
785-790, Port Chester, NY, October 1-3 1980.
- [532]
- R. B.
Brashear, D. R. Holberg, M. Ray Mercer, and L. T. Pillage.
ETA: Electrical-level timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
258-262, Santa Clara, CA, November 8-12 1992.
- [533]
- R. K. Brayton,
A. J. Hoffman, and T. R. Scott.
A theorem on inverses of convex sets of real matrices with application to the
worst case DC problem.
IEEE Transactions on Circuits and Systems, 24(8):409-415, August
1977.
- [534]
- Robert K.
Brayton, Gary D. Hachtel, Curtis T. McMullen, and Alberto L.
Sangiovanni-Vincentelli.
Logic Minimization Algorithms for VLSI Synthesis.
Kluwer Academic Publishers, Hingham, MA, 1984.
- [535]
- R. K. Brayton.
Compatible observability don't cares revisited.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 618-623, San Jose, CA, November 4-8 2001.
- [536]
- J. P. Brennan,
A. Dean, S. Kenyon, and S. Ventrone.
Low power methodology and design techniques for processor design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 268-273, Monterey, CA, August 10-12 1998.
- [537]
- U. Brenner.
Boonplace legalization: minimizing movement by iterative augmentation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(8):1215-1227, August 2013.
- [538]
- M. A. Breuer,
M. Sarrafzadeh, and F. Somenzi.
Fundamental CAD algorithms.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1449-1475, December 2000.
- [539]
- M. A. Breuer and
R. L. Harrison.
Procedures for eliminating static and dynamic hazards in test generation.
IEEE Transactions on Computers, C-23(10):1069-1974, October 1974.
- [540]
- M. Breuer.
Hardware that produces bounded rather than exact results.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
871-876, Anaheim, CA, June 13-18 2010.
- [541]
- F. Brglez,
D. Bryan, and K. Kozminski.
Combinational profiles of sequential benchmark circuits.
In IEEE International Symposium on Circuits and Systems, pages
1929-1934, 1989.
- [542]
- F. Brglez and
H. Fujiwara.
A neutral netlist of 10 combinational benchmark circuits and a target
translator in fortran.
In IEEE International Symposium on Circuits and Systems (ISCAS-85),
pages 663-698,, June 1985.
- [543]
- F. Brglez.
On testability analysis of combinational networks.
In IEEE International Symposium on Circuits and Systems, pages
221-225, 1984.
- [544]
- J. Briaire and K. S.
Krisch.
Principles of substrate crosstalk generation in CMOS circuits.
IEEE Transactions on Computer-Aided Design, 19(6):645-653, June
2000.
- [545]
- L. M. Brocco,
S. P. McCormick, and J. Allen.
Macromodeling CMOS circuits for timing simulation.
IEEE Transactions on Computer-Aided Design, 7(12):1237-1249, December
1988.
- [546]
- R. W.
Broderesen, M. A. Horowitz, D. Markovic, B. Nikolic, and V. Stojanovic.
Methods for true power minimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 35-42, San Jose, CA, November 10-14 2002.
- [547]
- R. W.
Brodersen, A. Chandrakasan, and S. Sheng.
Technologies for personal communications.
In 1991 Symposium on VLSI Circuits, pages 5-9, Tokyo, Japan, 1991.
- [548]
- S. Brokar.
Electronics beyond nano-scale CMOS.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
807-808, San Francisco, CA, July 24-28 2006.
- [549]
- R. F. Brown.
Model stability in use of moments to estimate pulse transfer functions.
Electronics Letters, 7(19):587-589, September 23 1971.
- [550]
- S. D. Brown.
An overview of technology, architecture and CAD tools for programmable logic
devices.
In IEEE Custom Integrated Circuits Conference, pages 69-76, 1994.
- [551]
- M. Brownlee,
P. K. Hanumolu, U.-K. Moon, and K. Mayaram.
The effect of power supply noise on right oscillator phase noise.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 225-228, Montreal, Quebec, June 20-23 2004.
- [552]
- D. Bruni,
G. Oliveri, A. Bogliolo, and L. Benini.
Delay-sensitive power estimation at the register-transfer level.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 1031-1034, St. Julian, Malta, September 2-5 2001.
- [553]
- L. Brusamarello, R. da Silva, G. I. Wirth, and R. A. L. Reis.
Probabilistic approach for yield analysis of dynamic logic circuits.
IEEE Transactions on Circuits and Systems, 55(8):2238-2248, September
2008.
- [554]
- K. Bryan and T. Leise.
Making do with less: an introduction to compressed sensing.
SIAM Review, 55(3):547-566, September 2013.
- [555]
- R. E. Bryant and Y-A.
Chen.
Verification of arithmetic circuits with binary moment diagrams.
In 32nd Design Automation Conference, pages 535-541, San Francisco,
CA, June 12-16 1995.
- [556]
- R. E. Bryant.
An algorithm for MOS logic simulation.
LAMDA, (Fourth Quarter):46-53, 1980.
- [557]
- R. E. Bryant.
A switch-level model and simulator for MOS digital systems.
IEEE Transactions on Computers, C-33(2):160-177, February 1984.
- [558]
- R. E. Bryant.
Graph-based algorithms for boolean function manipulation.
IEEE Transactions on Computers, C-35(8):677-691, August 1986.
- [559]
- R. E. Bryant.
Algorithmic aspects of symbolic switch network analysis.
IEEE Transactions on Computer-Aided Design, CAD-6(4):618-633, July
1987.
- [560]
- R. E. Bryant.
Boolean analysis of MOS circuits.
IEEE Transactions on Computer-Aided Design, CAD-6(4):634-649, July
1987.
- [561]
- R. E. Bryant.
A survey of switch-level algorithms.
IEEE Design & Test of Computers, 4(4):26-40, August 1987.
- [562]
- R. E. Bryant.
Binary decision diagrams and beyond: enabling technologies for formal
verification.
In IEEE/ACM International Conference on Computer-Aided Design, pages
236-243, San Jose, CA, November 5-9 1995.
- [563]
- I. Brynjolfson
and Z. Zilic.
Dynamic clock management for low power applications in fpgas.
In IEEE Custom Integrated Circuits Conference (CICC), pages
7.3.1-7.3.4, 2000.
- [564]
- M. Bucci,
L. Germani, R. Luzzi, P. Tommasino, A. Trifiletti, and M. Varanonuovo.
A high-speed IC random-number source for smartcard microcontrollers.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(11):1373-1380, November 2003.
- [565]
- M. Bucci,
L. Giancane, R. Luzzi, G. Scotti, and A. Trifiletti.
Delay-based dual-rail precharge logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(7):1147-1153, July 2011.
- [566]
- P. Buch, C. K.
Lennard, and A. R. Newton.
Engineering change for power optimization using global sensitivity and
synthesis flexibility.
In 1997 International Symposium on Low Power Electronics and Design,
pages 88-91, Monterey, CA, August 18-20 1997.
- [567]
- P. Buch,
A. Narayan, A. R. Newton, and A. Sangiovanni-Vincentelli.
Logic synthesis for large pass transistor circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
663-670, San Jose, CA, November 9-13 1997.
- [568]
- R. K.
Budhathoki, M. Pd. Sah, S. P. Adhikari, H. Kim, and L. Chua.
Composite behavior of multiple memristor circuits.
IEEE Transactions on Circuits and Systems, 60(10):2688-2700, October
2013.
- [569]
- M. Budnik,
A. Raychowdhury, A. Bansal, and K. Roy.
A high density, carbon nanotube capacitor for decoupling applications.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
935-938, San Francisco, CA, July 24-28 2006.
- [570]
- M. M. Budnik and K. Roy.
A power delivery and decoupling network minimizing ohmic loss and supply
voltage variation in silicon nanoscale technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(12):1336-1346, December 2006.
- [571]
- D. Bufistov,
J. Cortadella, M. Kishinevsky, and S. Sapatnekar.
A general model for performance optimization of sequential systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 362-369, San Jose, CA, November 5-8 2007.
- [572]
- D. E.
Bufistov, J. Cortadella, M. Galceran-Oms, J. Julvez, and M. Kishinevsky.
Retiming and recycling for elastic systems with early evaluation.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
288-291, San Francisco, CA, July 26-31 2009.
- [573]
- V. Bulovi,
I. Kymissis, I. Nausieda, K. Ryu, A. Wang, A. I. Akinwande, and C. G. Sodini.
Molecular organic electronic circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 830-831, San Jose, CA, November 5-9 2006.
- [574]
- J. Bunda, W. C.
Athas, and D. Fussell.
Evaluating power implications of CMOS microprocessor design decisions.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
147-152, Napa, CA, April 24-27 1994.
- [575]
- W. L Buntine,
L. Su, A. R. Newton, and A. Mayer.
Adaptive methods for netlist partitioning.
In IEEE/ACM International Conference on Computer-Aided Design, pages
356-363, San Jose, CA, November 9-13 1997.
- [576]
- A. Buonomo and A. L.
Schiavo.
A constructive method for finding the periodic response of nonlinear circuits.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(7):885-893, July 2003.
- [577]
- R. Burch,
J. Hall, F. Najm, D. Hocevar, P. Yang, and M. McGraw.
A CAD system for measuring voltage drop and electromigration in VLSI
metallization patterns.
Texas Instruments Technical Journal, 5(3):74-84, May-June 1988.
- [578]
- R. Burch,
F. Najm, P. Yang, and D. Hocevar.
Pattern-independent current estimation for reliability analysis of CMOS
circuits.
In 25th ACM/IEEE Design Automation Conference, pages 294-299,
Anaheim, CA, June 12-15 1988.
- [579]
- R. Burch, F. Najm,
P. Yang, and T. Trick.
Mcpower: A monte carlo approach to power estimation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
90-97, Santa Clara, CA, November 8-12 1992.
- [580]
- R. Burch, F. Najm,
P. Yang, and T. Trick.
A monte carlo approach for power estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
1(1):63-71, March 1993.
- [581]
- T. D. Burd and R. W.
Brodersen.
Design issues for dynamic voltage scaling.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 9-14, Italy, July 26-27 2000.
- [582]
- A. Burg,
C. Benkeser, C. Roth, and G. Karakonstantis.
On the exploitation of the inherent error resilience of wireless systems under
unreliable silicon.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
510-515, San Francisco, CA, June 3-7 2012.
- [583]
- D. Burke and T. Smy.
Thermal models for optical circuit simulation using a finite cloud method and
model reduction techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(8):1177-1186, August 2013.
- [584]
- T. M. Burks, K. A.
Sakallah, and T. N. Mudge.
Critical paths in circuits with level-sensitive latches.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
3(2):273-291, June 1995.
- [585]
- T. M. Burks and K. A.
Sakallah.
Min-max linear programming and the timing analysis of digital circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
152-155, Santa Clara, CA, November 7-11 1993.
- [586]
- W. P.
Burleson, M. Ciesielski, F. Klass, and W. Liu.
Wave-pipelining: A tutorial and research survey.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(3):464-474, September 1998.
- [587]
- J. R. Burnham,
C.-K. K. Yang, and H. Hindi.
A stochastic jitter model for analyzing digital timing-recovery circuits.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
116-121, San Francisco, CA, July 26-31 2009.
- [588]
- S. M. Burns,
M. Ketkar, N. Menezes, K. A. Bowman, J. W. Tschanz, and V. De.
Comparative analysis of conventional and statistical design techniques.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 31-36, Austin, Texas,
February 26-27 2007.
- [589]
- S. M. Burns,
M. Ketkar, N. Menezes, K. A. Bowman, J. W. Tschanz, and V. De.
Comparative analysis of conventional and statistical design techniques.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
238-243, San Diego, CA, June 4-8 2007.
- [590]
- J. Burns,
G. Carpenter, E. Kursun, R. Puri, J. Warnock, and M. Scheuermann.
Design, CAD and technology challenges for future processors: 3d perspectives.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
212-212, San Diego, CA, June 5-9 2011.
- [591]
- S. Bush.
Automatic generation of gate level models with accurate timing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 52-55, 1987.
- [592]
- M. Butts,
A. DeHon, and S. C. Goldstein.
Molecular electronics: Devices, systems and tools for gigagate, gigabit chips.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 433-440, San Jose, CA, November 10-14 2002.
- [593]
- K. M.
Buyuksahin, P. Patra, and F. N. Najm.
ESTIMA: an architectural-level power estimator for multi-ported pipelines
register files.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 294-297, Seoul, Korea, August 25-27 2003.
- [594]
- K. M. Buyuksahin
and F. N. Najm.
High-level power estimation with interconnect effects.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 197-202, Italy, July 26-27 2000.
- [595]
- K. M. Buyuksahin
and F. N. Najm.
High-level area estimation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 271-274, Monterey, California, August 12-14 2002.
- [596]
- K. M. Buyuksahin
and F. N. Najm.
Early power estimation for VLSI circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):1076-1088, July 2005.
- [597]
- R. H. Byrd, G. D.
Hachtel, M. R. Lightner, and M. H. Heydemann.
Switch level simulation: models, theory, and algorithms.
In A. L. Sangiovanni-Vincentelli, editor, Advances in Computer-Aided
Engineering Design, pages 93-148. JAI Press Inc., 1985.
- [598]
- E. Cai, D. Stamoulis,
and D. Marculescu.
Exploring aging deceleration in finfet-based multi-core systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [599]
- J-P. Caisso,
E. Cerny, and N. C. Rumin.
A recursive technique for computing delays in series-parallel MOS transistor
circuits.
IEEE Transactions on Computer-Aided Design, 10(5):589-595, May
1991.
- [600]
- N. Calazans,
R. Jacobi, Q. Zhang, and C. Trullemans.
Improving bdds manipulation through incremental reduction and enhanced
heuristics.
In IEEE Custom Integrated Circuits Conference, pages 11.3.1-11.3.5,
1991.
- [601]
- A. E.
Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, and A. Zelikovsky.
On wirelength estimation for row-based placement.
In ACM/IEEE International Symposium on Physical Design, pages 4-11,
Monterey, CA, April 6-8 1998.
- [602]
- A. E.
Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, and A. Zelikovsky.
On wirelength estimations for row-based placement.
IEEE Transactions on Computer-Aided Design, 18(9):1265-1278,
September 1999.
- [603]
- B. H. Calhoun,
F. A. Honore, and A. Chandrakasan.
Design methodology for fine-grained leakage control in MTCMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 104-109, Seoul, Korea, August 25-27 2003.
- [604]
- B. H. Calhoun,
A. Wang, N. Verma, and A. Chandrakasan.
Sub-threshold design: the challenges of minimizing circuit energy.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 366-368, Tegernsee, Germany, October 4-6 2006.
- [605]
- B. H. Calhoun
and A. Chandrakasan.
Characterizing and modeling minimum energy operation for subthreshold circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 90-95, Newport Beach, CA, August 9-11 2004.
- [606]
- B. H. Calhoun and
K. Craig.
Flexible on-chip power delivery for energy efficient heterogeneous systems.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [607]
- A. Calimera,
R. I. Bahar, E. Macii, and M. Poncino.
Temperature-insensitive dual-vth synthesis for nanometer CMOS technologies
under inverse temperature dependence.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(11):1608-1620, November 2010.
- [608]
- N. Callegari, P. Bastani, L.-C. Wang, and M. S. Abadir.
A statistical diagnosis approach for analyzing design - silicon timing
mismatch.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(11):1728-1741, November 2009.
- [609]
- N. Callegari, L.-C. Wang, and P. Bastani.
Speedpath analysis based on hypothesis pruning and ranking.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
346-351, San Francisco, CA, July 26-31 2009.
- [610]
- R. Cammarota, I. Banerjee, and O. Rosenberg.
Machine learning IP protection.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [611]
- D. Van
Campenhout, T. Mudge, and K. A. Sakallah.
Timing verification of sequential dynamic circuits.
IEEE Transactions on Computer-Aided Design, 18(5):645-658, May
1999.
- [612]
- P. Camurati,
P. Prinetto, and M. Sonza Reorda.
Random testability analysis : comparing and evaluating existing approaches.
In IEEE International Conference on Computer Design, pages 70-73,
1988.
- [613]
- A. C. Cangellaris.
Confronting and exploiting operating environment uncertainty in predictive
analysis of signal integrity.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 496, San Jose, CA, November 5-8 2012.
- [614]
- F. Cannillo,
C. Toumazou, and T. S. Lande.
Nanopower subthreshold MCML in submicrometer CMOS technology.
IEEE Transactions on Circuits and Systems, 56(8):1598-1611, August
2009.
- [615]
- R. Y. Cannon and K. D.
Brown.
Equation based timing: methodology and model for cell libraries.
In IEEE Custom Integrated Circuits Conference, pages 367-370, Santa
Clara, CA, May 1-4 1995.
- [616]
- M.-A. Cantin,
Y. Savaria, D. Prodanos, and P. Lavoie.
A metric for automatic word-length determination of hardware datapaths.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2228-2231, October 2006.
- [617]
- A. Cao, A. Adalal,
J. Bauman, P. Delisle, P. Dedood, P. Donehue, M. Dell'OcaKhouja, T. Doan,
M. Doreswamy, P. Ferolito, O. Geva, D. Greenhill, S. Gopaladhine, J. Irwin,
L. Lev, J. MacDonald, M. Ma, S. Mitra, P. Patel, A. Prabhu, et al.
CAD methodology for the design of the ultrasparc-I microprocessor at SUN
microsystems inc.
In 32nd Design Automation Conference, pages 19-22, San Francisco, CA,
June 12-16 1995.
- [618]
- Y. Cao, C. Hu,
X. Huang, A. B. Kahng, S. Muddu, D. Stroobandt, and D. Sylvester.
Effects of global interconnect optimizations on performance estimation of deep
submicron design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 56-61, San Jose, CA, November 5-9 2000.
- [619]
- Y. Cao, X. Huang,
N. Chang, S. Lin, O. S. Nakagawa, W. Xie, and C. Hu.
Effective on-chip inductance modeling for muliple signal lines and application
on repeater insertion.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 185-190, San Jose, CA, March 26-28 2001.
- [620]
- Y. Cao, Y.-M. Lee,
T.-H. Chen, and C. C.-P. Chen.
Hiprime: Hierarchical and passivity reserved interconnect macromodeling engine
for RLKC power delivery.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
379-384, New Orleans, LA, June 10-14 2002.
- [621]
- Y. Cao, C. Hu,
X. Huang, A. B. Kahng, I. L. Markov, M. Oliver, D. Stroobandt, and
D. Sylvester.
Improved a priori interconnect predictions and technology extrapolation in the
GTX system.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
11(1):3-14, February 2003.
- [622]
- Y. Cao, X.-D. Yang,
X. Huang, and D. Sylvester.
Switch-factor based loop RLC modeling for efficient timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 848-853, San Jose, CA, November 9-13 2003.
- [623]
- Y. Cao, X. Yang,
X. Huang, and D. Sylvester.
Switch-factor based loop RLC modeling for efficient timing analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(9):1072-1078, September 2005.
- [624]
- K. Cao, S. Dobre, and
J. Hu.
Standard cell characterization considering lithography induced variations.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
801-804, San Francisco, CA, July 24-28 2006.
- [625]
- Y. Cao and L. T. Clark.
Mapping statistical process variations toward circuit performance variability:
an analytical modeling approach.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
658-663, Anaheim, CA, June 13-17 2005.
- [626]
- Y. Cao and L. T. Clark.
Mapping statistical process variations toward circuit performance variability:
An analytical modeling approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(10):1866-1873, October 2007.
- [627]
- A. Cao and C.-K. Koh.
Post-layout logic optimization of domino circuits.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
820-825, San Diego, CA, June 7-11 2004.
- [628]
- Y. Cao and H. Yasuura.
A system-level energy minimization approach using datapath width optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 231-236, Huntington Beach, California, August 6-7
2001.
- [629]
- L. Cao.
Circuit power estimation using pattern recognition techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 412-417, San Jose, CA, November 10-14 2002.
- [630]
- M. Capobianchi, V. Labay, F. Shi, and G. Mizushima.
Simulating the electrical behaviour of integrated circuit devices in the
presence of thermal interactions.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2231-2241, October 2006.
- [631]
- L. Capodieci, P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang.
Toward a methodology for manufacturability-driven design rule exploration.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
311-316, San Diego, CA, June 7-11 2004.
- [632]
- J.-A.
Carballo, J. L. Burns, S.-M. Yoo, I. Vo, and V. R. Norman.
A semi-custom voltage-island technique and its application to high-speed serial
links.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 60-65, Seoul, Korea, August 25-27 2003.
- [633]
- F. Carbognani, F. Buergin, N. Felber, H. Kaeslin, and
W. Fichtner.
Transmission gates combined with level-restoring CMOS gates reduce glitches
in low-power low-frequency multipliers.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(7):830-836, July 2008.
- [634]
- J. Carletta,
R. Veillette, F. Krach, and Z. Fang.
Determining appropriate precisions for signals in fixed-point IIR filters.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
656-661, Anaheim, CA, June 2-6 2003.
- [635]
- L. P. Carloni,
P. C. McGeer, A. Saldanha, and A. L. Sangiovanni-Vincentelli.
Trace driven logic synthesis - application to power minimization.
In IEEE/ACM International Conference on Computer-Aided Design, pages
581-588, San Jose, CA, November 9-13 1997.
- [636]
- J. Carmona,
J.-M. Colom, J. Cortadella, and F. Garcia-Valles.
Synthesis of asynchronous controllers using integer linear programming.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1637-1651, September 2006.
- [637]
- J. Carmona,
J. Cortadella, Y. Takada, and F. Peper.
From molecular interactions to gates: a systematic approach.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 891-898, San Jose, CA, November 5-9 2006.
- [638]
- D. De Caro.
Glitch-free NAND-based digitally controlled delay-lines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(1):55-66, January 2013.
- [639]
- J. A. Carrasco and
V. Sune.
An ROBDD-based combinatorial method for the evaluation of yield of
defect-tolerant systems-on-chip.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):207-220, February 2009.
- [640]
- B. Carre.
Graphs and networks.
Clarendon Press-Oxford, Oxford, 1979.
- [641]
- H. Caruso.
The ESS muddle: physics vs relics.
In Annual Reliability and Maintainability Symposium, pages 233-241,
Washington, DC, January 16-19 1995.
- [642]
- G. Casinovi and A. Sangiovanni-Vincentelli.
A macromodeling algorithm for analog circuits.
IEEE Transactions on Computer-Aided Design, 10(2):150-160, February
1991.
- [643]
- G. Casinovi and
C. Young.
Estimation of power dissipation in switched-capacitor circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(12):1625-1636, December 2003.
- [644]
- P. Caspi, A. Mili,
and Ch. Robach.
An information measure on nets - application to the testability of digital
systems.
In B. Dubuisson, editor, Information and Systems, pages 35-39.
Pergamon, New York, NY, 1978.
- [645]
- M. R. Casu,
M. Graziano, G. Masera, G. Piccinini, and M. Zamboni.
An electromigration and thermal model of power wires for a priori high-level
reliability prediction.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):349-358, April 2004.
- [646]
- B. Catanzaro, K. Keutzer, and B.-Y. Su.
Parallelizing CAD: a timely research agenda for EDA.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages 12-17,
Anaheim, CA, June 8-13 2008.
- [647]
- S. Cauley,
V. Balakrishnan, and C.-K. Koh.
A parallel direct solver for the simulation of large-scale power/ground
networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):636-641, April 2010.
- [648]
- E. Cerny, J. P.
Hayes, and N. C. Rumin.
Accuracy of magnitude-class calculations in switch-level modeling.
IEEE Transactions on Computer-Aided Design, 11(4):443-452, April
1992.
- [649]
- E. Cerny and J. Gecsei.
Simulation of MOS circuits by decision diagrams.
IEEE Transactions on Computer-Aided Design, CAD-4(4):685-693, October
1985.
- [650]
- E. Cerny and C. Mauras.
Tautology checking using cross-controllability and cross-observability
relations.
In IEEE International Conference on Computer-Aided Design, pages
34-37, Santa Clara, CA, November 11-15 1990.
- [651]
- S. Cha, T. Liu, and
L. Milor.
Negative bias temperature instability and gate oxide breakdown modeling in
circuits with die-to-die calibration through power supply and ground signal
measurements.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(8):2271-2284, August 2017.
- [652]
- N. Chabini and W. Wolf.
Reducing dynamic power consumption in synchronous sequential digital designs
using retiming and supply voltage scaling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(6):573-589, June 2004.
- [653]
- D. Chai,
A. Kondratyev, Y. Ran, K. H. Tseng, Y. Watanabe, and M. Marek-Sadowska.
Temporofunctional crosstalk noise analysis.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
860-863, Anaheim, CA, June 2-6 2003.
- [654]
- W. Chai and D. Jiao.
Direct matrix solution of linear complexity for surface integral-equation based
impedance extraction of high bandwidth interconnects.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
206-211, San Diego, CA, June 5-9 2011.
- [655]
- G. J. Chaitin.
Randomness and mathematical proof.
Scientific American, 232(5):47-52, May 1975.
- [656]
- G. R. Chaji and S. M.
Fakhraie.
A low-power high-performance digital circuit for deep submicron techniques.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 123-126, Quebec City, Quebec, June 19-22 2005.
- [657]
- C. Chakrabarti, T. Mudge, S. Mahlke, Y. Park, M. Woh,
R. Dreslinski, S. Seo, and D. Blaauw.
Process variation in near-threshold wide SIMD architectures.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
980-987, San Francisco, CA, June 3-7 2012.
- [658]
- K. Chakrabarty, R. B. Fair, and J. Zeng.
Design tools for digital microfluidic biochips: toward functional
diversification and more than moore.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(7):1001-1017, July 2010.
- [659]
- K. Chakrabarty.
Design automation and test solutions for digital microfluidic biochips.
IEEE Transactions on Circuits and Systems, 57(1):4-17, January
2010.
- [660]
- A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram,
L. Benini, A. Macii, E. Macii, and M. Poncino.
Dynamic thermal clock skew compensation using tunable delay buffers.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(6):639-649, June 2008.
- [661]
- S. Chakraborty, A. Annaswamy, L. Thiele, D. Goswami, P. Kumar,
and K. Lampka.
A hybrid approach to cyber-physical systems verification.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
688-696, San Francisco, CA, June 3-7 2012.
- [662]
- A. Chakraborty
and D.-Z. Pan.
Skew management of NBTI impacted gated clock trees.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):918-927, June 2013.
- [663]
- S. T.
Chakradhar, M. L. Bushnell, and V. D. Agrawal.
Automatic test generation using neural networks.
In IEEE International Conference on Computer-Aided Design, pages
416-419, Santa Clara, CA, Nov. 7-10 1988.
- [664]
- S. T.
Chakradhar, V. D. Agrawal, and M. L. Bushnell.
Automatic test generation using quadratic 0-1 programming.
In 27th ACM/IEEE Design Automation Conference (DAC90), pages 654-659,
Orlando, FL, June 24-28 1990.
- [665]
- S. T.
Chakradhar and A. Raghunathan.
Best-effort computing: re-thinking parallel software and hardware.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
865-870, Anaheim, CA, June 13-18 2010.
- [666]
- S. Chakravarty
and H. B. Hunt, III.
On the computation of detection probability for multiple faults.
In IEEE International test conference, pages 252-262, Sept. 8-11
1986.
- [667]
- S. Chakravarty
and H. B. Hunt, III.
A note on detecting sneak paths in transistor networks.
IEEE Transactions on Computers, 38(6):861-864, June 1989.
- [668]
- S. Chakravarty
and H. B. Hunt, III.
On computing signal probability and detection probability of stuck-at faults.
IEEE Transactions on Computers, 39(11):1369-1377, November 1990.
- [669]
- S. Chakravarty
and H. B. Hunt, III.
On computing reliability-measures of boolean circuits.
IEEE Transactions on Reliability, 40(5):582-592, December 1991.
- [670]
- S. Chakravarty
and S. S. Ravi.
Computing optimal test sequences from complete test sets for stuck-open faults
in CMOS circuits.
IEEE Transactions on Computer-Aided Design, 9(3):329-331, March
1990.
- [671]
- S. Chakravarty.
A note on random versus deterministic testing of gate-level combinational
circuits.
In IEEE International Conference on Computer-Aided Design, pages
152-155, Santa Clara, CA, Nov. 9-12 1987.
- [672]
- S. Chakravarty.
On the complexity of using bdds for the synthesis and analysis of boolean
circuits.
In Proc. 27th Annual Allerton Conference on Communications, Control, and
Computing, pages 730-739, Monticello, IL, Sept. 27-29 1989.
- [673]
- S. K. Chakravarty.
On the complexity of computing tests for CMOS gates.
IEEE Transactions on Computer-Aided Design, 8(9):973-980, September
1989.
- [674]
- V. Champac,
V. Avendano, and J. Figueras.
Built-in sensor for signal integrity faults in digital interconnect signals.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):256-269, February 2010.
- [675]
- S. C. Chan, K. L.
Shepard, and D.-J. Kim.
Static noise analysis for digital integrated circuits in partially depleted
silicon-on-insulator technology.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(8):916-927, August 2002.
- [676]
- T. F. Chan, J. Cong,
T. Kong, J. R. Shinnerl, and K. Sze.
An enhanced multilevel algorithm for circuit placement.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 299-306, San Jose, CA, November 9-13 2003.
- [677]
- P. K. Chan and
K. Karplus.
Computing signal delay in general RC networks by tree/link partitioning.
In 26th ACM/IEEE Design Automation Conference, pages 485-490, June
1989.
- [678]
- P. K. Chan and K. Karplus.
Computing signal delay in general RC networks by tree/link partitioning.
IEEE Transactions on Computer-Aided Design, 9(8):898-902, August
1990.
- [679]
- V. Chan and W. Q. Meeker.
A failure-time model for infant-mortality and wearout failure modes.
IEEE Transactions on Reliability, 48(4):377-387, December 1999.
- [680]
- P. K. Chan and M. D. F.
Schlag.
Bounds on signal delay in RC mesh networks.
IEEE Transactions on Computer-Aided Design, 8(6):581-589, June
1989.
- [681]
- S. C. Chan and K. L.
Shepard.
Practical consideration in RLCK crosstalk analysis for digital integrated
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 598-604, San Jose, CA, November 4-8 2001.
- [682]
- P. K. Chan.
An extension of elmore's delay.
IEEE Transactions on Circuits and Systems, CAS-33(11):1147-1149,
November 1986.
- [683]
- P. K. Chan.
An extension of elmore's delay and its application for timing analysis of MOS
pass transistor networks.
IEEE Transactions on Circuits and Systems, CAS-33(11):1149-1152,
November 1986.
- [684]
- P. K. Chan.
Signal delay in RC networks with floating capacitors.
In IEEE International Conference on Circuits and Systems, pages
2831-2834, 1988.
- [685]
- P. K. Chan.
Comments on "asymptotic waveform evaluation for timing analysis".
IEEE Transactions on Computer-Aided Design, 10(8):1078-1079, August
1991.
- [686]
- V. Chandra,
H. Schmit, A. Xu, and L. Pileggi.
A power aware system level interconnect design methodology for
latency-insensitive systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 275-282, San Jose, CA, November 7-11 2004.
- [687]
- S. Chandra,
K. Lahiri, A. Raghunathan, and S. Dey.
Considering process variations during system-level power analysis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 342-345, Tegernsee, Germany, October 4-6 2006.
- [688]
- S. Chandra,
K. Lahiri, A. Raghunathan, and S. Dey.
System-on-chip power management considering leakage power variations.
In ACM/IEEE 44th Design Automation Conference (DAC-07), San Diego, CA,
June 4-8 2007.
- [689]
- S. Chandra,
K. Lahiri, A. Raghunathan, and S. Dey.
Variation-aware system-level power analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(8):1173-1184, August 2010.
- [690]
- S. Chandra,
A. Raghunathan, and S. Dey.
Variation-aware voltage level selection.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(5):925-936, May 2012.
- [691]
- A. P. Chandrakasan, M. Potkonjak, J. Rabaey, and R. W.
Brodersen.
HYPER-LP: A system for power minimization using architectural
transformations.
In IEEE/ACM International Conference on Computer-Aided Design, pages
300-303, Santa Clara, CA, November 8-12 1992.
- [692]
- A. P. Chandrakasan, S. Sheng, and R. W. Brodersen.
Low-power CMOS digital design.
IEEE Journal of Solid-State Circuits, 27(4):473-484, April 1992.
- [693]
- A. P. Chandrakasan, R. Allmon, A. Stratakos, and R. W.
Brodersen.
Design of portable systems.
In IEEE 1994 Custom Integrated Circuit Conference, pages 259-266, San
Diego, CA, May 1-4 1994.
- [694]
- A. P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. W.
Brodersen.
Optimizing power using transformations.
IEEE Transactions on Computer-Aided Design, 14(1):12-31, January
1995.
- [695]
- A. Chandrakasan, I. Yang, C. Vieri, and D. Antoniadis.
Design considerations and tools for low-voltage digital system design.
In 33rd Design Automation Conference, pages 113-118, Las Vegas, NV,
June 3-7 1996.
- [696]
- R. Chandramouli, N. Vijaykrishnan, and N. Ranganathan.
Sequential tests for integrated-circuit failures.
IEEE Transactions on Reliability, 47(4):463-471, December 1998.
- [697]
- V. Chandramouli and K. A. Sakallah.
Modeling the effects of temporal proximity of input transitions on gate
propagation delay and transition time.
In 33rd Design Automation Conference, pages 617-622, Las Vegas, NV,
June 3-7 1996.
- [698]
- R. Chandramouli and V. K. Srikantam.
Multimode power modeling and maximum-likelihood estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(11):1244-1248, November 2004.
- [699]
- K. Chandrasekar, C. Weis, B. Akesson, N. Wehn, and K. Goossens.
Towards variation-aware system-level power estimation of drams: an empirical
approach.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [700]
- A. Chandrasekharan, M. Soeken, D. Große, and R. Drechsler.
Approximation-aware rewriting of aigs for error tolerant applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [701]
- Chang, Manning,
and Metze.
Fault Diagnosis of Digital Systems.
R. E. Krieger Publishing Company, 1974.
- [702]
- F-C. Chang, C-F.
Chen, and P. Subramaniam.
An accurate and efficient gate level delay calculator for MOS circuits.
In 25th ACM/IEEE Design Automation Conference, pages 282-287,
Anaheim, CA, June 12-15 1988.
- [703]
- M-C. Chang, J-H.
Chern, and P. Yang.
An accurate grid local truncation error for device simulation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
275-282, Santa Clara, CA, November 7-11 1993.
- [704]
- S.-C. Chang,
M. Marek-Sadowska, and K.-T. Cheng.
Perturb and simplify: multilevel boolean network optimizer.
IEEE Transactions on Computer-Aided Design, 15(12):1494-1504,
December 1996.
- [705]
- S.-C. Chang,
L. P.P.P. van Ginneken, and M. Marek-Sadowska.
Fast boolean optimization by rewiring.
In IEEE/ACM International Conference on Computer-Aided Design, pages
262-269, San Jose, CA, November 10-14 1996.
- [706]
- N. Chang, K. Kim,
and J. Cho.
Bus encoding for low-power high-performance memory systems.
In Design Automation Conference, pages 800-805, Los Angeles, CA, June
5-9 2000.
- [707]
- N. Chang,
K. Kim, and H. G. Lee.
Cycle-accurate energy consumption measurement and analysis: case study of
arm7tdmi.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 185-190, Italy, July 26-27 2000.
- [708]
- C.-W. Chang,
K. Wang, and M. Marek-Sadowska.
Layout-driven hot-carrier degradation minimization using logic restructuring
techniques.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages 97-102,
Las Vegas, NV, June 18-22 2001.
- [709]
- Y.-J. Chang, C.-L.
Yang, and F. Lai.
A power-aware SWDR cell for reducing cache write power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 14-17, Seoul, Korea, August 25-27 2003.
- [710]
- C.-C. Chang,
J. Cong, M. Romesis, and M. Xie.
Optimality and scalability study of existing placement algorithms.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(4):537-549, April 2004.
- [711]
- C.-W. J. Chang,
M.-F. Hsiao, B. Hu, K. Wang, M. Marek-Sadowska, C.-K. Cheng, and S.-J. Chen.
Fast postplacement optimization using functional symmetries.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):102-118, January 2004.
- [712]
- Y.-J. Chang,
F. Lai, and C.-L. Yang.
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(8):827-836, August 2004.
- [713]
- H. Chang,
V. Zolotov, S. Narayan, and C. Visweswariah.
Parameterized block-based statistical timing analysis with non-gaussian
parameters, nonlinear delay functions.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 71-76,
Anaheim, CA, June 13-17 2005.
- [714]
- Y.-C. Chang,
K.-H. Tam, and L. He.
Power-optimal repeater insertion considering vdd and vth as design freedoms.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 137-142, San Diego, CA, August 8-10 2005.
- [715]
- A. C.-C. Chang,
R. H.-M. Huang, and C. H.-P. Wen.
CASSER: a closed-form analysis framework for statistical soft error rate.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1837-1848, October 2013.
- [716]
- J.-W. Chang,
S.-H. Yeh, T.-W. Huang, and T.-Y. Ho.
Integrated fluidic-chip co-design methodology for digital microfludic biochips.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(2):216-227, February 2013.
- [717]
- N. Chang,
D. Baek, and J. Hong.
Power consumption characterization, modeling and estimation of electric
vehicles.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 175-182, San Jose, CA, November 2-6 2014.
- [718]
- W.-H. Chang,
M.-C.-T. Chao, and S.-H. Chen.
Practical routability-driven design flow for multilayer power networks using
aluminum-pad layer.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1069-1081, May 2014.
- [719]
- K. Chang,
A. Koneru, K. Chakrabarty, and S.-K. Lim.
Design automation and testing of monolithic 3d ics: opportunities, challenges,
and solutions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 805-810, Irvine CA, November 13-16 2017.
- [720]
- K. Chang, B.-W.
Ku, S. Sinha, and S.-K. Lim.
Full-chip monolithic 3d IC design and power performance analysis with asap7
library.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 991-996, Irvine CA, November 13-16 2017.
- [721]
- W.-H. Chang,
C.-H. Lin, S.-P. Mu, L.-D. Chen, C.-H. Tsai, Y.-C. Chiu, and M.-C.-T. Chao.
Generating routing-driven power distribution networks with machine-learning
technique.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(8):1237-1250, August 2017.
- [722]
- H. Chang and J. A.
Abraham.
VIPER: An efficient vigorously sensitizable path extractor.
In 30th ACM/IEEE Design Automation Conference, pages 112-117, Dallas,
Texas, June 14-18 1993.
- [723]
- K.-H. Chang and C. Browy.
Improving gate-level simulation accuracy when unknowns exist.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
936-940, San Francisco, CA, June 3-7 2012.
- [724]
- M.-C. Chang and W.-H.
Chang.
Asynchoronous fine-grain power-gated logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(6):1143-1153, June 2013.
- [725]
- Y.-T. Chang and K.-T.
Cheng.
Self-referential verification for gate-level implementations of arithmetic
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(7):1102-1112, July 2004.
- [726]
- A. Chang and W. J. Dally.
Explaining the gap between ASIC and custom power: a custom perspective.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
281-284, Anaheim, CA, June 13-17 2005.
- [727]
- L. Chang and
W. Haensch.
Near-threshold operation for power-efficient computing? it depends...
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1155-1159, San Francisco, CA, June 3-7 2012.
- [728]
- Y.-S. Chang and C.-M.
Kyung.
Conforming block inversion for low power memory.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(1):15-19, February 2002.
- [729]
- S-C. Chang and
M. Marek-Sadowska.
Perturb and simplify: multi-level boolean network optimizer.
In IEEE/ACM International Conference on Computer-Aided Design, pages
2-5, San Jose, CA, November 6-10 1994.
- [730]
- J-M. Chang and M. Pedram.
Register allocation and binding for low power.
In 32nd Design Automation Conference, pages 29-35, San Francisco, CA,
June 12-16 1995.
- [731]
- J-M. Chang and M. Pedram.
Energy minimization using multiple supply voltages.
In International Symposium on Low Power Electronics and Design, pages
157-162, Monterey, CA, August 12-14 1996.
- [732]
- H. Chang and S. S.
Sapatnekar.
Statistical timing alaysis considering spatial correlations using a single
PERT-like traversal.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 621-625, San Jose, CA, November 9-13 2003.
- [733]
- H. Chang and S. S.
Sapatnekar.
Full-chip analysis of leakage power under process variations, including spatial
correlations.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
523-528, Anaheim, CA, June 13-17 2005.
- [734]
- H. Chang and S. S.
Sapatnekar.
Statistical timing analysis under spatial correlations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(9):1467-1482, September 2005.
- [735]
- M. C.-T. Chao, L.-C.
Wang, K.-T. Cheng, and S. Kundu.
Static statistical timing analysis for latch-based pipeline designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 468-472, San Jose, CA, November 7-11 2004.
- [736]
- T. Charania,
A. Opal, and M. Sachdev.
Analysis and design of on-chip decoupling capacitors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(4):648-658, April 2013.
- [737]
- A. Chatterjee, M. Nandakumar, and I-C. Chen.
An investigation of the impact of technology scaling on power wasted as
short-circuit current in low voltage static CMOS circuits.
In International Symposium on Low Power Electronics and Design, pages
145-150, Monterey, CA, August 12-14 1996.
- [738]
- B. Chatterjee, M. Sachdev, S. Hsu, R. Krishnamurthy, and
S. Borkar.
Effectiveness and scaling trends of leakage control techniques for sub-130nm
CMOS technologies.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 122-127, Seoul, Korea, August 25-27 2003.
- [739]
- B. Chatterjee, M. Sachdev, and R. Krishnamurthy.
Leakage control techniques for designing robust, low power wide-OR domino
logic for sub-130nm CMOS technologies.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 415-420, San Jose, CA, March 22-24 2004.
- [740]
- S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam.
Reducing structural bias in technology mapping.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 519-526, San Jose, CA, November 6-10 2005.
- [741]
- D. Chatterjee, A. DeOrio, and V. Bertacco.
Event-driven gate-level simulation with GP-gpus.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
557-562, San Francisco, CA, July 26-31 2009.
- [742]
- S. Chatterjee, M. Fawaz, and F. N. Najm.
Redundancy-aware electromigration checking for mesh power grids.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 540-547, San Jose, CA, November 18-21 2013.
- [743]
- S. Chatterjee, M. Fawaz, and F. N. Najm.
Redundancy-aware power grid electromigration checking under workload
uncertainties.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(9):1509-1522, September 2015.
- [744]
- S. Chatterjee, V. Sukharev, and F. N. Najm.
Fast physics-based electromigration checking for on-die power grids.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [745]
- S. Chatterjee, V. Sukharev, and F. N. Najm.
Fast physics-based electromigration assessment by efficient solution of linear
time-invariant (LTI) systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 659-666, Irvine, CA, November 13-16 2017.
- [746]
- S. Chatterjee, V. Sukharev, and F. N. Najm.
Power grid electromigration checking using physics-based models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 37(7):1317-1330, July 2018.
- [747]
- A. Chatterjee and
R. K. Roy.
Synthesis of low power linear DSP circuits using activity metrics.
In IEEE 7th International Conference on VLSI Design, pages 265-270,
January 1994.
- [748]
- S. Chattopadhyay, S. Roy, and P. P. Chaudhuri.
KGPMIN: An efficient multilevel multioutput AND-OR-XOR minimizer.
IEEE Transactions on Computer-Aided Design, 16(3):257-265, March
1997.
- [749]
- A. Chattopadhyay and Z. Zilic.
GALDS: a complete framework for designing multiclock asics and socs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):641-654, June 2005.
- [750]
- A. Chatzigeorgiou, S. Nikolaidis, and I. Tsoukalas.
A modeling technique for CMOS gates.
IEEE Transactions on Computer-Aided Design, 18(5):557-575, May
1999.
- [751]
- A. Chaudhary, D.-Z. Chen, X.-S. Hu, K. Whitton, and M. Niemier.
Eliminating wire crossings for molecular quantum-dot cellular automata
implementation.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 565-571, San Jose, CA, November 6-10 2005.
- [752]
- K. Chaudhary and
M. Pedram.
Computing the area versus delay trade-off curves in technology mapping.
IEEE Transactions on Computer-Aided Design, 14(12):1480-1489,
December 1995.
- [753]
- R. Chaudhry,
D. Blaauw, R. Panda, and T. Edwards.
Current signature compression for IR-drop analysis.
In Design Automation Conference, pages 162-167, Los Angeles, CA, June
5-9 2000.
- [754]
- S. Chaudhuri and
A. Hetzel.
SAT-based compilation to a non-vonneumann processor.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 675-682, Irvine CA, November 13-16 2017.
- [755]
- Y.-M. Chee, C. J.
Colbourn, and A.-C.-H. Ling.
Optimal memoryless encoding for low power off-chip data buses.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 369-374, San Jose, CA, November 5-9 2006.
- [756]
- H. H. Chen, R. G.
Mathews, and J. A. Newkirk.
Test generation for MOS circuits.
In IEEE 1984 International Test Conference, pages 70-79, 1984.
- [757]
- H. H. Chen, R. G.
Mathews, and J. A. Newkirk.
An algorithm to generate tests for MOS circuits at the switch level.
In IEEE 1985 International Test Conference, pages 304-312, 1985.
- [758]
- H-C Chen, D. H-C Du,
and L-R Liu.
Critical path selection for performance optimization.
IEEE Transactions on Computer-Aided Design, 12(2):185-195, February
1993.
- [759]
- X. Chen, P. Pan,
and C. L. Liu.
Desensitization for power reduction in sequential circuits.
In 33rd Design Automation Conference, pages 795-800, Las Vegas, NV,
June 3-7 1996.
- [760]
- Z. Chen, K. Roy,
and T-L Chou.
Power sensitivity - A new method to estimate power dissipation considering
uncertain specifications of primary inputs.
In IEEE/ACM International Conference on Computer-Aided Design, pages
40-44, San Jose, CA, November 9-13 1997.
- [761]
- Z. Chen, K. Roy,
and T-L Chou.
Sensitivity of power dissipation to uncertainties in primary input
specification.
In IEEE 1997 Custom Integrated Circuits Conference, pages 487-490,
Santa Clara, CA, May 5-8 1997.
- [762]
- C-P Chen, C. C. N.
Chu, and D. F. Wong.
Fast and exact simultaneous gate and wire sizing by lagrangian relaxation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
617-624, San Jose, CA, November 8-12 1998.
- [763]
- R. Y. Chen, R. M.
Owens, M. J. Irwin, and R. S. Bajwa.
Validation of an architectural level power analysis technique.
In IEEE/ACM 35th Design Automation Conference, pages 242-245, San
Francisco, CA, June 15-19 1998.
- [764]
- Z. Chen,
M. Johnson, L. Wei, and K. Roy.
Estimation of standby leakage power in CMOS circuits considering accurate
modeling of transistor stacks.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 239-244, Monterey, CA, August 10-12 1998.
- [765]
- Z. Chen, K. Roy,
and E. K. P. Chong.
Estimation of power sensitivity in sequential circuits with power macromodeling
application.
In IEEE/ACM International Conference on Computer-Aided Design, pages
468-472, San Jose, CA, November 8-12 1998.
- [766]
- Z. Chen, K. Roy,
and T.-L. Chou.
Efficient statistical approach to estimate power considering uncertain
properties of primary inputs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(3):484-492, September 1998.
- [767]
- J. Y. Chen, W. B.
Jone, J. S. Wang, H.-I. Lu, and T. F. Chen.
Segmented bus design for low-power systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
7(1):25-29, March 1999.
- [768]
- W. Chen, C.-T.
Hsieh, and M. Pedram.
Gate sizing with controlled displacement.
In 1999 International Symposium on Physical Design, pages 127-132,
Monterey, CA, April 12-14 1999.
- [769]
- C. Chen, X. Yang,
and M. Sarrafzadeh.
Potential slack: an effective metric of combinational circuit performance.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 198-201, San Jose, CA, November 5-9 2000.
- [770]
- D. Chen, E. Li,
E. Rosenbaum, and S.-M. Kang.
Interconnect thermal modeling for accurate simulation of circuit timing and
reliability.
IEEE Transactions on Computer-Aided Design, 19(2):197-205, February
2000.
- [771]
- P. Chen, D. A.
Kirkpatrick, and K. Keutzer.
Miller factor for gate-level coupling delay calculation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 68-74, San Jose, CA, November 5-9 2000.
- [772]
- P. Chen, D. A.
Kirkpatrick, and K. Keutzer.
Switching window computation for static timing analysis in the presence of
crosstalk noise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 331-337, San Jose, CA, November 5-9 2000.
- [773]
- W. Chen, C.-T.
Hsieh, and M. Pedram.
Simultaneous gate sizing and fanout optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 374-378, San Jose, CA, November 5-9 2000.
- [774]
- Z. Chen, K. Roy,
and E. K. Chong.
Estimation of power dissipation using a novel power macromodeling technique.
IEEE Transactions on Computer-Aided Design, 19(11):1363-1369,
November 2000.
- [775]
- C. Chen,
A. Srivastava, and M. Sarrafzadeh.
On gate level power optimization using dual-supply voltages.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(5):616-629, October 2001.
- [776]
- L.-C. Chen, S. K.
Gupta, and M. A. Breuer.
A new gate delay model for simultaneous switching and its applications.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
289-294, Las Vegas, NV, June 18-22 2001.
- [777]
- C. Chen, C. Kang,
and M. Sarrafzadeh.
Activity-sensitive clock tree construction for low power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 279-282, Monterey, California, August 12-14 2002.
- [778]
- C. Chen, X. Yang,
and M. Sarrafzadeh.
Predicting potential performance for digital circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(3):253-262, March 2002.
- [779]
- L. H. Chen,
M. Marek-Sadowska, and F. Brewer.
Coping with buffer delay change due to power and ground noise.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
860-865, New Orleans, LA, June 10-14 2002.
- [780]
- P. Chen,
Y. Kukimoto, and K. Keutzer.
Refining switching window by time slots for crosstalk noise calculation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 583-586, San Jose, CA, November 10-14 2002.
- [781]
- W.-Y. Chen, S. K.
Gupta, and M. A. Breuer.
Analytical models for crosstalk excitation and propagation in VLSI circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(10):1117-1131, October 2002.
- [782]
- Y. Chen, A. B.
Kahng, G. Robins, and A. Zelikovsky.
Area fill synthesis for uniform layout density.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(10):1132-1147, October 2002.
- [783]
- B. Chen, H. Yang,
R. Luo, and H. Wang.
A novel method for worst-case interconnect delay estimation.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(6):778-781, June 2003.
- [784]
- D. Chen, J. Cong,
and Y. Fan.
Low-power high-level synthesis for FPGA architctures.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 134-139, Seoul, Korea, August 25-27 2003.
- [785]
- H. Chen, C.-K.
Cheng, A. B. Kahng, I. Mandoiu, Q. Wang, and B. Yao.
The Y-architecture for on-chip interconnect: analysis and methodology.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 13-19, San Jose, CA, November 9-13 2003.
- [786]
- L.-H. Chen,
M. Marek-Sadowska, and F. Brewer.
Buffer delay change in the presence of power and ground noise.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):461-473, June 2003.
- [787]
- O. T.-C. Chen,
S. Wang, and Y.-W. Wu.
Minimization of switching activities of partial products for designing
low-power multipliers.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):418-433, June 2003.
- [788]
- T.-H. Chen,
C. Luk, and C. C.-P. Chen.
INDUCTWISE: inductance-wise interconnect simulator and extractor.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(7):884-894, July 2003.
- [789]
- T.-H. Chen,
C. Luk, and C. C.-P. Chen.
Supreme: substrate and power-delivery reluctance-enhanced macromodel
evaluation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 786-792, San Jose, CA, November 9-13 2003.
- [790]
- T.-C. Chen, S.-R.
Pan, and Y.-W. Chang.
Timing modeling and optimization under the transmission line model.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(1):28-41, January 2004.
- [791]
- T.-H. Chen, J.-L.
Tsai, C. C.-P. Chen, and T. Karnik.
Hisim: hierarchical interconnect-centric circuit simulator.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 489-496, San Jose, CA, November 7-11 2004.
- [792]
- H. Chen, C.-K.
Cheng, A. B. Kahng, I. I. Mandoiu, Q. Wang, and B. Yao.
The Y architecture for on-chip interconnect: analysis and methodology.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(4):588-599, April 2005.
- [793]
- H. Chen, C. Yeh,
G. Wilke, S. Reddy, H. Nguyen, W. Walker, and R. Murgai.
A sliding window scheme for accurate clock mesh analysis.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 939-946, San Jose, CA, November 6-10 2005.
- [794]
- H.-M. Chen, L.-D.
Huang, I.-M. Liu, and M.-D.-F. Wong.
Simultaneous power supply planning and noise avoidance in floorplan design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(4):578-587, April 2005.
- [795]
- X. Chen,
A. Davare, H. Hsieh, A. Sangiovanni-Vincentelli, and Y. Watanabe.
Simulation based deadlock analysis for system level designs.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
260-265, Anaheim, CA, June 13-17 2005.
- [796]
- Y. Chen, H. Li,
K. Roy, and C.-K. Koh.
Cascaded carry-select adder (c2sa): a new structure for low-power CSA design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 115-118, San Diego, CA, August 8-10 2005.
- [797]
- G.-K. Chen,
D. Blaauw, T. Mudge, D. Sylvester, and N.-S. Kim.
Yield-driven near-threshold SRAM design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 660-666, San Jose, CA, November 5-8 2007.
- [798]
- P.-Y. Chen, K.-H.
Ho, and T.-T. Hwang.
Skew aware polarity assignment in clock tree.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 376-379, San Jose, CA, November 5-8 2007.
- [799]
- R. Chen, E. A.
Foreman, P. A. Habitz, J. G. Hemmett, K. Kalafala, J. S. Piaget, P. Qi,
N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
Static timing: back to our roots.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 130-136, Austin,
Texas, February 26-27 2007.
- [800]
- Y. Chen, H. Li,
J. LI, and C.-K. Koh.
Variable-latency adder (VL-adder): new arithmetic circuit design practice to
overcome NBTI.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 195-200, Portland, Oregon, August 27-29 2007.
- [801]
- P.-Y. Chen, C.-Y.
Liu, and T.-T. Hwang.
Transition-aware decoupling-capacitor allocation in power noise reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 426-429, San Jose, CA, November 10-13 2008.
- [802]
- T.-W. Chen, K. Kim,
Y. Kim, and S. Mitra.
Delay shifts predict gate-oxide early life failures.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 120-127, Monterey, CA,
February 25-26 2008.
- [803]
- M. Chen, W. Zhao,
F. Liu, and Y. Cao.
Finite-point-based transistor model: a new approach to fast circuit simulation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(10):1470-1480, October 2009.
- [804]
- G. Chen,
D. Sylvester, D. Blaauw, and T. Mudge.
Yield-driven near-threshold SRAM design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(11):1590-1598, November 2010.
- [805]
- Y. Chen, H. Li,
C.-K. Koh, G. Sun, J. Li, Y. Xie, and K. Roy.
Variable-latency adder (VL-adder) designs for low power and NBTI tolerance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(11):1621-1624, November 2010.
- [806]
- Y. Chen, D. Niu,
Y. Xie, and K. Chakrabarty.
Cost-effective integration of three-dimensional (3d) ics emphasizing testing
cost analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 471-476, San Jose, CA, November 7-11 2010.
- [807]
- Y. Chen,
S. Safarpour, J. Marques-Silva, and A. Veneris.
Automated design debugging with maximum satisfiability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1804-1817, November 2010.
- [808]
- F.-W. Chen, S.-L.
Chen, Y.-S. Lin, and T.-T. Hwang.
A physical-location-aware X-bit redistribution for maximum IR-drop
reduction.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(12):2255-2264, December 2012.
- [809]
- H. Chen, C. c. Lu,
Y.-D. Wu, and T.-J. Chiu.
Learning from biological neurons to compute with electronic noise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 168-171, San Jose, CA, November 5-8 2012.
- [810]
- Q. Chen, S.-H.
Weng, and C.-K. Cheng.
A practical regularization technique for modified nodal analysis in large-scale
time-domain circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(7):1031-1040, July 2012.
- [811]
- X. Chen, Y. Wang,
and H. Yang.
NICSLU: an adaptive sparse matrix solver for parallel circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(2):261-274, February 2013.
- [812]
- Y.-C. Chen, C.-Y.
Wang, and C.-Y. Huang.
Verification of reconfigurable binary decision diagram-based single-electron
transistor arrays.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1473-1483, October 2013.
- [813]
- Y.-H. Chen, C.-L.
Hsu, L.-C. Tsai, T.-W. Huang, and T.-Y. Ho.
A reliability-oriented placement algorithm for reconfigurable digital
microfluidic biochips using 3-d deferred decision making technique.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(8):1151-1162, August 2013.
- [814]
- Y.-G. Chen, H. Geng,
K.-Y. Lai, Y. Shi, and S.-C. Chang.
Multibit retention registers for power gated designs: concept, design and
deployment.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(4):507-518, April 2014.
- [815]
- H.-B. Chen,
S.-X.-D. Tan, X. Huang, and V. Sukharev.
New electromigration modeling and analysis considering time-varying temperature
and current densities.
In 20th Asia and South Pacific Design Automation Conference, pages
352-357, Chiba/Tokyo, Japan, January 19-22 2015.
- [816]
- H.-B. Chen,
S.-X.-D. Tan, V. Sukharev, X. Huang, and T. Kim.
Interconnect reliability modeling and analysis for multi-branch interconnect
trees.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [817]
- X. Chen, X. Li,
and S.-X.-D. Tan.
From robust chip to smart building: CAD algorithms and methodologies for
uncertainty analysis of building performance.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 457-464, Austin, TX, November 2-6 2015.
- [818]
- C.-C. Chen, T. Liu,
and L. Milor.
System-level modeling of microprocessor reliability degradation due to bias
temperature instability and hot carrier injection.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(8):2712-2725, August 2016.
- [819]
- H.-B. Chen,
S.-X.-D. Tan, X. Huang, T. Kim, and V. Sukharev.
Analytical modeling and characterization of electromigration effects for
multibranch interconnect trees.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(11):1811-1824, November 2016.
- [820]
- X. Chen, L. Wang,
B. Li, Y. Wang, X. Li, Y. Liu, and H. Yang.
Modeling random telegraph noise as a randomness source and its application in
true random number generation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(9):1435-1448, September 2016.
- [821]
- Y.-C. Chen,
S. Ladenheim, H. Kalargaris, M. Mihajlovic, and V. F. Pavlidis.
Computationally efficient standard-cell FEM-based thermal analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 490-495, Irvine CA, November 13-16 2017.
- [822]
- P. Chen, C.-K.
Cheng, D. Park, and X. Wang.
Transient circuit simulation for differential algebraic systems using matrix
exponential.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [823]
- T.-H. Chen and C.-P. Chen.
Efficient large-scale power grid analysis based on preconditioned
krylov-subspace iterative methods.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
559-562, Las Vegas, NV, June 18-22 2001.
- [824]
- D. Chen and J. Cong.
Delay optimal low-power circuit clustering for fpgas with dual supply voltages.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 70-73, Newport Beach, CA, August 9-11 2004.
- [825]
- H-C. Chen and D. H. C. Du.
Path sensitization in critical path problem.
In IEEE International Conference on Computer-Aided Design, pages
208-211, Santa Clara, CA, November 11-14 1991.
- [826]
- H-C Chen and D. H-C Du.
Path sensitization in critical path problems.
IEEE Transactions on Computer-Aided Design, 12(2):196-207, February
1993.
- [827]
- H-Y. Chen and S. Dutta.
A timing model for static CMOS gates.
In IEEE International Conference on Computer-Aided Design, pages
72-75, 1989.
- [828]
- T. Chen and M. K. H. Fan.
On convex formulation of the floorplan area minimization problem.
In ACM/IEEE International Symposium on Physical Design, pages
124-128, Monterey, CA, April 6-8 1998.
- [829]
- G. Chen and E. G.
Friedman.
An RLC interconnect model based on fourier analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(2):170-183, February 2005.
- [830]
- G. Chen and E. G.
Friedman.
Low-power repeaters driving RC and RLC interconnects with interconnects
with delay and bandwidth constraints.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(2):161-172, February 2006.
- [831]
- T. Chen and A. Hajjar.
Analysing statistical timing behaviour of coupled interconnects using quadratic
delay change characteristics.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 183-188, San Jose, CA, March 24-26 2003.
- [832]
- T. Chen and A. Hajjar.
Statistical timing analysis of coupled interconnects using quadratic
delay-change characteristics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(12):1677-1683, December 2004.
- [833]
- T.-H. Chen and J. P. Hayes.
Equivalence among stochastic logic circuits and its application.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [834]
- J. Chen and L. He.
Piecewise linear model for transmission line with capacitive loading and ramp
input.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(6):928-937, June 2005.
- [835]
- J. Chen and L. He.
Worst case crosstalk noise for nonswitching victims in high-speed buses.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(8):1275-1283, August 2005.
- [836]
- J. Chen and L. He.
Modeling and synthesis of multiport transmission line for multichannel
communication.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1664-1676, September 2006.
- [837]
- J. Chen and L. He.
Efficient in-package decoupling capacitor optimization for I/O power
integrity.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):734-738, April 2007.
- [838]
- M.-J. Chen and J.-S. Ho.
A three-parameters-only MOSFET subthreshold current CAD model considering
back-gate bias and process variations.
IEEE Transactions on Computer-Aided Design, 16(4):343-352, April
1997.
- [839]
- P. Chen and K. Keutzer.
Towards true crosstalk noise analysis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
132-137, San Jose, CA, November 7-11 1999.
- [840]
- H. H. Chen and D. D. Ling.
Power supply noise analysis methodology for deep-submicron VLSI chip design.
In 34th Design Automation Conference, pages 638-643, Anaheim, CA,
June 9-13 1997.
- [841]
- Y.-Y. Chen and J.-J. Liou.
Extraction of statistical timing profiles using test data.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
509-514, San Diego, CA, June 4-8 2007.
- [842]
- L. H. Chen and
M. Marek-Sadowska.
Efficient closed-form crosstalk delay metrics.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 431-436, San Jose, CA, March 18-21 2002.
- [843]
- H. Chen and
J. Marques-Silva.
A two-variable model for SAT-based ATPG.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(12):1943-1956, December 2013.
- [844]
- T. Chen and
S. Naffziger.
Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV)
for improving delay and leakage under the presence of process variation.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(5):888-889, October 2003.
- [845]
- B. Chen and
I. Nedelchev.
Power compiler: A gate-level power optimization and synthesis system.
In IEEE Conference on Computer Design (ICCD), pages 74-79, Austin,
TX, October 1997.
- [846]
- Z. Chen and K. Roy.
A power macromodeling technique based on power sensitivity.
In IEEE/ACM 35th Design Automation Conference, pages 678-683, San
Francisco, CA, June 15-19 1998.
- [847]
- D-S. Chen and
M. Sarrafzadeh.
An exact algorithm for low power library specific gate re-sizing.
In 33rd Design Automation Conference, pages 783-788, Las Vegas, NV,
June 3-7 1996.
- [848]
- C. Chen and
M. Sarrafzadeh.
Provably good algorithm for low power consumption with dual supply voltages.
In IEEE/ACM International Conference on Computer-Aided Design, pages
76-79, San Jose, CA, November 7-11 1999.
- [849]
- C-H Chen and C-Y Tsui.
Towards the capability of providing power-area-delay trade-off at the register
transfer level.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 24-29, Monterey, CA, August 10-12 1998.
- [850]
- R. Chen and H. Zhou.
Clock schedule verification under process variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 619-625, San Jose, CA, November 7-11 2004.
- [851]
- R. Chen and H. Zhou.
Timing macro-modeling of IP blocks with crosstalk.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 155-159, San Jose, CA, November 7-11 2004.
- [852]
- R. Chen and H. Zhou.
An efficient data structure for maxplus merge in dynamic programming.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):3004-3009, December 2006.
- [853]
- R. Chen and H. Zhou.
Statistical timing verification for transparently latched circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1847-1855, September 2006.
- [854]
- R. Chen and H. Zhou.
Timing budgeting under arbitrary process variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 344-349, San Jose, CA, November 5-8 2007.
- [855]
- R. Chen and H. Zhou.
Fast estimation of timing yield bounds for process variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(3):241-248, March 2008.
- [856]
- Y. Chen and H. Zhou.
Synthesis of resilient circuits from guarded atomic actions.
In 20th Asia and South Pacific Design Automation Conference, pages
550-555, Chiba/Tokyo, Japan, January 19-22 2015.
- [857]
- T. Chen.
Impact of on-chip inductance when transitioning from al to cu based technology.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 173-178, San Jose, CA, March 26-28 2001.
- [858]
- T. Chen.
On the impact of on-chip inductance on signal nets under the influence of power
grid noise.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):339-348, March 2005.
- [859]
- J. Chen.
Carbon nanotubes for potential electronic and optoelectronic applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 649-650, San Jose, CA, November 5-9 2006.
- [860]
- D. I. Cheng,
K-T. Cheng, D. C. Wang, and M. Marek-Sadowska.
A new hybrid methodology for power estimation.
In 33rd Design Automation Conference, pages 439-444, Las Vegas, NV,
June 3-7 1996.
- [861]
- Y-K. Cheng, C-C.
Teng, A. Dharchoudhury, E. Rosenbaum, and S-M. Kang.
icet: A complete chip-level thermal reliability diagnosis tool for CMOS
VLSI chips.
In 33rd Design Automation Conference, pages 548-551, Las Vegas, NV,
June 3-7 1996.
- [862]
- D. I. Cheng,
K. T. Cheng, D. C. Wang, and M. Marek-Sadowska.
A hybrid methodology for switching activities estimation.
IEEE Transactions on Computer-Aided Design, 17(4):357-366, April
1998.
- [863]
- Y.-K. Cheng,
P. Raha, C.-C. Teng, E. Rosenbaum, and S.-M. Kang.
ILLIADS-T: An electrothermal timing simulator for temperature-sensitive
reliability diagnosis of CMOS VLSI chips.
IEEE Transactions on Computer-Aided Design, 17(8):668-681, August
1998.
- [864]
- L. Cheng, L. Deng,
D. Chen, and M. D.-F. Wong.
A fast simultaneous input vector generation and gate replacement algorithm for
leakage power reduction.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
117-120, San Francisco, CA, July 24-28 2006.
- [865]
- L. Cheng, F. Li,
P. Wong, and L. He.
Device and architecture cooptimization for FPGA power reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(7):1211-1221, July 2007.
- [866]
- L. Cheng,
J. Xiong, and L. He.
Non-linear statistical static timing analysis for non-gaussian variation
sources.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 80-85, Austin, Texas,
February 26-27 2007.
- [867]
- L. Cheng,
J. Xiong, and L. He.
Non-linear statistical static timing analysis for non-gaussian variation
sources.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
250-255, San Diego, CA, June 4-8 2007.
- [868]
- L. Cheng,
P. Gupta, and L. He.
Efficient additive statistical leakage estimation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(11):1777-1781, November 2009.
- [869]
- L. Cheng,
P. Gupta, C. Spanos, K. Qian, and L. He.
Physically justifiable die-level modeling of spatial variation in view of
systematic across wafer variability.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
104-109, San Francisco, CA, July 26-31 2009.
- [870]
- L. Cheng,
J. Xiong, and L. He.
Non-gaussian statistical timing anaylsis using second-order polynomial fitting.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(1):130-140, January 2009.
- [871]
- L. Cheng,
P. Gupta, C. J. Spanos, K. Qian, and L. He.
Physically justifiable die-level modeling of spatial variation in view of
systematic across wafer variability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(3):388-401, March 2011.
- [872]
- L. Cheng, F. Gong,
W. Xu, J. Xiong, L. He, and M. Sarrafzadeh.
Fourier series approximation for max operation in non-gaussian and quadratic
statistical static timing analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(8):1383-1391, August 2012.
- [873]
- Y. Cheng,
L. Zhang, Y. Han, and X. Li.
Thermal-constrained task allocation for interconnect energy reduction in 3-D
homogeneous mpsocs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(2):239-249, February 2013.
- [874]
- Y. Cheng,
A. Todri-Sanial, J. Yang, and W. Zhao.
Alleviating through-silicon-via electromigration for 3-D integrated circuits
taking advantage of self-healing effect.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(11):3310-3322, November 2016.
- [875]
- A.-C. Cheng, J.-D.
Dong, C.-H. Hsu, S.-H. Chang, M. Sun, S.-C. Chang, J.-Y. Pan, Y.-T. Chen,
W. Wei, and D.-C. Juan.
Searching toward pareto-optimal device-aware neural architectures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [876]
- K-T Cheng and
V. Agrawal.
An entropy measure for the complexity of multi-output boolean functions.
In 27th ACM/IEEE Design Automation Conference (DAC90), pages 302-305,
Orlando, FL, June 24-28 1990.
- [877]
- Y-K. Cheng and S-M. Kang.
Fast thermal analysis for CMOS VLSIC reliability.
In IEEE 1996 Custom Integrated Circuits Conference, pages 479-482,
San Diego, CA, May 5-8 1996.
- [878]
- Y.-K. Cheng and S.-M. Kang.
An efficient method for hot-spot identification in ULSI circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
124-127, San Jose, CA, November 7-11 1999.
- [879]
- Y.-K. Cheng and S.-M. Kang.
A temperature-aware simulation environment for reliable ULSI chip design.
IEEE Transactions on Computer-Aided Design, 19(9):1211-1220,
September 2000.
- [880]
- K.-T. Cheng and
A. S. Krishnakumar.
Automatic generation of functional vectors using the extended finite state
machine model.
ACM Transactions on Design Automation of Electronic Systems,
1(1):57-79, January 1996.
- [881]
- W.-C. Cheng and
M. Pedram.
Power-optimal encoding for DRAM address bus.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 250-252, Italy, July 26-27 2000.
- [882]
- W.-C. Cheng and
M. Pedram.
Memory bus encoding for low power: A tutorial.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 199-204, San Jose, CA, March 26-28 2001.
- [883]
- W.-C. Cheng and
M. Pedram.
Power-optimal encoding for a DRAM address bus.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(2):109-118, April 2002.
- [884]
- Y. Cheon, P.-H.
Ho, A. B. Kahng, S. Reda, and Q. Wang.
Power-aware placement.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
795-800, Anaheim, CA, June 13-17 2005.
- [885]
- B. S. Cherkauer
and E. G. Friedman.
Channel width tapering of serially connected mosfets with emphasis on power
dissipation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2(1):100-114, March 1994.
- [886]
- J.-H. Chern,
J. Huang, L. Arledge, P.-C. Li, and P. Yang.
Multilevel metal capacitance models for CAD design synthesis systems.
IEEE Electron Device Letters, 13(1):32-34, January 1992.
- [887]
- G. A. Cherry and S. J.
Qin.
Multiblock principal component analysis based on a combined index for
semiconductor fault detection and diagnosis.
IEEE Transactions on Semiconductor Manufacturing, 19(2):159-172, May
2006.
- [888]
- E. M. Cherry.
Loop gain, input impedance and output impedance of feedback amplifiers.
IEEE Circuits and Systems Magazine, 8(1):55-71, Q1 2008.
- [889]
- H. Cherupalli
and J. Sartori.
Graph-based dynamic analysis: efficient characterization of dynamic timing and
activity distributions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 729-735, Austin, TX, November 2-6 2015.
- [890]
- H. Cherupalli
and J. Sartori.
Scalable n-worst algorithms for dynamic timing and activity analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 585-592, Irvine CA, November 13-16 2017.
- [891]
- W.-T. Cheung and N. Wong.
Power optimization in a repeater-inserted interconnect via geometric
programming.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 226-231, Tegernsee, Germany, October 4-6 2006.
- [892]
- M. Chew, A. Aslyan,
J.-H. Choy, and X. Huang.
Accurate full-chip estimation of power map, current densities and temperature
for EM assessment.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 440-445, San Jose, CA, November 2-6 2014.
- [893]
- M. Chew and A. J.
Strojwas.
Re-evaluation mode timing simulation.
In IEEE International Symposium on Circuits and Systems, pages
2395-2398, June 1991.
- [894]
- A. Chhabra,
H. Rawat, M. Jain, P. Tessier, D. Pierredon, L. Bergher, and P. Kumar.
FALPEM: framework for architectural-level power estimation and optimization
for large memory sub-systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(7):1138-1142, July 2015.
- [895]
- S. R. Chhetri,
N. Rashid, S. Faezi, and M. A. Al Faruque.
Security trends and advances in manufacturing systems in the era of industry
4.0.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 1025-1032, Irvine CA, November 13-16 2017.
- [896]
- J. C. Chi, H. H. Lee,
S. H. Tsai, and M. C. Chi.
Gate level multiple supply voltage assignment algorithm for power optimization
under timing constraint.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(6):637-648, June 2007.
- [897]
- A. C. L. Chiang,
I. S. Reed, and A. V. Banes.
Path sensitization, partial boolean difference, and automated fault diagnosis.
IEEE Transactions on Computers, pages 189-195, February 1972.
- [898]
- T.-Y. Chiang,
K. Banerjee, and K. C. Saraswat.
Compact modeling and SPICE-based simulation for electrothermal analysis of
multilevel ULSI interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 165-172, San Jose, CA, November 4-8 2001.
- [899]
- K-W. Chiang and Z. G.
Vranesic.
Test generation for MOS complex gate networks.
In IEEE 12th International Symposium on Fault Tolerant Computing,
pages 149-157, June 1982.
- [900]
- K-W. Chiang and Z. G.
Vranesic.
On fault detection in CMOS logic circuits.
In IEEE 20th Design Automation Conference, pages 50-56, Miami Beach,
FL, June 27-29 1983.
- [901]
- H.-C. Chang Chien,
H.-C. Ou, T.-C. Chen, T.-Y. Kuan, and Y.-W. Chang.
Double patterning lithography-aware analog placement.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [902]
- A. Chinea,
P. Triverio, and S. Grivet-Talocia.
Campact macromodeling of electrically long interconnects.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 199-202, San Jose, CA, October 27-29 2008.
- [903]
- R.-L.-S. Ching,
E.-F.-Y. Young, K.-C.-K. Leung, and C. Chu.
Post-placement voltage island generation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 641-646, San Jose, CA, November 5-9 2006.
- [904]
- D. G.
Chinnery, B. Nikolic, and K. Keutzer.
Achieving 550 mhz in an ASIC methodology.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
420-425, Las Vegas, NV, June 18-22 2001.
- [905]
- D. G. Chinnery
and K. Keutzer.
Closing the power gap between ASIC and custom: an ASIC perspective.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
275-280, Anaheim, CA, June 13-17 2005.
- [906]
- D. G. Chinnery
and K. Keutzer.
Linear programming for sizing, vth and vdd assignment.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 149-154, San Diego, CA, August 8-10 2005.
- [907]
- M. Chinosi,
R. Zafalon, and C. Guardiani.
Automatic characterization and modeling of power consumption in static rams.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 112-114, Monterey, CA, August 10-12 1998.
- [908]
- M. Chinosi,
R. Zafalon, and C. Guardiani.
Parallel mixed-level power simulation based on spatio-temporal circuit
partitioning.
In Design Automation Conference, pages 562-567, New Orleans, LA, June
21-25 1999.
- [909]
- D.-S. Chiou, S.-H.
Chen, S.-C. Chang, and C. Yeh.
Timing driven power gating.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
121-124, San Francisco, CA, July 24-28 2006.
- [910]
- D.-S. Chiou, D.-C.
Juan, Y.-T. Chen, and S.-C. Chang.
Fine-grainted sleep transistor sizing algorithm for leakage power minimization.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 81-86,
San Diego, CA, June 4-8 2007.
- [911]
- V. K. Chippa,
D. Mohapatra, K. Roy, S. T. Chakradhar, and A. Raghunathan.
Scalable effort hardward design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(9):2004-2016, September 2014.
- [912]
- E. Chiprout and
M. Nakhla.
Generalized moment-matching methods for transient analysis of interconnect
networks.
In 29th ACM/IEEE Design Automation Conference, pages 201-206,
Anaheim, CA, June 8-12 1992.
- [913]
- E. Chiprout.
Fast flip-chip power grid analysis via locality and grid shells.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 485-488, San Jose, CA, November 7-11 2004.
- [914]
- E. Chiprout.
On-die power grids - the missing link.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
940-945, Anaheim, CA, June 13-18 2010.
- [915]
- E. Chiprout.
Power grid effects and their impact on-die.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 667-669, San Jose, CA, November 5-8 2012.
- [916]
- G.-R. Chiu, D. P.
Singh, V. Manohararajah, and S. D. Brown.
Mapping arbitrary logic functions into synchronous embedded memories for area
reduction on fpgas.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 135-142, San Jose, CA, November 5-9 2006.
- [917]
- C.-T. Chiu, W.-C.
Huang, C.-H. LIn, W.-C. Lai, and Y.-F. Tsao.
Embedded transition inversion coding with low switching activity for serial
links.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1797-1810, October 2013.
- [918]
- S-B. Cho, Y-C. Shin,
and I-C. Lim.
A test generation algorithm for CMOS circuits.
In IEEE International Symposium on Circuits and Systems, pages
1551-1554, Kyoto, Japan, 1985.
- [919]
- H. Cho, G. D. Hachtel,
B. Plessier, and F. Somenzi.
Algorithms for approximate FSM traversal.
In 30th ACM/IEEE Design Automation Conference, pages 25-30, Dallas,
Texas, June 14-18 1993.
- [920]
- M. Cho, S. Ahmed, and
D. Z. Pan.
TACO: temperature aware clock-tree optimization.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 582-587, San Jose, CA, November 6-10 2005.
- [921]
- C. Cho, D. Kim,
J. Kim, J.-O. Plouchart, and R. Trzcinski.
Statistical framework for technology-model-product co-design and convergence.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
503-508, San Diego, CA, June 4-8 2007.
- [922]
- M. Cho, K. Lu,
K. Yuan, and D.-Z. Pan.
Boxrouter 2.0: architecture and implementation of a hybrid and robust global
router.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 503-508, San Jose, CA, November 5-8 2007.
- [923]
- Y. Cho, Y. Kim,
S. Park, and N. Chang.
System-level power estimation using an on-chip bus performance monitoring unit.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 149-154, San Jose, CA, November 10-13 2008.
- [924]
- H. Cho, L. Leem, and
S. Mitra.
ERSA: error resilient system architecture for probabilistic applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):546-558, April 2012.
- [925]
- H. Cho, E. Cheng,
T. Shepherd, C.-Y. Cher, and S. Mitra.
System-level effects of soft errors in uncore components.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(9):1497-1510, September 2017.
- [926]
- J. Choi, J. Jeon,
and K. Choi.
Power minimization of functional units by partially guarded computation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 131-136, Italy, July 26-27 2000.
- [927]
- S. H. Choi,
F. Dartu, and K. Roy.
Timed pattern generation for noise-on-delay calculation.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
870-873, New Orleans, LA, June 10-14 2002.
- [928]
- S. H. Choi, B. C.
Paul, and K. Roy.
Novel sizing algorithm for yield improvement under process variation in
nanometer technology.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
454-459, San Diego, CA, June 7-11 2004.
- [929]
- K Choi, R. Soma, and
M. Pedram.
Fine-grained dynamic voltage and frequency scaling for precise energy and
performance tradeoff based on the ratio of off-chip access to on-chip
computation times.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):18-28, January 2005.
- [930]
- J.-H. Choi,
A. Bansal, M. Meterelliyoz, J. Murthy, and K. Roy.
Leakage power dependent temperature estimation to predict thermal runaway in
finfet circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 583-586, San Jose, CA, November 5-9 2006.
- [931]
- J.-H. Choi,
J. Murthy, and K. Roy.
The effect of process variation on device temperature in finfet circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 747-751, San Jose, CA, November 5-8 2007.
- [932]
- J.-C. Choi, S. D.
Brown, and J. H. Anderson.
From pthreads to multicore hardware systems in legup high-level synthesis for
fpgas.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(10):2867-2880, October 2017.
- [933]
- K.-W. Choi and
A. Chatterjee.
Ha2tsd: Hierarchical time slack distribution for ultra-low power CMOS VLSI.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 207-212, Monterey, California, August 12-14 2002.
- [934]
- K.-W. Choi and
A. Chatterjee.
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra
low-power CMOS VLSI.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 72-77, Seoul, Korea, August 25-27 2003.
- [935]
- M. Choi and L. Milor.
Impact on circuit performance of deterministic within-die variation in
nanoscale semiconductor manufacturing.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1350-1367, July 2006.
- [936]
- Y. Choi and E. E.
Swartzlander.
Speculative carry generation with prefix adder.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(3):321-326, March 2008.
- [937]
- A. Chojnacki and
L. Jozwiak.
High-quality FPGA designs through functional decomposition with sub-function
input support selection based on information relationship measures.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 409-414, San Jose, CA, March 26-28 2001.
- [938]
- K. Chopra,
S. Shah, A. Srivastava, D. Blaauw, and D. Sylvester.
Parametric yield maximization using gate sizing based on efficient statistical
power and delay gradient computation.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 1023-1028, San Jose, CA, November 6-10 2005.
- [939]
- K. Chopra,
B. Zhai, D. Blaauw, and D. Sylvester.
A new statistical max operation for propagating skewness in statistical timing
analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 237-243, San Jose, CA, November 5-9 2006.
- [940]
- K. Chopra,
N. Shenoy, and D. Blaauw.
Variogram based robust extraction of process variation.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 112-117, Austin,
Texas, February 26-27 2007.
- [941]
- K. Chopra,
C. Zhuo, D. Blaauw, and D. Sylvester.
A statistical approach for full-chip gate-oxide reliability analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 698-705, San Jose, CA, November 10-13 2008.
- [942]
- K. Chopra and
S. B. K. Vrudhula.
Implicit pseudo boolean enumeration algorithms for input vector control.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
767-772, San Diego, CA, June 7-11 2004.
- [943]
- K. Chopra and
S. Vrudhula.
Efficient symbolic algorithms for computing the minimum and bounded leakage
states.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2820-2832, December 2006.
- [944]
- T-L. Chou, K. Roy,
and S. Prasad.
Estimation of circuit activity considering signal correlations and simultaneous
switching.
In IEEE/ACM International Conference on Computer-Aided Design, pages
300-303, San Jose, CA, November 6-10 1994.
- [945]
- P. H. Chou, C. Park,
J. Park, K. Pham, and J. Liu.
B#: a battery emulator and power profiling instrument.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 288-293, Seoul, Korea, August 25-27 2003.
- [946]
- C.-H. Chou, N.-Y.
Tsai, H. Yu, C.-R. Lee, Y. Shi, and S.-C. Chang.
On the preconditioner of conjugate gradient method - a power grid simulation
perspective.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 494-497, San Jose, CA, November 7-10 2011.
- [947]
- T-L. Chou and K. Roy.
Statistical estimation of sequential circuit activity.
In IEEE/ACM International Conference on Computer-Aided Design, pages
34-37, San Jose, CA, November 5-9 1995.
- [948]
- T-L. Chou and K. Roy.
Accurate power estimation of CMOS sequential circuits.
IEEE Transactions on Very Large Integration (VLSI) Systems,
4(3):369-380, September 1996.
- [949]
- T.-L. Chou and K. Roy.
Estimation of activity for static and domino CMOS circuits considering signal
correlations and simultaneous switching.
IEEE Transactions on Computer-Aided Design, 15(10):1257-1265, October
1996.
- [950]
- M. R.
Choudhury, Q. Zhou, and K. Mohanram.
Design optimization for single-event upset robustness using simultaneous
dual-vdd and sizing techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 204-209, San Jose, CA, November 5-9 2006.
- [951]
- M. Choudhury, Y. Yoon, J. Guo, and K. Mohanram.
Technology exploration for graphene nanoribbon fets.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
272-277, Anaheim, CA, June 8-13 2008.
- [952]
- M. R. Choudhury
and K. Mohanram.
Reliability analysis of logic circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(3):392-405, March 2009.
- [953]
- M. R. Choudhury
and K. Mohanram.
Low cost concurrent error masking using approximate logic circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(8):1163-1176, August 2013.
- [954]
- P. Chow, S. O. Seo,
J. Rose, K. Chung, G. Paez-Monzon, and I. Rahardja.
The design of an SRAM-based field-programmable gate array - part I:
Architecture.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(2):191-197, June 1999.
- [955]
- P. Chow, S. O.
Seo, J. Rose, K. Chung, G. Paez-Monzon, and I. Rahardja.
The design of an SRAM-based field-programmable gate array - part II:
Circuit design and layout.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(3):321-330, September 1999.
- [956]
- Chee K. Chow.
Projection of circuit performance distributions by multivariate statistics.
IEEE Transactions on Semiconductor Manufacturing, 2(2):60-65, May
1989.
- [957]
- A. Chowdhary, K. Rajagopal, S. Venkatesan, T. Cao, V. Tiourin,
Y. Parasuram, and B. Halpin.
How accurately can we model timing in a placement engine?
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
801-806, Anaheim, CA, June 13-17 2005.
- [958]
- S. Chowdhury and J. S. Barkatullah.
Current estimation in MOS IC logic circuits.
In IEEE International Conference on Computer-Aided Design, Santa
Clara, CA, November 7-10 1988.
- [959]
- S. Chowdhury and J. S. Barkatullah.
Current estimation in MOS IC logic circuits.
In IEEE International Conference on Computer-Aided Design, pages
212-215, Santa Clara, CA, Nov. 7-10 1988.
- [960]
- S. Chowdhury
and J. S. Barkatullah.
Estimation of maximum currents in MOS IC logic circuits.
IEEE Transactions on Computer-Aided Design, 9(6):642-654, June
1990.
- [961]
- S. Chowdhury and
M. A. Breuer.
The construction of minimal area power and ground nets for VLSI circuits.
In IEEE 22nd Design Automation Conference, pages 794-797, 1985.
- [962]
- S. U. Chowdhury
and M. A. Breuer.
Minimal area design of power/ground nets having graph topologies.
IEEE Transactions on Circuits and Systems, CAS-34(12):1441-1451,
December 1987.
- [963]
- S. Chowdhury.
An automated design of minimum-area IC power/ground nets.
In 24th ACM/IEEE Design Automation Conference, pages 223-229,
1987.
- [964]
- S. U. Chowdhury.
Optimum design of reliable IC power networks having general graph topologies.
In 26th ACM/IEEE Design Automation Conference, pages 787-790, June
25-29 1989.
- [965]
- J.-H. Choy,
V. Sukharev, S. Chatterjee, F. N. Najm, A. Kteyan, and S. Moreau.
Finite-difference methodology for full-chip electromigration analysis applied
to 3d IC test structure: Simulation vs. experiment.
In IEEE International Conference on Simulation of Semiconductor Processes
and Devices (SISPAD-17), pages 41-44, Kamakura, Japan, September 7-9
2017.
- [966]
- W. A. Chren, Jr.
Low delay-power product CMOS design using one-hot residue coding.
In ACM/IEEE International Symposium on Low Power Design, pages
145-150, Dana Point, CA, April 23-26 1995.
- [967]
- P. Christie and
D. Stroobandt.
The interpretation and application of rent's rule.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(6):639-648, December 2000.
- [968]
- P. Christie.
Rent exponent prediction methods.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(6):679-688, December 2000.
- [969]
- C. Chu, E. F. Y.
Young, D. K. Y. Tong, and S. Dechu.
Retiming with interconnect and gate delay.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 221-226, San Jose, CA, November 9-13 2003.
- [970]
- C.-T. Chu, X. Zhang,
L. He, and T.-T. Jing.
Temperature aware microprocessor floorplanning considering application
dependent power load.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 586-589, San Jose, CA, November 5-8 2007.
- [971]
- C-Y Chu and M. A. Horowitz.
Charge sharing models for MOS circuits.
In IEEE International Conference on Computer-Aided Design, pages
274-277, Santa Clara, CA, Nov. 11-13 1986.
- [972]
- C-Y. Chu and M. A.
Horowitz.
Charge-sharing models for switch-level simulation.
IEEE Transactions on Computer-Aided Design, CAD-6(6):1053-1061,
November 1987.
- [973]
- C. C. N. Chu and D. F. Wong.
An efficient and optimal algorithm for simultaneous buffer and wire sizing.
IEEE Transactions on Computer-Aided Design, 18(9):1297-1304,
September 1999.
- [974]
- C. C. N. Chu and M. D. F.
Wong.
Greedy wire-sizing is linear time.
IEEE Transactions on Computer-Aided Design, 18(4):398-405, April
1999.
- [975]
- C. Chu.
FLUTE: fast lookup table based wirelength estimation technique.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 696-701, San Jose, CA, November 7-11 2004.
- [976]
- L. O. Chua and A-C. Deng.
Canonical piecewise-linear modeling.
IEEE Transactions on Circuits and Systems, CAS-33(5):511-525, May
1986.
- [977]
- L. O. Chua.
Global optimization : a naive approach.
IEEE Transactions on Circuits and Systems, 37(7):966-969, July
1990.
- [978]
- Y.-L. Chuang,
P.-W. Lee, and Y.-W. Chang.
Voltage-drop aware analytical placement by global power spreading for
mixed-size circuit designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 666-673, San Jose, CA, November 2-5 2009.
- [979]
- P. Chuang,
D. Li, and M. Sachdev.
Constant delay logic style.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(3):554-565, March 2013.
- [980]
- C. T. Chuang and R. Puri.
SOI digital CMOS VLSI - a design perspective.
In Design Automation Conference, pages 709-714, New Orleans, LA, June
21-25 1999.
- [981]
- E.-Y. Chung,
L. Benini, and G. De Micheli.
Dynamic power management using adaptive learning tree.
In IEEE/ACM International Conference on Computer-Aided Design, pages
274-279, San Jose, CA, November 7-11 1999.
- [982]
- E-Y. Chung,
L. Benini, and G. De Micheli.
Automatic source code specialization for energy reduction.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 80-83, Huntington Beach, California, August 6-7 2001.
- [983]
- J. Chung,
J. Xiong, V. Zolotov, and J. A. Abraham.
Path criticality computation in parameterized statistical timing analysis using
a novel operator.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):497-508, April 2012.
- [984]
- J. Chung,
J. Xiong, V. Zolotov, and J. A. Abraham.
Testability-driven statistical path selection.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(8):1275-1287, August 2012.
- [985]
- C.-C. Chung,
D. Sheng, and S.-E. Shen.
High-resolution all-digital duty-cycle corrector in 65-nm CMOS technology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1096-1105, May 2014.
- [986]
- J. Chung and J. A.
Abraham.
A hierarchy of subgraphs underlying a timing graph and its use in capturing
topological correlation in SSTA.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 321-327, San Jose, CA, November 2-5 2009.
- [987]
- J. Chung and J. A.
Abraham.
On computing criticality in refactored timing graphs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(12):1935-1939, December 2012.
- [988]
- J. Chung and J. A.
Abraham.
Refactoring of timing graphs and its use in capturing topological correction in
SSTA.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):485-496, April 2012.
- [989]
- J. Chung and J. A.
Abraham.
Concurrent path selection algorithm in statistical timing analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(9):1715-1726, September 2013.
- [990]
- Y.-T. Chung and J.-H. R.
Jiang.
Functional timing analysis made fast and general.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(9):1421-1434, September 2013.
- [991]
- K-S Chung and C. L. Liu.
Local transformation techniques for multi-level logic circuits utilizing
circuit symmetries for power reduction.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 215-220, Monterey, CA, August 10-12 1998.
- [992]
- J. Ciric and C. Sechen.
Efficient canonical form for boolean marching of complex functions in large
libraries.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 610-617, San Jose, CA, November 4-8 2001.
- [993]
- J. Ciric and C. Seehen.
Efficient canonical form for boolean matching of complex functions in large
libraries.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(5):535-544, May 2003.
- [994]
- M. A. Cirit.
Estimating dynamic power consumption of CMOS circuits.
In IEEE International Conference on Computer-Aided Design, pages
534-537, Nov. 9-12 1987.
- [995]
- M. A. Cirit.
RC trees revisited.
In IEEE 1988 Custom Integrated Circuits Conference, pages
6.7.1-6.7.4, Rochester, NY, May 16-19 1988.
- [996]
- M. A. Cirit.
Switch level random pattern testability analysis.
In 25th ACM/IEEE Design Automation Conference, pages 587-590,
Anaheim, CA, June 12-15 1988.
- [997]
- M. A. Cirit.
Characterizing a VLSI standard cell library.
In IEEE Custom Integrated Circuits Conference (CICC), pages
25.7.1-25.7.4, 1991.
- [998]
- J. Clabes,
J. Friedrich, M. Sweet, J. DiLullo, S. Chu, D. Plass, J. Dawson, P. Muench,
L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz,
S. Runyon, G. Gorman, P. Restle, R. Kalla, J. McGill, and S. Dodson.
Design and implementation of the power5 microprocessor.
In International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 143-145, Austin, TX, May 17-20 2004.
- [999]
- J. Clabes,
J. Friedrich, M. Sweet, J. DiLullo, S. Chu, D. Plass, J. Dawson, P. Muench,
L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz,
S. Runyon, G. Gorman, P. Restle, R. Kalla, J. McGill, and S. Dodson.
Design and implementation of the power5 microprocessor.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
670-672, San Diego, CA, June 7-11 2004.
- [1000]
- L. T. Clark,
B. Choi, and M. Wilkerson.
Reducing translation lookaside buffer active power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 10-13, Seoul, Korea, August 25-27 2003.
- [1001]
- L. T. Clark,
M. Morrow, and W. Brown.
Reverse-body bias and supply collapse for low effective standby power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(9):947-956, September 2004.
- [1002]
- L. T. Clark,
R. Patel, and T. S. Beatty.
Managing standby and active model leakage power in deep sub-micron design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 274-279, Newport Beach, CA, August 9-11 2004.
- [1003]
- E. M. Clarke,
K. L. McMillan, X. Zhao, M. Fujita, and J. Yang.
Spectral transforms for large boolean functions with applications to technology
mapping.
In 30th ACM/IEEE Design Automation Conference, pages 54-60, Dallas,
Texas, June 14-18 1993.
- [1004]
- J. J. Clement,
S. P. Riege, R. Cvijetic, and C. V. Thompson.
Methodology for electromigration critical threshold design rule evaluation.
IEEE Transactions on Computer-Aided Design, 18(5):576-581, May
1999.
- [1005]
- J. Clement.
Electromigration modeling for integrated circuit interconnect reliability
analysis.
IEEE Transactions on Device and Materials Reliability, 1(1):33-42,
March 2001.
- [1006]
- B. Cline,
K. Chopra, D. Blaauw, and Y. Cao.
Analysis and modeling of CD variation for statistical static timing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 60-66, San Jose, CA, November 5-9 2006.
- [1007]
- B. T. Cline,
V. Joshi, D. Sylvester, and D. Blaauw.
STEEL: a technique for stress-enhanced standard cell library design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 691-697, San Jose, CA, November 10-13 2008.
- [1008]
- J. Coburn,
S. Ravi, and A. Raghunathan.
Power emulation: a new paradigm for power estimation.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
700-705, Anaheim, CA, June 13-17 2005.
- [1009]
- P. Cocchini,
M. Pedram, G. Piccinini, and M. Zamboni.
Fanout optimization under a submicron transistor-level delay model.
In IEEE/ACM International Conference on Computer-Aided Design, pages
551-556, San Jose, CA, November 8-12 1998.
- [1010]
- P. Cocchini and
M. Pedram.
Fanout optimization using bipolar LT-trees.
IEEE Transactions on Computer-Aided Design, 19(3):339-349, March
2000.
- [1011]
- L. Codecasa.
Noval feedbak theory of electric circuits - part I: cut-based decomposition.
IEEE Transactions on Circuits and Systems, 59(7):1491-1504, July
2012.
- [1012]
- L. Codecasa.
Novel feedback theory of electric circuits - part II: loop invariants.
IEEE Transactions on Circuits and Systems, 59(7):1505-1518, July
2012.
- [1013]
- C. P. Coelho,
J. R. Phillips, and L. Miguel Silveira.
A convex programming approach to positive real rational approximation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 245-251, San Jose, CA, November 4-8 2001.
- [1014]
- C. P. Coelho,
J. Philips, and L. M. Silveira.
A convex programming approach for generating guaranteed passive approximations
to tabulated frequency-data.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(2):293-301, February 2004.
- [1015]
- J. Cong, C-K. Koh,
and K-S. Leung.
Simultaneous buffer and wire sizing for performance and power optimization.
In International Symposium on Low Power Electronics and Design, pages
271-276, Monterey, CA, August 12-14 1996.
- [1016]
- J. Cong, Z. Pan,
L. He, C-K Koh, and K-Y Khoo.
Interconnect design for deep submicron ics.
In IEEE/ACM International Conference on Computer-Aided Design, pages
478-485, San Jose, CA, November 9-13 1997.
- [1017]
- J. Cong, T. Kong,
J. R. Shinnerl, M. Xie, and X. Yuan.
Large-scale circuit placement: gap and promise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 883-890, San Jose, CA, November 9-13 2003.
- [1018]
- J. Cong, M. Romesis,
and J. R. Shinnerl.
Fast floorplanning by look-ahead enabled recursive bipartitioning.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1719-1732, September 2006.
- [1019]
- J. Cong, P. Gupta,
and J. Lee.
Evaluating statistical power optmization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1750-1762, November 2010.
- [1020]
- J. Cong and L. He.
Theory and algorithm of local-refinement-based optimization with application to
device and interconnect sizing.
IEEE Transactions on Computer-Aided Design, 18(4):406-420, April
1999.
- [1021]
- J. Cong and
M. Sarrafzadeh.
Incremental physical design.
In International Symposium on Physical Design, pages 84-92, San
Diego, CA, April 9-12 2000.
- [1022]
- A. R. Conn, P. K.
Coulman, R. A. Haring, G. L. Morrill, and C. Viswewariah.
Optimization of custom MOS circuits by transistor sizing.
In IEEE/ACM International Conference on Computer-Aided Design, pages
174-180, San Jose, CA, November 10-14 1996.
- [1023]
- A. R. Conn, P. K.
Coulman, R. A. Haring, G. L. Morrill, C. Visweswariah, and C. W. Wu.
Jiffytune: circuit optimization using time-domain sensitivities.
IEEE Transactions on Computer-Aided Design, 17(12):1291-1309,
December 1998.
- [1024]
- A. R. Conn, R. A.
Haring, and C. Visweswariah.
Noise considerations in circuit optimization.
In IEEE/ACM International Conference on Computer-Aided Design, pages
220-227, San Jose, CA, November 8-12 1998.
- [1025]
- A. R. Conn, I. M.
Elfadel, W. W. Molzen, P. R. O'Brien, P. N. Strenski, C. Visweswariah, and
C. B. Whan.
Gradient-based optimization of custom circuits using a static-timing
formulation.
In Design Automation Conference, pages 452-459, New Orleans, LA, June
21-25 1999.
- [1026]
- E. Consoli,
G. Palumbo, and M. Pennisi.
Reconsidering high-speed design criteria for transmission-gate-based
master-slave flip-flop.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):284-295, February 2012.
- [1027]
- G. A. Constantinides, P. Y. K. Cheung, and W. Luk.
Wordlength optimization for linear digital signal processing.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(10):1432-1449, October 2003.
- [1028]
- T. M. Conte, K. N.
Menezes, S. W. Sathaye, and M. C. Toburen.
System-level power consumption modeling and tradeoff analysis techniques for
superscalar processor design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(2):129-137, April 2000.
- [1029]
- M. Conti,
P. Crippa, S. Orcioni, and C. Turchetti.
Layout-based statistical modeling for the prediction of the matching properties
of MOS transistors.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(5):680-685, May 2002.
- [1030]
- C. Cook, Z. Sun,
T. Kim, and S. X.-D. Tan.
Finite difference method for electromigration analysis of multi-branch
interconnects.
In IEEE International Conference on Synthesis, Modeling, Analysis and
Simulation Methods and Applications to Circuit Design (SMACD), pages
1-4, Lisbon, Portugal, June 27-30 2016.
- [1031]
- C. Cook, Z. Sun,
E. Demircan, M. D. Shroff, and S. X.-D. Tan.
Fast electromigration stress evolution analysis for interconnect trees using
krylov subspace method, May 2018.
- [1032]
- R. W. Cook and M. J. Flynn.
Logical network cost and entropy.
IEEE Transactions on Computers, C-22(9):823-826, September 1973.
- [1033]
- S. A. Cook.
The complexity of theorem-proving procedures.
In The 3rd Annual ACM Symposium on Theory of Computing, pages
151-158, Shaker Heights, OH, May 3-5 1971.
- [1034]
- M. Cooke,
H. Mahmoodi-Meimand, and K. Roy.
Energy recovery clocking scheme and flip-flops for ultra low-energy
applications.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 54-59, Seoul, Korea, August 25-27 2003.
- [1035]
- M. M.
Corbalan, A. Keval, T. Toms, D. Lisk, R. Radojcic, and M. Nowak.
Power and signal integrity challenges in 3d systems.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1036]
- V. H. Cordero and
S. P. Khatri.
Clock distribution scheme using coplanar transmission lines.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 56-61, Monterey, CA,
February 25-26 2008.
- [1037]
- R. Cordone,
F. Ferrandi, D. Sciuto, and R. W. Calvo.
An efficient heuristic approach to solve the unate covering problem.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(12):1377-1388, December 2001.
- [1038]
- R. M. Corless and
J. E. Jankowski.
Variations on a theme of euler.
SIAM Review, 58(4):775-792, December 2016.
- [1039]
- J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev.
Synthesizing petri nets from state-based models.
In IEEE/ACM International Conference on Computer-Aided Design, pages
164-171, San Jose, CA, November 5-9 1995.
- [1040]
- J. Cortadella and M. Kishinevsky.
Synchronous elastic circuits with early evaluation and token counterflow.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
416-419, San Diego, CA, June 4-8 2007.
- [1041]
- J. C. Costa, J. C.
Monteiro, and S. Devadas.
Switching activity estimation using limited depth reconvergent path analysis.
In 1997 International Symposium on Low Power Electronics and Design,
pages 184-189, Monterey, CA, August 18-20 1997.
- [1042]
- M. Costagliola, D. de Caro, A. Girardi, R. Izzi, N. Rinaldi,
M. Spirito, and P. Spirito.
An experimental power-lines model for digital asics based on transmission
lines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(1):162-166, January 2012.
- [1043]
- O. Coudert,
R. Haddad, and K. Keutzer.
What is the state of the art in commercial EDA tools for low power?
In International Symposium on Low Power Electronics and Design, pages
181-187, Monterey, CA, August 12-14 1996.
- [1044]
- O. Coudert and
R. Haddad.
Integrated resynthesis for low power.
In International Symposium on Low Power Electronics and Design, pages
169-174, Monterey, CA, August 12-14 1996.
- [1045]
- O. Coudert and J. C.
Madre.
Implicit and incremental computation of primes and essential primes of boolean
functions.
In 29th ACM/IEEE Design Automation Conference, pages 36-39, Anaheim,
CA, June 8-12 1992.
- [1046]
- O. Coudert and J. C.
Madre.
New ideas for solving covering problems.
In 32nd Design Automation Conference, pages 641-646, San Francisco,
CA, June 12-16 1995.
- [1047]
- O. Coudert.
Gate sizing for constrained delay/power/area optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
5(4):465-472, December 1997.
- [1048]
- O. Coudert.
Timing and design closure in physical design flows.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 511-516, San Jose, CA, March 18-21 2002.
- [1049]
- O. Coudert.
An efficient algorithm to verify generalized false paths.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
188-193, Anaheim, CA, June 13-18 2010.
- [1050]
- S. L. Coumeri and
D. E. Thomas.
Memory modeling for system synthesis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 179-184, Monterey, CA, August 10-12 1998.
- [1051]
- S. L. Coumeri and
D. E. Thomas, Jr.
Memory modeling for system synthesis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):327-334, June 2000.
- [1052]
- P. F. Cox, R. G.
Burch, P. Yang, and D. E. Hocevar.
New implicit integration method for efficient latency exploitation in circuit
simulation.
IEEE Transactions on Computer-Aided Design, 8(10):1051-1064, October
1989.
- [1053]
- Y. L. Le Coz,
D. Krishna, D. M. Petranovic, W. M. Loh, and P. Bendix.
A sum-over-paths impulse-response moment extraction algorithm for
IC-interconnect networks: verification, coupled RC lines.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 665-670, San Jose, CA, November 9-13 2003.
- [1054]
- J. F. Croix and D. F. Wong.
A fast and accurate technique to optimize characterization tables for logic
synthesis.
In 34th Design Automation Conference, pages 337-340, Anaheim, CA,
June 9-13 1997.
- [1055]
- J. F. Croix and D. F. Wong.
Blade and razor: cell and interconnect delay analysis using current-based
models.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
386-389, Anaheim, CA, June 2-6 2003.
- [1056]
- J. Crossley,
A. Puggelli, H.-P. Le, B. Yang, R. Nancollas, K. Jung, L. Kong, N. Narevsky,
Y. Lu, N. Sutardja, E. J. An, A. L. Sangiovanni-Vincentelli, and E. Alon.
BAG: a designer-oriented integrated framework for the development of AMS
circuit generators.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 74-81, San Jose, CA, November 18-21 2013.
- [1057]
- A. L. Crouch and J. C.
Potter.
A box of dots: using scan-based path delay test for timing verification.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [1058]
- J. Cui and D. L. Maskell.
A fast high-level event-driven thermal estimator for dynamic thermal aware
scheduling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(6):904-917, June 2012.
- [1059]
- C. Cui and Z. Zhang.
Uncertainty quantification of electronic and photonic ics with non-gaussian
correlated process variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [1060]
- T. S. Czajkowski
and S. D. Brown.
Using negative edge triggered ffs to reduce glitching oower in FPGA circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
324-329, San Diego, CA, June 4-8 2007.
- [1061]
- T. S. Czajkowski
and S. D. Brown.
Functionally linear decomposition and synthesis of logic circuits for fpgas.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages 18-23,
Anaheim, CA, June 8-13 2008.
- [1062]
- T. S. Czajkowski
and S. D. Brown.
Decomposition-based vectorless toggle rate computation for FPGA circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1723-1735, November 2010.
- [1063]
- J. L. da Silva,
Jr., F. Catthoor, D. Verkest, and H. De Man.
Power exploration for dynamic data types through virtual memory management
refinement.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 311-316, Monterey, CA, August 10-12 1998.
- [1064]
- F. Dabiri,
A. Nahapetian, T. Massey, M. Potkonjak, and M. Sarrafzadeh.
General methodology for soft-error-aware power optimization using gate sizing.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1788-1797, October 2008.
- [1065]
- H. F. Dadgour,
R. V. Joshi, and K. Banerjee.
A novel variation-aware low-power keeper architecture for wide fan-in dynamic
gates.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
977-982, San Francisco, CA, July 24-28 2006.
- [1066]
- H. Dadgour,
V. De, and K. Banerjee.
Statistical modeling of metal-gate work-function variability in emerging device
technologies and implications for circuit design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 270-277, San Jose, CA, November 10-13 2008.
- [1067]
- H. F. Dadgour and
K. Banerjee.
Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power
applications.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
306-311, San Diego, CA, June 4-8 2007.
- [1068]
- H. F. Dadgour and
K. Banerjee.
A novel variation-tolerant keeper architecture for high-performance low-power
wide fan-in dynamic or gates.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(11):1567-1577, November 2010.
- [1069]
- W. Daems,
G. Gielen, and W. Sansen.
Simulation-based automatic generation of signomial and posynomial performance
models for analog integrated circuit sizing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 70-74, San Jose, CA, November 4-8 2001.
- [1070]
- A. J. Daga, L. Mize,
S. Sripada, C. Wolff, and Q. Wu.
Automated timing model generation.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
146-151, New Orleans, LA, June 10-14 2002.
- [1071]
- M. Dagenais.
Efficient algorithmic decomposition of transistor groups into series, parallel,
and bridge combinations.
IEEE Transactions on Circuits and Systems, 38(6):569-581, June
1991.
- [1072]
- J. Dai, L. Wang, and
F. Jain.
Analysis of defect tolerance in molecular crossbar electronics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(4):529-540, April 2009.
- [1073]
- W. W-M Dai.
Chip parasitic extraction and signal integrity verification.
In 34th Design Automation Conference, pages 717-719, Anaheim, CA,
June 9-13 1997.
- [1074]
- K. Daloukas,
N. Evmorfopoulos, G. Drasidis, M. Tsiampas, P. Tsompanopoulou, and G. I.
Stamoulis.
Fast transform-based preconditioners for large-scale power grid analysis on
massively parallel architectures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 384-391, San Jose, CA, November 5-8 2012.
- [1075]
- K. Daloukas,
N. Evmorfopoulos, P. Tsompanopoulou, and G. Stamoulis.
Parallel fast transform-based preconditioners for large-scale power grid
analysis on graphics processing units (gpus).
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(10):1653-1666, October 2016.
- [1076]
- J. Dambre,
D. Stroobandt, and J. Van Campenhout.
Toward the accurate prediction of placement wire length distributions in VLSI
circuits.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):339-348, April 2004.
- [1077]
- M. Damiani and G. De
Micheli.
Don't care set specifications in combinational and sequential logic circuits.
IEEE Transactions on Computer-Aided Design, 12(3):365-388, March
1993.
- [1078]
- R. I. Damper and
N. Burgess.
MOS test pattern generation using path algebras.
IEEE Transactions on Computers, C-36(9):1123-1128, September 1987.
- [1079]
- A. P. Dancy,
R. Amirtharajah, and A. P. Chandrakasan.
High-efficiency multiple output DC-DC conversion for low-voltage systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):252-263, June 2000.
- [1080]
- T. N. Dang,
A. Roychoudhury, T. Mitra, and P. Mishra.
Generating test programs to cover pipeline interactions.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
142-147, San Francisco, CA, July 26-31 2009.
- [1081]
- L. Daniel, A. L.
Sangiovanni-Vincentelli, and J. White.
Techniques for including dielectrics when extracting passive low-order models
of high speed interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 240-244, San Jose, CA, November 4-8 2001.
- [1082]
- L. Daniel, O.-C.
Siong, L.-S. Chay, K.-H. Lee, and J. White.
A multiparameter moment-matching model-reduction approach for generating
geometrically parameterized interconnect performance models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):678-693, May 2004.
- [1083]
- L. Daniel and
J. Phillips.
Model order reduction for strictly passive and causal distributed systems.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages 46-51,
New Orleans, LA, June 10-14 2002.
- [1084]
- H. Q. Dao, K. Nowka,
and V. G. Oklobdzija.
Analysis of clocked timing elements for dynamic voltage scaling effects over
process parameter variation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 56-59, Huntington Beach, California, August 6-7 2001.
- [1085]
- H.-Q. Dao, B. R.
Zeydel, and V. G. Oklobdzija.
Energy optimization of pipelined digital systems using circuit sizing and
supply scaling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(2):122-134, February 2006.
- [1086]
- J. Darringer, E. Davidson, D. Hathaway, B. Koenemann, M. Lavin,
J. K. Morrell, K. Rahmat, W. Roesner, E. Schanzenbach, G. Tellez, and
L. Trevillyan.
EDA in IBM: Past, present, and future.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1476-1497, December 2000.
- [1087]
- J. A. Darringer.
Multi-core design automation challenges.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
760-764, San Diego, CA, June 4-8 2007.
- [1088]
- F. Dartu,
N. Menezes, and L. T. Pileggi.
Performance computation for precharacterized CMOS gates with RC loads.
IEEE Transactions on Computer-Aided Design, 15(5):544-553, May
1996.
- [1089]
- F. Dartu and L. T.
Pileggi.
Calculating worst-case gate delays due to dominant capacitance coupling.
In 34th Design Automation Conference, pages 46-51, Anaheim, CA, June
9-13 1997.
- [1090]
- F. Dartu and L. T.
Pileggi.
TETA: Transistor-level engine for timing analysis.
In IEEE/ACM 35th Design Automation Conference, pages 595-598, San
Francisco, CA, June 15-19 1998.
- [1091]
- K. K. Das, R. V.
Joshi, C.-T. Chuang, P. W. Cook, and R. B. Brown.
New optimal design strategies and analysis of ultra-low leakage circuits for
nano-scale SOI technology.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 168-171, Seoul, Korea, August 25-27 2003.
- [1092]
- S. Das, A. P.
Chandrakasan, and R. Reif.
Calibration of rent's rule models for three-dimensional integrated circuits.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):359-366, April 2004.
- [1093]
- S. Das, D. Blaauw,
D. Bull, K. Flautner, and R. Aitken.
Addressing design margins through error-tolerant circuits.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 11-12,
San Francisco, CA, July 26-31 2009.
- [1094]
- D. Das, K. Killpack,
C. Kashyap, A. Jas, and H. Zhou.
Pessimism reduction in coupling-aware static timing analysis using timing and
logic filtering.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(3):466-478, March 2010.
- [1095]
- D. Das, A. Shebaita,
H. Zhou, Y. Ismail, and K. Killpack.
FA-STAC: an algorithmic framework for fast and accurate coupling aware
static timing analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(3):443-456, March 2011.
- [1096]
- S. Das, P. Whatmough,
and D. Bull.
Modeling and characterization of the system-level power delivery network for a
dual-core ARM cortex-a57 cluster in 28nm CMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 146-151, Rome, Italy, July 22-24 2015.
- [1097]
- A. Dasgupta and
R. Karri.
Electromigration reliability enhancement via bus activity distributions.
In 33rd Design Automation Conference, pages 353-356, Las Vegas, NV,
June 3-7 1996.
- [1098]
- A. Dasgupta and
R. Karri.
High-reliability, low-energy microarchitecture synthesis.
IEEE Transactions on Computer-Aided Design, 17(12):1273-1280,
December 1998.
- [1099]
- A. Datta,
S. Bhunia, S. Mukhopadhyay, and K. Roy.
Delay modeling and statistical design of pipelined circuit under process
variation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2427-2436, November 2006.
- [1100]
- A. Datta,
S. Bhunia, J.-H. Choi, S. Mukhopadhyay, and K. Roy.
Profit aware circuit design under process variations considering speed binning.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(7):806-815, July 2008.
- [1101]
- A. Davare,
K. Lwin, A. Kondratyev, and A. Sangiovanni-Vincentelli.
The best of both worlds: the efficient asynchronous implementation of
synchronous specifications.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
588-591, San Diego, CA, June 7-11 2004.
- [1102]
- M. Dave, M. Jain,
M. S. Baghini, and D. Sharma.
A variation tolerant current-mode signaling scheme for on-chip interconnects.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(2):342-353, February 2013.
- [1103]
- H. A. David and H. N.
Nagaraja.
Order Statistics.
John Wiley & Sons, Inc., Hoboken, NJ, 3rd edition, 2003.
- [1104]
- R. David and K. Wagner.
Analysis of detection probability and some applications.
IEEE Transactions on Computers, 39(10):1284-1291, October 1990.
- [1105]
- M. Davio,
A. Thayse, and G. Bioul.
Symbolic computation of fourier transforms of boolean functions.
Philips Research Reports, 27:386-403, August 1972.
- [1106]
- J. A. Davis, V. K.
De, and J. D. Meindl.
A stochastic wire length distribution for gigascale integration (GSI).
In IEEE 1997 Custom Integrated Circuits Conference, pages 145-150,
Santa Clara, CA, May 5-8 1997.
- [1107]
- M. H. A. Davis.
Linear Estimation and Stochastic Control.
Methuen, Slingsby, York, UK, June 1 1977.
- [1108]
- E. J. Davison.
A method for simplifying linear dynamic systems.
IEEE Transactions on Automatic Control, AC-11(1):93-101, January
1966.
- [1109]
- A. Davoodi,
V. Khandelwal, and A. Srivastava.
Empirical models for net-length probability distribution and applications.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1066-1075, October 2004.
- [1110]
- A. Davoodi,
V. Khandelwal, and A. Srivastaya.
Variability inspired implementation selection problem.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 423-427, San Jose, CA, November 7-11 2004.
- [1111]
- A. Davoodi,
V. Khandelval, and A. Srivastava.
Probabilistic evaluation solutions in variability-driven optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):3010-3016, December 2006.
- [1112]
- A. Davoodi and
A. Srivastava.
Voltage scheduling under unpredictabilities: a risk management paradigm.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 302-305, Seoul, Korea, August 25-27 2003.
- [1113]
- A. Davoodi and
A. Srivastava.
Probabilistic dual-vth leakage optimization under variability.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 143-148, San Diego, CA, August 8-10 2005.
- [1114]
- A. Davoodi and
A. Srivastava.
Variability driven gate sizing for binning yield optimization.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
959-964, San Francisco, CA, July 24-28 2006.
- [1115]
- A. Davoodi and
A. Srivastava.
Variability driven gate sizing for binning yield optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(6):683-692, June 2008.
- [1116]
- S. K. De and N. R. Aluru.
Physical and reduced-order dynamic analysis of MEMS.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 270-273, San Jose, CA, November 9-13 2003.
- [1117]
- V. De and S. Borkar.
Technology and design challenges for low power and high performance.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 163-168, San Diego, CA, August 16-17 1999.
- [1118]
- E. de Angel and
E. E. Swartzlander, Jr.
Survey of low power techniques for roms.
In 1997 International Symposium on Low Power Electronics and Design,
pages 7-11, Monterey, CA, August 18-20 1997.
- [1119]
- D. K. de Vries.
Methods to quantify the detection probability of killing defects.
IEEE Transactions on Semiconductor Manufacturing, 18(3):406-411,
August 2005.
- [1120]
- V. De.
Fine-grain power management in manycore processor and system-on-chip (soc)
designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 159-164, Austin, TX, November 2-6 2015.
- [1121]
- D. Debnath and
Z. G. Vranesic.
A fast algorithm for OR-AND-OR synthesis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(9):1166-1176, September 2003.
- [1122]
- V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Y. Xie, and
M. J. Irwin.
The effect of threshold voltages on the soft error rate.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 503-510, San Jose, CA, March 22-24 2004.
- [1123]
- V. Degalahal, L. Li, V. Narayanan, M. Kandemir, and M. J. Irwin.
Soft errors issues in low-power caches.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(10):1157-1166, October 2005.
- [1124]
- M. M. Dehnavi,
D. M. Fernandez, J.-L. Gaudiot, and D. D. Giannacopoulos.
Parallel sparse approximate inverse preconditioning on graphic processing
units.
IEEE Transactions on Parallel and Distributed Systems,
24(9):1852-1862, September 2013.
- [1125]
- A. DeHon and K. L.
Likharev.
Hybrid CMOS/nanoelectronic digital circuits: devices, archiectures, and
design automation.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 375-382, San Jose, CA, November 6-10 2005.
- [1126]
- D. L.
Deleganes, M. Barany, G. Geannopoulos, K. Kreitzer, A. P. Singh, and
S. Wijeratne.
Low voltage swing logic circuits for a pentiumr 4 processor integer core.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
678-680, San Diego, CA, June 7-11 2004.
- [1127]
- A. Demir,
A. Mehrotra, and J. Roychowdhury.
Phase noise in oscillators: a unifying theory and numerical methods for
characterization.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 47(5):655-675, May 2000.
- [1128]
- A. Demir and B. Erman.
Simulation of temporal stochastic phenomena in electronic and biological
systems: a comparative review, examples and synergies.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 811-818, San Jose, CA, November 18-21 2013.
- [1129]
- A. Demir and M. S. Hanay.
Numerical analysis of multidomain systems: coupled nonlinear pdes and daes with
noise.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 37(7):1445-1458, July 2018.
- [1130]
- S. Demko, W. F.
Moss, and P. W. Smith.
Decay rates for inverses of band matrices.
Mathematics of computation, 43(168):491-499, October 1984.
- [1131]
- A-C. Deng, Y-C.
Shiau, and K-H. Loh.
Time domain current waveform simulation of CMOS circuits.
In IEEE International Conference on Computer-Aided Design, pages
208-211, Santa Clara, CA, Nov. 7-10 1988.
- [1132]
- J. Deng,
K. Batselier, Y. Zhang, and N. Wong.
An efficient two-level DC operating points finder for transistor circuits.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [1133]
- Y. Deng and W. P. Maly.
2.5-dimensional VLSI system integration.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):668-677, June 2005.
- [1134]
- A-C. Deng and Y-C. Shiau.
Generic linear RC delay modeling for digital CMOS circuits.
IEEE Transactions on Computer-Aided Design, 9(4):367-376, April
1990.
- [1135]
- B. Dennington.
Low power design from technology challenge to great products.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 213-213, Tegernsee, Germany, October 4-6 2006.
- [1136]
- V. V. Deodhar and
J. A. Davis.
Optimization of throughput performance for low-power VLSI interconnects.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):308-318, March 2005.
- [1137]
- H. S. Deogun,
R. R. Rao, D. Sylvester, and D. Blaauw.
Leakage- and crosstalk-aware bus encoding for total power reduction.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
779-782, San Diego, CA, June 7-11 2004.
- [1138]
- H. S. Deogun,
R. Senger, D. Sylvester, R. Brown, and K. Nowka.
A dual-vdd boosted pulsed bus technique for low power and low leakage
operation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 73-78, Tegernsee, Germany, October 4-6 2006.
- [1139]
- U. Desai, S. Tam,
R. Kim, J. Zhang, and S. Rusu.
Itanium processor clock design.
In International Symposium on Physical Design, pages 94-98, San
Diego, CA, April 9-12 2000.
- [1140]
- D. Deschacht.
DSM interconnects: importance of inductance effects and corresponding range
of length.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(7):777-779, July 2006.
- [1141]
- Charles A. Desoer and
Ernest S. Kuh.
Basic Circuit Theory.
McGraw-Hill Book Company, 1969.
- [1142]
- P. F.
Desrumaux, Y. Dupret, J. Tingleff, S. Minehaney, M. Redfordy, L. Latorrez,
and P. Nou.
An efficient control variates method for yield estimation of analog circuits
based on a local model.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 415-421, San Jose, CA, November 5-8 2012.
- [1143]
- A. Deutsch,
P. W. Coteus, G. V. Kopcsay, H. H. Smith, C. W. Surovic, B. L. Krauter, D. C.
Edelstein, and P. J. Restle.
On-chip wiring design challenges for gigahertz operation.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
529-555, Las Vegas, NV, June 18-22 2001.
- [1144]
- S. Devadas,
K. Keutzer, and J. White.
Estimation of power dissipation in CMOS combinational circuits.
In IEEE Custom Integrated Circuits Conference, pages 19.7.1-19.7.6,
1990.
- [1145]
- S. Devadas,
K. Keutzer, S. Malik, and A. Wang.
Certified timing verification and the transition delay of a logic circuit.
In 29th ACM/IEEE Design Automation Conference, pages 549-555,
Anaheim, CA, June 8-12 1992.
- [1146]
- S. Devadas,
K. Keutzer, and J. White.
Estimation of power dissipation in CMOS combinational circuits using boolean
function manipulation.
IEEE Transactions on Computer-Aided Design, 11(3):373-383, March
1992.
- [1147]
- S. Devadas,
K. Keutzer, and S. Malik.
Computation of floating mode delay in combinational circuits: theory and
algorithms.
IEEE Transactions on Computer-Aided Design, 12(12):1913-1923,
December 1993.
- [1148]
- S. Devadas,
K. Keutzer, S. Malik, and A. Wang.
Computation of floating mode delay in combinational circuits: practice and
implementation.
IEEE Transactions on Computer-Aided Design, 12(12):1924-1936,
December 1993.
- [1149]
- S. Devadas,
K. Keutzer, S. Malik, and A. Wang.
Certified timing verification and the transition delay of a logic circuit.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2(3):333-342, September 1994.
- [1150]
- S. Devadas and
S. Malik.
A survey of optimization techniques targeting low power VLSI circuits.
In 32nd Design Automation Conference, pages 242-247, San Francisco,
CA, June 12-16 1995.
- [1151]
- S. Devadas.
Comparing two-level and ordered binary decision diagram representations of
logic functions.
IEEE Transactions on Computer-Aided Design, 12(5):722-723, May
1993.
- [1152]
- A. Devgan,
H. Ji, and W. Dai.
How to efficiently capture on-chip inductance effects: introducing a new
circuit element K.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 150-155, San Jose, CA, November 5-9 2000.
- [1153]
- A. Devgan and
C. Kashyap.
Block-based static timing analysis with uncertainty.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 607-614, San Jose, CA, November 9-13 2003.
- [1154]
- A. Devgan and P. R.
O'Brien.
Realizable reduction for RC interconnect circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
204-207, San Jose, CA, November 7-11 1999.
- [1155]
- A. Devgan and R. A.
Rohrer.
Event driven adaptively controlled explicit simulation of integrated circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
136-140, Santa Clara, CA, November 7-11 1993.
- [1156]
- A. Devgan.
Efficient and accurate transient simulation in charge-voltage plane.
In IEEE/ACM International Conference on Computer-Aided Design, pages
110-114, San Jose, CA, November 5-9 1995.
- [1157]
- A. Devgan.
Efficient coupled noise estimation for on-chip interconnects.
In IEEE/ACM International Conference on Computer-Aided Design, pages
147-151, San Jose, CA, November 9-13 1997.
- [1158]
- S. Dey, F. Brglez, and
G. Kedem.
Corolla based circuit partitioning and resynthesis.
In 27th ACM/IEEE Design Automation Conference (DAC90), pages 607-612,
Orlando, FL, June 24-28 1990.
- [1159]
- S. Dey,
A. Raghunathan, N. K. Jha, and K. Wakabayashi.
Controller-based power management for control-flow intensive designs.
IEEE Transactions on Computer-Aided Design, 18(10):1496-1508, October
1999.
- [1160]
- T. Dhaene and D. De
Zutter.
Selection of lumped element models for coupled lossy transmission lines.
IEEE Transactions on Computer-Aided Design, 11(7):805-815, July
1992.
- [1161]
- N. V. T. D'Halleweyn, J. Benson, W. Redman-White, K. Mistry, and
M. Swanenberg.
MOOSE: a physically based compact DC model of SOI ldmosfets for analogue
circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(10):1399-1410, October 2004.
- [1162]
- N. Dhanwada,
D. Hathaway, V. Zyuban, P. Peng, K. Moody, W. Dungan, A. Joseph, R. Rao, and
C. Gonzalez.
Efficient PVT independent abstraction of large IP blocks for hierarchical
power analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 458-465, San Jose, CA, November 18-21 2013.
- [1163]
- N. Dhanwada,
R. Davis, and J. Frenkil.
Towards a standard flow for system level power modeling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 73, San Jose, CA, November 2-6 2014.
- [1164]
- I. B. Dhaou,
M. Ismail, and H. Tenhunen.
Current mode, low-power, on-chip signaling in deep-submicron CMOS technology.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(3):397-406, March 2003.
- [1165]
- I. B. Dhaou and
H. Tenhunen.
Efficient library characterization for high-level power estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(6):657-661, June 2004.
- [1166]
- A. Dharchoudhury, R. Panda, D. Blaauw, R. Vaidyanathan,
B. Tutuianu, and D. Bearden.
Design and analysis of power distribution networks in powerpc microprocessors.
In IEEE/ACM 35th Design Automation Conference, pages 738-743, San
Francisco, CA, June 15-19 1998.
- [1167]
- A. Dharchoudhury and S. M. Kang.
Performance-constrained worst-case variability minimization of VLSI circuits.
In 30th ACM/IEEE Design Automation Conference, pages 154-158, Dallas,
TX, June 14-18 1993.
- [1168]
- A. Dharchoudhury and S. M. Kang.
Worst-case analysis and optimization of VLSI circuit performances.
IEEE Transactions on Computer-Aided Design, 14(4):481-492, April
1995.
- [1169]
- F. M. D'Heurle.
Electromigration and failure in electronics : an introduction.
In Proceedings of the IEEE, page 1409, October 1971.
- [1170]
- Y. S. Dhillon,
A. U. Diril, A. Chatterjee, and H.-H. S. Lee.
Algorithm for achieving minimum energy consumption in CMOS circuits using
multiple supply and threshold voltages at the module level.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 693-700, San Jose, CA, November 9-13 2003.
- [1171]
- Y. S. Dhillon,
A. U. Diril, A. Chatterjee, and A. D. Singh.
Analysis and optimization of nanometer CMOS circuits for soft-error
tolerance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(5):514-524, May 2006.
- [1172]
- G. Dhiman and T. S.
Rosing.
Dynamic power management using machine learning.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 747-754, San Jose, CA, November 5-9 2006.
- [1173]
- R. P. Dick,
G. Lakshminarayana, A. Raghunathan, and N. K. Jha.
Analysis of power dissipation in embedded systems using real-time operating
systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(5):615-627, May 2003.
- [1174]
- R. P. Dick.
Reliability, thermal, and power modeling and optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 181-184, San Jose, CA, November 7-11 2010.
- [1175]
- Donald L. Dietmeyer.
Logic Design of Digital Systems, 3rd Ed..
Allyn and Bacon, Inc., Boston, MA, 1988.
- [1176]
- G. Dimitrakopoulos and V. Paliouras.
A novel architecture and a systematic graph-based optimization methodology for
modulo multiplication.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(2):354-370, February 2004.
- [1177]
- C.-S. Ding, C.-T.
Hsieh, Q. Wu, and M. Pedram.
Stratified random sampling for power estimation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
576-582, San Jose, CA, November 10-14 1996.
- [1178]
- C-S Ding, Q. Wu, C-T
Hsieh, and M. Pedram.
Statistical estimation of the cumulative distribution function for power
dissipation in VLSI circuits.
In 34th Design Automation Conference, pages 371-376, Anaheim, CA,
June 9-13 1997.
- [1179]
- C-S Ding, C-T
Hsieh, and M. Pedram.
Improving sampling efficiency for system level power estimation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 115-117, Monterey, CA, August 10-12 1998.
- [1180]
- C.-S. Ding, C.-Y.
Tsui, and M. Pedram.
Gate-level power estimation using tagged probabilistic simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 17(11):1099-1107, November 1998.
- [1181]
- C.-S. Ding, Q. Wu,
C.-T. Hsieh, and M. Pedram.
Stratified random sampling for power estimation.
IEEE Transactions on Computer-Aided Design, 17(6):465-471, June
1998.
- [1182]
- C.-S. Ding, C.-T.
Hsieh, and M. Pedram.
Improving the efficiency of monte carlo power estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(5):584-593, October 2000.
- [1183]
- L. Ding, D. Blaauw,
and P. Mazumder.
Efficient crosstalk noise modeling using aggressor and tree reductions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 595-600, San Jose, CA, November 10-14 2002.
- [1184]
- L. Ding, D. Blaauw,
and P. Mazumder.
Accurate crosstalk noise modeling for early signal integrity analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(5):627-634, May 2003.
- [1185]
- Y. Ding, Y. Wu, and
W. Qian.
Generating multiple correlated probabilities for MUX-based stochastic
computing architecture.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 519-526, San Jose, CA, November 2-6 2014.
- [1186]
- L. Ding and P. Mazumder.
A novel technique to improve noise immunity of CMOS dynamic logic circuits.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
900-903, San Diego, CA, June 7-11 2004.
- [1187]
- L. Ding and
P. Mazumder.
On circuit techniques to improve noise immunity of CMOS dynamic logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(9):910-925, September 2004.
- [1188]
- Q. Dinh, D. Chen,
and M.-D.-F. Wong.
A routing approach to reduce glitches in low power fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(2):235-245, February 2010.
- [1189]
- S. W.
Director, P. K. Khosla, R. A. Rohrer, and R. A. Rutenbar.
Reengineering the curriculum: Design and analysis of a new undergraduate
electrical and computer engineering degree at carnegie mellon university.
In Proceedings of the IEEE, pages 1246-1269, September 1995.
- [1190]
- A. U. Diril, Y. S.
Dhillon, A. Chatterjee, and A. D. Singh.
Level-shifter free design of low power dual supply voltage CMOS circuits
using dual threshold voltages.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(9):1103-1107, September 2005.
- [1191]
- T. Djurhuus and
V. Krozer.
Theory of injection-locked oscillator phase noise.
IEEE Transactions on Circuits and Systems, 58(2):312-325, February
2011.
- [1192]
- V. B.
Dmitriev-Zdorov.
Multicycle generalization - a new way to improve the convergence of waveform
relaxation for circuit simulation.
IEEE Transactions on Computer-Aided Design, 17(5):435-443, May
1998.
- [1193]
- L. Dolecek,
M. Qazi, D. Shah, and A. Chandrakasan.
Breaking the simulation barrier: SRAM evaluation through norm minimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 322-329, San Jose, CA, November 10-13 2008.
- [1194]
- J. Donald and
M. Martonosi.
Power efficiency for variation-tolerant multicore processors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 304-309, Tegernsee, Germany, October 4-6 2006.
- [1195]
- W. E. Donath.
Equivalence of memory to "random logic".
IBM Journal of Research and Development, pages 401-407, September
1974.
- [1196]
- C. Dong, D. Chen,
S. Tanachutiwat, and W. Wang.
Performance and power evaluation of a 3d CMOS/nanomaterial reconfigurable
architecture.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 758-764, San Jose, CA, November 5-8 2007.
- [1197]
- W. Dong, P. Li,
and G.-M. Huang.
SRAM dynamic stability: theory, variability and analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 378-385, San Jose, CA, November 10-13 2008.
- [1198]
- W. Dong, P. Li,
and X. Ye.
Wavepipe: parallel transient simulation of analog and digital circuits on
multi-core shared-memory machines.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
238-243, Anaheim, CA, June 8-13 2008.
- [1199]
- X. Dong, J. Zhao,
and Y. Xie.
Fabrication cost analysis and cost-aware design space exploration for 3-D
ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(12):1959-1972, December 2010.
- [1200]
- W. Dong and P. Li.
Final-value odes: stable numerical integration and its application to parallel
circuit analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 403-409, San Jose, CA, November 2-5 2009.
- [1201]
- W. Dong and P. Li.
Parallelizable stable explicit numerical integration for efficient circuit
simulation.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
382-385, San Francisco, CA, July 26-31 2009.
- [1202]
- C. Dong and X. Li.
Efficient SRAM failure rate prediction via gibbs sampling.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
200-205, San Diego, CA, June 5-9 2011.
- [1203]
- N. Dong and
J. Roychowdhury.
General-purpose nonlinear model-order reduction using piecewise-polynomial
representations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):249-264, February 2008.
- [1204]
- M. Donno,
A. Ivaldi, L. Benini, and E. Macii.
Clock-tree power optimization based on RTL clock-gating.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
622-627, Anaheim, CA, June 2-6 2003.
- [1205]
- F. Dorfler and
F. Bullo.
Kron reduction of graphs with applications to electrical networks.
IEEE Transactions on Circuits and Systems, 60(1):150-163, January
2013.
- [1206]
- A. Doumar and H. Ito.
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable
gate arrays: a survey.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):386-405, June 2003.
- [1207]
- B. Doyle,
P. Mahoney, E. Fetzer, and S. Naffziger.
Clock distribution on a dual-core, multi-threaded itanium family
microprocessor.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 1-6, Austin, TX, May 9 - 11 2005.
- [1208]
- N. Dragone,
R. Zafalon, C. Guardiani, and C. Silvano.
Power invariant vector compaction based on bit clustering and temporal
partitioning.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 118-120, Monterey, CA, August 10-12 1998.
- [1209]
- R. Drechsler, M. Sauerhoff, and D. Sieling.
The complexity of the inclusion operation on ofdds.
IEEE Transactions on Computer-Aided Design, 17(5):457-459, May
1998.
- [1210]
- R. Drechsler, N. Drechsler, and W. Gunther.
Fast exact minimization of BDD's.
IEEE Transactions on Computer-Aided Design, 19(3):384-389, March
2000.
- [1211]
- F. Dresig, Ph.
Lanches, O. Rettig, and U. G. Baitinger.
Simulation and reduction of CMOS power dissipation at logic level.
In European Design Automation Conference (EDAC), pages 341-346,
1993.
- [1212]
- M. Drinic,
D. Kirovski, S. Megerian, and M. Potkonjak.
Latency-guided on-chip bus-network design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2663-2673, December 2006.
- [1213]
- D. G. Drmanac,
F. Liu, and L.-C. Wang.
Predicting variability in nanoscale lithography processes.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
545-550, San Francisco, CA, July 26-31 2009.
- [1214]
- N. Dronavalli
and V. Malik.
A design method for estimating power in CMOS gates using logical lffort.
In The First Annual Northeast Workshop on Circuits and Systems
(NEWCAS-03), pages 113-116, Montreal, Quebec, June 17-20 2003.
- [1215]
- Y. Du, D. Guo, M.-D.-F.
Wong, H. Yi, H.-S.-P. Wong, H. Zhang, and Q. Ma.
Block copolymer directed self-assembly (DSA) aware contact layer optimization
for 10 nm 1d standard cell library.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 186-193, San Jose, CA, November 18-21 2013.
- [1216]
- X. Duan, Y. Hu, and
K. Mayaram.
Simulation of ring oscillators using the harmonic balance method.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 137-140, Montreal, Quebec, June 20-23 2004.
- [1217]
- C. Duan, C. Zhu, and
S. P. Khatri.
Forbidden transition free crosstalk avoidance CODEC design.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 44-49, Monterey, CA,
February 25-26 2008.
- [1218]
- X. Duan and K. Mayaram.
An efficient and robust method for ring-oscillator simulation using the
harmonic-balance method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(8):1225-1233, August 2005.
- [1219]
- X. Duan and K. Mayaram.
Frequency-domain simulation of ring oscillators with a multiple-probe method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2833-2842, December 2006.
- [1220]
- F. Dubeau and
C. Gnang.
Fixed point and newton's methods for solving a nonlinear equation: from linear
to high-order convergence.
SIAM Review, 56(4):691-708, December 2014.
- [1221]
- F. Dubeau and C. Gnang.
Fixed point and newton's methods for solving a nonlinear equation: From linear
to higher-order convergence.
SIAM Review, 56(4):691-708, 2014.
- [1222]
- E. Dubrova,
M. Teslenko, and A. Martinelli.
Kauffman networks: analysis and applications.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 479-484, San Jose, CA, November 6-10 2005.
- [1223]
- R. J. Duffin.
Topology of series-parallel networks.
Journal of Mathematical Analysis and Applications, pages 303-318,
1965.
- [1224]
- L. Dupont,
S. Roy, and J.-Y. Chouinard.
A hardware architecture for the generation of wnaf random integers.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 99-102, Quebec City, Quebec, June 19-22 2005.
- [1225]
- J. A. Dussault.
A testability measure.
In IEEE Digital Semiconductor Test Symposium, pages 113-116, Cherry
Hill, NJ, Oct-Nov. 1978.
- [1226]
- R. Dutra,
J. Bachrach, and K. Sen.
Smtsampler: efficient stimulus generation from complex SMT constraints.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [1227]
- S. Dutt and W. Deng.
Probability-based approaches to VLSI circuit partitioning.
IEEE Transactions on Computer-Aided Design, 19(5):534-549, May
2000.
- [1228]
- R. Dutta and
M. Marek-Sadowska.
Automatic sizing of power/ground (p/g) networks in VLSI.
In 26th ACM/IEEE Design Automation Conference, pages 783-786, Las
Vegas, NV, June 25-29 1989.
- [1229]
- R. W. Dutton and
A. J. Strojwas.
Perspectives on technology and technology-driven CAD.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1544-1560, December 2000.
- [1230]
- S. G. Duvall.
Practical statistical design of complex integrated circuit products.
In ACM/IEEE Design Automation Conference, pages 561-565, Dallas, TX,
June 14-18 1993.
- [1231]
- S. G. Duvall.
Toward a practical methodology for the statistical design of complex integrated
circuits.
In 1993 International Symposium on VLSI Technology, Systems, and
Applications, pages 112-116, Taipei, Taiwan, May 12-14 1993.
- [1232]
- S. G. Duvall.
Statistical circuit modeling and optimization.
In IEEE International Workshop on Statistical Metrology, pages 56-63,
Honolulu, HI, June 11 2000.
- [1233]
- C. Duvvury.
ESD: Design for IC chip quality and reliability.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 251-259, San Jose, CA, March 20-22 2000.
- [1234]
- C. Dwyer.
Computer-aided design for DNA self-assembly: process and applications.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 662-667, San Jose, CA, November 6-10 2005.
- [1235]
- E. Dyer,
M. Majzoobi, and F. Koushanfar.
Hybrid modeling of non-stationary process variations.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
194-199, San Diego, CA, June 5-9 2011.
- [1236]
- L. G. e Silva,
L. M. Silveira, and J. R. Phillips.
Efficient computation of the worst-delay corner.
Design, Automation and Test in Europe (DATE-07), pages 1617-1622,
April 16-20 2007.
- [1237]
- L. G. e Silva,
J. Phillips, and L. M. Silveira.
Effective corner-based techniques for variation-aware IC timing verification.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(1):157-162, January 2010.
- [1238]
- L. G. e Silva,
J. R. Phillips, and L. M. Silveira.
Speedpath analysis under parametric timing models.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
268-273, Anaheim, CA, June 13-18 2010.
- [1239]
- R. Ebendt,
W. Gunther, and R. Drechsler.
An improved branch and bound algorithm for exact BDD minimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(12):1657-1663, December 2003.
- [1240]
- M. Ebrahimi,
F. Oboril, S. Kiamehr, and M. B. Tahoori.
Aging-aware logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 61-68, San Jose, CA, November 18-21 2013.
- [1241]
- D. Eckerbert and P. Larsson-Edefors.
Cycle-true leakage current modeling for CMOS gates.
In IEEE International Symposium on Circuits and Systems (ISCAS), pages
V.507-V.510, 2001.
- [1242]
- A. Edman and
C. Svensson.
Timing closure through a globally synchronous, timing partitioned design
methodology.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 71-74,
San Diego, CA, June 7-11 2004.
- [1243]
- N. Een and N. Sorensson.
Translating pseudo-boolean constraints into SAT.
Journal on Satisfiability, Boolean Modeling and Computation, 2:1-25,
February 2006.
- [1244]
- S. Eggersglub, R. Wille, and R. Drechsler.
Improved SAT-based ATPG: more constraints, better compaction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 85-90, San Jose, CA, November 18-21 2013.
- [1245]
- T. J. Eguia,
S.-X.-D. Tan, R. Shen, D. Li, E. H. Pacheco, M. Tirumala, and L. Wang.
General parameterized thermal modeling for high-performance microprocessor
design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):211-224, February 2012.
- [1246]
- E. B. Eichelberger.
Hazard detection in combinational and sequential switching circuits.
IBM Journal, pages 90-99, March 1965.
- [1247]
- M. Eiermann and
W. Stechele.
Novel modeling techniques for RTL power estimation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 323-328, Monterey, California, August 12-14 2002.
- [1248]
- M. Eisele,
J. Berthold, D. Schmitt-Landsiedel, and R. Mahnkopf.
The impact of intra-die device parameter variation on path delays and on the
design for yield of low voltage digital circuits.
In International Symposium on Low Power Electronics and Design, pages
237-242, Monterey, CA, August 12-14 1996.
- [1249]
- M. Eisele,
J. Berthold, D. Schmitt-Landsiedel, and R. Mahnkopf.
The impact of intra-die device parameter variations on path delays and on the
design for yield of low voltage digital circuits.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
5(4):360-368, December 1997.
- [1250]
- W. T. Eisenmann
and H. E. Graeb.
Fast transient power and noise estimation for VLSI circiuts.
In IEEE/ACM International Conference on Computer-Aided Design, pages
252-257, San Jose, CA, November 6-10 1994.
- [1251]
- D. A. El-Dib and M. I.
Elmasry.
Modified register-exchange viterbi decoder for low-power wireless
communications.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(2):371-378, February 2004.
- [1252]
- W. El-Essawy, D. H. Albonesi, and B. Sinharoy.
A microarchitectural-level step-power analysis tool.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 263-266, Monterey, California, August 12-14 2002.
- [1253]
- A. M.
El-Husseini and M. Morrise.
Clocking design automation in intel's core i7 and future designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 276-278, San Jose, CA, November 7-10 2011.
- [1254]
- T. El-Moselhy, I. M. Elfadel, and D. Widiger.
Efficient algorithm for the computation of on-chip capacitance sensitivities
with respect to a large set of parameters.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
906-911, Anaheim, CA, June 8-13 2008.
- [1255]
- T. A.
El-Moselhy, I. M. Elfadel, and L. Daniel.
A capacitance solver for incremental variation-aware extraction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 662-669, San Jose, CA, November 10-13 2008.
- [1256]
- T. El-Moselhy
and L. Daniel.
Stochastic integral equation solver for efficient variation-aware interconnect
extraction.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
415-420, Anaheim, CA, June 8-13 2008.
- [1257]
- T. El-Moselhy
and L. Daniel.
Stochastic dominant singular vectors method for variation-aware extraction.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
667-672, Anaheim, CA, June 13-18 2010.
- [1258]
- M. A. El-Moursy
and E. G. Friedman.
Power characteristics of inductive interconnect.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1295-1306, December 2004.
- [1259]
- M. A. El-Moursy
and E. G. Friedman.
Shielding effect of on-chip interconnect inductance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):396-400, March 2005.
- [1260]
- K. M.
El-Shennawy, G. P. Fiani, and M. B. Tayel.
Closed-form solutions for voltage pulse response of open, shorted, and loaded
distributed RC thin film structures.
IEEE Transactions on Circuits and Systems, 38(12):1567-1571, December
1991.
- [1261]
- Y. M. El-Ziq and S. Y. H.
Su.
Fault diagnosis of MOS combinational networks.
IEEE Transactions on Computers, C-31(2):129-139, February 1982.
- [1262]
- Y. M. El-Ziq.
Failure analysis and test generation for VLSI physical defects.
In IEEE Custom Integrated Circuits Conference, pages 300-303,
Rochester, NY, May 1983.
- [1263]
- R. D. Eldred.
Test routines based on symbolic logical statements.
Journal of the Association for Computing Machinery, 6(1):33-36,
January 1959.
- [1264]
- I. M. Elfadel and
D. D. Ling.
A block rational arnoldi algorithm for multipoint passive model-order reduction
of multiport RLC networks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
66-71, San Jose, CA, November 9-13 1997.
- [1265]
- I. M. Elfadel and
D. D. Ling.
Zeros and passivity of arnoldi-reduced-order models for interconnect networks.
In 34th Design Automation Conference, pages 28-33, Anaheim, CA, June
9-13 1997.
- [1266]
- M. Elgebaly and
M. Sachdev.
Efficient adaptive voltage scaling system through on-chip critical path
emulation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 375-380, Newport Beach, CA, August 9-11 2004.
- [1267]
- P. J. H. Elias and
N. P. van der Meijs.
Extracting circuit models for large RC interconnetions that are accurate up
to a predefined signal frequency.
In 33rd Design Automation Conference, pages 764-769, Las Vegas, NV,
June 3-7 1996.
- [1268]
- W. C. Elmore.
The transient response of damped linear networks with particular regard to
wideband amplifiers.
Journal of Applied Physics, 19(1):55-63, January 1948.
- [1269]
- Y. M. Elziq.
Automatic test generation for stuck-open faults in CMOS VLSI.
In IEEE 18th Design Automation Conference, pages 347-354, Nashville,
TN, June 1981.
- [1270]
- Y. M. Elziq.
Functional-level test generation for stuck-open faults in CMOS VLSI.
In IEEE International Test Conference, pages 536-546, Philadelphia,
PA, Oct. 27-29 1981.
- [1271]
- S. H. K. Embabi and
R. Damodaran.
Delay models for CMOS, bicmos and binmos circuits and their applications for
timing simulations.
IEEE Transactions on Computer-Aided Design, 13(9):1132-1142,
September 1994.
- [1272]
- T. Enami,
S. Ninomiya, and M. Hashimoto.
Statistical timing analysis considering spatially and temporally correlated
dynamic power supply noise.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(4):541-553, April 2009.
- [1273]
- Y. Eo, S. Shin, W. R.
Eisenstadt, and J. Shim.
A decoupling technique for efficient timing analysis of VLSI interconnects
with dynamic circuit switching.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1321-1337, September 2004.
- [1274]
- S. Ercolani,
M. Favalli, M. Damiani, P. Olivo, and B. Ricco.
Estimate of signal probability in combinational logic networks.
In IEEE European Test Conference, pages 132-138, 1989.
- [1275]
- S. Ercolani,
M. Favalli, M. Damiani, P. Olivo, and B. Ricco.
Testability measures in pseudorandom testing.
IEEE Transactions on Computer-Aided Design, 11(6):794-800, June
1992.
- [1276]
- M. Ercsey-Ravasz and Z. Toroczkai.
Optimization hardness as transient chaos in an analog approach to constraint
satisfaction.
Nature Physics, 7(12):966-970, December 2011.
- [1277]
- R. Erwe and N. Tanabe.
Efficient simulation of MOS circuits.
IEEE Transactions on Computer-Aided Design, 10(4):541-544, April
1991.
- [1278]
- B. Eschermann.
State assignment for hardwired VLSI control units.
ACM Computing Surveys, 25(4):415-436, December 1993.
- [1279]
- R. Escovar,
S. Ortiz, and R. Suaya.
An improved long distance treatment for mutual inductance.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(5):783-793, May 2005.
- [1280]
- R. Escovar and
R. Suaya.
Transmission line design of clock trees.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 334-340, San Jose, CA, November 10-14 2002.
- [1281]
- R. Escovar and
R. Suaya.
Optimal design of clock trees for multigigahertz applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(3):329-345, March 2004.
- [1282]
- K. S. Eshbaugh.
Generation of correlated parameters for statistical circuit simulation.
IEEE Transactions on Computer-Aided Design, 11(10):1198-1206, October
1992.
- [1283]
- S. E. Esmaeili
and A. J. Al-Khalili.
Integrated power and clock distribution network.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1941-1945, October 2013.
- [1284]
- E. Estrada and
N. Hatano.
Communicability angle and the spatial efficiency of networks.
SIAM Review, 58(4):692-715, December 2016.
- [1285]
- J. Evans, P. Lall,
and R. Bauernschub.
A framework fo reliability modeling of electronics.
In Annual Reliability and Maintainability Symposium, pages 144-151,
Washington, DC, January 16-19 1995.
- [1286]
- N. E. Evmorfopoulos, G. I. Stamoulis, and J. N. Avaritsiotis.
A monte carlo approach for maximum power estimation based on extreme value
theory.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(4):415-432, April 2002.
- [1287]
- N. E. Evmorfopoulos, D. P. Karampatzakis, and G. I. Stamoulis.
Voltage-drop-constrained optimization of power distribution network based on
reliable maximum current estimates.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 479-484, San Jose, CA, November 7-11 2004.
- [1288]
- N. Evmorfopoulos, D. Karampatzakis, and G. Stamoulis.
Precise identification of the worst-case voltage drop conditions in power grid
verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 112-118, San Jose, CA, November 5-9 2006.
- [1289]
- N. Evmorfopoulos, M.-A. Rammou, G. Stamoulis, and J. Moondanos.
Characterization of the worst-case current waveform excitations in general
RLC-model power grid analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 824-830, San Jose, CA, November 7-11 2010.
- [1290]
- A. Exposito,
B. Soler, and J. A. Rosendo Macias.
Application of generalized phasors to eigenvector and natural response
computation of LTI circuits.
IEEE Transactions on Circuits and Systems, 53(7):1533-1543, July
2006.
- [1291]
- S. A. Fahmy and A. R.
Moham.
Architecture for real-time nonparametric probability density function
estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(5):910-920, May 2013.
- [1292]
- B. J.
Falkowski, I. Schafer, and M. A. Perkowski.
Effective computer methods for the calculation of rademacher-walsh spectrum for
completely and incompletely specified boolean functions.
IEEE Transactions on Computer-Aided Design, 11(10):1207-1226, October
1992.
- [1293]
- F. Fallah,
S. Liao, and S. Devadas.
Solving covering problems using LPR-based lower bounds.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(1):9-17, February 2000.
- [1294]
- J. Fan, N. Mi, and
X.-D. Sheldon.
Statistical model order reduction for interconnect circuits considering spatial
correlations.
Design, Automation and Test in Europe (DATE-07), pages 1508-1513,
April 16-20 2007.
- [1295]
- S.-C. Fang, J.-M.
Wang, and W.-S. Feng.
A new direct design for three-input XOR function on the transistor level.
IEEE Transactions on Circuits and Systems, Part I, 43(4):343-348,
April 1996.
- [1296]
- P. Fang, J. Tao,
J. F. Chen, and C. Hu.
Design-in hot-carrier reliability for high performance logic applications.
In IEEE Custom Integrated Circuits Conference, pages 525-531, Santa
Clara, CA, May 11-14 1998.
- [1297]
- C. F. Fang, R. A.
Rutenbar, and T. Chen.
Fast, accurate static analysis for fixed-point finite-precision effects in
DSP designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 275-282, San Jose, CA, November 9-13 2003.
- [1298]
- C. F. Fang, R. A.
Rutenbar, M. Puschel, and T. Chen.
Toward efficient static analysis of finite-precision effects in DSP
applications via affine arithmetic modeling.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
496-501, Anaheim, CA, June 2-6 2003.
- [1299]
- H. Fang,
K. Chakrabarty, Z. Wang, and X. Gu.
Diagnosis of board-level functional failures under uncertainty using
dempster-shafer theory.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(10):1586-1599, October 2012.
- [1300]
- J. Fang, S. Gupta,
S. V. Kumar, S. K. Marella, V. Mishra, P. Zhou, and S. S. Sapatnekar.
Circuit reliability: from physics to architectures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 243-246, San Jose, CA, November 5-8 2012.
- [1301]
- E.-J.-W. Fang,
T.-C.-J. Shih, and D.-S.-Y. Huang.
IR to routing challenge and solution for interposer-based design.
In 20th Asia and South Pacific Design Automation Conference, pages
226-230, Chiba/Tokyo, Japan, January 19-22 2015.
- [1302]
- C. Fang, Q. Huang,
F. Yang, X. Zeng, D. Zhou, and X. Li.
Efficient performance modeling of analog integrated circuits via kernel density
based sparse regression.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [1303]
- Y.-C. Fang, H.-Y.
Lin, M.-Y. Su, C.-M. Li, and E.-J.-W. Fang.
Machine-learning-based dynamic IR drop prediction for ECO.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [1304]
- J.-W. Fang and Y.-W. Chang.
Area-I/O flip-chip routing for chip-package co-design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 518-522, San Jose, CA, November 10-13 2008.
- [1305]
- J. Fang and S. S.
Sapatnekar.
Scalable methods for analyzing the circuit failure probability due to gate
oxide breakdown.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(11):1960-1973, November 2012.
- [1306]
- I. Fang and S. S.
Sapatnekar.
Incorporating hot-carrier injection effects into timing analysis for large
circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(12):2738-2751, December 2014.
- [1307]
- G.-P. Fang.
A new time-stepping method for circuit simulation.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1308]
- M. A. Farhan,
M. S. Nakhla, E. Gad, and R. Achar.
Parallel high-order envelope-following method for fast transient analysis of
highly oscillatory circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(1):261-270, January 2017.
- [1309]
- N. R. Farnum and
P. Booth.
Uniqueness of maximum likelihood estimators of the 2-parameter weibull
distribution.
IEEE Transactions on Reliability, 46(4):523-525, December 1997.
- [1310]
- A. H. Farrahi,
D. J. Hathaway, M. Wang, and M. Sarrafzadeh.
Quality of EDA CAD tools: definitions, metrics, and directions.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 395-405, San Jose, CA, March 20-22 2000.
- [1311]
- A. H. Farrahi,
C. Chen, A. Srivastava, G. Tellez, and M. Sarrafzadeh.
Activity-driven clock design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(6):705-714, June 2001.
- [1312]
- K. Farzan and D. A.
Johns.
Coding schemes for chip-to-chip interconnect applications.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(4):393-406, April 2006.
- [1313]
- H. Fatemi,
S. Nazarian, and M. Pedram.
Statistical logic cell delay analysis using a current-based model.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
253-256, San Francisco, CA, July 24-28 2006.
- [1314]
- M. Favalli and
L. Benini.
Analysis of glitch power dissipation in CMOS ics.
In ACM/IEEE International Symposium on Low Power Design, pages
123-128, Dana Point, CA, April 23-26 1995.
- [1315]
- M. Fawaz,
S. Chatterjee, and F. N. Najm.
A vectorless framework for power grid electromigration checking.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 553-560, San Jose, CA, November 18-21 2013.
- [1316]
- M. Fawaz and F. N. Najm.
Accurate verification of RC power grids.
IEEE Design Automation and Test in Europe (DATE), pages 814-817,
March 14-18 2016.
- [1317]
- M. Fawaz and F. N. Najm.
Fast simulation-based verification of RC power grids.
In IEEE Canadian Conference on Electrical and Computer Engineering
(CCECE), pages 1182-1187, Vancouver, BC, May 15-18 2016.
- [1318]
- M. Fawaz and F. N. Najm.
Fast vectorless RLC grid verification.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(3):489-502, March 2017.
- [1319]
- M. Fawaz and F. N. Najm.
Parallel simulation-based verification of RC power grids.
In IEEE Computer Society Annual Symposium on VLSI (ISVLSI-17), pages
445-452, Bochum, Germany, July 3-5 2017.
- [1320]
- M. Fawaz and F. N. Najm.
Power grid verification under transient constraints.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 593-600, Irvine, CA, November 13-16 2017.
- [1321]
- M. Fayyazi and
L. Kirsch.
Efficient simulation of oscillatory combinational loops.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
777-780, Anaheim, CA, June 13-18 2010.
- [1322]
- Y. Fei, S. Ravi,
A. Raghunathan, and N. K. Jha.
A hybrid energy-estimation technique for extensible processors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):652-664, May 2004.
- [1323]
- W. Fei, H. Yu,
W. Zhang, and K.-S. Yeo.
Design exploration of hybrid CMOS and memristor circuit by new modified nodal
analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(6):1012-1025, June 2012.
- [1324]
- A. Feinberg and
A. Widom.
Connecting parametric aging to catastrophic failure through thermodynamics.
IEEE Transactions on Reliability, 45(1):28-33, March 1996.
- [1325]
- P. Feldmann, S. Abbaspour, D. Sinha, G. Schaeffer, R. Banerji,
and H. Gupta.
Driver waveform computation for timing analysis with multiple voltage threshold
driver models.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 74-79, Monterey, CA,
February 25-26 2008.
- [1326]
- P. Feldmann, S. Abbaspour, D. Sinha, G. Schaeffer, R. Banerji,
and H. Gupta.
Driver waveform computation for timing analysis with multiple voltage threshold
driver models.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
425-428, Anaheim, CA, June 8-13 2008.
- [1327]
- P. Feldmann and
S. Abbaspour.
Towards a more physical approach to gate modeling for timing, noise, and power.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
453-455, Anaheim, CA, June 8-13 2008.
- [1328]
- P. Feldmann and
R. W. Freund.
Efficient linear circuit analysis by pade approximation via the lanczos
process.
IEEE Transactions on Computer-Aided Design, 14(5):639-649, May
1995.
- [1329]
- P. Feldmann and
R. W. Freund.
Reduced-order modeling of large linear subcircuits via a block lanczos
algorithm.
In 32nd Design Automation Conference, pages 474-479, San Francisco,
CA, June 12-16 1995.
- [1330]
- P. Feldmann and
F. Liu.
Sparse and efficient reduced order modeling of linear subcircuits with large
number of terminals.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 88-92, San Jose, CA, November 7-11 2004.
- [1331]
- P. Feldmann and
R. A. Rohrer.
Proof of the number of independent kirchhoff equations in an electrical
circuit.
IEEE Transactions on Circuits and Systems, 38(7):681-684, July
1991.
- [1332]
- Z. Feng, P. Li, and
Y. Zhan.
Fast second-order statistical static timing analysis using parameter dimension
reduction.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
244-249, San Diego, CA, June 4-8 2007.
- [1333]
- Z. Feng, P. Li, and
Y. Zhan.
An on-the-fly parameter dimension reduction approach to fast second-order
statistical static timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(1):141-153, January 2009.
- [1334]
- C. Feng, H. Zhou,
C. Yan, J. Tao, and X. Zeng.
Efficient approximation algorithms for chemical mechanical polishing dummy
fill.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(3):402-415, March 2011.
- [1335]
- Z. Feng, Z. Zeng,
and P. Li.
Parallel on-chip power distribution network analysis on multi-core-GPU
platforms.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(10):1823-1836, October 2011.
- [1336]
- Z. Feng, X. Zhao,
and Z. Zeng.
Robust parallel preconditioned power grid simulation on GPU with adaptive
runtime performance modeling and optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(4):562-573, April 2011.
- [1337]
- Z. Feng and P. Li.
Performance-oriented statistical parameter reduction of parameterized systems
via reduced rank regression.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 868-875, San Jose, CA, November 5-9 2006.
- [1338]
- Z. Feng and P. Li.
A methodology for timing model characterization for statistical static timing
analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 725-729, San Jose, CA, November 5-8 2007.
- [1339]
- Z. Feng and P. Li.
Parameterized waveform-independent gate models for timing and noise analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 61-66, Austin, Texas,
February 26-27 2007.
- [1340]
- Z. Feng and P. Li.
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 647-654, San Jose, CA, November 10-13 2008.
- [1341]
- Z. Feng and P. Li.
Performance-oriented parameter dimension reduction of VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(1):137-150, January 2009.
- [1342]
- X. Feng and S. Li.
Design of an area-efficient million-bit integer multiplier using double modulus
NTT.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(9):2658-2662, September 2017.
- [1343]
- Z. Feng and Z. Zeng.
Parallel multigrid preconditioning on graphics processing units (gpus) for
robust power grid analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
661-666, Anaheim, CA, June 13-18 2010.
- [1344]
- Z. Feng.
Scalable multilevel vectorless power grid voltage integrity verification.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(8):1388-1397, August 2013.
- [1345]
- Z. Feng.
Scalable vectorless power grid current integrity verification.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1346]
- Z. Feng.
Fast RC reduction of flip-chip power grids using geometric templates.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(11):2357-2365, November 2014.
- [1347]
- Z. Feng.
Spectral graph sparsification in nearly-linear time leveraging efficient
spectral perturbation analysis.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [1348]
- F. J. Ferguson and
J. P. Shen.
Multiple-fault test sets for MOS complex gates.
In IEEE International Conference on Computer-Aided Design, pages
36-38, Santa Clara, CA, Nov. 18-21 1985.
- [1349]
- V. Ferragina, N. Ghittori, G. Torelli, G. Boselli, G. Trucco,
and V. Liberali.
A time-domain current model for fully CMOS logic gates.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 29-32, Montreal, Quebec, June 20-23 2004.
- [1350]
- A. Ferre and
J. Figueras.
Leakage power bounds in CMOS digital technologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(6):731-738, June 2002.
- [1351]
- R. Ferreira,
A-M Trullemans, J. Costa, and J. Monteiro.
Probabilistic bottom-up RTL power estimation.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 439-446, San Jose, CA, March 20-22 2000.
- [1352]
- I. A. Ferzli,
F. N. Najm, and L. Kruse.
Early power grid verification under circuit current uncertainties.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 116-121, Portland, Oregon, August 27-29 2007.
- [1353]
- I. A. Ferzli,
F. N. Najm, and L. Kruse.
A geometric approach for early power grid verification using current
constraints.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 40-47, San Jose, CA, November 5-8 2007.
- [1354]
- I. A. Ferzli,
E. Chiprout, and F. N. Najm.
Verification and co-design of the package and die power delivery system using
wavelets.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 7-10, San Jose, CA, October 27-29 2008.
- [1355]
- I. A. Ferzli,
E. Chiprout, and F. N. Najm.
Verification and codesign of the package and die power delivery system using
wavelets.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(1):92-102, January 2010.
- [1356]
- I. A. Ferzli and F. N.
Najm.
Statistical estimation of leakage-induced power grid voltage drop considering
within-die process variations.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
856-859, Anaheim, CA, June 2-6 2003.
- [1357]
- I. A. Ferzli and F. N.
Najm.
Statistical verification of power grids considering process-induced leakage
current variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 770-777, San Jose, CA, November 9-13 2003.
- [1358]
- I. Ferzli and F. N. Najm.
Statistical estimation of circuit timing vulnerability due to leakage-induced
power grid voltage drop.
In International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 17-24, Austin, TX, May 17-20 2004.
- [1359]
- I. A. Ferzli and F. N.
Najm.
Analysis and verification of power grids considering process-induced
leakage-current variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):126-143, January 2006.
- [1360]
- G. Fey, A. Sulflow,
and R. Drechsler.
Computing bounds for fault tolerance using formal techniques.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
190-195, San Francisco, CA, July 26-31 2009.
- [1361]
- G. Fey and R. Drechsler.
Minimizing the number of paths in bdds: theory and algorithm.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):4-11, January 2006.
- [1362]
- M. Fiedler.
Algebraic connectivity of graphs.
Czechoslovak Mathematical Journal, 23(98):298-305, 1973.
- [1363]
- M. Fiedler.
A property of eigenvectors of nonnegative symmetric matrices and its
application to graph theory.
Czechoslovak Mathematical Journal, 25(100):619-633, 1975.
- [1364]
- H. Filiol,
I. O'Connor, and D. Morche.
Analog IC variability bound estimation using the cornish-fisher expansion.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(9):1457-1461, September 2012.
- [1365]
- F. Filippetti
and M. Artioli.
Ime: 4-term formula method for the symbolic analysis of linear circuits.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(3):526-538, March 2004.
- [1366]
- S. Fine, S. Ur, and
A. Ziv.
Probabilistic regression suites for functional verification.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 49-54,
San Diego, CA, June 7-11 2004.
- [1367]
- M. S. Finkelstein.
On the exponential formula for reliability.
IEEE Transactions on Reliability, 53(2):265-268, July 2004.
- [1368]
- J. Finn, P. Nuzzo,
and A. Sangiovanni-Vincentelli.
A mixed discrete-continuous optimization scheme for cyber-physical system
architecture exploration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 216-223, Austin, TX, November 2-6 2015.
- [1369]
- F. Firouzi,
S. Kiamehr, and M. B. Tahoori.
Power-aware minimum NBTI vector selection using a linear programming
approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):100-110, January 2013.
- [1370]
- A. H. Fischer,
A. Abel, M. Lepper, A. E. Zitzelsberger, and A. von Glasgow.
Experimental data and statistical models for bimodal EM failures.
In Annual International Reliability Physics Symposium, pages 359-363,
San Jose, CA, April 10-13 2000.
- [1371]
- M. Fischer and H. K.
Dirks.
Multigranular parallel algorithms for solving linear equations in VLSI
circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):728-736, May 2004.
- [1372]
- J. P. Fishburn and
C. A. Schevon.
Shaping a distributed-RC line to minimize elmore delay.
IEEE Transactions on Circuits and Systems I, 42(12):1020-1022,
December 1995.
- [1373]
- C. Fisher,
R. Blankenship, J. Jensen, T. Rossman, and K. Svilich.
Optimization of standard cell libraries for low power, high speed, or minimal
area designs.
In IEEE 1996 Custom Integrated Circuits Conference, pages 493-496,
San Diego, CA, May 5-8 1996.
- [1374]
- M. P. Flynn and J.-J. Kang.
Global signaling over lossy transmission lines.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 985-992, San Jose, CA, November 6-10 2005.
- [1375]
- M. Foltin,
B. Foutz, and S. Tyler.
Efficient stimulus-independent timing abstraction model based on a new concept
of circuit block transparency.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
158-163, New Orleans, LA, June 10-14 2002.
- [1376]
- N. Fong, N. Wong,
Q. Wang, H. Liu, and Y. Zhang.
Fast nonlinear model order reduction via associated transforms of high-order
volterra transfer functions.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
289-294, San Francisco, CA, June 3-7 2012.
- [1377]
- R. A. Fonseca,
L. Dilillo, A. Bosio1, P. Girard, S. Pravossoudovitch, A. Virazel, and
N. Badereddine.
A statistical simulation method for reliability analysis of SRAM core-cells.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
853-856, Anaheim, CA, June 13-18 2010.
- [1378]
- E. A. Foreman,
P. A. Habitz, M.-C. Cheng, and C. Tamon.
Inclusion of chemical-mechanical polishing variation in statistical static
timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(11):1758-1762, November 2011.
- [1379]
- E. A. Foreman,
P. A. Habitz, M.-C. Cheng, and C. Visweswariah.
A novel method for reducing metal variation with statistical static timing
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(8):1293-1297, August 2012.
- [1380]
- W. Fornaciari, P. Gubian, D. Suito, and C. Silvano.
Power estimation of embedded systems: A hardware/software codesign approach.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(2):266-275, June 1998.
- [1381]
- G. E. Forsythe and
R. A. Leibler.
Matrix inversion by a monte carlo method.
Mathematical Tables and Other Aids to Computation, (4):127-129,
1950.
- [1382]
- H. D. Foster.
Why the design productivity gap never happened.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 581-584, San Jose, CA, November 18-21 2013.
- [1383]
- C. Fourie.
Single flux quantum circuit technology and CAD overview.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [1384]
- R. Fraer,
G. Kamhi, and M. K. Mhameed.
A new paradigm for synthesis and propagation of clock gating conditions.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
658-663, Anaheim, CA, June 8-13 2008.
- [1385]
- D. J. Frank,
R. Puri, and D. Roma.
Design and CAD challenges in 45nm CMOS and beyond.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 329-333, San Jose, CA, November 5-9 2006.
- [1386]
- A. T. Freitas and
A. L. Oliveira.
Circuit partitioning techniques for power estimation using the full set of
input correlations.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 903-907, St. Julian, Malta, September 2-5 2001.
- [1387]
- R. S. French,
M. S. Lam, J. R. Levitt, and K. Olukotun.
A general method for compiling event-driven simulations.
In 32nd Design Automation Conference, pages 151-156, San Francisco,
CA, June 12-16 1995.
- [1388]
- J. Frenkil.
Issues and directions in low power design tools: an industrial perspective.
In 1997 International Symposium on Low Power Electronics and Design,
pages 152-157, Monterey, CA, August 18-20 1997.
- [1389]
- J. Frenkil.
Tools and methodologies for low power design.
In 34th Design Automation Conference, pages 76-81, Anaheim, CA, June
9-13 1997.
- [1390]
- R. W. Freund and
P. Feldmann.
Efficient small-signal circuit analysis and sensitivity computations with the
PVL algorithm.
In IEEE/ACM International Conference on Computer-Aided Design, pages
404-411, San Jose, CA, November 6-10 1994.
- [1391]
- R. W. Freund and
P. Feldmann.
Reduced-order modeling of large passive linear circuits by means of the sypvl
algorithm.
In IEEE/ACM International Conference on Computer-Aided Design, pages
280-287, San Jose, CA, November 10-14 1996.
- [1392]
- R. W. Freund.
Passive reduced-order models for interconnect simulation and their computation
via krylov-subspace algorithms.
In Design Automation Conference, pages 195-200, New Orleans, LA, June
21-25 1999.
- [1393]
- R. W. Freund.
SPRIM: structure-preserving reduced-order interconnect macromodeling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 80-87, San Jose, CA, November 7-11 2004.
- [1394]
- R. Fried.
Termination circuits for reducing reflections and crosstalk.
IEEE Transactions on Circuits and Systems I, 42(12):1017-1020,
December 1995.
- [1395]
- J. S.
Friedman, L. E. Calvet, P. Bessiere, J. Droulez, and D. Querlioz.
Bayesian inference with muller C-elements.
IEEE Transactions on Circuits and Systems, 63(6):895-904, June
2016.
- [1396]
- S. J. Friedman and
K. J. Supowit.
Finding the optimal variable ordering for binary decision diagrams.
IEEE Transactions on Computers, 39(5):710-713, May 1990.
- [1397]
- D. F. Frost, K. F.
Poole, and D. A. Haeussler.
RELIANT: a reliability analysis tool for VLSI interconnects.
In IEEE 1988 Custom Integrated Circuits Conference, pages
27.8.1-27.8.4, Rochester, NY, May 16-19 1988.
- [1398]
- D. F. Frost and K. F.
Poole.
A method for predicting VLSI-device reliability using series models for
failure mechanisms.
IEEE Transactions on Reliability, R-36(2):234-242, June 1987.
- [1399]
- F. Frustaci,
M. Alioto, and P. Corsonello.
Tapered-vth approach for energy-efficient CMOS buffers.
IEEE Transactions on Circuits and Systems, 58(11):2698-2707, November
2011.
- [1400]
- Y. Fu, R. Panda,
B. Reschke, S. Sundareswaran, and M. Zhao.
A novel technique for incremental analysis of on-chip power distribution
networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 817-823, San Jose, CA, November 5-8 2007.
- [1401]
- M. Fujita,
H. Fujisawa, and N. Kawato.
Evaluation and improvements of boolean comparison method based on binary
decision diagrams.
In IEEE International Conference on Computer-Aided Design, pages 2-5,
Santa Clara, CA, Nov. 7-10 1988.
- [1402]
- M. Fujita,
Y. Matsunaga, and T. Kakuda.
Automatic and semi-automatic verification of switch-level circuits with
temporal logic and binary decision diagrams.
In IEEE International Conference on Computer-Aided Design (ICCAD),
pages 38-41, Santa Clara, CA, Nov. 11-15 1990.
- [1403]
- H. Fujiwara,
K. Nii, J. Miyakoshi, Y. Murachi, Y. Morita, H. Kawaguchi, and M. Yoshimoto.
A two-port SRAM for real-time video processor saving 53% of bitline power
with majority logic and data-bit reordering.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 61-66, Tegernsee, Germany, October 4-6 2006.
- [1404]
- H. Fujiwara and
T. Shimono.
On the acceleration of test generation algorithms.
IEEE Transactions on Computers, C-32(12):1137-1144, December 1983.
- [1405]
- Hideo Fujiwara.
Logic Testing and Design for Testability.
The MIT Press, Cambridge, MA, 1985.
- [1406]
- H. Fuketa,
M. Hashimoto, Y. Mitsuyama, and T. Onoye.
Transistor variability modeling and its validation with ring-oscillation
frequencies for body-biased subthreshold circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(7):1118-1129, July 2010.
- [1407]
- H. Fuketa,
M. Hashimoto, Y. Mitsuyama, and T. Onoye.
Adaptive performance compensation with in-situ timing error predictive sensors
for subthreshold circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):333-343, February 2012.
- [1408]
- H. Fuketa, S.-I.
O'uchi, and T. Matsukawa.
A closed-form expression for minimum operating voltage of CMOS D flip-flop.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(7):2007-2016, July 2017.
- [1409]
- E. Gad, M. Nakhla,
R. Achar, and Y. Zhou.
A-stable and L-stable high-order integration methods for solving stiff
differential equations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(9):1359-1372, September 2009.
- [1410]
- M. Gaggero,
M. Parodi, and M. Storace.
Multiresolution PWL approximations.
In European Conference on Circuit Theory and Design (ECCTD), pages
III.393-III.396, Cork, Ireland, August 29 - September 2 2005.
- [1411]
- S. Gai, A. Lioy, and
P. L. Montessoro.
An accurate timing model for gate-level simulation of MOS circuits.
In IEEE International Symposium on Circuits and Systems, pages
2403-2406, June 1991.
- [1412]
- L. Gal.
On-chip cross talk - the new signal integrity challenge.
In IEEE Custom Integrated Circuits Conference, pages 251-254, Santa
Clara, CA, May 1-4 1995.
- [1413]
- K. Gala, V. Zolotov,
R. Panda, B. Young, J. Want, and D. Blaauw.
On-chip inductance modeling and analysis.
In Design Automation Conference, pages 63-68, Los Angeles, CA, June
5-9 2000.
- [1414]
- K. Gala, D. Blaauw,
J. Wang, V. Zolotov, and M. Zhao.
Inductance 101: Analysis and design issues.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
329-334, Las Vegas, NV, June 18-22 2001.
- [1415]
- K. Gala, D. Blaauw,
V. Zolotov, P. M. Vaidya, and A. Joshi.
Inductance model and analysis methodology for high-speed on-chip interconnect.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):730-745, December 2002.
- [1416]
- J. Galambos.
The Asymptotic Theory of Extreme Order Statistics.
Krieger, Melbourne, FL, 1987.
- [1417]
- M. Galceran-Oms, J. Cortadella, and M. Kishinevsky.
Speculation in elastic systems.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
292-295, San Francisco, CA, July 26-31 2009.
- [1418]
- J. Galiay,
Y. Crouzet, and M. Vergniault.
Physical versus logical fault models in MOS LSI circuits, impact on their
testability.
In IEEE International Symposium on Fault Tolerant Computing, pages
195-202, Madison, WI, June 20-22 1979.
- [1419]
- M. Gall, P. S. Ho,
C. Capasso, D. Jawarani, R. Hernandez, and H. Kawasaki.
Electromigration early failure distribution in submicron interconnects.
In Stress Induced Phenomena in Metallization Workshop, pages 3-14,
Stuttgart, 1999.
- [1420]
- C. L. Gan, C. V.
Thompson, K. L. Pey, and W. K. Choi.
Experimental characterization and modeling of the reliability of three-terminal
dual-damascene cu interconnect trees.
Journal of Applied Physics, 94(2):1222-1228, July 15 2003.
- [1421]
- H. Gan, Q. He, and
D. Jiao.
Hierarchical and adaptive finite-element reduction-recovery method for
large-scale power and signal integrity analysis of high-speed IC and
packaging structures.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 127-130, San Jose, CA, October 27-29 2008.
- [1422]
- M. J. Gander,
M. Al-Khaleel, and A. E. Ruehli.
Optimized waveform relaxation methods for longitudinal partitioning of
transmission lines.
IEEE Transactions on Circuits and Systems, 56(8):1732-1743, August
2009.
- [1423]
- M. J. Gander and A. E.
Ruehli.
Optimized waveform relaxation methods for RC type circuits.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(4):755-768, April 2004.
- [1424]
- R. Gandikota, K. Chopra, D. Blaauw, D. Sylvester, and M. Becer.
Top-k aggressors set in delay noise analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 124-129, Austin,
Texas, February 26-27 2007.
- [1425]
- R. Gandikota, K. Chopra, D. Blaauw, D. Sylvester, and M. Becer.
Top-k aggressors sets in delay noise analysis.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
174-179, San Diego, CA, June 4-8 2007.
- [1426]
- R. Gandikota, K. Chopra, D. Blaauw, D. Sylvester, M. Becer, and
J. Geada.
Victim alignment in crosstalk aware timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 698-704, San Jose, CA, November 5-8 2007.
- [1427]
- R. Gandikota, D. Blaauw, and D. Sylvester.
Modeling corsstalk in statistical static timing analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 86-91, Monterey, CA,
February 25-26 2008.
- [1428]
- R. Gandikota, D. Blaauw, and D. Sylvester.
Modeling crosstalk in statistical static timing analysis.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
974-979, Anaheim, CA, June 8-13 2008.
- [1429]
- R. Gandikota, L. Ding, P. Tehrani, and D. Blaauw.
Worst-case aggressor-victim alignment with current-source driver models.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 13-18,
San Francisco, CA, July 26-31 2009.
- [1430]
- R. Gandikota, K. Chopra, D. Blaauw, and D. Sylvester.
Victim alignment in crosstalk-aware timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(2):261-274, February 2010.
- [1431]
- F. R. Gantmacher.
The Theory of Matrices (Vol. 1).
Chelsea Publishing Company, New York, NY, 1860.
- [1432]
- F. R. Gantmacher.
The Theory of Matrices (Vol. 2).
Chelsea Publishing Company, New York, NY, 1860.
- [1433]
- F. R. Gantmacher.
Applications of the Theory of Matrices.
Interscience Publishers, Inc., New York, NY, 1959.
- [1434]
- X. F. Gao, J. J. Liou,
J. Bernier, G. Croft, and A. Ortiz-Conde.
Implementation of a comprehensive and robust MOSFET model in cadence SPICE
for ESD applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(12):1497-1502, December 2002.
- [1435]
- M. Gao, Z. Ye,
Y. Wang, and Z. Yu.
Efficient tail estimation for massive correlated log-normal sums - with
applications in statistical leakage analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
475-480, Anaheim, CA, June 13-18 2010.
- [1436]
- M. Gao, Z. Ye,
Y. Wang, and Z. Yu.
Efficient full-chip statistical leakage analysis based on fast matrix vector
product.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(3):356-369, March 2012.
- [1437]
- F. Gao and J. P. Hayes.
ILP-based optimization of sequential circuits for low power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 140-145, Seoul, Korea, August 25-27 2003.
- [1438]
- F. Gao and J. P. Hayes.
Exact and heuristic approaches to input vector control for leakage power
reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 527-532, San Jose, CA, November 7-11 2004.
- [1439]
- F. Gao and J. P. Hayes.
Total power reduction in CMOS circuits via gate sizing and multiple threshold
voltages.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 31-36,
Anaheim, CA, June 13-17 2005.
- [1440]
- F. Gao and J. P. Hayes.
Exact and heuristic approaches to input vector control for leakage power
reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2564-2571, November 2006.
- [1441]
- A. Garcia, L. D.
Kabulepa, and M. Glesner.
Efficient estimation of signal transition activity in MAC architecture.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 319-322, Monterey, California, August 12-14 2002.
- [1442]
- A. Garcia-Ortiz, L. Kabulepa, T. Murgan, and M. Glesner.
Moment-based power estimation in very deep submicron technologies.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 107-112, San Jose, CA, November 9-13 2003.
- [1443]
- D. S. Gardner,
J. D. Meindl, and K. Saraswat.
Interconnection and electromigration scaling theory.
Submitted to T. Electron Devices, March-87, March 1987.
- [1444]
- M. R. Garey and D. S.
Johnson.
Approximation algorithms for combinatorial problems : an annotated
bibliography.
In J. F. Traub, editor, Algorithms and Complexity, pages 41-52.
Academic Press, Inc., New York, NY, 1976.
- [1445]
- Michael R. Garey and
David S. Johnson.
Computers and Intractability, A Guide to the Theory of
NP-Completeness.
W. H. Freeman and Company, San Fransicso, CA, 1979.
- [1446]
- R. Garg, C. Nagpal,
and S. Khatri.
A fast analytical estimator for the SEU-induced pulse width in combinational
designs.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 128-133, Monterey, CA,
February 25-26 2008.
- [1447]
- S. Garg,
D. Marculescu, and S. X. Herbert.
Process variation aware performance modeling and dynamic power management for
multi-core systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 89-92, San Jose, CA, November 7-11 2010.
- [1448]
- S. Garg and
D. Marculescu.
Mitigating the impact of process variation on the performance of 3-D
integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1903-1914, October 2013.
- [1449]
- V. Garg.
Common path pessimism removal: an industry perspective.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 592-595, San Jose, CA, November 2-6 2014.
- [1450]
- M. Garland.
Sparse matrix computations on manycore GPU's.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages 2-6,
Anaheim, CA, June 8-13 2008.
- [1451]
- A. Gattiker,
S. Nassif, R. Dinakar, and C. Long.
Timing yield estimation from static timing analysis.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 437-442, San Jose, CA, March 26-28 2001.
- [1452]
- A. Gattiker.
Using test data to improve IC quality and yield.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 771-777, San Jose, CA, November 10-13 2008.
- [1453]
- A. Gattiker.
System-level impact of chip-level failure mechanisms and screens.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 173-176, San Jose, CA, November 7-11 2010.
- [1454]
- C. Gebotys and R. J.
Gebotys.
An empirical comparison of algorithmic, instruction, and architectural power
prediction models for high performance embedded DSP processors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 121-123, Monterey, CA, August 10-12 1998.
- [1455]
- C. H. Gebotys.
Low energy memory and register allocation using network flow.
In 34th Design Automation Conference, pages 435-440, Anaheim, CA,
June 9-13 1997.
- [1456]
- A. Gebregiorgis, M. Ebrahimi, S. Kiamehr, F. Oboril,
S. Hamdioui, and M. B. Tahoori.
Aging mitigation in memory arrays using self-controlled bit-flipping technique.
In 20th Asia and South Pacific Design Automation Conference, pages
231-236, Chiba/Tokyo, Japan, January 19-22 2015.
- [1457]
- P. P. Gelsinger.
Microprocessors for the new millennium: challenges, opportunities, and new
frontiers.
In IEEE International Solid-State Circuits Conference (ISSCC), pages
22-25, 2001.
- [1458]
- H. Geng, J. Wu,
J. Liu, M. Choi, and Y. Shi.
Utilizing random noise in cryptography: where is the tofu?
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 163-167, San Jose, CA, November 5-8 2012.
- [1459]
- Y. Geng, H. Zou,
C. Li, J. Sun, H. Wang, and P. Wang.
Short pulse generation with on-chip pulse-forming lines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(9):1553-1564, September 2012.
- [1460]
- G. Georgakos, U. Schlichtmann, R. Schneider, and S. Chakraborty.
Reliability challenges for electric vehicles: from devices to architecture and
systems software.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1461]
- B. J. George,
G. Yeap, M. G. Wloka, S. C. Tyler, and D. Gossain.
Power analysis and characterization for semi-custom design.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
215-218, Napa, CA, April 24-27 1994.
- [1462]
- B. J. George,
G. Yeap, M. G. Wloka, S. C. Tyler, and D. Gossain.
Power analysis for semi-custom design.
In IEEE 1994 Custom Integrated Circuit Conference, pages 249-252, San
Diego, CA, May 1-4 1994.
- [1463]
- V. George,
H. Zhang, and J. Rabaey.
The design of a low energy FPGA.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 188-193, San Diego, CA, August 16-17 1999.
- [1464]
- A. George and J. W-H. Liu.
Computer solution of large sparse positive definite systems.
Prentice-Hall, Inc., Englewood Cliffs, NJ 07632, 1981.
- [1465]
- D. George.
How to make computers that work like the brain.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
420-423, San Francisco, CA, July 26-31 2009.
- [1466]
- J. Gergov and
C. Meinel.
Efficient boolean manipulation with OBDD's can be extended to FBDD's.
IEEE Transactionson Computers, 43(10):1197-1209, October 1994.
- [1467]
- A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura,
D. Araki, and Y. Nishihara.
Specify-explore-refine (SER): from specification to implementation.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
586-591, Anaheim, CA, June 8-13 2008.
- [1468]
- G. Ghai and J. Mi.
Mean residual life and its association with failure rate.
IEEE Transactions on Reliability, 48(3):262-266, September 1999.
- [1469]
- R. S. Ghaida,
K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta.
A framework for double patterning-enabled design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 14-20, San Jose, CA, November 7-10 2011.
- [1470]
- N. H. Abdul Ghani and F. N.
Najm.
Handling inductance in early power grid verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 127-134, San Jose, CA, November 5-9 2006.
- [1471]
- N. H. Abdul Ghani and F. N.
Najm.
Fast vectorless power grid verification using an approximate inverse technique.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
184-189, San Francisco, CA, July 26-31 2009.
- [1472]
- N. Abdul Ghani and F. N.
Najm.
Power grid verification using node and branch dominance.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
682-687, San Diego, CA, June 5-9 2011.
- [1473]
- N. H. Abdul Ghani and
F. N. Najm.
Fast vectorless power grid verification under an RLC model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(5):691-703, May 2011.
- [1474]
- N. H. Abdul Ghani and
F. N. Najm.
Fast vectorless power grid verification under an RLC model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(5):691-703, May 2011.
- [1475]
- P. Ghanta,
S. Vrudhula, S. Bhardwaj, and R. Panda.
Stochastic variational analysis of large power grids considering intra-die
correlations.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
211-216, San Francisco, CA, July 24-28 2006.
- [1476]
- R. Gharpurey and
R. G. Meyer.
Modeling and analysis of substrate coupling in integrated circuits.
In IEEE Custom Integrated Circuits Conference, pages 125-128, Santa
Clara, CA, May 1-4 1995.
- [1477]
- M. Ghasemazar
and M. Pedram.
Minimizing the energy cost of throughput in a linear pipeline by opportunistic
time borrowing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 155-160, San Jose, CA, November 10-13 2008.
- [1478]
- M. S. Ghausi and J. J.
Kelly.
Introduction to distributed-parameter networks.
R. E. Krieger Pub. Co., 1968.
- [1479]
- S. Ghiasi,
E. Bozorgzadeh, S. Choudhuri, and M. Sarrafzadeh.
A unified theory of timing budget management.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 653-659, San Jose, CA, November 7-11 2004.
- [1480]
- S. Ghiasi,
E. Bozorgzadeh, P.-K. Huang, R. Jafari, and M. Sarrafzadeh.
A unified theory of timing budget management.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2364-2375, November 2006.
- [1481]
- M. A. Ghodrat,
K. Lahiri, and A. Raghunathan.
Accelerating system-on-chip power analysis using hybrid power estimation.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
883-886, San Diego, CA, June 4-8 2007.
- [1482]
- M. Ghoeima and Y. I.
Ismail.
Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 66-69, Newport Beach, CA, August 9-11 2004.
- [1483]
- M. Ghoneima, Y. I. Ismail, M. Khellah, J. Tschanz, and V. De.
Serial-link bus: a low-power on-chip bus architecture.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 541-546, San Jose, CA, November 6-10 2005.
- [1484]
- M. Ghoneima, Y. I. Ismail, M. M. Khellah, J. W. Tschanz, and
V. De.
Formal derivation of optimal active shielding for low-power on-chip buses.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):821-836, May 2006.
- [1485]
- M. Ghoneima, Y. I. Ismail, M. M. Khellah, J. W. Tschanz, and
V. De.
Reducing the effective coupling capacitance in buses using threshold voltage
adjustment techniques.
IEEE Transactions on Circuits and Systems, 53(9):1928-1933, September
2006.
- [1486]
- M. Ghoneima and
Y. I. Ismail.
Optimum positioning of interleaved repeaters in bidirectional buses.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
586-591, Anaheim, CA, June 2-6 2003.
- [1487]
- M. Ghoneima and
Y. I. Ismail.
Formal derivation of optimal active shielding for low-power on-chip buses.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 800-807, San Jose, CA, November 7-11 2004.
- [1488]
- M. Ghoneima and
Y. I. Ismail.
Utilizing the effect of relative delay on energy dissipation in low-power
on-chip buses.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1348-1359, December 2004.
- [1489]
- M. Ghoneima and
Y. I. Ismail.
Optimum positioning of interleaved repeaters in bidirectional buses.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):461-469, March 2005.
- [1490]
- A. Ghosh,
S. Devadas, K. Keutzer, and J. White.
Estimation of average switching activity in combinational and sequential
circuits.
In 29th ACM/IEEE Design Automation Conference, pages 253-259,
Anaheim, CA, June 8-12 1992.
- [1491]
- S. Ghosh,
S. Bhunia, and K. Roy.
A new paradigm for low-power, variation-tolerant circuit synthesis using
critical path isolation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 619-624, San Jose, CA, November 5-9 2006.
- [1492]
- S. Ghosh,
S. Mukhopadhyay, K. Kim, and K. Roy.
Self-calibration technique for reduction of hold failures in low-power
nano-scaled SRAM.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
971-976, San Francisco, CA, July 24-28 2006.
- [1493]
- S. Ghosh,
S. Bhunia, and K. Roy.
CRISTA: A new paradigm for low-power, variation-tolerant, and adaptive
circuit synthesis using critical path isolation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(11):1947-1956, November 2007.
- [1494]
- A. Ghosh, S. Boyd,
and A. Saberi.
Minimizing effective resistance of a graph.
SIAM Review, 50(1):37-66, 2008.
- [1495]
- G. Gielen,
E. Maricau, and P. De Wit.
Design automation towards reliable analog integrated circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 248-251, San Jose, CA, November 7-11 2010.
- [1496]
- J. Gil, M. Je, J. Lee,
and H. Shin.
A high speed and low power SOI inverter using active body-bias.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 59-63, Monterey, CA, August 10-12 1998.
- [1497]
- J. L.
Gilkinson, S. D. Lewis, B. B. Winter, and A. Hekmatpour.
Automated technology mapping.
IBM Journal of Research and Development, 28(5):546-556, September
1984.
- [1498]
- B. S. Gill,
C. Papashristou, and F. G. Wolff.
A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA.
Design, Automation and Test in Europe (DATE-07), pages 1460-1465,
April 16-20 2007.
- [1499]
- Arthur Gill.
Linear Sequential Circuits, Analysis, Synthesis, and Applications.
McGraw-Hill Book Company, New York, NY, 1966.
- [1500]
- B. P.
Ginsburg and A. P. Chandrakasan.
The mixed signal optimum energy point: voltage and parallelism.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
244-249, Anaheim, CA, June 8-13 2008.
- [1501]
- P. Girard,
C. Landrault, S. Pravossoudovitch, and D. Severac.
A gate resising technique for high reduction in power consumption.
In 1997 International Symposium on Low Power Electronics and Design,
pages 281-286, Monterey, CA, August 18-20 1997.
- [1502]
- T. D.
Givargis, J. Henkel, and F. Vahid.
Interface and cache power exploration for core-based embedded system design.
In IEEE/ACM International Conference on Computer-Aided Design, pages
270-273, San Jose, CA, November 7-11 1999.
- [1503]
- T. Givargis, F. Vahid, and J. Henkel.
Instruction-based system-level power evaluation of system-on-a-chip peripheral
cores.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):856-863, December 2002.
- [1504]
- T. Givargis and
F. Vahid.
Platune: A tuning framework for system-on-a-chip platforms.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(11):1317-1327, November 2002.
- [1505]
- E. Gizdarski
and H. Fujiwara.
SPIRIT: A highly robust combinational test generation algorithm.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(12):1446-1458, December 2002.
- [1506]
- M. Glass,
M. Lukasiewycz, C. Haubelt, and J. Teich.
Towards scalable system-level reliability analysis?
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
234-239, Anaheim, CA, June 13-18 2010.
- [1507]
- A. L. Glebov,
D. Blaauw, and L. G. Jones.
Transistor reordering for low power CMOS gates using an SP-BDD
representation.
In ACM/IEEE International Symposium on Low Power Design, pages
161-166, Dana Point, CA, April 23-26 1995.
- [1508]
- A. Glebov,
S. Gavrilov, D. Blaauw, S. Sirichotiyakul, C. Oh, and V. Zolotov.
False-noise analysis using logic implications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 515-521, San Jose, CA, November 4-8 2001.
- [1509]
- A. Glebov,
S. Gavrilov, D. Blaauw, V. Zolotov, R. Panda, and C. Oh.
False-noise analysis using resolution method.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 437-442, San Jose, CA, March 18-21 2002.
- [1510]
- A. Glebov,
S. Gavrilov, R. Soloviev, V. Zolotov, M. R. Becer, C. Oh, and R. Panda.
Delay noise pessimism reduction by logic correlations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 160-167, San Jose, CA, November 7-11 2004.
- [1511]
- C. T. Glover and M. R.
Mercer.
A method of delay fault test generation.
In 25th ACM/IEEE Design Automation Conference, pages 90-95, Anaheim,
CA, June 12-15 1988.
- [1512]
- S. Goel, M. A.
Elgamel, M. A. Bayoumi, and Y. Hanafy.
Design methodologies for high-performance noise-tolerant XOR-XNOR circuits.
IEEE Transactions on Circuits and Systems, 53(4):867-878, April
2006.
- [1513]
- M. Goel and N. R.
Shanbhag.
Low-power adaptive filter architectures via strength reduction.
In International Symposium on Low Power Electronics and Design, pages
217-220, Monterey, CA, August 12-14 1996.
- [1514]
- M. Goel and N. R.
Shanbhag.
Dynamic algorithm transformations (DAT) for low-power adaptive signal
processing.
In 1997 International Symposium on Low Power Electronics and Design,
pages 161-166, Monterey, CA, August 18-20 1997.
- [1515]
- M. Goel and N. R.
Shanbhag.
Dynamic algorithm transformations (DAT) - A systematic approach to
low-power reconfigurable signal processing.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(4):463-476, December 1999.
- [1516]
- A. Goel and S. Vrudhula.
Statistical waveform and current source based standard cell models for accurate
timing analysis.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
227-230, Anaheim, CA, June 8-13 2008.
- [1517]
- P. Goel.
An implicit enumeration algorithm to generate tests for combinational logic
circuits.
IEEE Transactions on Computers, C-30(3):215-222, March 1981.
- [1518]
- S. K. Goel.
Test challenges in designing complex 3d chips: what in on the horizon for EDA
industry?
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 273, San Jose, CA, November 5-8 2012.
- [1519]
- I. C. Goknar,
H. Kutuk, and S.-M. Kang.
MOMCO: Method of moment components for passive model order reduction of
RLCG interconnects.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(4):459-474, April 2001.
- [1520]
- E. I.
Goldberg, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
Theory and algorithms for face hypercube embedding.
IEEE Transactions on Computer-Aided Design, 17(6):472-488, June
1998.
- [1521]
- E. I.
Goldberg, L. P. Carloni, T. Villa, R. K. Brayton, and A. L.
Sangiovanni-Vincentelli.
Negative thinking in branch-and-bound: the case of unate covering.
IEEE Transactions on Computer-Aided Design, 19(3):281-294, March
2000.
- [1522]
- A. V. Goldberg and
R. E. Tarjan.
A new approach to the maximum flow problem.
In ACM Symposium on the Theory of Computing, pages 136-146, May
1986.
- [1523]
- L. Goldstein.
Controllability/observability analysis of digital circuits.
IEEE Transactions on Circuits and Systems, CAS-26(9):685-693,
September 1979.
- [1524]
- S. C. Goldstein.
The impact of the nanoscale on computing systems.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 655-661, San Jose, CA, November 6-10 2005.
- [1525]
- G. H. Golub and C. F. Van
Loan.
Matrix Computations.
The Johns Hopkins University Press, Baltimore, MD, 3rd edition, 1996.
- [1526]
- M. C. Golumbic and
A. Mintz.
Factoring logic functions using graph partitioning.
In IEEE/ACM International Conference on Computer-Aided Design, pages
195-198, San Jose, CA, November 7-11 1999.
- [1527]
- A. F. Gomez.
Early selection of critical paths for reliable NBTI aging-delay monitoring.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(7):2438-2448, July 2016.
- [1528]
- M. Gong, H. Zhou,
J. Tao, and X. Zeng.
Binning optimization based on SSTA for transparently-latched circuits  .
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 328-335, San Jose, CA, November 2-5 2009.
- [1529]
- F. Gong, H. Yu,
Y. Shi, D. Kim, J. Ren, and L. He.
Quickyield: an efficient global-search based parametric yield estimation with
performance constraints.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
392-397, Anaheim, CA, June 13-18 2010.
- [1530]
- M. Gong, H. Zhou,
L. Li, J. Tao, and X. Zeng.
Binning optimization for transparently-latched circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(2):270-283, February 2011.
- [1531]
- F. Gong, H. Yu,
L. Wang, and L. He.
A parallel and incremental extraction of variational capacitance with
stochastic geometric moments.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(9):1729-1737, September 2012.
- [1532]
- F. Gong,
S. Basir-Kazeruni, L. He, and H. Yu.
Stochastic behavioral modeling and analysis for analog/mixed-signal circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):24-33, January 2013.
- [1533]
- N. Gong, J. Wang,
and R. Sridhar.
Variation aware sleep vector selection in dual vt dynamic or circuits for low
leakage register file design.
IEEE Transactions on Circuits and Systems, 61(7):1970-1983, July
2014.
- [1534]
- W.-B. Gong and H. Yang.
Rational approximants for some performance analysis problems.
IEEE Transactions on Computers, 44(12):1394-1404, December 1995.
- [1535]
- R. Gonzalez and
M. Horowitz.
Energy dissipation in general purpose microprocessors.
IEEE Journal of Solid-State Circuits, 31(9):1277-1284, September
1996.
- [1536]
- J. Goodenough
and R. Aitken.
Post-silicon is too late avoiding the 50 million paperweight starts with
validated designs.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages 8-11,
Anaheim, CA, June 13-18 2010.
- [1537]
- N. Gopal, D. P.
Neikirk, and L. T. Pillage.
Evaluating RC-interconnect using moment-matching approximations.
In IEEE International Conference on Computer-Aided Design, pages
74-77, Santa Clara, CA, November 11-14 1991.
- [1538]
- N. Gopal, C. L.
Ratzlaff, and L. T. Pillage.
Constrained approximation of dominant time constant(s) in RC circuit delay
models.
13th IMACS World Congress on Computation and Applied Mathematics,
pages ?--?, July 22-26 1991.
- [1539]
- P. Gopalakrishnan, A. Odabasioglu, L. Pileggi, and S. Raje.
An analysis of the wire-load model uncertainty problem.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(1):23-31, January 2002.
- [1540]
- B. Goplen and
S. Sapatnekar.
Efficient thermal placement of standard cells in 3d ics using a force directed
approach.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 86-89, San Jose, CA, November 9-13 2003.
- [1541]
- C. Gordon,
T. Blazeck, and R. Mittra.
Time-domain simulation of multiconductor transmission lines with
frequency-dependent losses.
IEEE Transactions on Computer-Aided Design, 11(11):1372-1387,
November 1992.
- [1542]
- W. Gosti,
A. Narayan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
Wireplanning in logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
26-33, San Jose, CA, November 8-12 1998.
- [1543]
- E. Goto, K. Murata,
K. Nakazawa, K. Nakagawa, T. Moto-Oka, Y. Matsuoka, Y. Ishibashi, H. Ishida,
T. Soma, and E. Wada.
Esaki diode high-speed logical circuits.
IRE Transactions on Electronic Computers, pages 25-29, March 1960.
- [1544]
- E. Gourdin,
P. Hansen, and B. Jaumard.
Finding maximum likelihood estimators for the three-parameter weibull
distribution.
Journal of Global Optimization, 5:373-397, 1994.
- [1545]
- N. C. Gov, M. K.
Mihcak, and S. Eurgun.
True random number generation via sampling from flat band-limited gaussian
process.
IEEE Transactions on Circuits and Systems, 58(5):1044-1051, May
2011.
- [1546]
- M. K. Gowan, L. L.
Biro, and D. B. Jackson.
Power considerations in the design of the alpha 21264 microprocessor.
In IEEE/ACM 35th Design Automation Conference, pages 726-731, San
Francisco, CA, June 15-19 1998.
- [1547]
- A. Goyal and F. N. Najm.
Efficient RC power grid verification using node elimination.
Design, Automation and Test in Europe (DATE-11), pages 257-260, March
14-18 2011.
- [1548]
- H. E. Graeb, C. U.
Wieser, and K. J. Antreich.
Improved methods for worst-case analysis and optimization incorporating
operating tolerances.
In 30th ACM/IEEE Design Automation Conference, pages 142-147, Dallas,
TX, June 14-18 1993.
- [1549]
- P. Gray and R. Meyer.
Analysis and Design of Analog Integrated Circuits.
John Wiley and Sons, New York, NY, 1984.
- [1550]
- J. L. Greathouse
and G. H. Loh.
Machine learning for performance and power modeling of heterogeneous systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [1551]
- C. Grecu, P. P.
Pande, A. Ivanov, and R. Saleh.
A scalable communication-centric soc interconnect architecture.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 343-350, San Jose, CA, March 22-24 2004.
- [1552]
- S. Greenberg, J. Rabinowicz, R. Tsechanski, and E. Paperno.
Selective state retention power gating based on gate-level analysis.
IEEE Transactions on Circuits and Systems, 61(4):1095-1104, April
2014.
- [1553]
- J. Gregg and T.-W. Chen.
Post silicon power/performance optimization in the presence of process
variations using individual well adaptive body biasing (IWABB).
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 453-458, San Jose, CA, March 22-24 2004.
- [1554]
- W. P. Griffin and
K. Roy.
CLIP: circuit level IC protection through direct injection of process
variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(5):791-803, May 2012.
- [1555]
- R. Griffith and
M. Nakhla.
A new high-order absolutely-stable explicit numerical integration algorithm for
the time-domain simulation of nonlinear circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
276-280, San Jose, CA, November 9-13 1997.
- [1556]
- S. Grivet-Talocia.
Passivity enforcement via perturbation of hamiltonian matrices.
IEEE Transactions on Circuits and Systems, 51(9):1755-1769, September
2004.
- [1557]
- E. Grochowski, D. Ayers, and V. Tiwari.
Microarchitectural di/dt control.
IEEE Design & Test of Computers, pages 40-47, May-June 2003.
- [1558]
- J. Grodstein, E. Lehman, H. Harkness, B. Grundmann, and
Y. Watanabe.
A delay model for logic synthesis of continuously-sized networks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
458-462, San Jose, CA, November 5-9 1995.
- [1559]
- P. D. Gross,
R. Arunachalam, K. Rajagopal, and L. T. Pileggi.
Determination of worst-case aggressor alignment for delay calculation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
212-219, San Jose, CA, November 8-12 1998.
- [1560]
- E. Grossar,
J. Croon, M. Stucchi, W. Dehaene, and K. Maex.
A yield-aware modeling methodology for nano-scaled SRAM designs.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 33-36, Austin, TX, May 9 - 11 2005.
- [1561]
- M. J. Grote and
T. Huckle.
Parallel preconditioning with sparse approximate inverses.
SIAM Journal on Scientific Computing, 18(3):838-853, May 1997.
- [1562]
- T. Grund,
P. Christie, and M. D. Butala.
Web-based tools for system-level interconnect prediction.
In Workshop on System-Level Interconnect Prediction, Monterey, CA,
April 10-11 1999.
- [1563]
- W. J.
Grundmann, D. Dobberpuhl, R. L. Allmon, and N. L. Rethman.
Designing high performance CMOS microprocessors using full custom techniques.
In 34th Design Automation Conference, pages 722-727, Anaheim, CA,
June 9-13 1997.
- [1564]
- J. Gu, J. Keane, and
C. Kim.
Modeling and analysis of leakage induced damping effect in low voltage lsis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 382-387, Tegernsee, Germany, October 4-6 2006.
- [1565]
- J. Gu, H. Eom, and
C.-H. Kim.
Sleep transistor sizing and control for resonant supply noise damping.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 80-85, Portland, Oregon, August 27-29 2007.
- [1566]
- J. Gu, S. S.
Sapatnekar, and C. Kim.
Width-dependent statistical leakage modeling for random dopant induced
threshold voltage shift.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 87-92,
San Diego, CA, June 4-8 2007.
- [1567]
- J. Gu, J. Keane,
S. Sapatnekar, and C. H. Kim.
Statistical leakage estimation of double gate finfet devices considering the
width quantization property.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(2):206-209, February 2008.
- [1568]
- J. Gu, R. Harjani, and
C. H. Kim.
Design and implementation of active decoupling capacitor circuits for power
supply regulation in digital ics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):292-301, February 2009.
- [1569]
- J. Gu, J. Keane, and
C.-H. Kim.
Modeling, analysis and application of leakage induced damping effect of power
supply integrity.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(1):128-136, January 2009.
- [1570]
- C. Gu, E. Chiprout, and
X. Li.
Efficient moment estimation with extremely small sample size via bayesian
inference for analog/mixed-signal validation.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1571]
- Y. Gu and S. Chakraborty.
Control theory-based DVS for interactive 3d games.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
740-745, Anaheim, CA, June 8-13 2008.
- [1572]
- R. X. Gu and M. I. Elmasry.
Power dissipation analysis and optimization of deep submicron CMOS digital
circuits.
IEEE Journal of Solid-State Circuits, 31(5):707-713, May 1996.
- [1573]
- J. Gu and C.-H. Kim.
Multi-story power delivery for supply noise reduction and low voltage
operation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 192-197, San Diego, CA, August 8-10 2005.
- [1574]
- C. Gu and
J. Roychowdhury.
Model reduction via projection onto nonlinear manifolds, with applications to
analog circuits and biochemical systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 85-92, San Jose, CA, November 10-13 2008.
- [1575]
- C. Gu and
J. Roychowdhury.
Generalized nonlinear timing/phase macromodeling: theory, numerical methods and
applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 284-291, San Jose, CA, November 7-11 2010.
- [1576]
- C. Gu.
QLMOR: a new projection-based approach for nonlinear model order reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 389-396, San Jose, CA, November 2-5 2009.
- [1577]
- C. Gu.
QLMOR: a projection-based nonlinear model order reduction approach using
quadratic-linear representation of nonlinear systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(9):1307-1320, September 2011.
- [1578]
- C. Gu.
Challenges in post-silicon validation of high-speed I/O links.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 547-550, San Jose, CA, November 5-8 2012.
- [1579]
- S.-U. Guan,
S. Zhang, and M. T. Quieta.
2-D CA variation with asymmetric neighborship for pseudorandom number
generation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(3):378-388, March 2004.
- [1580]
- Z. Guan and
M. Marek-Sadowska.
An efficient and accurate algorithm for computing RC current response with
applications to EM reliability evaluation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [1581]
- C. Guardiani, A. Macii, E. Macii, M. Poncino, M. Rossello,
R. Scarsi, C. Silvano, and R. Zafalon.
RTL power estimation in an industrial design flow.
In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages
91-96, Como, Italy, March 4-5 1999.
- [1582]
- C. Guardiani, S. Saxena, P. McNamara, P. Schumaker, and
D. Coder.
An assymptotically constant, linearly bounded methodology for the statistical
simulation of analog circuits including component mismatch effects.
In Design Automation Conference, pages 15-18, Los Angeles, CA, June
5-9 2000.
- [1583]
- C. Guardiani, M. Bertoletti, N. Dragone, M. Malcotti, and
P. McNamara.
An effective DFM strategy requires accurate process and IP
pre-characterization.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
760-761, Anaheim, CA, June 13-17 2005.
- [1584]
- N. Guilar,
A. Chen, T. Kleeburg, and R. Amirtharajah.
Integrated solar energy harvesting and storage.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 20-24, Tegernsee, Germany, October 4-6 2006.
- [1585]
- R. S. Guindi,
R. C. Kordasiewicz, and F. N. Najm.
Optimization technique for FB/TB assignment in PD-SOI digital CMOS
circuits.
In The First Annual Northeast Workshop on Circuits and Systems
(NEWCAS-03), pages 157-160, Montreal, Quebec, June 17-20 2003.
- [1586]
- R. S. Guindi and F. N.
Najm.
Design techniques for gate-leakage reduction in CMOS circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 61-65, San Jose, CA, March 24-26 2003.
- [1587]
- K. Gulati,
N. Jayakumar, and S. P. Khatri.
An algebraic decision diagram (ADD) based technique to find leakage
histograms of combinational designs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 111-114, San Diego, CA, August 8-10 2005.
- [1588]
- U. Guler and G. Dundar.
Modeling CMOS ring oscillator performance as a randomness source.
IEEE Transactions on Circuits and Systems, 61(3):712-724, March
2014.
- [1589]
- R. Guo, S. M. Reddy,
and I. Pomeranz.
PROPTEST: a property-based test generator for synchronous sequential
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(8):1080-1091, August 2003.
- [1590]
- W. Guo, Y. Zhong, and
T. Burd.
Context-sensitive static transistor-level IR analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 797-803, San Jose, CA, November 10-13 2008.
- [1591]
- Q. Guo, T. Chen,
Y. Chen, and F. Franchetti.
Accelerating architectural simulation via statistical techniques: a survey.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(3):433-446, March 2016.
- [1592]
- R. Gupta,
B. Krauter, B. Tutuianu, J. Willis, and L. T. Pileggi.
The elmore delay as a bound for RC trees with generalized input signals.
In 32nd Design Automation Conference, pages 364-369, San Francisco,
CA, June 12-16 1995.
- [1593]
- R. Gupta,
B. Tutuianu, and L. T. Pileggi.
The elmore delay as a bound for RC trees with generalized input signals.
IEEE Transactions on Computer-Aided Design, 16(1):95-104, January
1997.
- [1594]
- R. Gupta,
J. Willis, and L. T. Pileggi.
Analytic termination metrics for pin-to-pin lossy transmission lines with
nonlinear drivers.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(3):457-463, September 1998.
- [1595]
- P. Gupta,
L. Zhong, and N. K. Jha.
A high-level interconnect power model for design space exploration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 551-558, San Jose, CA, November 9-13 2003.
- [1596]
- P. Gupta, A. B.
Kahng, P. Sharma, and D. Sylvester.
Selective gate-length biasing for cost-effective runtime leakage control.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
327-330, San Diego, CA, June 7-11 2004.
- [1597]
- P. Gupta, A. B.
Kahng, Y. Kim, and D. Sylvester.
Self-compensating design for focus variation.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
365-368, Anaheim, CA, June 13-17 2005.
- [1598]
- P. Gupta, A. B.
Kahng, P. Sharma, and D. Sylvester.
Gate-length biasing for runtime-leakage control.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(8):1475-1485, August 2006.
- [1599]
- M. S. Gupta,
J. L. Oatley, R. Joseph, G.-Y. Wei, and D. M. Brooks.
Understanding voltage variations in chip multiprocessors using a distributed
power-delivery network.
Design, Automation and Test in Europe (DATE-07), pages 624-629, April
16-20 2007.
- [1600]
- P. Gupta, A. B.
Kahng, Y. Kim, and D. Sylvester.
Self-compensating design for reduction of timing and leakage sensitivity to
systematic pattern-dependent variation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(9):1614-1624, September 2007.
- [1601]
- P. Gupta,
Y. Agarwal, L. Dolecek, N. Dutt, R. K. Gupta, R. Kumar, S. Mitra, A. Nicolau,
T. S. Rosing, M. B. Srivastava, S. Swanson, and D. Sylvester.
Underdesigned and opportunistic computing in presence of hardware variability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):8-23, January 2013.
- [1602]
- V. Gupta,
D. Mohapatra, A. Raghunathan, and K. Roy.
Low-power digital signal processing using approximate adders.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):124-137, January 2013.
- [1603]
- V. Gupta and M. Anis.
Statistical design of the 6t SRAM bit cell.
IEEE Transactions on Circuits and Systems, 57(1):93-104, January
2010.
- [1604]
- P. Gupta and F.-L. Heng.
Toward a systematic-variation aware timing methodology.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
321-326, San Diego, CA, June 7-11 2004.
- [1605]
- P. Gupta and A. B.
Kahng.
Manufacturing-aware physical design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 681-687, San Jose, CA, November 9-13 2003.
- [1606]
- P. Gupta and A. B. Kahng.
Quantifying error in dynamic power estimation of CMOS circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 273-278, San Jose, CA, March 24-26 2003.
- [1607]
- P. Gupta and A. B. Kahng.
Bounded-lifetime integrated circuits.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
347-348, Anaheim, CA, June 8-13 2008.
- [1608]
- S. Gupta and
S. Katkoori.
Intrabus crosstalk estimation using word-level statistics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):469-478, March 2005.
- [1609]
- S. Gupta and F. N. Najm.
Power macromodeling for high level power estimation.
In 34th Design Automation Conference, pages 365-370, Anaheim, CA,
June 9-13 1997.
- [1610]
- S. Gupta and F. N. Najm.
Analytical model for high level power modeling of combinational and sequential
circuits.
In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages
164-172, Como, Italy, March 4-5 1999.
- [1611]
- S. Gupta and F. N. Najm.
Energy-per-cycle estimation at RTL.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 121-126, San Diego, CA, August 16-17 1999.
- [1612]
- S. Gupta and F. N. Najm.
Power macro-models for DSP blocks with application to high-level synthesis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 103-105, San Diego, CA, August 16-17 1999.
- [1613]
- S. Gupta and F. N. Najm.
Analytical models for RTL power estimation of combinational and sequential
circuits.
IEEE Transactions on Computer-Aided Design, 19(7):808-814, July
2000.
- [1614]
- S. Gupta and F. N. Najm.
Power modeling for high-level power estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(1):18-29, February 2000.
- [1615]
- S. Gupta and F. N. Najm.
Energy and peak-current per-cycle estimation at RTL.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):525-537, August 2003.
- [1616]
- S. Gupta and S. S.
Sapatnekar.
Compact current source models for timing analysis under temperature and body
bias variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(11):2104-2117, November 2012.
- [1617]
- S. Gupta and
S. Sapatnekar.
Variation-aware variable latency design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1106-1117, May 2014.
- [1618]
- N. Gupte and J. Wang.
Secure power grid simulation on cloud.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(3):422-432, March 2015.
- [1619]
- N. Gupte and J. Wang.
Transient noise bounds using vectorless power grid verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 713-720, Austin, TX, November 2-6 2015.
- [1620]
- M. R. Guthaus,
N. Venkateswaran, C. Visweswariah, and V. Zolotov.
Gate sizing using incremental parameterized statistical timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 1029-1036, San Jose, CA, November 6-10 2005.
- [1621]
- M. R. Guthaus,
J. E. Stine, S. Ataei, B. Chen, B. Wu, and M. Sarwar.
Openram: an open-source memory compiler.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [1622]
- M. R. Guthaus and
B. Taskin.
High-performance, low-power resonant clocking.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 742-745, San Jose, CA, November 5-8 2012.
- [1623]
- W. E. Guthrie,
M. Pedram, W. Dai, R. Chadha, J. Cong, C. X. Huang, A. Devgan, T. Mozdzen,
and A. Yang.
Panel: Noise and signal integrity in deep submicron design.
In 34th Design Automation Conference, pages 720-721, Anaheim, CA,
June 9-13 1997.
- [1624]
- H. Gutierrez-Pulido, V. Aguirre-Torres, and J. A. Christen.
A practical method for obtaining prior distributions in reliability.
IEEE Transactions on Reliability, 54(2):262-269, June 2005.
- [1625]
- K. h. Chang,
I. L. Markov, and V. Bertacco.
Automating post-silicon debugging and repair.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 91-98, San Jose, CA, November 5-8 2007.
- [1626]
- M. Ha, K. Srinivasan,
and M. Swaminathan.
Chip-package co-simulation with multiscale structures.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 339-342, San Jose, CA, October 27-29 2008.
- [1627]
- H. Habal,
K. Mayaram, and T. S. Fiez.
Accurate and efficient simulation of synchronous digital switching noise in
systems on a chip.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):330-338, March 2005.
- [1628]
- H. Habal and H. Graeb.
Constraint-based layout-driven sizing of analog circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(8):1089-1102, August 2011.
- [1629]
- G. D.
Hachtel, M. Hermida, A. Pardo, M. Poncino, and F. Somenzi.
Re-encoding sequential circuits to reduce power dissipation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
70-73, San Jose, CA, November 6-10 1994.
- [1630]
- G. D.
Hachtel, E. Macii, A. Pardo, and F. Somenzi.
Probabilistic analysis of large finite state machines.
In 31st ACM/IEEE Design Automation Conference, pages 270-275, San
Diego, CA, June 6-10 1994.
- [1631]
- G. D.
Hachtel, E. Macii, A. Pardo, and F. Somenzi.
Symbolic algorithms to calculate steady-state probabilities of a finite state
machine.
In European Design Automation Conference, pages 214-218, Paris,
France, February 1994.
- [1632]
- G. D.
Hachtel, M. H. De La Rica, A. Pardo, M. Poncino, and F. Somenzi.
Re-encoding sequential circuits to reduce power dissipation.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
69-74, Napa, CA, April 24-27 1994.
- [1633]
- G. D. Hachtel,
E. Macii, A. Pardo, and F. Somenzi.
Markovian analysis of large finite state machines.
IEEE Transactions on Computer-Aided Design, 15(12):1479-1493,
December 1996.
- [1634]
- G. D. Hachtel and
R. A. Rohrer.
Techniques for the optimal design and synthesis of switching circuits.
In Proceedings of the IEEE, pages 1864-1877, November 1967.
- [1635]
- P. Al Haddad and F. N.
Najm.
Power grid correction using sensitivity analysis under an RC model.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
688-693, San Diego, CA, June 5-9 2011.
- [1636]
- G. Hadjiyiannis and S. Devadas.
Techniques for accurate performance evaluation in architecture exploration.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):601-615, August 2003.
- [1637]
- W. Haensch.
Why should we do 3d integration?
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
674-675, Anaheim, CA, June 8-13 2008.
- [1638]
- M. Hafed,
M. Oulmane, and N. C. Rumin.
Delay and current estimation in a CMOS inverter with an RC load.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(1):80-89, January 2001.
- [1639]
- F. B. Hagedorn and
P. M. Hall.
Right-angle bends in thin strip conductors.
Journal of Applied Physics, 34(1):128-133, January 1963.
- [1640]
- L. Hagen and A. Kahng.
Fast spectral methods for ratio cut partitioning and clustering.
In IEEE International Conference on Computer-Aided Design, pages
10-13, Santa Clara, CA, November 11-14 1991.
- [1641]
- K. Haghdad and M. Anis.
Design-specific optimization considering supply and threshold voltage
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1891-1901, October 2008.
- [1642]
- K. Haghdad and M. Anis.
Power yield analysis under process and temperature variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(10):1794-1803, October 2012.
- [1643]
- A. Hagiescu,
W.-F. Wong, D. F. Bacon, and R. Rabbah.
A computing origami: folding streams in fpgas.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
282-287, San Francisco, CA, July 26-31 2009.
- [1644]
- A. Hajimiri.
Generalized time- and transfer-constant circuit analysis.
IEEE Transactions on Circuits and Systems, 57(6):1105-1121, June
2010.
- [1645]
- I. N. Hajj, V. B.
Rao, R. Iimura, H. Cha, and R. Burch.
A system for electromigration analysis in VLSI metal patterns.
In IEEE Custom Integrated Circuits Conference, pages 4.4.1-4.4.4,
1991.
- [1646]
- I. N. Hajj and F. N. Najm.
Test generation for physical faults in MOS VLSI circuits.
In IEEE Comp-Euro Conference, pages 386-389, Hamburg, West Germany,
May 11-15 1987.
- [1647]
- I. N. Hajj and D. G. Saab.
Fault modeling and logic simulation of MOS VLSI circuits based on logic
expression extraction.
In IEEE International Conference on Computer-Aided Design, pages
99-100, Santa Clara, CA, September 1983.
- [1648]
- I. N. Hajj and D. G. Saab.
Symbolic logic simulation of MOS circuits.
In IEEE International Symposium on Circuits and Systems, pages
246-249, Newport Beach, CA, May 1983.
- [1649]
- I. N. Hajj and D. G. Saab.
On the functional logic representation of digital transistor circuits.
In IEEE International Symposium on Circuits and Systems, pages
1281-1284, Kyoto, Japan, 1985.
- [1650]
- I. N. Hajj and D. Saab.
Switch-level logic simulation of digital bipolar circuits.
IEEE Transactions on Computer-Aided Design, CAD-6(2):251-258, March
1987.
- [1651]
- I. N. Hajj.
A path algebra for switch-level simulation.
In IEEE International Conference on Computer-Aided Design, pages
153-155, Santa Clara, CA, Nov. 18-21 1985.
- [1652]
- I. N. Hajj.
An algebra for labeled weighted graphs.
private communication, 1986.
- [1653]
- I. N. Hajj.
An algebra for switch-level simulation.
In IEEE International Conference on Computer-Aided Design (ICCAD),
pages 488-491, Santa Clara, CA, November 11-15 1990.
- [1654]
- I. N. Hajj.
Extended nodal analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(1):89-100, January 2012.
- [1655]
- I. N. Hajj.
On device modeling for circuit simulation with application to carbon-nanotube
and graphene nano-ribbon field-effect transistors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(3):495-499, March 2015.
- [1656]
- A. Hajjar,
T. Chen, I. Munn, A. Andrews, and M. Bjorkman.
Stopping criteria comparison: towards high quality behavioral verification.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 31-37, San Jose, CA, March 26-28 2001.
- [1657]
- H.Albalawi, Y. Li, and X. Li.
Computer-aided design of machine learning algorithm: training fixed-point
classifier for on-chip low-power implementation.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [1658]
- J. E. Hall, D. E.
Hocevar, P. Yang, and M. J. McGraw.
SPIDER - a CAD system for checking current density and voltage drop in
VLSI metallization patterns.
In IEEE International Conference on Computer-Aided Design, pages
278-281, Santa Clara, CA, Nov. 11-13 1986.
- [1659]
- J. E. Hall, D. E.
Hocevar, P. Yang, and M. McGraw.
SPIDER - a CAD system for modeling VLSI metallization patterns.
IEEE Transactions on Computer-Aided Design, CAD-6(6):1023-1031,
November 1987.
- [1660]
- P. Hallschmid
and R. Saleh.
Fast design space exploration using local regression modeling with application
to asips.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(3):508-515, March 2008.
- [1661]
- P. Hallschmid
and S. J. E. Wilton.
Routing architecture optimizations for high-density embedded programmable IP
cores.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1320-1324, November 2005.
- [1662]
- J. P. Halter and F. N.
Najm.
A gate-level leakage power reduction method for ultra-low-power CMOS
circuits.
In IEEE 1997 Custom Integrated Circuits Conference, pages 475-478,
Santa Clara, CA, May 5-8 1997.
- [1663]
- T. Hamada, C-K
Cheng, and P. M. Chau.
A wire length estimation technique utilizing neighborhood density equations.
In 29th ACM/IEEE Design Automation Conference, pages 57-61, Anaheim,
CA, June 8-12 1992.
- [1664]
- T. Hamada, C-K.
Cheng, and P. M. Chau.
A wire length estimation technique using neighborhood density equations.
IEEE Transactions on Computer-Aided Design, 15(8):912-922, August
1996.
- [1665]
- S. Hamdioui,
Z. Al-Ars, A. J. van de Goor, and M. Rodgers.
Linked faults in ramdom access memories: concept, fault models, test
algorithms, and industrial results.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):737-757, May 2004.
- [1666]
- S. Hamedi-Hagh.
Introducting suspendance analysis.
IEEE Transactions on Circuits and Systems I: Regular Papers,
64(2):333-346, February 2017.
- [1667]
- R. W. Hamming.
Coding and Information Theory, 2nd Ed..
Prentice-Hall, 1986.
- [1668]
- F. Hamzaoglu and
M. R. Stan.
Circuit-level techniques to control gate leakage for sub- 100nm CMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 60-63, Monterey, California, August 12-14 2002.
- [1669]
- D. Han, B.-S. Kim, and
A. Chatterjee.
DSP-driven self-tuning of RF circuits for process-induced performance
variability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):305-314, February 2010.
- [1670]
- S. Han, J. Choung,
B.-S. Kim, B.-H. Lee, H. Choi, and J. Kim.
Statistical aging analysis with process variation consideration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 412-419, San Jose, CA, November 7-10 2011.
- [1671]
- S. Han, V. Sirigiri,
D. G. Saab, and M. Tabib-Azar.
Ultra-low power NEMS FPGA.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 533-538, San Jose, CA, November 5-8 2012.
- [1672]
- L. Han, X. Zhao, and
Z. Feng.
An efficient graph sparsification approach to scalable harmonic balance (HB)
analysis of strongly nonlinear RF circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 494-499, San Jose, CA, November 18-21 2013.
- [1673]
- L. Han, X. Zhao, and
Z. Feng.
Tinyspice: a parallel SPICE simulator on GPU for massively repeated small
circuit simulations.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1674]
- S. Han, B.-S. Kim,
and J. Kim.
Variation-aware aging analysis in digital ics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(12):2214-2225, December 2013.
- [1675]
- K. Han, A. B. Kahng,
and H. Lee.
Scalable detailed placement legalization for complex sub-14nm constraints.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 867-873, Austin, TX, November 2-6 2015.
- [1676]
- S. Han and W. Dally.
Invited: bandwidth-efficient deep learning.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [1677]
- L. Han and Z. Feng.
Tinyspice plus: scaling up statistical SPICE simulations on GPU leveraging
shared-memory based sparse matrix solution techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [1678]
- N. Hanchate
and N. Ranganathan.
LECTOR: a technique for leakage reduction in CMOS circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(2):196-205, February 2004.
- [1679]
- H. Hanson, M. S.
Hrishikesh, V. Agarwal, S. W. Keckler, and D. Burger.
Static energy reduction techniques for microprocessor caches.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):303-313, June 2003.
- [1680]
- S. Hanson,
D. Sylvester, and D. Blaauw.
A new technique for jointly optimizing gate sizing and supply voltage in
ultra-low energy circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 338-341, Tegernsee, Germany, October 4-6 2006.
- [1681]
- S. Hanson,
B. Zhai, D. Blaauw, D. Sylvester, A. Bryant, and X. Wang.
Energy optimality and variability in subthreshold design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 363-365, Tegernsee, Germany, October 4-6 2006.
- [1682]
- S. Hanson,
M. Seok, D. Sylvester, and D. Blaauw.
Nanometer device scaling in subthreshold circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
700-705, San Diego, CA, June 4-8 2007.
- [1683]
- V. Hanumaiah, S. Vrudhula, and K. S. Chatha.
Performance optimal online DVFS and task migration techniques for thermally
constrained multi-core processors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(11):1677-1690, November 2011.
- [1684]
- Z. Hao, S.-X.-D. Tan,
R. Shen, and G. Shi.
Performance bound analysis of analog circuits considering process variations.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
310-315, San Diego, CA, June 5-9 2011.
- [1685]
- Z. Hao, G. Shi,
S.-X.-D. Tan, and E. Tlelo-Cuautle.
Symbolic moment computation for statistical analysis of large interconnect
networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(5):944-957, May 2013.
- [1686]
- G. Harber,
S. Bass, and X. Hu.
Maximal solution of linear systems of equations and an application in VLSI.
In IEEE International Symposium on Circuits and Systems (ISCAS), pages
2337-2340, 1990.
- [1687]
- M. G. Harbour and
J. M. Drake.
Calculation of multiterminal resistances in integrated circuits.
IEEE Transactions on Circuits and Systems, CAS-33(4):462-465, April
1986.
- [1688]
- M. G. Harbour and
J. M. Drake.
Calculation of signal delay in integrated interconnections.
IEEE Transactions on Circuits and Systems, 36(2):272-276, February
1989.
- [1689]
- B. P. Harish,
N. Bhat, and M. B. Patil.
On a generalized framework for modeling the effects of process variations on
circuit delay performance using response surface methodology.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(3):606-614, March 2007.
- [1690]
- H. Harizi,
R. Haubler, M. Olbrich, and E. Barke.
Efficient modeling techniques for dynamic voltage drop analysis.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
706-711, San Diego, CA, June 4-8 2007.
- [1691]
- C. L. Harkness
and D. P. Lopresti.
Modeling uncertainty in RC timing analysis.
In IEEE International Conference on Computer-Aided Design, pages
516-519, 1989.
- [1692]
- C. L. Harkness
and D. P. Lopresti.
Interval methods for modeling uncertainty in RC timing analysis.
IEEE Transactions on Computer-Aided Design, 11(11):1388-1401,
November 1992.
- [1693]
- J. E. Harlow, III and
F. Brglez.
Design of experiments in BDD variable ordeing: lessons learned.
In IEEE/ACM International Conference on Computer-Aided Design, pages
646-652, San Jose, CA, November 8-12 1998.
- [1694]
- D. Harris,
M. Horowitz, and D. Liu.
Timing analysis including clock skew.
IEEE Transactions on Computer-Aided Design, 18(11):1608-1618,
November 1999.
- [1695]
- D. Harris,
M. Horowitz, and D. Liu.
Timing analysis with clock skew.
In ACM/IEEE 1999 International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU-99), pages 15-20,
Monterey, CA, March 8-9 1999.
- [1696]
- D. Harris and
S. Naffziger.
Statistical clock skew modeling with data delay variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(6):888-898, December 2001.
- [1697]
- D. M. Harris.
Sequential element timing parameter definition considering clock uncertainty.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(11):2705-2708, November 2015.
- [1698]
- M. A. Hasan, A. H.
Namin, and C. Negre.
Toeplitz matrix approach for binary field multiplication using quadrinomials.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(3):449, March 2012.
- [1699]
- J. Y. Hasani.
Three-port model of a modern MOS transistor in millimeter wave bank,
considering distributed effects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(9):1509-1518, September 2016.
- [1700]
- S. Hashemi,
R. I. Bahar, and S. Reda.
DRUM: a dynamic range unbiased multiplier for approximate applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 418-425, Austin, TX, November 2-6 2015.
- [1701]
- M. Hashimoto, H. Onodera, and K. Tamaru.
A power optimization method considering glitch reduction by gate sizing.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 221-226, Monterey, CA, August 10-12 1998.
- [1702]
- M. Hashimoto, H. Onodera, and K. Tamaru.
A practical gate resizing technique considering glitch reduction for low power
design.
In Design Automation Conference, pages 446-451, New Orleans, LA, June
21-25 1999.
- [1703]
- M. Hashimoto, Y. Yamada, and H. Onodera.
Equivalent waveform propagation for static timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 169-175, San Jose, CA, November 9-13 2003.
- [1704]
- M. Hashimoto, Y. Yamada, and H. Onodera.
Equivalent waveform propagation for static timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(4):498-508, April 2004.
- [1705]
- M. Hashimoto, J. Yamaguchi, and H. Onodera.
Timing analysis considering spatial power/ground level variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 814-820, San Jose, CA, November 7-11 2004.
- [1706]
- H. Hassan,
M. Anis, and M. Elmasry.
LAP: a logic activity packing methodology for leakage power-tolerant fpgas.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 257-262, San Diego, CA, August 8-10 2005.
- [1707]
- H. Hassan,
M. Anis, and M. Elmasry.
Input vector reordering for leakage power reduction in fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(9):1555-1564, September 2008.
- [1708]
- H. A. Hassan,
M. Anis, and M. Elmasry.
Total power modeling in fpgas under spatial correlation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(4):578-587, April 2009.
- [1709]
- Z. Hassan,
N. Allec, F. Yang, L. Shang, R. P. Dick, and X. Zeng.
Full-spectrum spatial-temporal dynamic thermal analysis for nanometer-scale
integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(12):2276-2289, December 2011.
- [1710]
- S. Hassoun,
C. Cromer, and E. Calvillo-Gamez.
Static timing analysis for level-clocked circuits in the presence of crosstalk.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(9):1270-1277, September 2003.
- [1711]
- S. Hassoun.
Critical path analysis using a dynamically bounded delay model.
In Design Automation Conference, pages 260-265, Los Angeles, CA, June
5-9 2000.
- [1712]
- N. A. J. Hastings
and H. J. G. Bartlett.
Estimating the failure order-number from reliability data with suspended items.
IEEE Transactions on Reliability, 46(2):266-268, June 1997.
- [1713]
- H. Hatamkhani, F. Lambrecht, V. Stojanovic, and C.-K. K. Yang.
Power-centric design of high-speed I/os.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
867-872, San Francisco, CA, July 24-28 2006.
- [1714]
- T. Hattori,
T. Irita, M. Ito, E. Yamamoto, H. Kato, G. Sado, T. Yamada, K. Nishiyama,
H. Yagi, T. Koike, Y. Tsuchihashi, M. Higashida, H. Asano, I. Hayashibara,
K. Tatezawa, Y. Shimazaki, N. Morino, Y. Yasu, T. Hoshi, Y. Miyairi,
K. Yanagisawa, K. Hirose, S. Tamaki, S. Yoshioka, T. Ishii, Y. Kanno,
H. Mizuno, T. Yamada, N. Irie, R. Tsuchihashi, N. Arai, T. Akiyama, and
K. Ohno.
Hierarchical power distribution and power management scheme for a single chip
mobile processor.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
292-295, San Francisco, CA, July 24-28 2006.
- [1715]
- S. P. Hau-Riege
and C. V. Thompson.
Experimental characterization and modeling of the reliability of interconnect
trees.
Journal of Applied Physics, 89(1):601-609, January 1 2001.
- [1716]
- C. Haubelt,
T. Schlichte, J. Keinert, and M. Meredith.
Systemcodesigner: automatic design space exploration and rapid prototyping from
behavioral models.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
580-585, Anaheim, CA, June 8-13 2008.
- [1717]
- M. Hauschildt, M. Gall, S. Thrasher, P. Justison, R. Hernandez,
H. Kawasaki, and P. S. Ho.
Statistical analysis of electromigration lifetimes and void evolution.
Journal of Applied Physics, 101(4):043523, 2007.
- [1718]
- S. Hayashi and
M. Yamada.
EMI-noise analysis under ASIC design environment.
IEEE Transactions on Computer-Aided Design, 19(11):1337-1346,
November 2000.
- [1719]
- Seymour Hayden and
John F. Kennison.
Zermelo-Fraenkel Set Theory.
Charles E. Merrill Publishing Company, Columbus, OH, 1968.
- [1720]
- John P. Hayes.
Computer Architecture and Organization.
McGraw-Hill Book Company, 1978.
- [1721]
- J. P. Hayes.
Digital simulation with multiple logic values.
IEEE Transactions on Computer-Aided Design, CAD-5(2):274-283, April
1986.
- [1722]
- J. P. Hayes.
Pseudo-boolean logic circuits.
IEEE Transactions on Computers, C-35(7):602-612, July 1986.
- [1723]
- J. P. Hayes.
Uncertainty, energy, and multiple-valued logics.
IEEE Transactions on Computers, C-35(2):107-114, February 1986.
- [1724]
- J. P. Hayes.
An introduction to switch-level modeling.
IEEE Design & Test of Computers, 4(4):18-25, August 1987.
- [1725]
- H. Haznedar,
M. Gall, V. Zolotov, P.-S. Ku, C. Oh, and R. Panda.
Impact of stress-induced backflow on full-chip electromigration risk
assessment.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(6):1038-1046, June 2006.
- [1726]
- A. Hazra,
S. Goyal, P. Dasgupta, and A. Pal.
Formal verification of architectural power intent.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(1):78-91, January 2013.
- [1727]
- L. He, W. Liao, and
M. R. Stan.
System level leakage reduction considering the interdependence of temperature
and leakage.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 12-17,
San Diego, CA, June 7-11 2004.
- [1728]
- X. He, T. Huang,
L. Xiao, H. Tian, and E. F.-Y. Young.
Ripple: a robust and effective routability-driven placer.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1546-1556, October 2013.
- [1729]
- X. He, P. Du, S.-H.
Weng, and C.-K. Cheng.
Worst case noise prediction with nonzero current transition times for power
grid planning.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(3):607-620, March 2014.
- [1730]
- K. He, S.-X.-D. Tan,
H. Wang, and G. Shi.
GPU-accelerated parallel sparse LU factorization method for fast circuit
analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(3):1140-1150, March 2016.
- [1731]
- C. He and M. F. Jacome.
Defect-aware high-level synthesis targeted at reconfigurable nanofabrics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(5):817-833, May 2007.
- [1732]
- Z. He and L. T. Pileggi.
A simple algorithm for calculating frequency-dependent inductance bounds.
In IEEE Custom Integrated Circuits Conference, pages 199-202, Santa
Clara, CA, May 11-14 1998.
- [1733]
- R. Heald and P. Wang.
Variability in sub-100nm SRAM designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 347-352, San Jose, CA, November 7-11 2004.
- [1734]
- M. B. Healy and S.-K. Lim.
Distributed TSV topology for 3-D power-supply networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(11):2066-2079, November 2012.
- [1735]
- J. R. Heath.
A systems approach to molecular electronics.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, page 359, Seoul, Korea, August 25-27 2003.
- [1736]
- R. Hegde and
N. Shanbhag.
Energy efficiency in presence of deep submicron noise.
In IEEE/ACM International Conference on Computer-Aided Design, pages
228-234, San Jose, CA, November 8-12 1998.
- [1737]
- R. Hegde and N. R.
Shanbhag.
Energy-efficient signal processing via algorithmic noise-tolerance.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 30-35, San Diego, CA, August 16-17 1999.
- [1738]
- R. Hegde and N. R.
Shanbhag.
Soft digital signal processing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(6):813-823, December 2001.
- [1739]
- W. Heidergott.
SEU tolerant device, circuit and processor design.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 5-10,
Anaheim, CA, June 13-17 2005.
- [1740]
- H. T.
Heineken, J. Khare, W. Maly, P. K. Nag, C. Ouyang, and W. A. Pleskacz.
CAD at the design-manufacturing interface.
In 34th Design Automation Conference, pages 321-326, Anaheim, CA,
June 9-13 1997.
- [1741]
- H. T. Heineken and
W. Maly.
Interconnect yield model for manufacturability prediction in synthesis of
standard cell designs.
In IEEE/ACM International Conference on Computer-Aided Design, pages
368-373, San Jose, CA, November 10-14 1996.
- [1742]
- H. T. Heineken and
W. Maly.
Standard cell interconnect length prediction from structural circuit
attributes.
In IEEE 1996 Custom Integrated Circuits Conference, pages 167-170,
San Diego, CA, May 5-8 1996.
- [1743]
- J. A. Heinen.
Sufficient conditions for stability of interval matrices.
International Journal of Control, 39(6):1323-1328, 1984.
- [1744]
- A. E. Helal, A. M.
Bayoumi, and Y. Y. Hanafy.
Parallel circuit simulation using the direct method on a heterogeneous cloud.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [1745]
- S. Held, B. Korte,
J. Mabberg, M. Ringe, and J. Vygen.
Clock scheduling and clocktree construction for high performance asics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 232-239, San Jose, CA, November 9-13 2003.
- [1746]
- A. Heldring,
J. M. Rius, J. M. Tamayo, and J. Parron.
Compressed block-decomposition algorithm for fast capacitance extraction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):265-271, February 2008.
- [1747]
- L. Hellerman.
A measure of computational work.
IEEE Transactions on Computers, C-21(5):439-446, May 1972.
- [1748]
- D. Helms,
G. Ehmen, and W. Nebel.
Analysis and modeling of subthreshold leakage of RT-components under PTV
and state variation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 220-225, Tegernsee, Germany, October 4-6 2006.
- [1749]
- D. Helms,
R. Eilers, M. Metzdorf, and W. Nebel.
Leakage models for high-level power estimation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 37(8):1627-1639, August 2018.
- [1750]
- K. R. Heloue,
N. Azizi, and F. N. Najm.
Modeling and estimation of full-chip leakage current considering within-die
correlation.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 93-98,
San Diego, CA, June 4-8 2007.
- [1751]
- K. R. Heloue,
S. Onaissi, and F. N. Najm.
Efficient block-based parameterized timing analysis covering all potentially
critical paths.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 173-180, San Jose, CA, November 10-13 2008.
- [1752]
- K. R. Heloue,
N. Azizi, and F. N. Najm.
Full-chip model for leakage-current estimation considering within-die
correlation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(6):874-887, June 2009.
- [1753]
- K. R. Heloue,
C. V. Kashyap, and F. N. Najm.
Quantifying robustness metrics in parameterized static timing analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-09), pages 49-54, Austin, TX,
February 23-24 2009.
- [1754]
- K. R. Heloue,
C. V. Kashyap, and F. N. Najm.
Quantifying robustness metrics in parameterized static timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 209-216, San Jose, CA, November 2-5 2009.
- [1755]
- K. R. Heloue,
S. Onaissi, and F. N. Najm.
Efficient block-based parameterized timing analysis covering all potenially
critical paths.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):472-484, April 2012.
- [1756]
- K. R. Heloue,
S. Onaissi, and F. N. Najm.
Efficient block-based parameterized timing analysis covering all potentially
critical paths.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):472-484, April 2012.
- [1757]
- K. R. Heloue and F. N.
Najm.
Effect of statistical clock skew variations on chip timing yield.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 211-214, Quebec City, Quebec, June 19-22 2005.
- [1758]
- K. R. Heloue and F. N.
Najm.
Statistical timing analysis with two-sided constraints.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 829-836, San Jose, CA, November 6-10 2005.
- [1759]
- K. R. Heloue and F. N.
Najm.
Early analysis of timing margins and yield.
In 20th Canadian Conference on Electrical and Computer Engineering
(CCECE), pages 1114-1120, Vancouver, BC, April 22-26 2007.
- [1760]
- K. R. Heloue and F. N.
Najm.
Early statistical timing analysis with unknown within-die correlations.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 13-18, Austin, Texas,
February 26-27 2007.
- [1761]
- K. R. Heloue and F. N.
Najm.
Early analysis and budgeting of margins and corners using two-sided analytical
yield models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1826-1839, October 2008.
- [1762]
- K. R. Heloue and F. N.
Najm.
Parameterized timing analysis with general delay models and arbitrary variation
sources.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 14-19, Monterey, CA,
February 25-26 2008.
- [1763]
- K. R. Heloue and F. N.
Najm.
Parameterized timing analysis with general delay models and arbitrary variation
sources.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
403-408, Anaheim, CA, June 8-13 2008.
- [1764]
- J. Henkel and
H. Lekatsas.
A2bc: Adaptive address bus coding for low power deep sub-micron designs.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
744-749, Las Vegas, NV, June 18-22 2001.
- [1765]
- J. Henkel and Y. Li.
Avalanche: an environment for design space exploration and optimization of
low-power embedded systems.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(4):454-468, August 2002.
- [1766]
- J. Henkel.
A low power hardware/software partitioning approach for core-based embedded
systems.
In Design Automation Conference, pages 122-127, New Orleans, LA, June
21-25 1999.
- [1767]
- S. Henzler,
T. Nirschl, J. Berthold, G. Georgakos, and D. Schmitt-Landsiedel.
Design and technology of fine-grained sleep transistor circuits in ultra-deep
sub-micron CMOS technologies.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 223-228, Austin, TX, May 9 - 11 2005.
- [1768]
- S. Heo, K. Barr, and
K. Asanovic.
Reducing power density through activity migration.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 217-222, Seoul, Korea, August 25-27 2003.
- [1769]
- S. Heo and K. Asanovic.
Power-optimal pipelining in deep submicron technology.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 218-223, Newport Beach, CA, August 9-11 2004.
- [1770]
- S. Heo and K. Asanovic.
Replacing global wires with an on-chip network: a power analysis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 369-374, San Diego, CA, August 8-10 2005.
- [1771]
- S. Herbert and
D. Marculescu.
Analysis of dynamic voltage/frequency scaling nchip-multiprocessors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 38-43, Portland, Oregon, August 27-29 2007.
- [1772]
- S. Herbert and
D. Marculescu.
Characterizing chip-multiprocessor variability-tolerance.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
313-318, Anaheim, CA, June 8-13 2008.
- [1773]
- S. Herbert and
D. Marculescu.
Mitigating the impact of variability on chip-multiprocessor power and
performance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(10):1520-1533, October 2009.
- [1774]
- S. Hertz,
D. Sheridan, and S. Vasudevan.
Mining hardware assertions with guidance from static analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):952-965, June 2013.
- [1775]
- P. Heydari,
A. Abbaspour, and M. Pedram.
Interconnect energy dissipation in high-speed ULSI circuits.
IEEE Transactions on Circuits and Systems, 51(8):1501-1514, August
2004.
- [1776]
- P. Heydari and
R. Mohanavelu.
Design of ultrahigh-speed low-voltage CMOS CML buffers and latches.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1081-1093, October 2004.
- [1777]
- P. Heydari and
M. Pedram.
Model reduction of variable-geometry interconnects using variational
spectrally-weighted balanced truncation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 586-591, San Jose, CA, November 4-8 2001.
- [1778]
- P. Heydari and
M. Pedram.
Ground bounce in digital VLSI circuits.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(2):180-193, April 2003.
- [1779]
- P. Heydari and
M. Pedram.
Capacitive coupling noise in high-speed VLSI circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):478-488, March 2005.
- [1780]
- P. Heydari and
M. Pedram.
Model-order reduction using variational balanced truncation with spectral
shaping.
IEEE Transactions on Circuits and Systems, 53(4):879-891, April
2006.
- [1781]
- P. Heydari.
Design and analysis of low-voltage current-mode logic buffers.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 293-298, San Jose, CA, March 24-26 2003.
- [1782]
- K. Heyrman,
A. Papanikolaou, F. Gatthoor, P. Veelaert, and W. Philips.
Control for power gating of wires.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(9):1287-1300, September 2010.
- [1783]
- P. Hicks,
M. Walnock, and R. M. Owens.
Analysis of power consumption in memory hierarchies.
In 1997 International Symposium on Low Power Electronics and Design,
pages 239-242, Monterey, CA, August 18-20 1997.
- [1784]
- D. D. Hill and E. Detjens.
FPGA design principles (a tutorial).
In 29th ACM/IEEE Design Automation Conference, pages 45-46, Anaheim,
CA, June 8-12 1992.
- [1785]
- A. M. Hill and S-M. Kang.
Accuracy bounds in switching activity estimation.
In IEEE Custom Integrated Circuits Conference, pages 73-76, Santa
Clara, CA, May 1-4 1995.
- [1786]
- A. M. Hill and S-M. Kang.
Determining accuracy bounds for simulation-based switching activity estimation.
In ACM/IEEE International Symposium on Low Power Design, pages
215-220, Dana Point, CA, April 23-26 1995.
- [1787]
- A. M. Hill and S-M. Kang.
Determining accuracy bounds for simulation-based switching activity estimation.
IEEE Transactions on Computer-Aided Design, 15(6):611-618, June
1996.
- [1788]
- F. J. Hill and G. R.
Peterson.
Digital Logic and Microprocessors.
John Wiley & Sons, Inc., New York, NY, 1984.
- [1789]
- M. Hirabayashi, K. Nose, and T. Sakurai.
Design methodology and optimization strategy for dual-vth scheme using
commercially available tools.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 283-286, Huntington Beach, California, August 6-7
2001.
- [1790]
- A. Hirata,
H. Onodera, and K. Tamaru.
Proposal of a timing model for CMOS logic gates driving a CRC pi load.
In IEEE/ACM International Conference on Computer-Aided Design, pages
537-544, San Jose, CA, November 8-12 1998.
- [1791]
- H. Hirose.
Parameter estimation for the 3-parameter gamma distribution using the
continuation method.
IEEE Transactions on Reliability, 47(2):188-196, June 1998.
- [1792]
- I. A. Hiskens.
Power system modeling for inverse problems.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(3):539-551, March 2004.
- [1793]
- I. A. Hiskens.
What's smart about the smart grid?
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
937-939, Anaheim, CA, June 13-18 2010.
- [1794]
- R. B.
Hitchcock, Sr., G. L. Smith, and D. D. Cheng.
Timing analysis of computer hardware.
IBM Journal of Research and Development, 26(1):100-105, January
1982.
- [1795]
- R. B. Hitchcock, Sr.
Timing verification and the timing analysis program.
In IEEE 19th Design Automation Conference, pages 594-604, 1982.
- [1796]
- J. Hlavicka and
P. Fiser.
BOOM - a heuristic boolean minimizer.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 439-442, San Jose, CA, November 4-8 2001.
- [1797]
- P. S. Ho, F. M.
d'Heurle, and A. Gangulee.
Implications of electromigration on device reliability.
In R. E. Hummel and H. B. Huntington, editors, Electro- and
Thermo-Transport in Metals and Alloys, pages 109-139. American Society
for Metals, Niagara Falls, NY, Sept. 22 1976.
- [1798]
- R. Ho, K. Mai,
H. Kapadia, and M. Horowitz.
Interconnect scaling implications for CAD.
In IEEE/ACM International Conference on Computer-Aided Design, pages
425-429, San Jose, CA, November 7-11 1999.
- [1799]
- T.-Y. Ho, J. Zeng, and
K. Chakrabarty.
Digital microfluidic biochips: a vision for functional diversity and more than
moore.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 578-585, San Jose, CA, November 7-11 2010.
- [1800]
- M.-H. Ho, Y.-Q. Ai,
T.-C.-P. Chau, S.-C.-L. Yuen, C.-S. Choy, P.-H.-W. Leong, and K.-P. Pun.
Architecture and design flow for a highly efficient structured ASIC.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(3):424-433, March 2013.
- [1801]
- H. H. Hoang and J. M.
McDavid.
Electromigration in multilayer metallization systems.
Solid State Technology, pages 121-126, October 1987.
- [1802]
- A. Hochman,
B. N. Bond, and J. K. White.
A stabilized discrete empirical interpolation method for model reduction of
electrical, thermal, and microelectromechanical systems.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
540-545, San Diego, CA, June 5-9 2011.
- [1803]
- D. A. Hodges and H. G.
Jackson.
Analysis and Design of Digital Integrated Circuits.
McGraw-Hill, 1988.
- [1804]
- R. V. Hogg and A. T. Craig.
Introduction to Mathematical Statistics.
Prentice-Hall, Inc., Englewood Cliffs, NJ, 5th edition, 1995.
- [1805]
- F. E. Hohn and L. R.
Schissler.
Boolean matrices and the design of combinational relay switching circuits.
The Bell System Technical Journal, pages 177-202, January 1955.
- [1806]
- T. S. Hohol and L. A.
Glasser.
Relic: a reliability simulator for integrated circuits.
In IEEE International Conference on Computer-Aided Design, pages
517-520, Santa Clara, CA, Nov. 11-13 1986.
- [1807]
- D. E. Holcomb and
S. A. Seshia.
Compositional performance verification of network-on-chip designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(9):1370-1383, September 2014.
- [1808]
- I. Hong,
D. Kirovski, G. Qu, M. Potkonjak, and M. B. Srivastava.
Power optimization of variable voltage core-based systems.
In IEEE/ACM 35th Design Automation Conference, pages 176-181, San
Francisco, CA, June 15-19 1998.
- [1809]
- I. Hong,
D. Kirovski, G. Qu, M. Potkonjak, and M. B. Srivastava.
Power optimization of variable-voltage core-based systems.
IEEE Transactions on Computer-Aided Design, 18(12):1702-1714,
December 1999.
- [1810]
- S. Hong and T. Kim.
Bus optimization for low-power data path synthesis based on network flow
method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 312-317, San Jose, CA, November 5-9 2000.
- [1811]
- T. B. Hook,
J. Brown, and X. Tian.
Proximity effects and VLSI design.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 167-170, Austin, TX, May 9 - 11 2005.
- [1812]
- J. Hopcroft and
J. Ullman.
Introduction to Automata Theory, Languages and Computation.
Addison-Wesley, Reading, MA, 1979.
- [1813]
- B. Hoppe,
G. Neuendorf, D. Schmitt-Landsiedel, and W. Specks.
Optimization of high-speed CMOS logic circuits with analytical models for
signal delay, chip area, and dynamic power dissipation.
IEEE Transactions on Computer-Aided Design, 9(3):236-247, March
1990.
- [1814]
- M. Horowitz,
M. Jeeradit, F. Lau, S. Liao, B. Lim, and J. Mao.
Fortifying analog models with equivalence checking and coverage analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
425-430, Anaheim, CA, June 13-18 2010.
- [1815]
- M. Horowitz.
Timing models for MOS pass networks.
In IEEE International Symposium on Circuits and Systems, pages
198-201, 1983.
- [1816]
- R. Hossain,
L. D. Wronski, and A. Albicki.
Low power design using double edge triggered flip-flops.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2(2):261-265, June 1994.
- [1817]
- R. Hossain,
M. Zheng, and A. Albicki.
Reducing power dissipation in CMOS circuits by signal probability based
reordering.
IEEE Transactions on Computer-Aided Design, 15(3):361-368, March
1996.
- [1818]
- R. Hossain,
F. Viglione, and M. Cavalli.
Designing fast on-chip interconnects for deep submicrometer technologies.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(2):276-280, April 2003.
- [1819]
- C. Hough, T. Xue,
and E. Kuh.
New approaches for on-chip power switching noise reduction.
In IEEE Custom Integrated Circuits Conference, pages 133-136, Santa
Clara, CA, May 1-4 1995.
- [1820]
- A. S. Householder.
The Theory of Matrices in Numerical Analysis.
Dover Publications, Inc., New York, NY, 1964.
- [1821]
- M. S. Hsiao,
E. M. Rudnick, and J. H. Patel.
Effects of delay models on peak power estimation of VLSI sequential circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
45-51, San Jose, CA, November 9-13 1997.
- [1822]
- M. S. Hsiao,
E. M. Rudnick, and J. H. Patel.
K2: An estimator for peak sustainable power of VLSI circuits.
In 1997 International Symposium on Low Power Electronics and Design,
pages 178-183, Monterey, CA, August 18-20 1997.
- [1823]
- M. S. Hsiao, E. M.
Rudnick, and J. H. Patel.
Peak power estimation of VLSI circuits: new peak power measures.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(4):435-439, August 2000.
- [1824]
- K.-S. Hsiao and C.-H. Chen.
Wake-up logic optimizations through selective match and wakeup range
limitation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(10):1089-1102, October 2006.
- [1825]
- C.-T. Hsieh,
Q. Wu, C.-S. Ding, and M. Pedram.
Statistical sampling and regression analysis for RT-level power evaluation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
583-588, San Jose, CA, November 10-14 1996.
- [1826]
- C-T Hsieh,
M. Pedram, G. Mehta, and F. Rastgar.
Profile-driven program synthesis for evaluation of system power dissipation.
In 34th Design Automation Conference, pages 576-581, Anaheim, CA,
June 9-13 1997.
- [1827]
- C.-T. Hsieh, J.-C.
Lin, and S.-C. Chang.
A vectorless estimation of maximum instantaneous current for sequential
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 537-540, San Jose, CA, November 7-11 2004.
- [1828]
- C.-T. Hsieh, J.-C.
Lin, and S.-C. Chang.
Vectorless estimation of maximum instantaneous current for sequential circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2341-2352, November 2006.
- [1829]
- W.-W. Hsieh, P.-Y.
Chen, C.-Y. Wang, and T. T. Hwang.
A bus-encoding scheme for crosstalk elimination in high-performance processor
design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(12):2222-2227, December 2007.
- [1830]
- A.-C. Hsieh and T. Hwang.
TSV redundancy: architecture and design issues in 3-D ic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(4):711-722, April 2012.
- [1831]
- C.-T. Hsieh and
M. Pedram.
Microprocessor power estimation using profile-driven program synthesis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 17(11):1080-1089, November 1998.
- [1832]
- C.-T. Hsieh and
M. Pedram.
Architectural energy optimization by bus splitting.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(4):408-414, April 2002.
- [1833]
- W-J. Hsu, C-C. Shih,
and B. J. Sheu.
RELY: a reliability simulator for VLSI circuits.
In IEEE 1988 Custom Integrated Circuits Conference, pages
27.4.1-27.4.4, Rochester, NY, May 16-19 1988.
- [1834]
- C-H. Hsu, U. Kremer,
and M. Hsiao.
Compiler-directed dynamic voltage/frequency scheduling for energy reduction in
microprocessors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 275-278, Huntington Beach, California, August 6-7
2001.
- [1835]
- J. Hsu, S. Zahedi,
A. Kansal, M. Srivastava, and V. Raghunathan.
Adaptive duty cycling for energy harvesting systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 180-185, Tegernsee, Germany, October 4-6 2006.
- [1836]
- S.-H. Hsu, Y.-S.
Cheng, W.-D. Guo, H.-H. Cheng, C.-C. Wang, and R.-B. Wu.
Placement of shorting vias for power integrity in multi-layered structures.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 91-94, San Jose, CA, October 27-29 2008.
- [1837]
- C.-H. Hsu, C. Liu,
E.-H. Ma, and J. C.-M. Li.
Static timing analysis for flexible TFT circuits.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
799-802, Anaheim, CA, June 13-18 2010.
- [1838]
- H.-C. Hsu and J. Lin.
Analysis of entire power distribution system of chip, package and board for
high speed IO design.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 99-102, San Jose, CA, October 27-29 2008.
- [1839]
- W.-J. Hsu and W.-Z. Shen.
Coalgebraic division for multilevel synthesis.
In 29th ACM/IEEE Design Automation Conference, pages 438-442,
Anaheim, CA, June 8-12 1992.
- [1840]
- Y. Hu, X. Duan, and
K. Mayaram.
A comparison of time-domain and harmonic balance steady-state analyses for
coupled device and circuit simulation.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 93-96, Montreal, Quebec, June 20-23 2004.
- [1841]
- M. Hu, H. Li, and
R. E. Pino.
Fast statistical model of tio2 thin-film memristor and design implication.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 345-352, San Jose, CA, November 7-10 2011.
- [1842]
- W. Hu, J. Oberg,
A. Irturk, M. Tiwari, T. Sherwood, D. Mu, and R. Kastner.
Theoretical fundamentals of gate level information flow tracking.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(8):1128-1139, August 2011.
- [1843]
- W. Hu, J. Oberg, D. Mu,
and R. Kastner.
Simultaneous information flow security and circuit redundancy in boolean gates.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 585-590, San Jose, CA, November 5-8 2012.
- [1844]
- J. Hu, M.-C. Kim, and
I. L. Markov.
Taming the complexity of coordinated place and route.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1845]
- X. Hu, P. Du, J. F.
Buckwalter, and C.-K. Cheng.
Modeling and analysis of power distribution networks in 3-D ics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(2):354-366, February 2013.
- [1846]
- J. Hu, D. Sinha, and
I. Keller.
TAU 2014 contest on removing common path pessimism during timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 591, San Jose, CA, November 2-6 2014.
- [1847]
- M. Hu, Y. Chen, J.-J.
Yang, Y. Wang, and H.-H. Li.
A compact memristor-based dynamic synapse for spiking neural networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(8):1353-1366, August 2017.
- [1848]
- H. Hu, P. Li, and J.-Z.
Huang.
Parallelizable bayesian optimization for analog and mixed-signal rare failure
detection with high coverage.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [1849]
- F. Hu and V. A. Agrawal.
Input-specific dynamic power optimization for VLSI circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 232-237, Tegernsee, Germany, October 4-6 2006.
- [1850]
- A. J. Hu and D. L. Dill.
Reducing BDD size by exploiting functional dependencies.
In 30th ACM/IEEE Design Automation Conference, pages 266-271, Dallas,
Texas, June 14-18 1993.
- [1851]
- S. Hu and J. Hu.
Unified adaptivity optimization of clock and logic signals.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 125-130, San Jose, CA, November 5-8 2007.
- [1852]
- J. Hu and R. Marculescu.
Energy- and performance-aware mapping for regular noc architectures.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(4):551-562, April 2005.
- [1853]
- Y. Hu and K. Mayaram.
Comparison of algorithms for frequency domain coupled device and circuit
simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2571-2578, November 2006.
- [1854]
- J. Hu and S. S. Sapatnekar.
Simultaneous buffer insertion and non-hanan optimization for VLSI
interconnect under a higher order AWE model.
In 1999 International Symposium on Physical Design, pages 133-138,
Monterey, CA, April 12-14 1999.
- [1855]
- J. Hu and S. Sapatnekar.
A timing-constrained algorithm for simultaneous global routing of multiple
nets.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 99-103, San Jose, CA, November 5-9 2000.
- [1856]
- J. Hu and S. S.
Sapatnekar.
Algorithms for non-hanan-based optimization for VLSI interconnect under a
higher-order AWE model.
IEEE Transactions on Computer-Aided Design, 19(4):446-458, April
2000.
- [1857]
- H. Hu and S. S.
Sapatnekar.
Efficient inductance extraction using circuit-aware techniques.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):746-761, December 2002.
- [1858]
- J. Hu and S. S.
Sapatnekar.
A timing-constrained simultaneous global routing algorithm.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(9):1025-1036, September 2002.
- [1859]
- B. Hu and C.-J. R. Shi.
Fast-yet-accurate PVT simulation by combined direct and iterative methods.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 495-501, San Jose, CA, November 6-10 2005.
- [1860]
- B. Hu and C.-J. Richard Shi.
Simulation of closely related dynamic nonlinear systems with application to
process-voltage-temperature corner analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(5):883-892, May 2008.
- [1861]
- C. Hu.
Reliability issues of MOS and bipolar ics.
In IEEE International Conference on Computer Design, pages 438-442,
1989.
- [1862]
- C. Hu.
IC reliability prediction.
In IEEE Custom Integrated Circuits Conference, pages 4.1.1-4.1.4,
1991.
- [1863]
- C. Hu.
New sub-20nm transistors -- why and how.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
460-463, San Diego, CA, June 5-9 2011.
- [1864]
- W. Hua and R. Manohar.
Exact timing analysis for asynchronous systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 37(1):203-216, January 2018.
- [1865]
- S. Hua and G. Qu.
Approaching the maximum energy saving on embedded systems with multiple
voltages.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 26-29, San Jose, CA, November 9-13 2003.
- [1866]
- S. Hua and G. Qu.
Voltage setup problem for embedded systems with multiple voltages.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(7):869-877, July 2005.
- [1867]
- Y. Huai, Y. Zhou,
I. Tudosa, R. Malmhall, R. Ranjan, and J. Zhang.
Progress and outlook for STT-MRAM.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 235, San Jose, CA, November 7-10 2011.
- [1868]
- X. Huang,
V. Raghavan, and R. A. Rohrer.
Awesim: a program for the efficient analysis of linear(ized) circuits.
In IEEE International Conference on Computer-Aided Design (ICCAD),
pages 534-537, Santa Clara, CA, Nov. 11-15 1990.
- [1869]
- C. X. Huang,
B. Zhang, A-C. Deng, and B. Swirski.
The design and implementation of powermill.
In ACM/IEEE International Symposium on Low Power Design, pages
105-109, Dana Point, CA, April 23-26 1995.
- [1870]
- S-Y. Huang, K-C.
Chen, K-T. Cheng, and T-C. Lee.
Compact vector generation for accurate power simulation.
In 33rd Design Automation Conference, pages 161-164, Las Vegas, NV,
June 3-7 1996.
- [1871]
- S-Y. Huang, K-T.
Cheng, K-C. Chen, and M. T-C. Lee.
A novel methodology for transistor-level power estimation.
In International Symposium on Low Power Electronics and Design, pages
67-72, Monterey, CA, August 12-14 1996.
- [1872]
- C.-T. Huang, C.-F.
Wu, J.-F. Li, and C.-W. Wu.
Built-in redundancy analysis for memory yield improvement.
IEEE Transactions on Reliability, 52(4):386-399, December 2003.
- [1873]
- L.-D. Huang,
X. Tang, H. Xiang, D. F. Wong, and I.-M. Liu.
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna
problem.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):141-147, January 2004.
- [1874]
- W. Huang, M. R.
Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy.
Compact thermal modeling for temperature-aware design.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
878-883, San Diego, CA, June 7-11 2004.
- [1875]
- H. Huang, K.-G.
Shin, C. Lefurgy, and T. Keller.
Improving energy efficiency by making DRAM less randomly accessed.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 393-398, San Diego, CA, August 8-10 2005.
- [1876]
- S.-H. Huang,
Y.-T. Nieh, and F.-P. Lu.
Race-condition-aware clock skew scheduling.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
475-478, Anaheim, CA, June 13-17 2005.
- [1877]
- S.-H. Huang,
C.-M. Chang, and Y.-T. Nieh.
State re-encoding for peak current minimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 33-38, San Jose, CA, November 5-9 2006.
- [1878]
- W. Huang,
S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. R. Stan.
Hotspot: a compact thermal modeling methodology for early-stage VLSI design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(5):501-513, May 2006.
- [1879]
- C.-Y. Huang, G.-A.
Wu, and T.-H. Lin.
Qutesat: a robust circuit-based SAT solver for complex circuit structure.
Design, Automation and Test in Europe (DATE-07), pages 1313-1318,
April 16-20 2007.
- [1880]
- W. Huang, M. R.
Stan, K. Sankaranarayanan, R. J. Ribando, and K. Skadron.
Many-core design from a thermal perspective.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
746-749, Anaheim, CA, June 8-13 2008.
- [1881]
- T.-W. Huang,
P.-C. Wu, and M.-D.-F. Wong.
Fast path-based timing analysis for CPPR.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 596-599, San Jose, CA, November 2-6 2014.
- [1882]
- X. Huang, T. Yu,
V. Sukharev, and S.-X.-D. Tan.
Physics-based electromigration assessment for power grid networks.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [1883]
- Z.-C. Huang,
C.-K. Chen, and R.-S. Tsay.
AROMA: a highly accurate microcomponent-based approach for embedded processor
power analysis.
In 20th Asia and South Pacific Design Automation Conference, pages
761-766, Chiba/Tokyo, Japan, January 19-22 2015.
- [1884]
- Q. Huang,
C. Fang, F. Yang, X. Zeng, D. Zhou, and X. Li.
Efficient performance modeling via dual-prior bayesian model fusion for analog
and mixed-signal circuits.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [1885]
- T.-W. Huang,
M.-D.-F. Wong, D. Sinha, K. Kalafala, and N. Venkateswaran.
A distributed timing analysis framework for large designs.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [1886]
- X. Huang,
A. Kteyan, S.-X.-D. Tan, and V. Sukharev.
Physics-based electromigration models and full-chip assessment for power grid
networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(11):1848-1861, November 2016.
- [1887]
- X. Huang,
V. Sukharev, J.-H. Choy, M. Chew, T. Kim, and S. X.-D.Tan.
Electromigration assessment for power grid networks considering temperature and
thermal stress effects.
Integration, the VLSI Journal, 55:307-315, September 2016.
- [1888]
- H.-Y. Huang and S.-L.
Chen.
Interconnect accelerating techniques for sub-100-nm gigascale systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(11):1192-1200, November 2004.
- [1889]
- D. Huang and T.-W.-S. Chow.
Efficiently searching the important input variables using bayesian
discriminant.
IEEE Transactions on Circuits and Systems, 52(4):785-793, April
2005.
- [1890]
- Y.-J. Huang and J.-F. Li.
Built-in self-repair scheme for the tsvs in 3-D ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(10):1600-1613, October 2012.
- [1891]
- T.-W. Huang and M.-D.-F.
Wong.
Accelerated path-based timing analysis with mapreduce.
In ACM International Symposium on Physical Design 2015, pages
103-110, Monterey, California, March 29 - April 1 2015.
- [1892]
- T.-W. Huang and M.-D.-F.
Wong.
UI-timer 1.0: an ultrafast path-based timing analysis algorithm for CPPR.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(11):1862-1875, November 2016.
- [1893]
- S. Huda and
A. Sheikholeslami.
A novel STT-MRAM cell with disturbance-free read operation.
IEEE Transactions on Circuits and Systems, 60(6):1534-1547, June
2013.
- [1894]
- F. Huebbers,
A. Dasdan, and Y. I. Ismail.
Computation of accurate interconnect process parameter values for performance
corners under process variations.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
797-800, San Francisco, CA, July 24-28 2006.
- [1895]
- F. Huebbers,
A. Dasdan, and Y. I. Ismail.
Multi-layer interconnect performance corners for variation-aware timing
analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 713-718, San Jose, CA, November 5-8 2007.
- [1896]
- D. A. Huffman.
A method for the construction of minimum-redundancy codes.
In Proceedings of the IRE, pages 1098-1101, September 1952.
- [1897]
- L. M. Huisman.
Diagnosing arbitrary defects in logic designs using single location at a time
(SLAT).
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):91-101, January 2004.
- [1898]
- C. M. Huizer.
Power dissipation analysis of CMOS VLSI circuits by means of switch- level
simulation.
In IEEE European Solid State Circuits Conference, pages 61-64,
Grenoble, France, 1990.
- [1899]
- H. Hulgaard,
P. F. Williams, and H. R. Andersen.
Equivalence checking of combinational circuits using boolean expression
diagrams.
IEEE Transactions on Computer-Aided Design, 18(7):903-917, July
1999.
- [1900]
- W. Hung, Y. Xie,
N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and Y. Tsai.
Total power optimization through simultaneously multiple-VDD multiple-VTH
assignment and device sizing with stack forcing.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 144-149, Newport Beach, CA, August 9-11 2004.
- [1901]
- W.-N.-N. Hung,
X. Song, G. Yang, J. Yang, and M. Perkowski.
Quantum logic synthesis by symbolic reachability analysis.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
838-841, San Diego, CA, June 7-11 2004.
- [1902]
- W.-N.-N. Hung,
X. Song, G. Yang, J. Yang, and M. Perkowski.
Optimal synthesis of multiple output boolean functions using a set of quantum
gates by symbolic reachability analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1652-1663, September 2006.
- [1903]
- S. L. Hurst, D. M.
Miller, and J. C. Muzio.
Spectral Techniques in Digital Logic.
Academic Press Inc., Orlando, FL, 1985.
- [1904]
- S. L. Hurst.
The logical processing of digital signals.
Crane, Russack & Company, Inc., New York, NY, 1978.
- [1905]
- A. P. Hurst.
Automatic synthesis of clock gating logic with controlled netlist perturbation.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
654-657, Anaheim, CA, June 8-13 2008.
- [1906]
- A. Hussain.
Models for interconnect capacitance extraction.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 167-172, San Jose, CA, March 26-28 2001.
- [1907]
- M. D. Hutton,
J. S. Rose, and D. G. Corneil.
Automatic generation of synthetic sequential benchmark circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(8):928-940, August 2002.
- [1908]
- T. Huynh-Bao, J. Ryckaert, Z. Tokei, A. Mercha, D. Verkest,
A.-V.-Y. Thean, and P. Wambaeq.
Statistical timing analysis considering device and interconnect variability for
BEOL requirements in the 5-nm node and beyond.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(5):1669-1680, May 2017.
- [1909]
- S. H. Hwang,
Y. H. Kim, and A. R. Newton.
An accurate delay modeling technique for switch-level timing verification.
In IEEE 23rd Design Automation Conference, pages 227-233, 1986.
- [1910]
- M.-E. Hwang,
T. Cakici, and K. Roy.
Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling.
Design, Automation and Test in Europe (DATE-07), pages 1550-1555,
April 16-20 2007.
- [1911]
- M.-E. Hwang,
S.-O. Jung, and K. Roy.
Slope interconnect effort: gate-interconnect interdependent delay model for
CMOS logic gates with scaled supply voltage.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 387-390, Portland, Oregon, August 27-29 2007.
- [1912]
- M.-E. Hwang, S.-O.
Jung, and K. Roy.
Slope interconnect effort: gate-interconnect interdependent delay modeling for
early CMOS circuit simulation.
IEEE Transactions on Circuits and Systems, 56(7):1427-1440, July
2009.
- [1913]
- Y.-T. Hwang, J.-F.
Lin, and M.-H. Sheu.
Low-power pulse-triggered flip-flop design with conditional pulse-enhancement
scheme.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):361-366, February 2012.
- [1914]
- E.-J. Hwang,
W. Kim, and Y.-H. Kim.
Timing yield slack for timing yield-constrained optimization and its
application to statistical leakage minimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1783-1796, October 2013.
- [1915]
- K. S. Hwang and M. R.
Mercer.
Derivation and refinement of fan-out constraints to generate tests in
combinational logic circuits.
IEEE Transactions on Computer-Aided Design, CAD-5(4):564-572, October
1986.
- [1916]
- J. P. Hwang.
REX - A VLSI parasitic extraction tool for electromigration and signal
analysis.
In 28th ACM/IEEE Design Automation Conference, pages 717-722,
1991.
- [1917]
- R. Hyman,
N. Ranganathan, T. Bingel, and D.-T. Vo.
A clock control strategy for peak power and RMS current reduction using path
clustering.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(2):259-269, February 2013.
- [1918]
- O. H. Ibarra and S. K.
Sahni.
Polynomially complete fault detection problems.
IEEE Transactions on Computers, C-24(3):242-249, March 1975.
- [1919]
- W. Ibrahim,
V. Beiu, and A. Beg.
GREDA: a fast and more accurate gate reliability EDA tool.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):509-521, April 2012.
- [1920]
- K. Ibuki,
K. Naemura, and A. Nozaki.
General theory of complete sets of logical functions.
Electronics and Communications in Japan, (IEEE Translation),
46(7):55-65, July 1963.
- [1921]
- M. Igarashi,
K. Usami, K. Nogami, F. Minami, Y. Kawasaki, T. Aoki, M. Takano, C. Mizuno,
T. Ishikawa, M. Kanazawa, S. Sonoda, M. Ichida, and N. Hatanaka.
A low-power design method using multiple supply voltages.
In 1997 International Symposium on Low Power Electronics and Design,
pages 36-41, Monterey, CA, August 18-20 1997.
- [1922]
- T. Iizuka,
M. Ikeda, and K. Asada.
Timing-aware cell layout de-compaction for yield optimization by critical area
minimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(6):716-720, June 2007.
- [1923]
- A. Ilumoka.
Chip level signal integrity analysis & crosstalk prediction using artificial
neural nets.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 175-180, San Jose, CA, March 18-21 2002.
- [1924]
- H. Im, T. Inukai,
H. Gomyo, T. Hiramoto, and T. Sakurai.
VTCMOS characteristics and its optimum conditions predicted by a compact
analytical model.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 123-128, Huntington Beach, California, August 6-7
2001.
- [1925]
- H. Im, T. Inukai,
H. Gomyo, T. Hiramoto, and T. Sakurai.
VTCMOS characteristics and its optimum conditions predicted by a compact
analytical model.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(5):755-761, October 2003.
- [1926]
- Y. Im and K. Roy.
Cash: A novel "clock as shield" design methodology for noise immune
precharge-evaluate logic.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 337-341, San Jose, CA, November 4-8 2001.
- [1927]
- Y. Im and K. Roy.
O2aba: A novel high-performance predictable circuit architecture for the deep
submicron era.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):221-229, June 2002.
- [1928]
- M. Imai, T. Sato,
N. Nakayama, and K. Masu.
Non-parametric statistical static timing analysis: an SSTA framework for
arbitrary distribution.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
698-701, Anaheim, CA, June 8-13 2008.
- [1929]
- S. Iman and M. Pedram.
Multi-level network optimization for low power.
In IEEE/ACM International Conference on Computer-Aided Design, pages
372-377, San Jose, CA, November 6-10 1994.
- [1930]
- S. Iman and M. Pedram.
Logic extraction and factorization for low power.
In 32nd Design Automation Conference, pages 248-253, San Francisco,
CA, June 12-16 1995.
- [1931]
- S. Iman and M. Pedram.
Two-level logic minimization for low power.
In IEEE/ACM International Conference on Computer-Aided Design, pages
433-438, San Jose, CA, November 5-9 1995.
- [1932]
- S. Iman and M. Pedram.
An approach for multilevel logic optimization targeting low power.
IEEE Transactions on Computer-Aided Design, 15(8):889-901, August
1996.
- [1933]
- S. Iman and M. Pedram.
POSE: Power optimization and synthesis environment.
In 33rd Design Automation Conference, pages 21-26, Las Vegas, NV,
June 3-7 1996.
- [1934]
- C. Inacio,
H. Schmit, D. Nagle, A. Ryan, D. E. Thomas, Y. Tong, and B. Klass.
Vertical benchmarks for CAD.
In Design Automation Conference, pages 408-413, New Orleans, LA, June
21-25 1999.
- [1935]
- T. Inukai,
T. Hiramoto, and T. Sakurai.
Variable threshold voltage CMOS (VTCMOS) in series connected circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 201-206, Huntington Beach, California, August 6-7
2001.
- [1936]
- R. Ionutiu,
J. Rommes, and W. H. A. Schilders.
Sparserc: sparsity preserving model reduction for RC circuits with many
terminals.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(12):1828-1841, December 2011.
- [1937]
- I. C. F. Ipsen and C. D.
Meyer.
The idea behind krylov methods.
American Mathematical Monthly, 105(10):889-899, December 1998.
- [1938]
- N. Iqbal and J. Henkel.
SETS: stochastic execution time scheduling for multicore systems by joint
state space and monte carlo.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 123-130, San Jose, CA, November 7-11 2010.
- [1939]
- S. Irani,
G. Singh, S. K. Shukla, and R. K. Gupta.
An overview of the competitive and adversarial approaches to designing dynamic
power management strategies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(12):1349-1361, December 2005.
- [1940]
- A. Iranli and
M. Pedram.
Cycle-based decomposition of markov chains with applications to low-power
synthesis and sequence compaction for finite state machines.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2712-2725, December 2006.
- [1941]
- F. Ishihara,
F. Sheikh, and B. Nikolic.
Level conversion for dual-supply systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(2):185-195, February 2004.
- [1942]
- T. Ishihara and
H. Yasuura.
Basic experimentation on accuracy of power estimation for CMOS VLSI
circuits.
In International Symposium on Low Power Electronics and Design, pages
117-120, Monterey, CA, August 12-14 1996.
- [1943]
- R. Islam,
A. Brand, and D. Lippincott.
Low power SRAM techniques for handheld products.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 198-202, San Diego, CA, August 8-10 2005.
- [1944]
- A. K. M. M. Islam and
H. Onodera.
Pvt2: process, voltage, temperature and time-dependent variability in scaled
CMOS process.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [1945]
- A. A. Ismaeel and
M. A. Breuer.
The probability of error detection in sequential circuits using random test
vectors.
Journal of Electronic Testing, 1:245-256, January 1991.
- [1946]
- Y. I. Ismail,
E. G. Friedman, and J. L. Neves.
Figures of merit to characterize the importance of on-chip inductance.
In IEEE/ACM 35th Design Automation Conference, pages 560-565, San
Francisco, CA, June 15-19 1998.
- [1947]
- Y. I. Ismail,
E. G. Friedman, and J. L. Neves.
Power dissipated by CMOS gates driving lossless transmission lines.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 139-141, Monterey, CA, August 10-12 1998.
- [1948]
- Y. I. Ismail,
E. G. Friedman, and J. L. Neves.
Equivalent elmore delay for RLC trees.
In Design Automation Conference, pages 715-720, New Orleans, LA, June
21-25 1999.
- [1949]
- Y. I. Ismail,
E. G. Friedman, and J. L. Neves.
Equivalent elmore delay for RLC trees.
IEEE Transactions on Computer-Aided Design, 19(1):83-97, January
2000.
- [1950]
- M. Ismail,
O. Hasan, T. Ebi, M. Shafique, and J. Henkel.
Formal verification of distributed dynamic thermal management.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 248-255, San Jose, CA, November 18-21 2013.
- [1951]
- Y. I. Ismail and C. S.
Amin.
Computation of signal-threhold crossing times directly from higher order
moments.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1264-1276, August 2004.
- [1952]
- Y. I. Ismail and C. S.
Amin.
Computation of signal threshold crossing times directly from higher order
moments.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 246-253, San Jose, CA, November 7-11 2004.
- [1953]
- Y. I. Ismail and
E. G. Friedman.
DTT: Direct truncation of the transfer function - an alternative to moment
matching for tree structured interconnect.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(2):131-144, February 2002.
- [1954]
- Y. I. Ismail.
On-chip inductance cons and pros.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):685-694, December 2002.
- [1955]
- Y. I. Ismail.
Improved model-order reduction by using spacial information in moments.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(5):900-908, October 2003.
- [1956]
- K. Itoh, K. Osada,
and T. Kawahara.
Trends in low-voltage embedded rams.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 45-48, Montreal, Quebec, June 20-23 2004.
- [1957]
- K. Itoh.
Low-voltage memories for power-aware systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 1-6, Monterey, California, August 12-14 2002.
- [1958]
- K. Itoh.
Low-voltage embedded rams in the nanometer era.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 235-242, Austin, TX, May 9 - 11 2005.
- [1959]
- A. Iyer and
D. Marculescu.
Microarchitecture-level power management.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):230-239, June 2002.
- [1960]
- A. Iyer and
D. Marculescu.
Power efficiency of voltage scaling in multiple clock, multiple voltage cores.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 379-386, San Jose, CA, November 10-14 2002.
- [1961]
- R. K. Iyer.
Hierarchical application aware error detection and recovery.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 79-79,
San Diego, CA, June 7-11 2004.
- [1962]
- R. Jacobi,
N. Calazans, and C. Trullemans.
Incremental reduction of binary decision diagrams.
In IEEE International Symposium on Circuits and Systems, pages
3174-3177, June 1991.
- [1963]
- M. Jacome,
C. He, G. de Veciana, and S. Bijansky.
Defect tolerant probabilistic design paradigm for nanotechnologies.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
596-601, San Diego, CA, June 7-11 2004.
- [1964]
- N. Jafarzadeh, M. Palesi, A. Khademzadeh, and A. Afzali-Kusha.
Data encoding techniques for reducing energy consumption in network-on-chip.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(3):675-685, March 2014.
- [1965]
- J. Jaffair and M. Anis.
On efficient LHS-based yield analysis of analog circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(1):159-163, January 2011.
- [1966]
- J. Jaffari and M. Anis.
Variability-aware device optimization under ion and leakage current
constraints.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 119-122, Tegernsee, Germany, October 4-6 2006.
- [1967]
- J. Jaffari and
M. Anis.
On efficient monte carlo-based statistical static timing analysis of digital
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 196-203, San Jose, CA, November 10-13 2008.
- [1968]
- J. Jaffari and
M. Anis.
Statistical thermal profile considering process vairations: analysis and
applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(6):1027-1040, June 2008.
- [1969]
- J. Jaffari and M. Anis.
Advanced variance reduction and sampling techniques for efficient statistical
timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(12):1894-1907, December 2010.
- [1970]
- U. Jagau.
SIMCURRENT - an efficient program for the estimation of the current flow of
complex CMOS circuits.
In IEEE International Conference on Computer-Aided Design (ICCAD),
pages 396-399, Santa Clara, CA, Nov. 11-15 1990.
- [1971]
- J. Jain, J. Bitner,
D. S. Fussell, and J. A. Abraham.
Probabilistic design verification.
In IEEE International Conference on Computer-Aided Design, pages
468-471, Santa Clara, CA, November 11-14 1991.
- [1972]
- S. Jain, R. E.
Bryant, and A. Jain.
Automatic clock abstraction from sequential circuits.
In 32nd Design Automation Conference, pages 707-711, San Francisco,
CA, June 12-16 1995.
- [1973]
- J. Jain, C.-K. Koh,
and V. Balakrishnan.
Fast simulation of VLSI interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 93-98, San Jose, CA, November 7-11 2004.
- [1974]
- A. Jain, D. Blaauw,
and V. Zolotov.
Accurate delay computation for noisy waveform shapes.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 947-953, San Jose, CA, November 6-10 2005.
- [1975]
- P. Jain, F. Cano,
B. Pudi, and N. V. Arvind.
Asymmetric aging: introduction and solution for power-managed mixed-signal
socs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(3):691-695, March 2014.
- [1976]
- P. Jain, S. S.
Sapatnekar, and J. Cortadella.
A retargetable and accurate methodology for logic-IP-internal
electromigration assessment.
In 20th Asia and South Pacific Design Automation Conference, pages
346-351, Chiba/Tokyo, Japan, January 19-22 2015.
- [1977]
- P. Jain, V. Mishra,
and S. S. Sapatnekar.
Fast stochastic analysis of electromigration in power distribution networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(9):2512-2524, September 2017.
- [1978]
- S. K. Jain and V. D.
Agrawal.
Test generation for MOS circuits using D-algorithm.
In IEEE 20th Design Automation Conference, pages 64-70, Miami Beach,
FL, June 27-29 1983.
- [1979]
- S. K. Jain and V. D.
Agrawal.
STAFAN: an alternative to fault simulation.
In IEEE 21st Design Automation Conference, pages 18-23, 1984.
- [1980]
- P. Jain and A. Jain.
Accurate current estimation for interconnect reliability analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(9):1634-1644, September 2012.
- [1981]
- R. Jakushokas
and E. G. Friedman.
Multi-layer interdigitated power distribution networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(5):774-786, May 2011.
- [1982]
- R. Jakushokas
and E. G. Friedman.
Power network optimization based on link breaking methodology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(5):983-987, May 2013.
- [1983]
- S. Jallepalli, R. Mooraka, S. Parihar, E. Hunter, and
E. Maalouf.
Employing scaled sigma sampling for efficient estimation of rare event
probabilities in the absence of input domain mapping.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(6):943-956, June 2016.
- [1984]
- S. Jallepalli, R. Mooraka, S. Parihar, E. Hunter, and
E. Maalouf.
Rapid assessment of design sensitivity to process excursions via scaled sigma
sampling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(6):957-970, June 2016.
- [1985]
- M. H. B. Jamaa,
K. E. Moselund, D. Atienza, D. Bouvet, A. M. Ionescu, Y. Leblebici, and G. De
Micheli.
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 765-772, San Jose, CA, November 5-8 2007.
- [1986]
- M. H. Ben Jamaa,
Y. Leblebici, and G. De Micheli.
Decoding nanowire arrays fabricated with the multi-spacer patterning technique.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 77-82,
San Francisco, CA, July 26-31 2009.
- [1987]
- F. James.
Monte carlo theory and practice.
Reports on Progress in Physics, 43:1145-1189, 1980.
- [1988]
- P. Jamieson and
J. Rose.
Mapping multiplexers onto hard multipliers in fpgas.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 323-326, Quebec City, Quebec, June 19-22 2005.
- [1989]
- P. A. Jamieson and
J. Rose.
Enhancing the area efficiency of fpgas with hard circuits using shadow
clusters.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(12):1696-1709, December 2010.
- [1990]
- R. K. Jana, G. L.
Snider, and D. Jena.
Energy-efficient clocking based on resonant switching for low-power
computation.
IEEE Transactions on Circuits and Systems, 61(5):1400-1408, May
2014.
- [1991]
- V. Janakiraman, A. Bharadwaj, and V. Visvanathan.
Voltage and temperature aware statistical leakage analysis framework using
artificial neural networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(7):1056-1069, July 2010.
- [1992]
- V. Jandhyala.
Physics-based field-theoretic design automation tools for social networks and
web search.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
280-281, San Diego, CA, June 5-9 2011.
- [1993]
- J.-W. Jang, S.-B.
Choi, and V. K. Prasanna.
Energy- and time-efficient matrix multiplication on fpgas.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1305-1319, November 2005.
- [1994]
- H. Jang and T. Kim.
Simultaneous clock buffer sizing and polarity assignment for power/ground noise
minimization.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
794-799, San Francisco, CA, July 26-31 2009.
- [1995]
- K. Jasrotia and
J. Zhu.
Stacked FSMD: a power efficient micro-architecture for high level synthesis.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 425-432, San Jose, CA, March 22-24 2004.
- [1996]
- H. Javaid,
A. Ignjatovic, and S. Parameswaran.
Fidelity metrics for estimation models.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 1-8, San Jose, CA, November 7-11 2010.
- [1997]
- N. Jayakumar, S. Dhar, and S. P. Khatri.
A self-adjusting scheme to determine the optimum RBB by monitoring leakage
currents.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 43-46,
Anaheim, CA, June 13-17 2005.
- [1998]
- N. Jayakumar and
S. P. Khatri.
An ASIC design methodology with predictably low leakage, using leakage-immune
standard cells.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 128-133, Seoul, Korea, August 25-27 2003.
- [1999]
- N. Jayakumar and
S. P. Khatri.
A variation-tolerant sub-threshold design approach.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
716-719, Anaheim, CA, June 13-17 2005.
- [2000]
- N. Jayakumar and
S. P. Khatri.
An algorithm to minimize leakage through simultaneous input vector control and
circuit modification.
Design, Automation and Test in Europe (DATE-07), pages 618-623, April
16-20 2007.
- [2001]
- R. Jejurikar, C. Pereira, and R. Gupta.
Leakage aware dynamic voltage scaling for real-time embedded systems.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
275-280, San Diego, CA, June 7-11 2004.
- [2002]
- G. Jennings and
E. Jennings.
A discrete syntax for level-sensitive latched circuits having n clocks and m
phases.
IEEE Transactions on Computer-Aided Design, 15(1):111-126, January
1996.
- [2003]
- D. Jenson and
M. Riedel.
A deterministic approach to stochastic computation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [2004]
- S-W. Jeong,
B. Plessier, G. Hachtel, and F. Somenzi.
Extended bdds: trading off canonicity for structure in verification algorithms.
In IEEE International Conference on Computer-Aided Design, pages
464-467, Santa Clara, CA, November 11-14 1991.
- [2005]
- K. Jeong, A. B.
Kahng, C.-H. Park, and H. Yao.
Dose map and placement co-optimization for timing yield enhancement and leakage
power reduction.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
516-521, Anaheim, CA, June 8-13 2008.
- [2006]
- K. Jeong, A. B.
Kahng, C.-H. Park, and H. Yao.
Dose map and placement co-optimization for improved timing yield and leakage
power.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(7):1070-1082, July 2010.
- [2007]
- G. Jerke,
J. Lienig, and J. Scheible.
Reliability-driven layout decompaction for electromigration failure avoidance
in complex mixed-signal IC designs.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
181-184, San Diego, CA, June 7-11 2004.
- [2008]
- G. Jerke and J. Lienig.
Hierarchical current-density verification in arbitrarily shaped metallization
patterns of analog circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):80-90, January 2004.
- [2009]
- J. A. G. Jess,
K. Kalafala, W. R. Naidu, R. H. J. M. Otten, and C. Visweswariah.
Statistical timing for parametric yield prediction of digital integrated
circuits.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
932-937, Anaheim, CA, June 2-6 2003.
- [2010]
- J. A. G. Jess,
K. Kalafala, S. R. Naidu, R. H. J. M. Otten, and C. Visweswariah.
Statistical timing for parametric yield prediction of digital integrated
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2376-2392, November 2006.
- [2011]
- J. A. G. Jess.
Designing electronic engines with electronic engines: 40 years of bootstrapping
of a technology upon itself.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1404-1427, December 2000.
- [2012]
- M. Jessa and
M. Walentynowicz.
Statistical properties of number sequences generated by 1d chaotic maps
considered as a potential source of pseudorandom number sequences.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 449-455, St. Julian, Malta, September 2-5 2001.
- [2013]
- N. K. Jha.
Low power system scheduling and synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 259-263, San Jose, CA, November 4-8 2001.
- [2014]
- T. Jhaveri,
V. Rovner, L. Liebmann, L. Pileggi, A. J. Strojwas, and J. D. Hibbeler.
Co-optimization of circuits, layout and lithography for predictive technology
scaling beyond gratings.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):509-527, April 2010.
- [2015]
- Y-M Jiang, K-T
Cheng, and A. Krstic.
Estimation of maximum power and instantaneous current using a genetic
algorithm.
In IEEE 1997 Custom Integrated Circuits Conference, pages 135-138,
Santa Clara, CA, May 5-8 1997.
- [2016]
- Y-M. Jiang, K-T.
Cheng, and A-C. Deng.
Estimation of maximum power supply noise for deep sub-micron designs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 233-238, Monterey, CA, August 10-12 1998.
- [2017]
- Y.-M. Jiang,
T. K. Young, and K.-T. Cheng.
VIP - an input pattern generator for identifying critical voltage drop for
deep sub-micron designs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 156-161, San Diego, CA, August 16-17 1999.
- [2018]
- Y.-M. Jiang,
A. Krstic, and K.-T. Cheng.
Estimation of maximum instantaneous current through supply lines for CMOS
circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(1):61-73, February 2000.
- [2019]
- Y-M Jiang,
A. Krstic, and K-T (Tim) Cheng.
Dynamic timing analysis considering power supply noise effects.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 137-143, San Jose, CA, March 20-22 2000.
- [2020]
- Y.-M. Jiang, H.-Y.
Koh, and K.-T. Cheng.
HRM - A hierarchical simulator for full-chip power network reliability
analysis.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 307-312, San Jose, CA, March 26-28 2001.
- [2021]
- R. Jiang, W. Fu,
J.-M. Wang, V. Lin, and C. C.-P. Chen.
Efficient statistical capacitance variability modeling with orthogonal
principle factor analysis.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 683-690, San Jose, CA, November 6-10 2005.
- [2022]
- Z. Jiang, S. Hu,
and W. Shi.
A new twisted differential line structure in global bus design.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
180-183, San Diego, CA, June 4-8 2007.
- [2023]
- I. H.-R. Jiang,
H.-Y. Chang, L.-G. Chang, and H.-B. Hung.
New spare cell design for IR drop minimization in engineering change order.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
408-411, San Francisco, CA, July 26-31 2009.
- [2024]
- J.-H. R. Jiang,
H.-P. Lin, and W.-L. Hung.
Interpolating functions from large boolean relations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 779-784, San Jose, CA, November 2-5 2009.
- [2025]
- I.-H.-R. Jiang,
G.-J. Nam, H.-Y. Chang, S. R. Nassif, and J. Hayes.
Smart grid load balancing techniques via simultaneous switch/tie-line/wire
configurations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 382-388, San Jose, CA, November 2-6 2014.
- [2026]
- J.-H. R. Jiang and R. K.
Brayton.
On the verification of sequential equivalence.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(6):686-697, June 2003.
- [2027]
- J.-H.-R. Jiang and R. K.
Brayton.
Retiming and resynthesis: a complexity perspective.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2674-2686, December 2006.
- [2028]
- I.-H.-R. Jiang and H.-Y.
Chang.
Wit: optimal wiring topology for electromigration avoidance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(4):581-592, April 2012.
- [2029]
- Y.-L. Jiang and H.-B.
Chen.
Application of general orthogonal polynomials to fast simulation of nonlinear
descriptor systems through piecewise-linear approximation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(5):804-808, May 2012.
- [2030]
- Y.-M. Jiang and K.-T.
Cheng.
Analysis of performance impact cause by power supply noise in deep submicron
devices.
In Design Automation Conference, pages 760-765, New Orleans, LA, June
21-25 1999.
- [2031]
- Y.-M. Jiang and K. T.
Cheng.
Vector generation for power supply noise estimation and verification of deep
submicron designs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(2):329-340, April 2001.
- [2032]
- X. Jiang and
S. Horiguchi.
Statistical skew modeling for general clock distribution networks in presence
of process variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(5):704-717, October 2001.
- [2033]
- H. Jiang and
M. Marek-Sadowska.
Power gating scheduling for power/ground noise reduction.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
980-985, Anaheim, CA, June 8-13 2008.
- [2034]
- R. Jiang and D. N. P.
Murthy.
The exponentiated weibull family: A graphical approach.
IEEE Transactions on Reliability, 48(1):68-72, March 1999.
- [2035]
- Y.-L. Jiang.
A general approvah to waveform relaxation solutions of nonlinear
differential-algebraic equations: the continuous-time and discrete-time
cases.
IEEE Transactions on Circuits and Systems, 51(9):1770-1780, September
2004.
- [2036]
- W. Jigang,
T. Srikanthan, and X. Han.
Preprocessing and partial rerouting techniques for accelerating reconfiguration
of degradable VLSI arrays.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):315-319, February 2010.
- [2037]
- W. Jin, P. C. H. Chan,
and M. Chan.
On the power dissipation in dynamic threshold silicon-on-insulator CMOS
inverter.
In 1997 International Symposium on Low Power Electronics and Design,
pages 247-250, Monterey, CA, August 18-20 1997.
- [2038]
- H.-S. Jin, M.-S. Jang,
J.-S. Song, J.-Y. Lee, T.-S. Kim, and J.-T. Kong.
Dynamic power estimation using the probabilistic contribution measure (PCM).
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 279-281, San Diego, CA, August 16-17 1999.
- [2039]
- T. Jindal, C. J.
Alpert, J. Hu, Z. Li, G.-J. Nam, and C. B. Winn.
Detecting tangled logic structures in VLSI netlists.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
603-608, Anaheim, CA, June 13-18 2010.
- [2040]
- G. Jochens,
L. Kruse, E. Schmidt, and W. Nebel.
A new parametrizable power macro-model for datapath components.
IEEE Design Automation and Test in Europe (DATE), pages 29-36,
1999.
- [2041]
- J. John and C. Riddle.
Smart phone power.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
935-936, Anaheim, CA, June 13-18 2010.
- [2042]
- M. Johnson,
D. Somasekhar, and K. Roy.
Leakage control with efficient use of transistor stacks in single threshold
CMOS.
In Design Automation Conference, pages 442-445, New Orleans, LA, June
21-25 1999.
- [2043]
- M. C.
Johnson, D. Somasekhar, and K. Roy.
Models and algorithms for bounds on leakage in CMOS circuits.
IEEE Transactions on Computer-Aided Design, 18(6):714-725, June
1999.
- [2044]
- M. C. Johnson,
D. Somasekhar, L.-Y. Chiou, and K. Roy.
Leakage control with efficient use of transistor stacks in single threshold
CMOS.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(1):1-5, February 2002.
- [2045]
- Norman L. Johnson and
Samuel Kotz.
Continuous Univariate Distributions, volume 1 and 2.
John Wiley & Sons, New York, NY, 1970.
- [2046]
- Norman L. Johnson and
Samuel Kotz.
Discrete Distributions.
John Wiley & Sons, New York, NY, 1970.
- [2047]
- J. Jones and J. Hayes.
A comparison of electronic-reliability prediction models.
IEEE Transactions on Reliability, 48(2):127-134, June 1999.
- [2048]
- D. De Jonghe and
G. Gielen.
Efficient analytical macromodeling of large analog circuits by transfer
function trajectories.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 91-94, San Jose, CA, November 7-10 2011.
- [2049]
- D. De Jonghe and
G. Gielen.
Characterization of analog circuits using transfer function trajectories.
IEEE Transactions on Circuits and Systems, 59(8):1796-1804, August
2012.
- [2050]
- Y. Joo, Y. Choi, and
H. Shim.
Energy exploration and reduction of SDRAM memory systems.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
892-897, New Orleans, LA, June 10-14 2002.
- [2051]
- R. Joseph,
Z. Hu, and M. Martonosi.
Wavelet analysis for microprocessor design: Experiences with wavelet-based
di/dt characterization.
In 10th International Symposium on High Performance Computer Architecture
(HPCA-04), pages 36-46, Madrid, Spain, Feb. 14-18 2004.
- [2052]
- A. Joseph,
A. Haridass, C. Lefurgy, S. Pai, S. Rachamalla, and F. Campisano.
Freqleak: a frequency step based method for efficient leakage power
characterization in a system.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 195-200, Rome, Italy, July 22-24 2015.
- [2053]
- V. Joshi,
D. Blaauw, and D. Sylvester.
Soft-edge flip-flops for improved timing yield: design and optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 667-673, San Jose, CA, November 5-8 2007.
- [2054]
- V. Joshi,
B. Cline, D. Sylvester, D. Blaauw, and K. Agarwal.
Leakage power reduction using stress-enhanced layouts.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
912-917, Anaheim, CA, June 8-13 2008.
- [2055]
- R. Joshi, R. Kanj,
P. Wang, and H. Li.
Universal statistical cure for predicting memory loss.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 236-239, San Jose, CA, November 7-10 2011.
- [2056]
- S. Joshi and S. Boyd.
An efficient method for large-scale gate sizing.
IEEE Transactions on Circuits and Systems, 55(9):2760-2773, October
2008.
- [2057]
- N. P. Jouppi.
TV: An nmos timing analyzer.
In 3rd Caltech Conference on VLSI, pages 71-85, 1983.
- [2058]
- N. P. Jouppi.
Derivation of signal flow direction in MOS VLSI.
IEEE Transactions on Computer-Aided Design, CAD-6(3):480-490, May
1987.
- [2059]
- N. P. Jouppi.
Timing analysis and performance improvements of MOS VLSI designs.
IEEE Transactions on Computer-Aided Design, CAD-6(4):650-665, July
1987.
- [2060]
- J. W. Joyner,
P. Zarkesh-Ha, and J. D. Meindl.
Global interconnect design in a three-dimensional system-on-a-chip.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):367-372, April 2004.
- [2061]
- Y-C Ju, V. B. Rao, and
R. A. Saleh.
Consistency checking and optimization of time-domain macromodels.
Submitted to ICCAD-89, rejected., 1989.
- [2062]
- Y-C. Ju, V. B. Rao, and
R. A. Saleh.
Consistency checking and optimization of macromodels.
IEEE Transactions on Computer-Aided Design, 10(8):957-967, August
1991.
- [2063]
- D.-C. Juan, Y.-T.
Chen, M.-C. Lee, and S.-C. Chang.
An efficient wake-up strategy considering spurious glitches phenomenon for
power gating designs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):246-255, February 2010.
- [2064]
- P. Julian.
The complete canonical piecewise-linear representation: functional form for
minimal degenerate intersections.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(3):387-396, March 2003.
- [2065]
- Y-H. Jun, K. Jun, and
S-B. Park.
An accurate and efficient delay time modeling for MOS logic circuits using
polynomial approximation.
IEEE Transactions on Computer-Aided Design, 8(9):1027-1032, September
1989.
- [2066]
- S.-O. Jung, K.-W.
Kim, and S.-M. (Steve) Kang.
Noise constrained transistor sizing and power optimization for dual vt domino
logic.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):532-541, October 2002.
- [2067]
- S.-O. Jung, K.-W.
Kim, and S.-M. Kang.
Timing constraints for domino logic gates with timing-dependent keepers.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(1):96-104, January 2003.
- [2068]
- K. Jung, W. R.
Eisenstadt, and R. M. Fox.
SPICE-based mixed-model S-parameter calculations for four-port and
three-port circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):909-913, May 2006.
- [2069]
- H. Jung, P. Rong,
and M. Pedram.
Stochastic modeling of a thermally-managed multi-core system.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
728-733, Anaheim, CA, June 8-13 2008.
- [2070]
- M. Jung, J. Mitra,
D.-Z. Pan, and S.-K. Lim.
TSV stress-aware full-chip mechanical reliability analysis and optimization
for 3d IC.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
188-193, San Diego, CA, June 5-9 2011.
- [2071]
- M. Jung, D. Pan,
and S.-K. Lim.
Chip/package co-analysis of thermo-mechanical stress and reliability in
TSV-based 3-D ics.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
317-326, San Francisco, CA, June 3-7 2012.
- [2072]
- S. Jung, Y. Choi,
and J. Kim.
Variability-aware, discrete optimization for analog circuits.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
536-541, San Francisco, CA, June 3-7 2012.
- [2073]
- M. Jung, D. Z. Pan,
and S. K. Lim.
Chip/package mechanical stress impact on 3-D IC reliability and mobility
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(11):1694-1707, November 2013.
- [2074]
- J. Jung, I.-H.-R
Jiang, G.-J. Nam, V. N. Kravets, L. Behjat, and Y.-L. Li.
Opendesign flow database: the infrastructure for VLSI design and design
automation research.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [2075]
- J. Jung and T. Kim.
Variation-aware false path analysis based on statistical dynamic timing
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(11):1684-1697, November 2012.
- [2076]
- J. Jung and T. Kim.
Statistical viability analysis for detecting false paths under delay variation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):111-123, January 2013.
- [2077]
- H. Jung and M. Pedram.
Supervised learning based power management for multicore processors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(9):1395-1408, September 2010.
- [2078]
- H.-F. Jyu, S. Malik,
S. Devadas, and K. W. Keutzer.
Statistical timing analysis of combinational logic circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
1(2):126-137, June 1993.
- [2079]
- A. Kabbani,
D. Al-Khalili, and A. J. Al-Khalili.
Technology-portable analytical model for DSM CMOS inverter transition-time
estimation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(9):1177-1187, September 2003.
- [2080]
- A. Kabbani,
D. Al-Khalili, and A. J. Al-Khalili.
Delay analysis of CMOS gates using modified logical effort model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(6):937-947, June 2005.
- [2081]
- A. Kabbani and
A. J. Al-Khalili.
A technique for dynamic CMOS noise immunity evaluation.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(1):74-88, January 2003.
- [2082]
- D. Kagaris.
MOTO-X: a multiple-output transistor-level synthesis CAD tool.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(1):114-127, January 2016.
- [2083]
- B. Kagstrom.
Bounds and perturbation bounds for the matrix exponential.
BIT Numerical Mathematics, 17(1):39-57, March 1977.
- [2084]
- A. B. Kahng,
K. Masuko, and S. Muddu.
Analytical delay models for VLSI interconnects under ramp inputs.
In IEEE/ACM International Conference on Computer-Aided Design, pages
30-36, San Jose, CA, November 10-14 1996.
- [2085]
- A. B. Kahng,
S. Mantik, and D. Stroobandt.
Requirements for models of achievable routing.
In International Symposium on Physical Design, pages 4-11, San Diego,
CA, April 9-12 2000.
- [2086]
- A. B. Kahng,
S. Muddu, and E. Sarto.
On switch factor based analysis of coupled RC interconnects.
In Design Automation Conference, pages 79-84, Los Angeles, CA, June
5-9 2000.
- [2087]
- A. B. Kahng,
S. Muddu, N. Pol, and D. Vidhani.
Noise model for multiple segmented coupled RC interconnects.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 145-150, San Jose, CA, March 26-28 2001.
- [2088]
- A. B. Kahng,
B. Liu, and I. I. Mandoiu.
Non-tree routing for reliability and yield improvement.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 260-266, San Jose, CA, November 10-14 2002.
- [2089]
- A. B. Kahng,
B. Liu, and I. I. Mandoiu.
Non-tree routing for reliability and yield improvement.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):148-156, January 2004.
- [2090]
- A. B. Kahng,
S. Muddu, and P. Sharma.
Defocus-aware leakage estimation and control.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 263-268, San Diego, CA, August 8-10 2005.
- [2091]
- A. B. Kahng,
S. Reda, and Q. Wang.
Architecture and details of a high quality, large-scale analytical placer.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 891-898, San Jose, CA, November 6-10 2005.
- [2092]
- A. B. Kahng,
B. Liu, and Q. Wang.
Stochastic power/ground supply voltage prediction and optimization via
analytical placement.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(8):904-912, August 2007.
- [2093]
- A. B. Kahng,
B. Liu, and X. Xu.
Statistical timing analysis in the presence of signal-integrity effects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(10):1873-1877, October 2007.
- [2094]
- A. B. Kahng,
P. Sharma, and R. O. Topaloglu.
Exploiting STI stress for performance.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 83-90, San Jose, CA, November 5-8 2007.
- [2095]
- A. B. Kahng,
S. Muddu, and P. Sharma.
Defocus-aware leakage estimation and control.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):230-240, February 2008.
- [2096]
- A. B. Kahng,
S. Kang, H. Lee, I. L. Markov, and P. Thapar.
High-performance gate sizing with a signoff timer.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 450-457, San Jose, CA, November 18-21 2013.
- [2097]
- A. B. Kahng,
M. Luo, G.-J. Nam, S. Nath, D.-Z. Pan, and G. Robins.
Toward metrics of design automation research impact.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 263-270, Austin, TX, November 2-6 2015.
- [2098]
- A. B. Kahng,
J. Li, and L. Wang.
Improved flop tray-based design implementation for power reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [2099]
- A. B. Kahng and
F. Koushanfar.
Evolving EDA beyond its e-roots: an overview.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 247-254, Austin, TX, November 2-6 2015.
- [2100]
- A. B. Kahng and
S. Mantik.
Measurement of inherent noise in EDA tools.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 206-211, San Jose, CA, March 18-21 2002.
- [2101]
- A. B. Kahng and S. Muddu.
New efficient algorithms for computing effective capacitance.
In ACM/IEEE International Symposium on Physical Design, pages
147-151, Monterey, CA, April 6-8 1998.
- [2102]
- A. B. Kahng and S. Reda.
Intrinsic shortest path length: a new, accurate a priori wirelength estimator.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 173-180, San Jose, CA, November 6-10 2005.
- [2103]
- A. B. Kahng and
K. Samadi.
CMP fill synthesis: a survey of recent studies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(1):3-19, January 2008.
- [2104]
- A. B. Kahng.
The ITRS design technology and system drivers roadmap: process and status.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2105]
- A. B. Kahng.
New game, new goal posts: a recent history of timing closure.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [2106]
- A. B. Kahng.
Invited: reducing time and effort in IC implementation: a roadmap of
challenges and solutions.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [2107]
- T. Kailath.
Linear Systems.
Prentice-Hall, Englewood Cliffs, NJ, 1980.
- [2108]
- A. Kaizerman, S. Fisher, and A. Fish.
Subthreshold dual mode logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(5):979-983, May 2013.
- [2109]
- S. Kajihara and
K. Miyase.
On identifying don't care inputs of test patterns for combinational circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 364-369, San Jose, CA, November 4-8 2001.
- [2110]
- C. Kalonakis, C. Antoniadis, P. Giannakou, D. Dioudis,
G. Pinitas, and G. Stamoulis.
Tktimer: fast & accurate clock network pessimism removal.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 606-610, San Jose, CA, November 2-6 2014.
- [2111]
- T. Kam, S. Rawat,
D. Kirkpatrick, R. Roy, G. S. Spirakis, N. Sherwani, and C. Peterson.
EDA challenges facing future microprocessor design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1498-1506, December 2000.
- [2112]
- M. B. Kamble and
K. Ghose.
Analytical energy dissipation models for low power caches.
In 1997 International Symposium on Low Power Electronics and Design,
pages 143-148, Monterey, CA, August 18-20 1997.
- [2113]
- M. Kamon,
S. McCormick, and K. Shepard.
Interconnect parasitic extraction in the digital IC design methodology.
In IEEE/ACM International Conference on Computer-Aided Design, pages
223-230, San Jose, CA, November 7-11 1999.
- [2114]
- M. Kandemir,
N. Vijaykrishnana, M. J. Irwin, and W. Ye.
Influence of compile optimizations on system power.
In Design Automation Conference, pages 304-307, Los Angeles, CA, June
5-9 2000.
- [2115]
- A. Kanduri,
M.-H. Haghbayan, A. M. Rahmani, P. Liljeberg, A. Jantsch, N. Dutt, and
H. Tenhunen.
Approximation knob: power capping meets energy efficiency.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [2116]
- K. Kang, K. Kim,
A. E. Islam, M. A. Alam, and K. Roy.
Characterization and estimation of circuit reliability degradation under NBTI
using on-line IDDQ measurement.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
358-363, San Diego, CA, June 4-8 2007.
- [2117]
- K. Kang, K. Kim,
and K. Roy.
Variation resilient low-power circuit design methodology using on-chip phase
locked loop.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
934-939, San Diego, CA, June 4-8 2007.
- [2118]
- K. Kang, S.-P.
Park, K. Roy, and M. A. Alam.
Estimation of statistical variation in temporal NBTI degradation and its
impact on lifetime circuit performance.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 730-734, San Jose, CA, November 5-8 2007.
- [2119]
- K. Kang, S.-P. Park,
K. Kim, and K. Roy.
On-chip variability sensor using phase-locked loop for detecting and correcting
parametric timing failures.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):270-280, February 2010.
- [2120]
- M. Z. Kang and W. W-M Dai.
Arbitrary rectilinear block packing based on sequence pair.
In IEEE/ACM International Conference on Computer-Aided Design, pages
259-266, San Jose, CA, November 8-12 1998.
- [2121]
- S.-M. (Steve) Kang.
Elements of low power design for integrated systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 205-210, Seoul, Korea, August 25-27 2003.
- [2122]
- R. Kanj, T. Lehner,
B. Agrawal, and E. Rosenbaum.
Noise characterization of static CMOS gates.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
888-893, San Diego, CA, June 7-11 2004.
- [2123]
- R. Kanj, R. Joshi,
and S. Nassif.
Mixture importance sampling and its application to the analysis of SRAM
designs in the presence of rare failure events.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 69-72,
San Francisco, CA, July 24-28 2006.
- [2124]
- R. Kanj, R. Joshi,
C. Adams, J. Warnock, and S. Nassif.
An elegant hardware-corroborated statistical repair and test methodology for
conquering aging effects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 497-504, San Jose, CA, November 2-5 2009.
- [2125]
- R. Kanj, T. Li,
R. Joshi, K. Agarwal, A. Sadigh, D. Winston, and S. Nassif.
Accelerated statistical simulation via on-demand hermite spline interpolations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 353-360, San Jose, CA, November 7-10 2011.
- [2126]
- R. Kanj, R. Joshi,
Z. Li, J. Hayes, and S. Nassif.
Yield estimation via multi-cones.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1107-1112, San Francisco, CA, June 3-7 2012.
- [2127]
- R. Kanj and
E. Rosenbaum.
Critical evaluation of SOI design guidelines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(9):885-894, September 2004.
- [2128]
- P. Kannan,
S. Balachandran, and D. Bhatia.
On metrics for comparing interconnect estimation methods for fpgas.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):381-385, April 2004.
- [2129]
- P. Kannan and
D. Bhatia.
Interconnect estimation for fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(8):1523-1534, August 2006.
- [2130]
- I. Kantorovich and C. Honghton.
Effectiveness of on-die decoupling capacitance in improving chip performance.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 165-168, San Jose, CA, October 27-29 2008.
- [2131]
- A. Kanuma.
CMOS circuit optimization.
Solid State Electronics, 26(1):47-58, 1983.
- [2132]
- J. Kao,
A. Chandrakasan, and D. Antoniadis.
Transistor sizing issues and tool for multi-threshold CMOS technology.
In 34th Design Automation Conference, pages 409-414, Anaheim, CA,
June 9-13 1997.
- [2133]
- J. Kao, S. Narendra,
and A. Chandrakasan.
Subthreshold leakage modeling and reduction techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 141-148, San Jose, CA, November 10-14 2002.
- [2134]
- J. T. Kao and A. P.
Chandrakasan.
Dual-threshold voltage techniques for low-power digital circuits.
IEEE Journal of solid-state circuits, 35(7):1009-1017, July 2000.
- [2135]
- H. Kapadia,
G. De Micheli, and L. Benini.
Reducing switching activity on datapath buses with control-signal gating.
In IEEE Custom Integrated Circuits Conference, pages 589-592, Santa
Clara, CA, May 11-14 1998.
- [2136]
- H. Kapadia and
M. Horowitz.
Using partitioning to help convergence in the standard-cell design automation
methodology.
In Design Automation Conference, pages 592-597, New Orleans, LA, June
21-25 1999.
- [2137]
- N. Kapadia and
S. Pasricha.
A runtime framework for robust application scheduling with adaptive parallelism
in the dark-silicon era.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(2):534-546, February 2017.
- [2138]
- A. Kapare,
H. Cherupalli, and J. Sartori.
Automated error prediction for approximate sequential circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [2139]
- A. Kapoor,
N. Jayakumar, and S. P. Khatri.
A novel clock distribution and dynamic de-skewing methodology.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 626-631, San Jose, CA, November 7-11 2004.
- [2140]
- A. Kapoor,
N. Jayakumar, and S. P. Khatri.
Dynamically de-skewable clock distribution methodology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(9):1220-1229, September 2008.
- [2141]
- A. Kapoor,
Y. Hu, and R. Bashirullah.
A current-density centric logical effort delay and power model for high-speed
CML gates.
IEEE Transactions on Circuits and Systems, 60(10):2618-2630, October
2013.
- [2142]
- B. Kapoor.
Improving the accuracy of circuit activity measurement.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
111-116, Napa, CA, April 24-27 1994.
- [2143]
- B. Kapoor.
Improving the accuracy of circuit activity measurement.
In 31st ACM/IEEE Design Automation Conference, pages 734-739, San
Diego, CA, June 6-10 1994.
- [2144]
- N. Kapre and A. DeHon.
SPICE: spatial processors interconnected for concurrent execution for
accelerating the SPICE circuit simulator using an FPGA.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(1):9-22, January 2012.
- [2145]
- S. Kapur and D. E. Long.
Large-scale full-wave simulation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
806-809, San Diego, CA, June 7-11 2004.
- [2146]
- I. Karafyllidis.
Design and simulation of a single-electron random-access memory array.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(9):1370-1375, September 2002.
- [2147]
- G. Karakonstantis, N. Banerjee, K. Roy, and C. Chakrabarti.
Design methodology to trade off power, output quality and error resiliency:
application to color interpolation filtering.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 199-204, San Jose, CA, November 5-8 2007.
- [2148]
- G. Karakonstantis, N. Bellas, C. Antonopoulos, G. Tziantzioulis,
V. Gupta, and K. Roy.
Significance driven computation on next-generation unreliable platforms.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
290-291, San Diego, CA, June 5-9 2011.
- [2149]
- S. K.
Karandikar and S. S. Sapatnekar.
Logical effort based technology mapping.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 419-422, San Jose, CA, November 7-11 2004.
- [2150]
- S. K.
Karandikar and S. S. Sapatnekar.
Fast comparisons of circuit implementations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(12):1329-1339, December 2005.
- [2151]
- S. K.
Karandikar and S. S. Sapatnekar.
Technology mapping using logical effort for solving the load-distribution
problem.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(1):45-58, January 2008.
- [2152]
- K. Karmarkar
and S. Tragoudas.
On-chip codeword generation to cope with crosstalk.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(2):237-250, February 2014.
- [2153]
- T. Karnik, C-C.
Teng, and S-M. Kang.
High-level hot carrier reliability-driven synthesis using macro-models.
In IEEE Custom Integrated Circuits Conference, pages 65-68, Santa
Clara, CA, May 1-4 1995.
- [2154]
- T. Karnik,
S. Borkar, and V. De.
Sub-90nm technologies - challenges and opportunities for CAD.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 203-206, San Jose, CA, November 10-14 2002.
- [2155]
- T. Karnik,
Y. Ye, J. Tschanz, L. Wei, and S. Burns.
Total power optimization by simultaneous dual-vt allocation and device sizing
in high performance microprocessors.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
486-491, New Orleans, LA, June 10-14 2002.
- [2156]
- T. Karnik,
M. Pant, and S. Borkar.
Power management and delivery for high-performance microprocessors.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2157]
- R. M. Karp.
The probabilistic analysis of some combinatorial search algorithms.
In J. F. Traub, editor, Algorithms and Complexity, pages 1-19.
Academic Press, Inc., New York, NY, 1976.
- [2158]
- A. V. Karthik,
S. Ray, and J. Roychowdhury.
BEE: predicting realistic worst case and stochastic eye diagrams by
accounting for correlated bitstreams and coding strategies.
In 20th Asia and South Pacific Design Automation Conference, pages
366-371, Chiba/Tokyo, Japan, January 19-22 2015.
- [2159]
- A. V. Karthik
and J. Roychowdhury.
ABCD-L: approximating continuous linear systems using boolean models.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2160]
- K. Kasamsetty, M. Ketkar, and S. S. Sapatnekar.
A new class of convex functions for delay modeling and its appliction to the
transistor sizing problem.
IEEE Transactions on Computer-Aided Design, 19(7):779-788, July
2000.
- [2161]
- C. V. Kashyap,
C. J. Alpert, and A. Devgan.
An "effective" capacitance based delay metric for RC interconnect.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 229-234, San Jose, CA, November 5-9 2000.
- [2162]
- C. V. Kashyap,
C. J. Alpert, F. (Y.) Liu, and A. Devgan.
Closed-form expressions for extending step delay and slew metrics to ramp
inputs for RC trees.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(4):509-516, April 2004.
- [2163]
- C. Kashyap,
C. Amin, N. Menezes, and E. Chiprout.
A nonlinear cell macromodel for digital applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 678-685, San Jose, CA, November 5-8 2007.
- [2164]
- C. Kashyap1,
P. Bastani, K. Killpack, and C. Amin1.
Silicon feedback to improve frequency of high-performance microprocessors - an
overview.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 778-782, San Jose, CA, November 10-13 2008.
- [2165]
- A. Kasnavi,
J.-W. Wang, M. Shahram, and J. Zejda.
Analytical modeling of crosstalk noise waveforms using weibull function.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 141-146, San Jose, CA, November 7-11 2004.
- [2166]
- R. Kastner,
E. Bozorgzadeh, and M. Sarrafzadeh.
Predictable routing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 110-113, San Jose, CA, November 5-9 2000.
- [2167]
- S. Katkoori and
R. Vemuri.
Simulation based architectural power estimation for PLA-based controllers.
In International Symposium on Low Power Electronics and Design, pages
121-124, Monterey, CA, August 12-14 1996.
- [2168]
- K. Katoh,
K. Namba, and H. Ito.
An on-chip delay measurement technique using signature registers for
small-delay defect detection.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(5):804-817, May 2012.
- [2169]
- H. Kaul,
d. Sylvester, M. Anders, and R. Krishnamurthy.
Spatial encoding circuit techniques for peak power reduction of on-chip
high-performance buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 194-199, Newport Beach, CA, August 9-11 2004.
- [2170]
- H. Kaul,
D. Sylvester, and D. Blaauw.
Performance optimization of critical nets through active shielding.
IEEE Transactions on Circuits and Systems, 51(12):2417-2435, December
2004.
- [2171]
- H. Kaul,
D. Sylvester, M. A. Anders, and R. K. Krishnamurthy.
Design and analysis of spatial encoding circuits for peak power reduction in
on-chip buses.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1225-1238, November 2005.
- [2172]
- H. Kaul, M. Anders,
S. Hsu, A. Agarwal, R. Krishnamurthy, and S. Borkar.
Near-threshold voltage (NTV) design - opportunities and challenges.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1149-1154, San Francisco, CA, June 3-7 2012.
- [2173]
- H. Kaul and
D. Sylvester.
Low-power on-chip communication based on transition-aware global signaling
(TAGS).
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):464-476, May 2004.
- [2174]
- B. K. Kaushik and
S. Sankar.
Crosstalk analysis for a CMOS-gate-driven coupled interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(6):1150-1154, June 2008.
- [2175]
- R. Kawakami,
H. Galvao, S. Hadjiloucas, K. H. Kienitz, H. M. Paiva, and R. J. M. Afonso.
Fractional order modeling of large three-dimensional RC networks.
IEEE Transactions on Circuits and Systems, 60(3):624-637, March
2013.
- [2176]
- S. Kaxiras,
P. Xekalakis, and G. Keramidas.
A simple mechanism to adapt leakage-control policies to temperature.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 54-59, San Diego, CA, August 8-10 2005.
- [2177]
- S. Kaxiras and
P. Xekalakis.
4t-decay sensors: a new class of small, fast, robust, and low-power,
temperature/leakage sensors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 108-113, Newport Beach, CA, August 9-11 2004.
- [2178]
- R. Kay and L. T. Pileggi.
PRIMO: Probability interpretation of moments for delay calculation.
In IEEE/ACM 35th Design Automation Conference, pages 463-468, San
Francisco, CA, June 15-19 1998.
- [2179]
- R. Kay and R. A. Rutenbar.
Wire packing - A strong formulation of crosstalk-aware chip-level track/layer
assignment with an efficient integer programming solution.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(5):672-679, May 2001.
- [2180]
- M. K. Kazimierczuk, V. G. Krizhanovski, J. V. Rassokhina, and
D. V. Chernov.
Injection-locked class-E oscillator.
IEEE Transactions on Circuits and Systems, 53(6):1214-1222, June
2006.
- [2181]
- J. Keane, H. Eom,
T.-H. Kim, S. Sapatnekar, and C. Kim.
Subthreshold logical effort: a systematic framework for optimal subthreshold
device sizing.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
425-428, San Francisco, CA, July 24-28 2006.
- [2182]
- J. Keane, T.-H.
Kim, and C. H. Kim.
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 189-194, Portland, Oregon, August 27-29 2007.
- [2183]
- I. Keller,
K. Tseng, and N. Verghese.
A robust cell-level crosstalk delay change analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 147-154, San Jose, CA, November 7-11 2004.
- [2184]
- I. Keller, K.-H.
Tam, and V. Kariat.
Challenges in gate level modeling for delay and SI at 65nm and below.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
468-473, Anaheim, CA, June 8-13 2008.
- [2185]
- S. Keller, D. M.
Harris, and A. J. Martin.
A compact transregional model for digital CMOS circuits operating near
threshold.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(10):2041-2053, October 2014.
- [2186]
- E. Kellerman.
A formula for logical network cost.
IEEE Transactions on Computers, C-17(9):881-884, September 1968.
- [2187]
- J. G. Kemeny and J. L.
Snell.
Finite Markov Chains.
Van Nostrand, Princeton, NJ, 1960.
- [2188]
- B. Keng,
S. Safarpour, and A. Veneris.
Bounded model debugging.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1790-1803, November 2010.
- [2189]
- M. P. Kennedy.
Three steps to chaos - part I: Evolution.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 40(10):640-656, October 1993.
- [2190]
- M. P. Kennedy.
Three steps to chaos - part II: A chua's circuit primer.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 40(10):657-674, October 1993.
- [2191]
- M.-D. Ker, S.-L. Chen,
and C.-S. Tsai.
Overview and design of mixed voltage i/o buffers with low-voltage thin-oxide
CMOS transistors.
IEEE Transactions on Circuits and Systems, 53(9):1934-1945, September
2006.
- [2192]
- O. Keren and R. S.
Stankovic.
Determining the number of paths in decision diagrams by using autocorrelation
coefficients.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(1):31-44, January 2011.
- [2193]
- K. J. Kerns and A. T. Yang.
Preservation of passivity during RLC network reduction via split congruence
transformations.
In 34th Design Automation Conference, pages 34-39, Anaheim, CA, June
9-13 1997.
- [2194]
- J. Keshava,
N. Hakim, and C. Prudvi.
Post-silicon validation challenges: how EDA and academia can help.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages 3-7,
Anaheim, CA, June 13-18 2010.
- [2195]
- A. Keshavarzi, K. Roy, and C. F. Hawkins.
Intrinsic leakage in deep submicron CMOS ics - measurement-based test
solutions.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(6):717-723, December 2000.
- [2196]
- A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry,
T. Ghani, S. Borkar, and V. De.
Effectiveness of referse body bias for leakage control in scaled dual vt CMOS
ics.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 207-212, Huntington Beach, California, August 6-7
2001.
- [2197]
- A. Keshavarzi, G. Schrom, S. Tang, S. Ma, K. Bowman, S. Tyagi,
K. Zhang, T. Linton, N. Hakim, S. Duvall, J. Brews, and V. De.
Measurements and modeling of intrinsic fluctuations in MOSFET threshold
voltage.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 26-29, San Diego, CA, August 8-10 2005.
- [2198]
- M. Ketkar,
K. Kasamsetty, and S. Sapatnekar.
Convex delay models for transistor sizing.
In Design Automation Conference, pages 655-660, Los Angeles, CA, June
5-9 2000.
- [2199]
- M. Ketkar and
E. Chiprout.
A microarchitecture-based framework for pre- and post-silicon power delivery
analysis.
In IEEE/ACM International Symposium on Microarchitecture (MICRO-42),
New York, NY, December 12-16 2009.
- [2200]
- M. Ketkar and S. S.
Sapatnekar.
Standby power optimization via transistor sizing and dual threshold voltage
assignment.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 375-378, San Jose, CA, November 10-14 2002.
- [2201]
- H. Kettani and B. R.
Barmish.
A new monte carlo circuit simulation paradigm with specific results for
resistive networks.
IEEE Transactions on Circuits and Systems, 53(6):1289-1299, June
2006.
- [2202]
- K.-M. Keung,
V. Manne, and A. Tyagi.
A novel charge recycling design scheme based on adiabatic charge pump.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(7):733-745, July 2007.
- [2203]
- K. Keutzer,
S. Malik, A. R. Newton, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli.
System-level design: Orthogonalization of concerns and platform-based design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1523-1543, December 2000.
- [2204]
- K. Keutzer and
D. Sylvester.
Chip-level assembly (and not the integration of synthesis and physical) is the
key to DSM design.
In ACM/IEEE 1999 International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU-99), pages 23-24,
Monterey, CA, March 8-9 1999.
- [2205]
- K. Keutzer.
Three competing design methodologies for asics: architectural synthesis, logic
synthesis and module generation.
In 26th ACM/IEEE Design Automation Conference, pages 308-313, June
25-29 1989.
- [2206]
- B. Khailany,
E. Krimer, R. Venkatesan, J. Clemons, J. S. Emer, M. Fojtik, A. Klinefelter,
M. Pellauer, N. Pinckney, Y.-S. Shao, S. Srinath, C. Torng, S.-L. Xi,
Y. Zhang, and B. Zimmer.
Invited: a modular digital VLSI flow for high-productivity soc design.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [2207]
- D. Khalil,
M. Khellah, N.-S. Kim, Y. I. Ismail, T. Karnik, and V. K. De.
Accurate estimation of SRAM dynamic stability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(12):1639-1647, December 2008.
- [2208]
- D. Khalil,
D. Sinha, H. Zhou, and Y. I. Ismail.
A timing-dependent power estimation framework considering coupling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(6):843-847, June 2009.
- [2209]
- M. U. K. Khan,
M. Shafique, and J. Henkel.
Hierarchical power budgeting for dark silicon chips.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 213-218, Rome, Italy, July 22-24 2015.
- [2210]
- V. Khandelwal, A. Davoodi, and A. Srivastava.
Efficient statistical timing analysis through error budgeting.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 473-477, San Jose, CA, November 7-11 2004.
- [2211]
- V. Khandelwal, A. Davoodi, and A. Srivastava.
Simultaneous vt selection and assignment for leakage optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):762-765, June 2005.
- [2212]
- S. Khandelwal, H. Agarwal, J. P. Duarte, K. Chan, S. Dey, Y. S.
Chauhan, and C. Hu.
Modeling STI edge parasitic current for accurate circuit simulations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(8):1291-1294, August 2015.
- [2213]
- V. Khandelwal and A. Srivastava.
Active mode leakage reduction using fine-grained forward body biasing strategy.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 150-155, Newport Beach, CA, August 9-11 2004.
- [2214]
- V. Khandelwal and A. Srivastava.
Leakage control through fine-grained placement and sizing of sleep transistors.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 533-536, San Jose, CA, November 7-11 2004.
- [2215]
- V. Khandelwal and A. Srivastava.
A general framework for accurate statistical timing analysis considering
correlations.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 89-94,
Anaheim, CA, June 13-17 2005.
- [2216]
- V. Khandelwal and A. Srivastava.
Leakage control through fine-grained placement and sizing of sleep transistors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(7):1246-1255, July 2007.
- [2217]
- V. Khandelwal and A. Srivastava.
Monte-carlo driven stochastic optimization framework for handling fabrication
variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 105-110, San Jose, CA, November 5-8 2007.
- [2218]
- V. Khandelwal and A. Srivastava.
A quadratic modeling-based framework for accurate statistical timing analysis
considering correlations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(2):206-215, February 2007.
- [2219]
- A. B. Khang and S. Muddu.
An analytical delay model for RLC interconnects.
IEEE Transactions on Computer-Aided Design of Circuits and Systems,
16(12):1507-1514, December 1997.
- [2220]
- S. Khanna,
C. Lursinsap, A. Pitaksanonkul, and V. Techangam.
Analytical models for sizing of VLSI power/ground nets under
electromigration, inductive, and resistive constraints.
In 1991 IEEE International Symposium on Circuits and Systems, pages
2272-2275, June 1991.
- [2221]
- S. P. Khatri,
A. Mehrotra, R. K. Brayton, A. Sangiovanni-Vincentelli, and R. H. J. M.
Otten.
A novel VLSI layout fabric for deep sub-micron applications.
In Design Automation Conference, pages 491-496, New Orleans, LA, June
21-25 1999.
- [2222]
- S. P. Khatri,
R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
Cross-talk immune VLSI design using a network of plas embedded in a regular
layout fabric.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 412-418, San Jose, CA, November 5-9 2000.
- [2223]
- H. Khdr, H. Amrouch,
and J. Henkel.
Aging-constrained performance optimization for multi cores.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [2224]
- V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani, Y. Takegawa,
A. J. Strojwas, and L. Pileggi.
Design methodology for IC manufacturability based on regular logic-bricks.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
353-358, Anaheim, CA, June 13-17 2005.
- [2225]
- G. Khodabandehloo, M. Mirhassani, and M. Almadi.
Analog implementation of a novel resistive-type sigmoidal neuron.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(4):750-754, April 2012.
- [2226]
- K. S. Khouri,
G. Lakshminarayana, and N. K. Jha.
Fast high-level estimation for control-flow intensive designs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 299-304, Monterey, CA, August 10-12 1998.
- [2227]
- K. S. Khouri,
G. Lakshminarayana, and N. K. Jha.
High-level synthesis of low-power control-flow intensive circuits.
IEEE Transactions on Computer-Aided Design, 18(12):1715-1729,
December 1999.
- [2228]
- K. S. Khouri and N. K.
Jha.
Leakage power analysis and reduction during behavioral synthesis.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):876-885, December 2002.
- [2229]
- R. A. Kiehl.
Information processing in nanoscale arrays: DNA assembly, molecular devices,
nano-array architectures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 828-829, San Jose, CA, November 5-9 2006.
- [2230]
- J. Kil, J. Gu, and
C.-H. Kim.
A high-speed variation-tolerant interconnectd technique for sub-threshold
circuits using capacitive boosting.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 67-72, Tegernsee, Germany, October 4-6 2006.
- [2231]
- D. Kilinc and A. Demir.
Simulation of noise in neurons and neuronal circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 589-596, Austin, TX, November 2-6 2015.
- [2232]
- K. Killpack, C. Kashyap, and E. Chiprout.
Silicon speedpath measurement and feedback into EDA flows.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
390-395, San Diego, CA, June 4-8 2007.
- [2233]
- K. Killpack.
A fast tolerance-based incremental timing analysis algorithm.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 137-142, Austin,
Texas, February 26-27 2007.
- [2234]
- Y. H. Kim, S. H.
Hwang, and A. R. Newton.
Electrical-logic simulation and its applications.
IEEE Transactions on Computer-Aided Design, 8(1):8-22, January
1989.
- [2235]
- S-Y Kim, N. Gopal, and
L. T. Pillage.
AWE macromodels of VLSI interconnect for circuit simulation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
64-70, Santa Clara, CA, November 8-12 1992.
- [2236]
- S-Y Kim, N. Gopal, and
L. T. Pillage.
Time-domain macromodels for VLSI interconnect analysis.
IEEE Transactions on Computer-Aided Design, 13(10):1257-1270, October
1994.
- [2237]
- K.-W. Kim, C. L. Liu,
and S.-M. Kang.
Implication graph based domino logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
111-114, San Jose, CA, November 7-11 1999.
- [2238]
- K.-W. Kim, K.-H. Baek,
N. Shanbhag, C.-L. Liu, and S.-M. Kang.
Coupling-driven signal encoding scheme for low-power interface design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 318-321, San Jose, CA, November 5-9 2000.
- [2239]
- K.-W. Kim, S.-O.
Jung, P. Saxena, C. L. Liu, and S.-M. Kang.
Coupling delay optimization by temporal decorrelation using dual threshold
voltage technique.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
732-737, Las Vegas, NV, June 18-22 2001.
- [2240]
- S. Kim, C. H.
Ziesler, and M. C. Papaefthymiou.
A true single-phase 8-bit adiabatic multiplier.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
758-763, Las Vegas, NV, June 18-22 2001.
- [2241]
- T. Kim, K.-S. Chung,
and C. L. Liu.
A static estimation technique of power sensitivity in logic circuits.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
215-219, Las Vegas, NV, June 18-22 2001.
- [2242]
- J. Kim, C. H. Ziesler,
and M. C. Papaefthymiou.
Energy recovering static memory.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 92-97, Monterey, California, August 12-14 2002.
- [2243]
- C. Kim, K.-W. Kim,
and S.-M. (Steve) Kang.
Energy-efficient skewed static logic with dual vt: design and synthesis.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
11(1):64-70, February 2003.
- [2244]
- C. H. Kim, J.-J.
Kim, S. Mukhopadhyay, and K. Roy.
A forward body-biased low-leakage SRAM cache: device and architecture
considerations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 6-9, Seoul, Korea, August 25-27 2003.
- [2245]
- C. H. Kim, K. Roy,
S. Hsu, A. Alvandpour, R. K. Krishnamurthy, and S. Borkar.
A process variation compensating technique for sub-90nm dynamic circuits.
In VLSI Symposium, Japan, June 2003.
- [2246]
- C. H.-I. Kim,
H. Soeleman, and K. Roy.
Ultra-low-power DLMS adaptive filter for hearing aid applications.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(6):1058-1067, December 2003.
- [2247]
- H.-S. Kim,
N. Vijaykrishnan, M. Kandemir, E. Brockmeyer, F. Catthoor, and M. J. Irwin.
Estimating influence of data layout optimizations on SDRAM energy
consumption.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 40-43, Seoul, Korea, August 25-27 2003.
- [2248]
- K. Kim, R. V. Joshi,
and C.-T. Chuang.
Strained-si devices and circuits for low-power applications.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 180-183, Seoul, Korea, August 25-27 2003.
- [2249]
- N. S. Kim,
D. Blaauw, and T. Mudge.
Leakage power optimization techniques for ultra deep sub-micron multi-level
caches.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 627-632, San Jose, CA, November 9-13 2003.
- [2250]
- S. Kim, S. V.
Kosonocky, and D. R. Knebel.
Understanding and minimizing ground bounce during mode transition of power
gating structures.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 22-25, Seoul, Korea, August 25-27 2003.
- [2251]
- N.-S. Kim,
K. Flautner, D. Blaauw, and T. Mudge.
Circuit and microarchitectural techniques for reducing cache leakage power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(2):167-184, February 2004.
- [2252]
- N.-S. Kim,
K. Flautner, D. Blaauw, and T. Mudge.
Single-VDD and single-VT super-drowsy techniques for low-leakage
high-performance instruction caches.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 54-57, Newport Beach, CA, August 9-11 2004.
- [2253]
- N.-S. Kim, T. Kgil,
V. Bertacco, T. Austin, and T. Mudge.
Microarchitectural power modeling techniques for deep sub-micron
microprocessors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 212-217, Newport Beach, CA, August 9-11 2004.
- [2254]
- S. Kim, S. V.
Kosonocky, D. R. Knebel, and K. Stawizsa.
Experimental measurement of a novel power gating structure with intermediate
power saving mode.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 20-25, Newport Beach, CA, August 9-11 2004.
- [2255]
- T. Kim, X. Li, and
D. J. Allstot.
Compact model generation for on-chip transmission lines.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(3):459-470, March 2004.
- [2256]
- C.-H. Kim, K. Roy,
S. Hsu, R. K. Krishnamurthy, and S. Borkar.
An on-die CMOS leakage current sensor for measuring process variation in
sub-90nm generations.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 221-222, Austin, TX, May 9 - 11 2005.
- [2257]
- C. H.-I. Kim, J.-J.
Kim, S. Mukhopadhyay, and K. Roy.
A forward body-biased low-leakage SRAM cache: device, circuit and
architecture considerations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):349-357, March 2005.
- [2258]
- K.-O. Kim, M.-J.
Zuo, and W. Kuo.
On the relationship of semiconductor yield and reliability.
IEEE Transactions on Semiconductor Manufacturing, 18(3):422-429,
August 2005.
- [2259]
- N.-S. Kim,
D. Blaauw, and T. Mudge.
Quantitative analysis and optimization techniques for on-chip cache leakage
power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(10):1147-1156, October 2005.
- [2260]
- N.-S. Kim, T. Kgil,
K. Bowman, V. De, and T. Mudge.
Total power-optimal pipelining and parallel processing under process variations
in nanometer technology.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 535-540, San Jose, CA, November 6-10 2005.
- [2261]
- C.-H. Kim, K. Roy,
S. Hsu, R. Krishnamurthy, and S. Borkar.
A process variation compensating technique with an on-die leakage current
sensor for nanometer scale dynamic circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(6):646-649, June 2006.
- [2262]
- T.-H. Kim, H. Eom,
J. Keane, and C. Kim.
Utilizing reverse short channel effect for optimal subthreshold circuit design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 127-130, Tegernsee, Germany, October 4-6 2006.
- [2263]
- J. Kim, K. D. Jones,
and M. A. Horowitz.
Fast, non-monte-carlo estimation of transient performance variation due to
device mismatch.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
440-443, San Diego, CA, June 4-8 2007.
- [2264]
- J. Kim, K. D. Jones,
and M. A. Horowitz.
Variable domain transformation for linear PAC analysis of mixed-signal
systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 887-894, San Jose, CA, November 5-8 2007.
- [2265]
- K. Kim, H. Mahmoodi,
and K. Roy.
A low-power SRAM using bit-line charge-recycling technique.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 177-182, Portland, Oregon, August 27-29 2007.
- [2266]
- J. Kim, J. Ren, and
M. A. Horowitz.
Stochastic steady-state and AC analyses of mixed-signal systems.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
376-381, San Francisco, CA, July 26-31 2009.
- [2267]
- J. Kim, K. D. Jones,
and M. A. Horowitz.
Fast, non-monte-carlo estimation of transient performance variaton due to
device mismatch.
IEEE Transactions on Circuits and Systems, 57(7):1746-1755, July
2010.
- [2268]
- J. Kim,
L. Vandenberghe, and C.-K. K. Yang.
Convex piecewise-linear modeling method for circuit optimization via geometric
programming.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1823-1827, November 2010.
- [2269]
- W. Kim, K. T. Do, and
Y. H. Kim.
Statistical leakage estimation based on sequential addition of cell leakage
currents.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(4):602-615, April 2010.
- [2270]
- D. Kim, H. Kim, and
Y. Eo.
Analytical eye-diagram determination for the efficient and accurate signal
integrity verification of single interconnect lines.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(10):1536-1545, October 2012.
- [2271]
- H. Kim, M. P. Sah,
C. Yang, S. Cho, and L.-0. Chua.
Memristor emulator for memristor circuit applications.
IEEE Transactions on Circuits and Systems, 59(10):2422-2431, October
2012.
- [2272]
- J. Kim, P. M.
Solomon, and S. Tiwari.
Adaptive circuit design using independently biased back-gated double-gate
MOSFETS.
IEEE Transactions on Circuits and Systems, 59(4):806-819, April
2012.
- [2273]
- D. Kim,
M. Ciesielski, and S. Yang.
MULTES: multilevel temporal-parallel event-driven simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):845-857, June 2013.
- [2274]
- Y. Kim, D. Shin,
M. Petricca, S. Park, M. Poncino, and N. Chang.
Computer-aided design of electrical energy systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 194-201, San Jose, CA, November 18-21 2013.
- [2275]
- T. Kim, B. Zheng,
H.-B. Chen, Q. Zhu, V. Sukharev, and S.-X.-D. Tan.
Lifetime optimization for real-time embedded systems considering
electromigration effects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 434-439, San Jose, CA, November 2-6 2014.
- [2276]
- J.-H. Kim, W. Kim, and
Y.-H. Kim.
Efficient statistical timing analysis using deterministic cell delay models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(11):2709-2713, November 2015.
- [2277]
- T. Kim, Z. Sun,
C. Cook, J. Gaddipati, H. Wang, H. Chen, and S.-X.-D. Tan.
Dynamic reliability management for near-threshold dark silicon processors.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [2278]
- Y. Kim, P. Mercati,
A. More, E. Shriver, and T. Rosing.
P4: phase-based power/performance prediction of heterogeneous systems via
neural networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 683-690, Irvine CA, November 13-16 2017.
- [2279]
- V. Kim and P. Banerjee.
Parallel algorithms for power estimation.
In IEEE/ACM 35th Design Automation Conference, pages 672-677, San
Francisco, CA, June 15-19 1998.
- [2280]
- D. Kim and K. Choi.
Power-conscious high level synthesis using loop folding.
In 34th Design Automation Conference, pages 441-445, Anaheim, CA,
June 9-13 1997.
- [2281]
- J. Kim and D. H. C. Du.
Performance optimization by gate sizing and path sensitization.
IEEE Transactions on Computer-Aided Design, 17(5):459-462, May
1998.
- [2282]
- K. Kim and G. Jeong.
Memory technologies in the nano-era : challenges and opportunities.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 63-67, Austin, TX, May 9 - 11 2005.
- [2283]
- T. Kim and W. Kuo.
Modeling manufacturing yield and reliability.
IEEE Transactions on Semiconductor Manufacturing, 12(4):485-492,
November 1999.
- [2284]
- N. S. Kim and T. Mudge.
The microarchitecture of a low power register file.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 384-389, Seoul, Korea, August 25-27 2003.
- [2285]
- C. H. Kim and K. Roy.
Dynamic vt SRAM: A leakage tolerant cache memory for low voltage
microprocessors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 251-254, Monterey, California, August 12-14 2002.
- [2286]
- J.-J. Kim and K. Roy.
A leakage-tolerant low-swing circuit style in partially depleted
silicon-on-insulator CMOS technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(5):549-552, May 2006.
- [2287]
- H.-O. Kim and Y. Shin.
Physical design methodology of power gating circuits for standard-cell-based
design.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
109-112, San Francisco, CA, July 24-28 2006.
- [2288]
- J. Kim and Y. Shin.
Minimizing leakage power in sequential circuits by using mixed vt flip-flops.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 797-802, San Jose, CA, November 5-8 2007.
- [2289]
- S. Y. Kim and S. S. Wong.
Closed-form RC and RLC delay models considering input rise time.
IEEE Transactions on Circuits and Systems, 54(9):2001-2010, September
2007.
- [2290]
- M. Kimura,
S. Inoue, and T. Shimoda.
Table look-up model of thin-film transistors for circuit simulation using
spline interpolation with transformation by y=x+log(x).
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(9):1101-1104, September 2002.
- [2291]
- J. Kin, C. Lee, W. H.
Mangione-Smith, and M. Potkonjak.
Power efficient mediaprocessors: design space exploration.
In Design Automation Conference, pages 321-326, New Orleans, LA, June
21-25 1999.
- [2292]
- T. I.
Kirkpatrick and N. R. Clark.
PERT as an aid to logic design.
IBM Journal of Research and Development, 10(2):135-141, March
1966.
- [2293]
- D. A. Kirkpatrick and A. L. Sangiovanni-Vincentelli.
Digital sensitivity: predicting signal interaction using functional analysis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
536-541, San Jose, CA, November 10-14 1996.
- [2294]
- D. A. Kirkpatrick.
The deep sub-micron signal integrity challenge.
In 1999 International Symposium on Physical Design, pages 4-7,
Monterey, CA, April 12-14 1999.
- [2295]
- D. Kirovski,
Y.-Y. Hwang, M. Potkonjak, and J. Cong.
Protecting combinational logic synthesis solutions.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2687-2696, December 2006.
- [2296]
- C. M. Kirsch and
H. Payer.
Incorrect systems: it's not the problem, it's the solution.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
913-917, San Francisco, CA, June 3-7 2012.
- [2297]
- M. Kishor and
J. Pineda de Gyvez.
Threshold voltage and power-supply tolerance of CMOS logic design families.
In IEEE International Symposium on Defect and Fault Tolerance in VLSI
Systems, pages 329-357, Yamanashi, Japan, October 25-27 2000.
- [2298]
- G. Kissin.
Upper and lower bounds on switching energy in VLSI.
Journal of the Association for Computing Machinery, 38(1):222-254,
January 1991.
- [2299]
- N. Kitchen and
A. Kuehlmann.
Stimulus generation for constrained random simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 258-265, San Jose, CA, November 5-8 2007.
- [2300]
- J. Kitchin.
Statistical electromigration budgeting for reliable design and verification in
a 300-mhz microprocessor.
In 1995 Symposium on VLSI Circuits, pages 115-116, 1995.
- [2301]
- H. Klauk and
U. Zschieschang.
Manufacturing and characteristics of low-voltage organic thin-film transistors.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 493-495, San Jose, CA, November 7-11 2010.
- [2302]
- V. B.
Kleeberger, H. Graeb, and U. Schlichtmann.
Predicting future product performance: modeling and evaluation of standard
cells in finfet technologies.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2303]
- V. B.
Kleeberger, S. Rutkowski, and R. Coppens.
Design & verification of automotive soc firmware.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [2304]
- F. Klein,
G. Araujo, and R. Azevedo.
A multi-model power estimation engine for accuracy optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 280-285, Portland, Oregon, August 27-29 2007.
- [2305]
- F. Klein, R. Leao,
G. Araujo, L. Santos, and R. Azevedo.
A multi-model engine for high-level power estimation accuracy optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(5):600-673, May 2009.
- [2306]
- T. Klemas,
L. Daniel, and J. K. White.
Segregation by primary phase factors: a full-wave algorithm for model order
reduction.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
943-946, Anaheim, CA, June 13-17 2005.
- [2307]
- G.-A. Klutte,
P. C. Kiessler, and M. A. Wortman.
A critical look at the bathtub curve.
IEEE Transactions on Reliability, 52(1):125-129, March 2003.
- [2308]
- M. C. Knapp, P. J.
Kindlmann, and M. C. Papaefthymiou.
Implementing and evaluating adiabatic arithmetic units.
In IEEE 1996 Custom Integrated Circuits Conference, pages 115-118,
San Diego, CA, May 5-8 1996.
- [2309]
- D. W. Knapp.
Fasolt: A program for feedback-driven data-path optimization.
IEEE Transactions on Computer-Aided Design, 11(6):677-695, June
1992.
- [2310]
- J. Knechtel, I. L. Markov, and J. Lienig.
Assembling 2-D blocks into 3-D chips.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(2):228-241, February 2012.
- [2311]
- J. Knechtel, I. L. Markov, J. Lienig, and M. Thiele.
Multiobjective optimization of deadspace, a critical resource for 3d-IC
integration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 705-712, San Jose, CA, November 5-8 2012.
- [2312]
- L. Knockaert, G. Lippens, and D. De Zutter.
Reduced-order modeling via oblique projections on a bandlimited kautz basis.
IEEE Transactions on Circuits and Systems, 53(7):1544-1555, July
2006.
- [2313]
- L. Knockaert and
T. Dhaene.
Orthonormal bandlimited kautz sequences for global system modeling from
piecewise rational models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1377-1391, July 2006.
- [2314]
- D. E. Knuth.
The Art of Computer Programming. Volume I: Fundamental Algorithms,
volume I.
Addison-Wesley, Reading, MA, 1968.
- [2315]
- D. E. Knuth.
The Art of Computer Programming. Volume III: Sorting and Searching,
volume III.
Addison-Wesley, Reading, MA, 1973.
- [2316]
- U. Ko, P. T. Balsara,
and W. Lee.
Low-power design techniques for high-performance CMOS adders.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
3(2):327-333, June 1995.
- [2317]
- U. Ko, A. Hill, and
P. T. Balsara.
Design techniques for high-performance, energy efficient control logic.
In International Symposium on Low Power Electronics and Design, pages
97-100, Monterey, CA, August 12-14 1996.
- [2318]
- U. Ko, A. Pua, A. Hill,
and P. Srivastava.
Hybrid dual-threshold design techniques for high-performance processors with
low-power features.
In 1997 International Symposium on Low Power Electronics and Design,
pages 307-311, Monterey, CA, August 18-20 1997.
- [2319]
- U. Ko and T. Balsara.
Short-circuit driven gate sizing technique for reducing power dissipation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
3(3):450-455, September 1995.
- [2320]
- U. Ko and P. T. Balsara.
High-performance energy-efficient D-flip-flop circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(1):94-98, February 2000.
- [2321]
- N. Kobayashi and
S. Malik.
Delay abstraction in combinational logic circuits.
IEEE Transactions on Computer-Aided Design of Circuits and Systems,
16(10):1205-1212, October 1997.
- [2322]
- L. Kocarev,
J. Szczepanski, J. M. Amigo, and I. Tomovski.
Discrete chaos - I: theory.
IEEE Transactions on Circuits and Systems, 53(6):1300-1309, June
2006.
- [2323]
- M. Kocher and
G. Rappitsch.
Statistical methods for the determination of process corners.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 133-137, San Jose, CA, March 18-21 2002.
- [2324]
- C. Kodama,
H. Ichikawa, K. Nakayama, F. Nakajima, S. Nojima, T. Kotani, T. Thara, and
A. Takahashi.
Self-aligned double and quadruple pattering aware grid routing methods.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(5):753-765, May 2015.
- [2325]
- K. L.
Kodandapani and D. K. Pradhan.
Undetectability of bridging faults and validity of stuck at fault test sets.
IEEE Transactions on Computers, C-29(1):55-59, January 1980.
- [2326]
- Zvi Kohavi.
Switching and Finite Automata Theory.
McGraw-Hill Book Company, 1978.
- [2327]
- K. Kohno,
Y. Inouye, and M. Kawamoto.
A matrix pseudo-inversion lemma for positive semidefinite hermitian matrices
and its application to adaptive blind deconvolution of MIMO systems.
IEEE Transactions on Circuits and Systems, 55(2):412-423, February
2008.
- [2328]
- A. A. Kokrady and
C. P. Ravikumar.
Static verification of test vectors for IR drop failure.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 760-764, San Jose, CA, November 9-13 2003.
- [2329]
- J.-T. Kong, S. Z.
Hussain, and D. Overhauser.
Performance estimation of complex CMOS gates.
IEEE Transactions on Circuits and Systems I, 44(9):785-795, September
1997.
- [2330]
- J-T. Kong and
D. Overhauser.
Methods to improve digital MOS macromodel accuracy.
IEEE Transactions on Computer-Aided Design, 14(7):868-881, July
1995.
- [2331]
- J.-T. Kong.
CAD for nanometer silicon design challenges and success.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(11):1132-1147, November 2004.
- [2332]
- J.-E. Koo, K.-H. Lee,
Y.-H. Cheon, J.-H. Choi, M.-H. Yoo, and J.-T. Kong.
A variable reduction technique for the analysis of ultra large-scale power
distribution networks.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 137-142, San Jose, CA, March 22-24 2004.
- [2333]
- M. A.
Korhonen, P. Borgesen, D. D. Brown, and C.-Y. Li.
Microstructure based statistical model of electromigration damage in confined
line metallizations in the presence of thermally induced stresses.
Journal of Applied Physics, 74(8):4995-5004, October 15 1993.
- [2334]
- M. A.
Korhonen, P. Borgesen, K. N. Tu, and C.-Y. Li.
Stress evolution due to electromigration in confined metal lines.
Journal of Applied Physics, 73(8):3790-3799, April 15 1993.
- [2335]
- M. A.
Korhonen, T. M. Korhonen, D. D. Brown, and C.-Y. Li.
Simulation of electromigration damage in chip level interconnect lines: A
grain structure based statistical approach.
In IEEE 37th Annual International Reliability Physics Symposium, pages
227-232, San Diego, CA, March 23-25 1999.
- [2336]
- P. Korkmaz,
B. E. S. Akgul, and K. V. Palem.
Energy, performance, and probability tradeoffs for energy-efficient
probabilistic CMOS circuits.
IEEE Transactions on Circuits and Systems, 55(8):2249-2262, September
2008.
- [2337]
- A. Korobkov,
A. Agarwal, and S. Venkateswaran.
Efficient finfet device model implementation for SPICE simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(10):1696-1699, October 2015.
- [2338]
- A. Korshak and J.-C.
Lee.
An effective current source cell model for VDSM delay calculation.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 296-300, San Jose, CA, March 26-28 2001.
- [2339]
- A. Korshak.
Noise-rejection model based on charge-transfer equation for digital CMOS
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(10):1460-1465, October 2004.
- [2340]
- T. Korsmeyer, J. Zeng, and K. Greiner.
Design tools for biomems.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
622-627, San Diego, CA, June 7-11 2004.
- [2341]
- S. Kose, E. Salman,
and E. G. Friedman.
Shielding methodologies in the presence of power/ground noise.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(8):1458-1468, August 2011.
- [2342]
- S. Kose and E. G.
Friedman.
Fast algorithms for IR voltage drop analysis exploiting locality.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
996-1001, San Diego, CA, June 5-9 2011.
- [2343]
- S. Kose.
Thermal implications of on-chip voltage regulation: upcoming challenges and
possible solutions.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [2344]
- S. V.
Kosonocky, M. Immediato, P. Cottrell, T. Hook, R. Mann, and J. Brown.
Enhanced multi-threshold (MTCMOS) circuits using variable well bias.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 165-169, Huntington Beach, California, August 6-7
2001.
- [2345]
- D. Kouroussis, R. Ahmadi, and F. N. Najm.
Worst-case circuit delay taking into account power supply variations.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
652-657, San Diego, CA, June 7-11 2004.
- [2346]
- D. Kouroussis, R. Ahmadi, and F. N. Najm.
A worst-case circuit delay verification technique considering power grid
voltage variations.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 157-160, Montreal, Quebec, June 20-23 2004.
- [2347]
- D. Kouroussis, I. A. Ferzli, and F. N. Najm.
Incremental partitioning-based vectorless power grid verification.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 358-364, San Jose, CA, November 6-10 2005.
- [2348]
- D. Kouroussis, R. Ahmadi, and F. N. Najm.
Voltage-aware static timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2156-2169, October 2006.
- [2349]
- D. Kouroussis and
F. N. Najm.
A static pattern-independent technique for power grid voltage integrity
verification.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 99-104,
Anaheim, CA, June 2-6 2003.
- [2350]
- F. Koushanfar, P. Boufounos, and D. Shamsi.
Post-silicon timing characterization by compressed sensing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 185-189, San Jose, CA, November 10-13 2008.
- [2351]
- F. Koushanfar, A. Mirhoseini, G. Qu, and Z. Zhang.
DA systemization of knowledge: a catalog of prior forward-looking
initiatives.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 255-262, Austin, TX, November 2-6 2015.
- [2352]
- F. Koushanfar.
Hierarchical hybrid power supply networks.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
629-630, Anaheim, CA, June 13-18 2010.
- [2353]
- J. Kozhaya,
S. R. Nassif, and F. N. Najm.
I/O buffer placement methodology for asics.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 245-248, St. Julian, Malta, September 2-5 2001.
- [2354]
- J. N.
Kozhaya, S. R. Nassif, and F. N. Najm.
Multigrid-like technique for power grid analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 480-487, San Jose, CA, November 4-8 2001.
- [2355]
- J. N. Kozhaya,
S. R. Nassif, and F. N. Najm.
A multigrid-like technique for power grid analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(10):1148-1160, October 2002.
- [2356]
- J. Kozhaya,
P. Restle, and H. Qian.
Myth busters: microprocessor clocking is from mars, ASIC's clocking is from
venus.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 271-275, San Jose, CA, November 7-10 2011.
- [2357]
- J. N. Kozhaya and F. N.
Najm.
Accurate power estimation for large sequential circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
488-493, San Jose, CA, November 9-13 1997.
- [2358]
- J. N. Kozhaya and
F. N. Najm.
Power estimation for large sequential circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(2):400-407, April 2001.
- [2359]
- V. J.
Kozhikkottu, R. Venkatesan, A. Raghunathan, and S. Dey.
Emulation-based analysis of system-on-chip performance under variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(12):3401-3414, December 2016.
- [2360]
- A. Kozik.
Fully dynamic evaluation of sequence pair.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):894-904, June 2013.
- [2361]
- S. Koziol,
S. Brink, and J. Hasler.
A neuromorphic approach to path planning using a reconfigurable neuron array
IC.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(12):2724-2737, December 2014.
- [2362]
- B. Krauter and
D. Widiger.
Variable frequency crosstalk noise analysis: A methodology to guarantee
functionality from dc to fmax.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
665-668, New Orleans, LA, June 10-14 2002.
- [2363]
- J. L.
Krichmar, N. Dutt, J. M. Nageswaran, and M. Richert.
Neuromorphic modeling abstractions and simulation of large-scale cortical
networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 334-338, San Jose, CA, November 7-10 2011.
- [2364]
- H. Kriplani,
F. Najm, and I. Hajj.
Maximum current estimation in CMOS circuits.
In 29th ACM/IEEE Design Automation Conference, pages 2-7, Anaheim,
CA, June 8-12 1992.
- [2365]
- H. Kriplani,
F. Najm, and I. Hajj.
Improved delay and current models for estimating maximum currents in CMOS
VLSI circuits.
In IEEE International Symposium on Circuits and Systems, pages
435-438, London, England, June 1994.
- [2366]
- H. Kriplani,
F. N. Najm, and I. N. Hajj.
Pattern independent maximum current estimation in power and ground bus of
CMOS VLSI circuits: algorithms, signal correlations, and their
resolution.
IEEE Transactions on Computer-Aided Design, 14(8):998-1012, August
1995.
- [2367]
- S. Krishnamoorthy and A. Khouja.
Efficient power analysis of combinational circuits.
In IEEE 1996 Custom Integrated Circuits Conference, pages 393-396,
San Diego, CA, May 5-8 1996.
- [2368]
- B. Krishnamurthy and I. G. Tollis.
Improved techniques for estimating signal probabilities.
In IEEE International Test Conference, pages 244-251, Sept. 8-11
1986.
- [2369]
- B. Krishnamurthy and I. G. Tollis.
Improved techniques for estimating signal probabilities.
IEEE Transactions on Computers, 38(7):1041-1045, July 1989.
- [2370]
- S. Krishnan and
J. G. Fossum.
Grasping SOI floating-body effects.
IEEE Circuits and Devices Magazine, 14(4):32-37, July 1998.
- [2371]
- S. Krishnaswamy, S. M. Plaza, I. L. Markov, and J. P. Hayes.
Enhancing design robustness with reliability-aware resynthesis and logic
simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 149-154, San Jose, CA, November 5-8 2007.
- [2372]
- S. Krishnaswamy, I. L. Markov, and J. P. Hayes.
On the role of timing masking in reliable logic circuit design.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
924-949, Anaheim, CA, June 8-13 2008.
- [2373]
- T. H. Krodel.
Powerplay - fast dynamic power estimation based on logic simulation.
In IEEE International Conference on Computer Design, pages 96-100,
October 1991.
- [2374]
- D. Kroft.
All paths through a maze.
In Proceedings of the IEEE, pages 88-90, January 1967.
- [2375]
- S. J. Krolikoski.
Standardizing ASIC libraries in VHDL using VITAL: a tutorial.
In IEEE Custom Integrated Circuits Conference, pages 603-610, Santa
Clara, CA, May 1-4 1995.
- [2376]
- A. Krstic and K-T Cheng.
Vector generation for maximum instantaneous current through supply lines for
CMOS circuits.
In 34th Design Automation Conference, pages 383-388, Anaheim, CA,
June 9-13 1997.
- [2377]
- L. Kruse,
E. Schmidt, G. Jochens, and W. Nebel.
Lower and upper bounds on the switching activity in scheduled data flow graphs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 115-120, San Diego, CA, August 16-17 1999.
- [2378]
- L. Kruse,
E. Schmidt, G. Jochens, A. Stammermann, A. Schulz, E. Macii, and W. Nebel.
Estimation of lower and upper bounds on the power consumption from scheduled
data flow graphs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(1):3-14, February 2001.
- [2379]
- J. C. Ku and Y. I. Ismail.
Area optimization for leakage reduction and thermal stability in
nanometer-scale technologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):241-248, February 2008.
- [2380]
- K. Kucukcakar.
Analysis of emerging core-based design lifecycle.
In IEEE/ACM International Conference on Computer-Aided Design, pages
445-449, San Jose, CA, November 8-12 1998.
- [2381]
- P. Kudva,
A. Sullivan, and W. Dougherty.
Metrics for structural logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 551-556, San Jose, CA, November 10-14 2002.
- [2382]
- M. Kuhlmann and
S. S. Sapatnekar.
Exact and efficient crosstalk estimation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(7):858-866, July 2001.
- [2383]
- K. J. Kuhn.
CMOS scaling beyond 32nm: challenges and opportunities.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
310-313, San Francisco, CA, July 26-31 2009.
- [2384]
- Y. Kukimoto, W. Gosti, A. Saldanha, and R. K. Brayton.
Approximate timing analysis of combinational circuits under the xbd0 model.
In IEEE/ACM International Conference on Computer-Aided Design, pages
176-181, San Jose, CA, November 9-13 1997.
- [2385]
- Y. Kukimoto and
R. K. Brayton.
Exact required time analysis via false path detection.
In 34th Design Automation Conference, pages 220-225, Anaheim, CA,
June 9-13 1997.
- [2386]
- S. H.
Kulkarni, A. N. Srivastava, and D. Sylvester.
A new algorithm for improved VDD assignment in low power dual VDD systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 200-205, Newport Beach, CA, August 9-11 2004.
- [2387]
- S. H.
Kulkarni, D. Sylvester, and D. Blaauw.
A statistical framework for post-silicon tuning through body bias clustering.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 39-46, San Jose, CA, November 5-9 2006.
- [2388]
- S. H.
Kulkarni, D. M. Sylvester, and D. T. Blaauw.
Design-time optimization of post-silicon-tuned circuits using adaptive body
bias.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(3):481-494, March 2008.
- [2389]
- N. Kulkarni, N. Nukala, and S. Vrudhula.
Minimizing area and power of sequential CMOS circuits using threshold
decomposition.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 605-612, San Jose, CA, November 5-8 2012.
- [2390]
- N. Kulkarni,
J. Yang, J.-S. Seo, and S. Vrudhula.
Reducing power, leakage, and area of standard-cell asics using threshold logic
flip-flops.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(9):2873-2886, September 2016.
- [2391]
- M. Kulkarni and
T. Chen.
A sensitivity-based approach to analyzing signal delay uncertainty of coupled
interconnect.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(9):1336-1346, September 2005.
- [2392]
- J. P. Kulkarni and
K. Roy.
Ultralow-voltage process-variation-tolerant schmitt-trigger-based SRAM
design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):319-332, February 2012.
- [2393]
- S. H. Kulkarni
and D. Sylevster.
High performance level conversion for dual VDD design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(9):926-936, September 2004.
- [2394]
- P. Kulshreshtha, R. Palermo, M. Mortazavi, C. Bamji, and
H. Yalcin.
Transistor-level timing analysis using embedded simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 344-348, San Jose, CA, November 5-9 2000.
- [2395]
- T. Kumakura.
8k LCD : technologies and challenges toward the realization of SUPER
hi-VISION TV.
In 20th Asia and South Pacific Design Automation Conference, pages
680-683, Chiba/Tokyo, Japan, January 19-22 2015.
- [2396]
- S. V. Kumar, C.-H.
Kim, and S. S. Sapatnekar.
An analytical model for negative bias temperature instability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 493-496, San Jose, CA, November 5-9 2006.
- [2397]
- S. V. Kumar,
C.-H. Kim, and S. S. Sapatnekar.
NBTI-aware synthesis of digital circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
370-375, San Diego, CA, June 4-8 2007.
- [2398]
- S. V. Kumar,
C. V. Kashyap, and S. S. Sapatnekar.
A framework for block-based timing sensitivity analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 1-6, Monterey, CA,
February 25-26 2008.
- [2399]
- S. V. Kumar,
C. V. Kashyap, and S. S. Sapatnekar.
A framework for block-based timing sensitivity analysis.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
688-693, Anaheim, CA, June 8-13 2008.
- [2400]
- S. V. Kumar,
C. H. Kim, and S. S. Sapatnekar.
Body bias voltage computations for process and temperature compensation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(3):249-262, March 2008.
- [2401]
- S. V. Kumar, C. H.
Kim, and S. S. Sapatnekar.
Adaptive techniques for overcoming performance degradation due to aging in
CMOS circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(4):603-614, April 2011.
- [2402]
- J. A. Kumar,
S. Vasudevan, and S. N. Ahmadyan.
Goal-oriented stimulus generation for analog circuits.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1018-1023, San Francisco, CA, June 3-7 2012.
- [2403]
- A. Kumar and M. Anis.
Dual-threshold CAD framework for subthreshold leakage power aware fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):53-66, January 2007.
- [2404]
- A. Kumar and M. Anis.
FPGA design for timing yield under process variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(3):423-435, March 2010.
- [2405]
- A. Kumar and M. Anis.
IR-drop management in fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(6):988-993, June 2010.
- [2406]
- S. K. Kumar and M. A.
Breuer.
Probabilistic aspects of boolean switching functions via a new transform.
Journal of the Association for Computing Machinery, 28(3):502-520,
July 1981.
- [2407]
- J. A. Kumar and
S. Vasudevan.
Formal probabilistic timing verification in RTL.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(5):788-801, May 2013.
- [2408]
- R. Kumar.
Interconnect and noise immunity design for the pentium 4 processor.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
938-943, Anaheim, CA, June 2-6 2003.
- [2409]
- B. Kumthekar, I.-H. Moon, and F. Somenzi.
A symbolic algorithm for low power sequential synthesis.
In 1997 International Symposium on Low Power Electronics and Design,
pages 56-61, Monterey, CA, August 18-20 1997.
- [2410]
- P. D.
Kundarewich and J. Rose.
Synthetic circuit generation using clustering and iteration.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):869-887, June 2004.
- [2411]
- K. Kundert,
H. Chang, D. Jeffereis, G. Lamant, E. Malavasi, and F. Sendig.
Design of mixed-signal systems-on-a-chip.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1561-1571, December 2000.
- [2412]
- K. Kundert and
H. Chang.
Model-based functional verification.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
421-424, Anaheim, CA, June 13-18 2010.
- [2413]
- K. Kundert.
Simulation methods for RF integrated circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
752-765, San Jose, CA, November 9-13 1997.
- [2414]
- S. Kundu, S. T.
Zachariah, Y.-S. Chang, and C. Tirumurti.
On modeling crosstalk faults.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(12):1909-1915, December 2005.
- [2415]
- S. Kundu,
M. Ganai, and R. Gupta.
Partial order reduction for scalable testing of systemc TLM designs.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
936-941, Anaheim, CA, June 8-13 2008.
- [2416]
- R. Kundu and
R. D. (Shawn) Blanton.
ATPG for noise-induced switch failures in domino logic.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 765-768, San Jose, CA, November 9-13 2003.
- [2417]
- S. Kundu.
Pitfalls of hierachical fault simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(2):312-314, February 2004.
- [2418]
- J. Kung, I. Han,
S. Sapatnekar, and Y. Shin.
Thermal signature: a simple yet accurate thermal index for floorplan
optimization.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
108-113, San Diego, CA, June 5-9 2011.
- [2419]
- D. S. Kung and R. Puri.
Optimal P/N width ratio selection for standard cell libraries.
In IEEE/ACM International Conference on Computer-Aided Design, pages
178-184, San Jose, CA, November 7-11 1999.
- [2420]
- D.-K. Kung.
Timing closure for low-fo4 microprocessor design.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
265-266, San Diego, CA, June 7-11 2004.
- [2421]
- W. Kunz, D. Stoffel,
and P. R. Menon.
Logic optimization and equivalence checking by implication analysis.
IEEE Transactions on Computer-Aided Design, 16(3):266-281, March
1997.
- [2422]
- C.-C. Kuo, Y.-L. Chen,
I-C. Tsai, L.-Y. Chan, and C. N.-J. Liu.
Behavior-level yield enhancement approach for large-scaled analog circuits.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
903-908, Anaheim, CA, June 13-18 2010.
- [2423]
- S.-H. Kuo and J. White.
A spectrally accurate integral equation solver for molecular surface
electrostatics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 899-906, San Jose, CA, November 5-9 2006.
- [2424]
- C.-C. Kuo and A. C.-H. Wu.
Delay budgeting for a timing-closure-driven design method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 202-207, San Jose, CA, November 5-9 2000.
- [2425]
- W. Kuo.
Reliability, yield and stress burn-in: a unified approach.
Kluwer Academic Publishers, Boston, MA, 1998.
- [2426]
- I. Kuon and J. Rose.
Measuring the gap between fpgas and asics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(2):203-215, February 2007.
- [2427]
- I. Kuon and J. Rose.
Exploring area and delay tradeoffs in fpgas with architecture and automated
transistor design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(1):71-84, January 2011.
- [2428]
- F. Kurdahi and A. C.
Parker.
Techniques for area estimation of VLSI layouts.
IEEE Transactions on Computer-Aided Design, 8(1):81-92, January
1989.
- [2429]
- M. Kurimoto,
H. Suzuki, R. Akiyama, T. Yamanaka, H. Ohkuma, H. Takata, and H. Shinohara.
Phase-adjustable error detection flip-flops with 2-stage hold driven
optimization and slack based grouping scheme for dynamic voltage scaling.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
884-889, Anaheim, CA, June 8-13 2008.
- [2430]
- T. Kuroda.
Optimization and control of vdd and vth for low-power, high-speed CMOS
design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 28-34, San Jose, CA, November 10-14 2002.
- [2431]
- R. P. Kurshan and
K. L. McMillan.
Analysis of digital circuits through symbolic reduction.
IEEE Transactions on Computer-Aided Design, 10(11):1356-1371,
November 1991.
- [2432]
- E. Kursun,
S. Ghiasi, and M. Sarrafzadeh.
Transistor level budgeting for power optimization.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 116-121, San Jose, CA, March 22-24 2004.
- [2433]
- V. Kursun,
S. G. Narendra, V. K. De, and E. G. Friedman.
High input voltage step-down DC-DC converters for integration in a low
voltage CMOS process.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 517-521, San Jose, CA, March 22-24 2004.
- [2434]
- V. Kursun and E. G.
Friedman.
Domino logic with variable threshold voltage keeper.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(6):1080-1093, December 2003.
- [2435]
- V. Kursun and E. G.
Friedman.
Node voltage dependent subthreshold leakage current characteristics of dynamic
circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 104-109, San Jose, CA, March 22-24 2004.
- [2436]
- V. Kursun and E. G.
Friedman.
Sleep switch dual threshold voltage domino logic with reduced standby leakage
current.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):485-496, May 2004.
- [2437]
- V. Kuruvilla, D. Sinha, J. Piaget, C. Visweswariah, and
N. Chandrachoodan.
Speeding up computation of the max/min of a set of gaussians for statistical
timing analysis and optimization.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2438]
- E. Kusse and J. Rabaey.
Low-energy embedded FPGA structures.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 155-160, Monterey, CA, August 10-12 1998.
- [2439]
- T. Kutzschebauch and L. Stok.
Regularity driven logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 439-446, San Jose, CA, November 5-9 2000.
- [2440]
- S. B. Kuusinen and
C. Hu.
Hot-carrier induced degradation of critical paths modeled by rule-based
analysis.
In IEEE Custom Integrated Circuits Conference, pages 69-72, Santa
Clara, CA, May 1-4 1995.
- [2441]
- M. Kvassay,
E. Zaitseva, V. Levashenko, and J. Kostolny.
Reliability analysis of multiple-outputs logic circuits based on structure
function approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(3):398-411, March 2017.
- [2442]
- H. H. Kwak, I.-H.
Moon, J. H. Kukula, and T. R. Shiple.
Combinational equivalence checking through function transformation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 526-533, San Jose, CA, November 10-14 2002.
- [2443]
- B. Kwak and E. S. Park.
An optimization-based error calculation for statistical power estimation of
CMOS logic circuits.
In IEEE/ACM 35th Design Automation Conference, pages 690-693, San
Francisco, CA, June 15-19 1998.
- [2444]
- K. Kwon, A. Amid,
A. Gholami, B. Wu, K. Asanovic, and K. Keutzer.
Invited: co-design of deep neural nets and neural net accelerators for embedded
vision applications.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [2445]
- W.-C. Kwon and T. Kim.
Optimal voltage allocation techniques for dynamically variable voltage
processors.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
125-130, Anaheim, CA, June 2-6 2003.
- [2446]
- J. Kwong and A. P.
Chandrakasan.
Variation-driven device sizing for minimum energy sub-threshold circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 8-13, Tegernsee, Germany, October 4-6 2006.
- [2447]
- E. D. Kyriakis-Bitzaros, S. Nikolaidis, and A. Tatsaki.
Accurate calculation of bit-level transition activity using word-level
statistics and entropy function.
In IEEE/ACM International Conference on Computer-Aided Design, pages
607-610, San Jose, CA, November 8-12 1998.
- [2448]
- C. Labrecque.
Near-term industrial perspective of analog CAD.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 456-457, San Jose, CA, November 5-9 2006.
- [2449]
- A. Labun.
Rapid method to account for process variation in full-chip capacitance
extraction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):941-951, June 2004.
- [2450]
- D. E. Lackey,
P. S. Zuchowski, and T. R. Bednar.
Managing power and performance for system-on-chip designs using voltage
islands.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 195-202, San Jose, CA, November 10-14 2002.
- [2451]
- V. Laddha and
M. Swaminathan.
Correlation of PDN impedance with jitter and voltage margin for high speed
channels.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 73-76, San Jose, CA, October 27-29 2008.
- [2452]
- S. Ladenheim, Y.-C. Chen, M. Mihajlovic, and V. Pavlidis.
IC thermal analyzer for versatile 3-D structures using multigrid
preconditioned krylov methods.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [2453]
- C. M. Lagoa,
F. Dabbene, and R. Tempo.
Hard bounds on the probability of performance with application to circuit
analysis.
IEEE Transactions on Circuits and Systems, 55(10):3178-3187, November
2008.
- [2454]
- K. Lahiri,
A. Raghunathan, and S. Dey.
Efficient power profiling for battery-driven embedded system design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):919-932, June 2004.
- [2455]
- S. Lai, B. Yan, and
P. Li.
Stability assurance and design optimization of large power delivery networks
with multiple on-chip voltage regulators.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 247-254, San Jose, CA, November 5-8 2012.
- [2456]
- S. Lai, B. Yan, and
P. Li.
Localized stability checking and design of IC power delivery with distributed
voltage regulators.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(9):1321-1334, September 2013.
- [2457]
- X. Lai and
J. Roychowdhury.
Automated oscillator macromodelling techniques for capturing amplitude
variations and injection locking.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 687-694, San Jose, CA, November 7-11 2004.
- [2458]
- L. Lai and N. Suda.
Enabling deep learning at the iot edge.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [2459]
- M. Lajolo,
A. Raghunathan, S. Dey, and L. Lavagno.
Cosimulation-based power estimation for system-on-chip design.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):253-266, June 2002.
- [2460]
- Z. Lak and N. Nicolici.
In-system and on-the-fly clock tuning mechanism to combat lifetime performance
degradation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 434-441, San Jose, CA, November 7-10 2011.
- [2461]
- G. Lakshminarayana, A. Raghunathan, K. S. Khouri, N. K. Jha, and
S. Dey.
Common-case computations: a high-level energy and performance-optimization
technique.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):33-49, January 2004.
- [2462]
- G. Lakshminarayana and N. K. Jha.
FACT: A framework for the application of throughput and power optimizing
transformations to control-flow intensive behavioral descriptions.
In IEEE/ACM 35th Design Automation Conference, pages 102-107, San
Francisco, CA, June 15-19 1998.
- [2463]
- G. Lakshminarayana and N. K. Jha.
FACT: A framework for applying throughput and power optimizing
transformations to control-flow-intensive behavioral descriptions.
IEEE Transactions on Computer-Aided Design, 18(11):1577-1594,
November 1999.
- [2464]
- M. Lal and R. Mitra.
Simplification of large system dynamics using a moment evaluation algorithm.
IEEE Transactions on Automatic Control, AC-19(10):602-603, October
1974.
- [2465]
- Parag K. Lala.
Fault Tolerant & Fault Testable Hardware Design.
Prentice/Hall International, Englewood Cliffs, NJ, 1985.
- [2466]
- S. N. Lalgudi,
M. Swaminathan, and Y. Kretchmer.
On-chip power-grid simulation using latency insertion method.
IEEE Transactions on Circuits and Systems, 55(3):914-931, April
2008.
- [2467]
- K. N. Lalgudi
and M. C. Papaefthymiou.
Fixed-phase retiming for low power design.
In International Symposium on Low Power Electronics and Design, pages
259-264, Monterey, CA, August 12-14 1996.
- [2468]
- P. Lall.
Temperature as an input to microelectronics-reliability models.
IEEE Transactions on Reliability, 45(1):3-9, March 1996.
- [2469]
- W. K. C. Lam, R. K.
Brayton, and A. L. Sangiovanni-Vincentelli.
Circuit delay models and their exact computation using timed boolean functions.
In 30th ACM/IEEE Design Automation Conference, pages 128-134, Dallas,
Texas, June 14-18 1993.
- [2470]
- W.-C. D. Lam, J. Jain,
C.-K. Koh, V. Balakrishnan, and Y. Chen.
Statistical based link insertion for robust clock network design.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 588-591, San Jose, CA, November 6-10 2005.
- [2471]
- J. Lamoureux, G. G. F. Lemieux, and S. J. E. Wilton.
Glithless: dynamic power minimization in the fpgas through edge alignment and
glitch filtering.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(11):1521-1534, November 2008.
- [2472]
- J. Lamoureux and
S. J. E. Wilton.
On the interaction between power-aware FPGA CAD algorithms.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 701-708, San Jose, CA, November 9-13 2003.
- [2473]
- P. E. Landman and
J. M. Rabaey.
Power estimation for high-level synthesis.
In European Design Automation Conference (EDAC), pages 361-366,
1993.
- [2474]
- P. E. Landman and
J. M. Rabaey.
Black-box capacitance models for architectural power analysis.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
165-170, Napa, CA, April 24-27 1994.
- [2475]
- P. E. Landman and
J. M. Rabaey.
Activity-sensitive architectural power analysis for the control path.
In ACM/IEEE International Symposium on Low Power Design, pages 93-98,
Dana Point, CA, April 23-26 1995.
- [2476]
- P. E. Landman and
J. M. Rabaey.
Architectural power analysis: the dual bit type method.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
3(2):173-187, June 1995.
- [2477]
- P. E. Landman and
J. M. Rabaey.
Activity-sensitive architectural power analysis.
IEEE Transactions on Computer-Aided Design, 15(6):571-587, June
1996.
- [2478]
- P. Landman.
High-level power estimation.
In International Symposium on Low Power Electronics and Design, pages
29-35, Monterey, CA, August 12-14 1996.
- [2479]
- A. Lange,
C. Sohrmann, R. Jancke, J. Haase, B. Cheng, A. Asenov, and U. Schlichtmann.
Multivariate modeling of variability supporting non-gaussian and correlected
parameters.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(2):197-210, February 2016.
- [2480]
- M. Y.
Lanzerotti, G. Fiorenza, and R. A. Rand.
Assessment of on-chip wire-length distribution models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1108-1112, October 2004.
- [2481]
- M. Y.
Lanzerotti, G. Fiorenza, and R. A. Rand.
Interpretation of rent's rule for ultralarge-scale integrated circuit designs,
with an application to wirelength distribution models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1330-1347, December 2004.
- [2482]
- T. Larrabee.
Efficient generation of test patterns using boolean difference.
In IEEE International Test Conference, pages 795-801, 1989.
- [2483]
- T. Larrabee.
A framework for evaluating test pattern generation strategies.
In IEEE International Conference on Computer Design, pages 44-47,
1989.
- [2484]
- T. Larrabee.
Test pattern generation using boolean satisfiability.
IEEE Transactions on Computer-Aided Design, 11(1):4-15, January
1992.
- [2485]
- B. Lasbouygues, S. Engels, R. Wilson, P. Maurine, N. Azemard,
and D. Auvergne.
Logical effort model extension to propagation delay representation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1677-1684, September 2006.
- [2486]
- B. Lasbouygues, R. Wilson, N. Azemard, and P. Maurine.
Temperature and voltage-aware timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):801-815, April 2007.
- [2487]
- B. Lasbouygues, R. Wilson, N. Azemard, and P. Maurine.
Temperature and voltage aware timing analysis: application to voltage drops.
Design, Automation and Test in Europe (DATE-07), pages 1012-1017,
April 16-20 2007.
- [2488]
- L. Latorre,
V. Beroulle, and P. Nouet.
Design of CMOS MEMS based on mechanical resonators using a RF simulation
approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):962-967, June 2004.
- [2489]
- R. Lauwereins.
Biomedical electronics serving as physical environmental and emotional
watchdogs.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages 1-5,
San Francisco, CA, June 3-7 2012.
- [2490]
- J. Lavaei,
A. Babakhani, A. Hajimiri, and J. C. Doyle.
Solving large-scale hybrid circuit-antenna problems.
IEEE Transactions on Circuits and Systems, 58(2):374-387, February
2011.
- [2491]
- L. Lavagno,
P. C. McGeer, A. Saldanha, and A. L. Sangiovanni-Vincentelli.
Timed shannon circuits: a power-efficient design style and synthesis tool.
In 32nd Design Automation Conference, pages 254-260, San Francisco,
CA, June 12-16 1995.
- [2492]
- L. Lavagno,
C. W. Moon, R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
An efficient heuristic procedure for solving the state assignment problem for
event-based specifications.
IEEE Transactions on Computer-Aided Design, 14(1):45-60, January
1995.
- [2493]
- M. Lavin and
L. Liebmann.
CAD computation for manufacturability: Can we save VLSI technology from
itself.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 424-431, San Jose, CA, November 10-14 2002.
- [2494]
- E. L. Lawler.
Combinatorial optimization: networks and matroids.
Holt, Rinehart and Winston, New York, NY, 1976.
- [2495]
- J. F. Lawless.
Statistical Models and Methods for Lifetime Data.
John Wiley & Sons, New York, NY, 1982.
- [2496]
- J. Le, X. Li, and L. T.
Pileggi.
STAC: statistical timing analysis with correlation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
343-348, San Diego, CA, June 7-11 2004.
- [2497]
- J. Le, C. Hanken,
M. Held, M. S. Hagedorn, K. Mayaram, and T. S. Fiez.
Experimental characterization and analysis of an asynchronous approach for
reduction of substrate noise in digital circuitry.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):344-356, February 2012.
- [2498]
- Y. Leblebici and
S. M. Kang.
An integrated hot-carrier degradation simulator for VLSI reliability
analysis.
In IEEE International Conference on Computer-Aided Design (ICCAD),
pages 400-403, Santa Clara, CA, Nov. 11-15 1990.
- [2499]
- Y. Leblebici and
S-M. Kang.
Modeling of nmos transistors for simulation of hot-carrier-induced device and
circuit degradation.
IEEE Transactions on Computer-Aided Design, 11(2):235-246, February
1992.
- [2500]
- R. J. Lechner.
Harmonic analysis of switching functions.
In A. Mukhopadhyay, editor, Recent Developments in Switching Theory,
pages 121-228. Academic Press, New York, NY, 1971.
- [2501]
- K-J Lee, R. Gupta, and
M. A. Breuer.
A new method for assigning signal flow directions to MOS transistors.
In IEEE International Conference on Computer-Aided Design (ICCAD),
pages 492-495, Santa Clara, CA, November 11-15 1990.
- [2502]
- K.-J. Lee, C.-N. Wang,
R. Gupta, and M. A. Breuer.
An integrated system for assigning signal flow directions to CMOS
transistors.
IEEE Transactions on Computer-Aided Design, 14(12):1445-1458,
December 1995.
- [2503]
- J.-F. Lee, D. L.
Ostapko, J. Soreff, and C. K. Wong.
On the signal bounding problem in timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 507-514, San Jose, CA, November 4-8 2001.
- [2504]
- D. Lee, W. Kwong,
D. Blaauw, and D. Sylvester.
Analysis and minimization techniques for total leakage considering gate oxide
leakage.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
175-180, Anaheim, CA, June 2-6 2003.
- [2505]
- D. Lee, W. Kwong,
D. Blaauw, and D. Sylvester.
Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in
nanometer CMOS design.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 287-292, San Jose, CA, March 24-26 2003.
- [2506]
- H. G. Lee, S. Nam,
and N. Chang.
Cycle-accurate energy measurment and high-level energy characterization of
fpgas.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 267-272, San Jose, CA, March 24-26 2003.
- [2507]
- J. Lee, K.-W. Kim,
Y. Huh, P. Bendix, and S.-M. Kang.
Chip-level charged-device modeling and simulation in CMOS integrated
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(1):67-81, January 2003.
- [2508]
- S. Lee, Y. Cheon,
and M. D. F. Wong.
A min-cost flow based detailed router for fpgas.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 388-393, San Jose, CA, November 9-13 2003.
- [2509]
- D. Lee, D. Blaauw,
and D. Sylvester.
Gate oxide leakage current analysis and reduction for VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(2):155-166, February 2004.
- [2510]
- D. Lee, V. Zolotov,
and D. Blaauw.
Static timing analysis using backward signal propagation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
664-669, San Diego, CA, June 7-11 2004.
- [2511]
- K. Lee, S.-J. Lee,
and H.-J. Yoo.
SILENT: serialized low energy transmission coding for on-chip interconnection
networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 448-451, San Jose, CA, November 7-11 2004.
- [2512]
- S. Lee, S. Das,
V. Bertacco, and T. Austin.
Circuit-aware architectural simulation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
305-310, San Diego, CA, June 7-11 2004.
- [2513]
- W.-H. Lee, S. Pant,
and D. Blaauw.
Analysis and reduction of on-chip inductance effects in power supply grids.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 131-136, San Jose, CA, March 22-24 2004.
- [2514]
- D. Lee, D. Blaauw,
and D. Sylvester.
Static leakage reduction through simultaneous vt/tox and state assignment.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):1014-1029, July 2005.
- [2515]
- D.-U. Lee, A. Abdul
Gaffar, O. Mencer, and W. Luk.
Minibit: bit-width optimization via affine arithmetic.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
837-840, Anaheim, CA, June 13-17 2005.
- [2516]
- K.-I. Lee, C. Lee,
H. Shin, Y.-J. Park, and H.-S. Min.
Efficient frequency-domain simulation technique for short-channel MOSFET.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(6):862-868, June 2005.
- [2517]
- Y.-M. Lee, Y. Cao,
T.-H. Chen, J.-M. Wang, and C. C.-P. Chen.
Hiprime: hierarchical and passivity preserved interconnect macromodeling engine
for RLKC power delivery.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(6):797-806, June 2005.
- [2518]
- B. N. Lee, L.-C.
Wang, and M. S. Abadir.
Refined statistical static timing analysis through learning spatial delay
correlations.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
149-154, San Francisco, CA, July 24-28 2006.
- [2519]
- D. Lee, D. Blaauw,
and D. Sylvester.
Runtime leakage minimization through probability-aware optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(10):1075-1088, October 2006.
- [2520]
- D.-U. Lee, A. A.
Guffar, R. C.-C. Cheung, O. Mencer, W. Luk, and G. A. Constantinides.
Accuracy-guaranteed bit-width optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):1990-2000, October 2006.
- [2521]
- Y. Lee, D.-K. Jeong,
and T. Kim.
Simultaneous control of power/ground current, wakeup time and transistor
overhead in power gated circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 169-172, San Jose, CA, November 10-13 2008.
- [2522]
- W.-P. Lee, H.-Y. Liu,
and Y.-W. Chang.
Voltage-island partitioning and floorplanning under timing constraints.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(5):690-702, May 2009.
- [2523]
- D.-J. Lee, M.-C.
Kim, and I. L. Markov.
Low-power clock trees for cpus.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 444-451, San Jose, CA, November 7-11 2010.
- [2524]
- H. Lee, S. Paik, and
Y. Shin.
Pulse width allocation and clock skew scheduling: optimizing sequential
circuits based on pulsed latches.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(3):355-366, March 2010.
- [2525]
- M.-S.-M. Lee, W.-T.
Liao, and C.-N.-J. Liu.
Levelized high-level current model of logic blocks for dynamic supply noise
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(6):845-857, June 2012.
- [2526]
- Y. Lee, D. Kim,
J. Cai, I. Lauer, L. Chang, S. J. Koester, D. Blaauw, and D. Sylvester.
Low-power circuit analysis and design based on heterojunction tunneling
transistors (hetts).
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(9):1632-1643, September 2013.
- [2527]
- Y.-J. Lee,
D. Limbrick, and S.-K. Lim.
Power benefit study for ultra-high density transistor-level monolithic 3d ics.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2528]
- D. Lee, T. Kim,
K. Han, Y. Hoskote, L. K. John, and A. Gerstlauer.
Learning-based power modeling of system-level black-box ips.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 847-853, Austin, TX, November 2-6 2015.
- [2529]
- W. Lee, Y. Wang, and
M. Pedram.
Optimizing a reconfigurable power distribution network in a multicore platform.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(7):1110-1123, July 2015.
- [2530]
- W. Lee, Y. Wang,
D. Shin, S. Nazarian, and M. Pedram.
Design and optimization of a reconfigurable power delivery network for
large-area, DVS-enabled oled displays.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 159-164, Rome, Italy, July 22-24 2015.
- [2531]
- H.-I. Lee, C.-Y. Han,
and J.-C.-M. Li.
A multicircuit simulator based on inverse jacobian matrix reuse.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(7):1130-1137, July 2016.
- [2532]
- H. Lee, M. Shafique,
and M. A. Al Faruque.
Low-overheaded aging-aware resource management on embedded gpus.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [2533]
- W.-K. Lee, R. Achar,
and M. S. Nakhla.
Dynamic GPU parallel sparse LU factorization for fast circuit simulation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
26(11):2518-2529, November 2018.
- [2534]
- D. Lee and D. Blaauw.
Static leakage reduction through simultaneouos threshold voltage and state
assignment.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
191-194, Anaheim, CA, June 2-6 2003.
- [2535]
- H.-C. Lee and Y.-W. Chang.
A chip-package-board co-design methodology.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1082-1087, San Francisco, CA, June 3-7 2012.
- [2536]
- H.-G. Lee and N. Chang.
Powering the iot: storage-less and converter-less energy harvesting.
In 20th Asia and South Pacific Design Automation Conference, pages
124-129, Chiba/Tokyo, Japan, January 19-22 2015.
- [2537]
- Y.-M. Lee and C. C.-P. Chen.
Power grid transient simulation in linear time based on
tranmission-line-modeling alternating-direction-implicit method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 75-80, San Jose, CA, November 4-8 2001.
- [2538]
- Y.-M. Lee and C. C.-P. Chen.
Power grid transient simulation in linear time based on
transmission-line-modeling alternating-direction-implicit method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(11):1343-1352, November 2002.
- [2539]
- Y.-M. Lee and C. C.-P. Chen.
A hierarchical analysis methodology for chip-level power delivery with
realizable model reduction.
In IEEE/ACM Asia and South Pacific Design Automation Conference
(ASP-DAC), pages 614-618, Kitakyushu, Japan, January 21-24 2003.
- [2540]
- Y.-M. Lee and C. C.-P. Chen.
The power grid transient simulation in linear time based on 3-D
alternating-direction-implicit method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(11):1545-1550, November 2003.
- [2541]
- Y.-M. Lee and C.-T. Ho.
Intrasim: incremental transient simulation of power grids.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(12):2052-2065, December 2017.
- [2542]
- C.-Y. Lee and N. K. Jha.
Fincanon: a PVT-aware integrated delay and power modeling framework of
finfet-based caches and on-chip networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1150-1163, May 2014.
- [2543]
- Y.-J. Lee and S. K. Lim.
Co-optimization and analysis of signal, power, and thermal interconnects in
3-D ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(11):1635-1648, November 2011.
- [2544]
- Y.-S. Lee and P. M. Maurer.
Bit-parallel multidelay simulation.
IEEE Transactions on Computer-Aided Design, 15(12):1547-1554,
December 1996.
- [2545]
- J. Y. Lee and R. A. Rohrer.
Awesymbolic: compiled analysis of linear(ized) circuits using asymptotic
waveform evaluation.
In 29th ACM/IEEE Design Automation Conference, pages 213-218,
Anaheim, CA, June 8-12 1992.
- [2546]
- S. Lee and T. Sakurai.
Run-time voltage hopping for low-power real-time systems.
In Design Automation Conference, pages 806-809, Los Angeles, CA, June
5-9 2000.
- [2547]
- E. A. Lee
and A. L. Sangiovanni-Vincentelli.
Comparing models of computation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
234-241, San Jose, CA, November 10-14 1996.
- [2548]
- J. Lee and
A. Shrivastava.
Static analysis of register file vulnerability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(4):607-616, April 2011.
- [2549]
- S.-H. Lee and
S. Vishwanath.
Boolean functions over nano-fabrics: improving resilience through coding.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(11):2054-2065, November 2012.
- [2550]
- L. Lee and L.-C. Wang.
On bounding the delay of a critical path.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 81-88, San Jose, CA, November 5-9 2006.
- [2551]
- H. B. Lee.
Matrix filtering as an aid to numerical integration.
In Proceedings of the IEEE, pages 1826-1831, November 1967.
- [2552]
- E. A. Lee.
CPS foundations.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
737-742, Anaheim, CA, June 13-18 2010.
- [2553]
- L. Leem, H. Cho,
H.-H. Lee, Y.-M. Kim, Y. Li, and S. Mitra1.
Cross-layer error resilience for robust systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 177-180, San Jose, CA, November 7-11 2010.
- [2554]
- D. M. W. Leenaerts.
Application of interval analysis for circuit design.
IEEE Transactions on Circuits and Systems, 37(6):803-807, June
1990.
- [2555]
- D. M. W. Leenaerts.
Low power RF IC design for wireless communication.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 428-433, Seoul, Korea, August 25-27 2003.
- [2556]
- S. Lefteriu and
A. C. Antoulas.
A new approach to modeling multiport systems from frequency-domain data.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(1):14-27, January 2010.
- [2557]
- S. Lefteriu and
J. Mohring.
Generating parametric models from tabulated data.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
679-682, Anaheim, CA, June 13-18 2010.
- [2558]
- E. Lehman,
Y. Watanabe, J. Grodstein, and H. Harkness.
Logic decomposition during technology mapping.
In IEEE/ACM International Conference on Computer-Aided Design, pages
264-271, San Jose, CA, November 5-9 1995.
- [2559]
- E. Lehman,
Y. Watanabe, J. Grodstein, and H. Harkness.
Logic decomposition during technology mapping.
IEEE Transactions on Computer-Aided Design, 16(8):813-834, August
1997.
- [2560]
- L. Lei, F. Xie, and
K. Cong.
Post-silicon conformance checking with virtual prototypes.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2561]
- L. Lei and T. Nakamura.
A fast algorithm for evaluating the matrix polynomial
I+A+...+a^lbraceN-1rbrace.
IEEE Transactions on Circuits and Systems, Vol. I, 39(4):299-300,
April 1992.
- [2562]
- C. E. Leiserson.
The cilk++ concurrency platform.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
522-527, San Francisco, CA, July 26-31 2009.
- [2563]
- H. Lekatsas,
J. Henkel, and W. Wolf.
Approximate arithmetic coding for bus transition reduction in low power
designs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):696-707, June 2005.
- [2564]
- T. Lengauer and
R. E. Tarjan.
A fast algorithm for finding dominators in a flowgraph.
ACM Transactions on Programming Languages and Systems, 1(1):121-141,
July 1979.
- [2565]
- T. Lengauer.
Combinatorial Algorithms for Integrated Circuit Layout.
John Wiley & Sons, New York, NY, 1990.
- [2566]
- C. K.
Lennard, P. Buch, and A. R. Newton.
Logic synthesis using power-sensitive don't care sets.
In International Symposium on Low Power Electronics and Design, pages
293-296, Monterey, CA, August 12-14 1996.
- [2567]
- C. K. Lennard and
A. R. Newton.
An estimation technique to guide low power resynthesis algorithms.
In ACM/IEEE International Symposium on Low Power Design, pages
227-232, Dana Point, CA, April 23-26 1995.
- [2568]
- C. K. Lennard and
A. R. Newton.
On estimation accuracy for guiding low-power resynthesis.
IEEE Transactions on Computer-Aided Design, 15(6):644-664, June
1996.
- [2569]
- K.-S. Leung.
SPIDER: simultaneous post-layout IR-drop and metal density enhancement wire
redundant fill.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 33-38, San Jose, CA, November 6-10 2005.
- [2570]
- I. Levi, A. Belenky,
and A. Fish.
Logical effort for CMOS-based dual model logic gates.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1042-1053, May 2014.
- [2571]
- S. P. Levitan,
J. A. Martinez, T. P. Kurzweg, A. J. Davare, M. Kahrs, M. Bails, and D. M.
Chiarulli.
System simulation of mixed-signal multi-domain microsystems with piecewise
linear models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(2):139-154, February 2003.
- [2572]
- S. P. Levitan and
D. M. Chiarulli.
Massively parallel processing: It's deja vu all over again.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
534-538, San Francisco, CA, July 26-31 2009.
- [2573]
- S. P. Levitan.
You can get there from here: connectivity of random graphs on grids.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
272-273, San Diego, CA, June 4-8 2007.
- [2574]
- H. Levy, W. Scott,
D. MacMillen, and J. White.
A rank-one update method for efficient processing of interconnect parasitics in
timing analysis.
In Design Automation Conference, pages 75-78, Los Angeles, CA, June
5-9 2000.
- [2575]
- R. Levy,
D. Blaauw, G. Braca, A. Dasgupta, A. Grinshpon, C. Oh, B. Orshav,
S. Sirichotiyakul, and V. Zolotov.
Clarinet: A noise analysis tool for deep submicron design.
In Design Automation Conference, pages 233-238, Los Angeles, CA, June
5-9 2000.
- [2576]
- F. L. Lewis,
L. Xie, and D. Popa.
Optimal and Robust Estimation: With an Introduction to Stochastic Control
Theory.
Taylor & Francis Group, Boca Raton, FL, 2nd edition, 2008.
- [2577]
- D. M. Lewis.
Device model approximation using 2^N trees.
IEEE Transactions on Computer-Aided Design, 9(1):30-38, January
1990.
- [2578]
- P-C. Li, G. I.
Stamoulis, and I. N. Hajj.
A probabilistic timing approach to hot-carrier effect estimation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
210-213, Santa Clara, CA, November 8-12 1992.
- [2579]
- T. Li, C-H Tsai, and
S-M Kang.
Efficient transient electrothermal simulation of CMOS VLSI circuits under
electrical overstress.
In IEEE/ACM International Conference on Computer-Aided Design, pages
6-11, San Jose, CA, November 8-12 1998.
- [2580]
- C.-S. Li, K. N.
Sivarajan, and D. G. Messerschmitt.
Statistical analysis of timing rules for high-speed synchronous VLSI systems.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(4):477-482, December 1999.
- [2581]
- W. Li, Q. Li, J. S.
Yuan, J. McConkey, Y. Chen, S. Chetlur, J. Zhou, and A. S. Oates.
Hot-carrier-induced circuit degradation for 0.18um CMOS technology.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 284-289, San Jose, CA, March 26-28 2001.
- [2582]
- X. Li, X. Zeng,
D. Zhou, and X. Ling.
Behavioral modeling of analog circuits by wavelet collocation method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 65-69, San Jose, CA, November 4-8 2001.
- [2583]
- X. Li, B. Hu, X. Ling,
and X. Zeng.
A wavelet-balance approach for steady-state analysis of nonlinear circuits.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(5):688-694, May 2002.
- [2584]
- L. Li, N. Vijaykrishnan,
M. Kandemir, and M. J. Irwin.
Adaptive error protection for energy efficiency.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 2-7, San Jose, CA, November 9-13 2003.
- [2585]
- F. Li, Y. Lin, and
L. He.
FPGA power reduction using configurable dual-vdd.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
735-740, San Diego, CA, June 7-11 2004.
- [2586]
- F. Li, Y. Lin, and
L. He.
Vdd programmability to reduce FPGA interconnect power.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 760-765, San Jose, CA, November 7-11 2004.
- [2587]
- F. Li, Y. Lin, L. He,
and J. Cong.
Low-power FPGA using pre-defined dual-vdd/dual-vt fabrics.
In ACM/SIGDA International Symposium on Field Programmable Gate
Arrays, pages 42-50, Monterey, CA, February 22-24 2004.
- [2588]
- H. Li, S. Bhunia,
Y. Chen, K. Roy, and T. N. Vijaykumar.
DCG: deterministic clock-gating for low-power microprocessor design.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(3):245-254, March 2004.
- [2589]
- P. Li, L. T. Pileggi,
M. Asheghi, and R. Chandra.
Efficient full-chip thermal modeling and analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 319-326, San Jose, CA, November 7-11 2004.
- [2590]
- X. Li,
P. Gopalakrishnan, Y. Xu, and L. T. Pileggi.
Robust analog/RF circuit design with projection-based posynomial modeling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 855-862, San Jose, CA, November 7-11 2004.
- [2591]
- X. Li, J. Le,
P. Gopalakrishnan, and L. T. Pileggi.
Asymptotic probability extraction for non-normal distributions of circuit
performance.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 2-9, San Jose, CA, November 7-11 2004.
- [2592]
- X. Li, Y. Xu, P. Li,
P. Gopalakrishnan, and L. T. Pileggi.
A frequency relaxation approach for analog/RF system-level simulation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
842-847, San Diego, CA, June 7-11 2004.
- [2593]
- B. Li, J. Gill, C. J.
Christiansen, T. D. Sullivan, and P. S. McLaughlin.
Impact of via-line contact on cu interconnect electromigration performance.
In IEEE International Reliability Physics Symposium, pages 24-30,
April 17-21 2005.
- [2594]
- F. Li, Y. Lin, L. He,
D. Chen, and J. Cong.
Power modeling and characteristics of field programmable gate arrays.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(11):1712-1724, November 2005.
- [2595]
- H. Li, C.-Y. Cher, and
T. N. Vijaykumar.
Combined circuit and architectural level variable supply-voltage scaling for
low power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(5):564-576, May 2005.
- [2596]
- H. Li, Z. Qi, S. X.-D.
Tan, L. Wu, Y. Cai, and X. Hong.
Partitioning-based approach to fast on-chip decap budgeting and minimization.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
170-175, Anaheim, CA, June 13-17 2005.
- [2597]
- X. Li, J. Le,
M. Celik, and L. T. Pileggi.
Defining statistical sensitivity for timing optimization of logic circuits with
large-scale process and environmental variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 844-851, San Jose, CA, November 6-10 2005.
- [2598]
- X. Li, J. Le, L. T.
Pileggi, and A. Strojwas.
Projection-based performance modeling for inter/intra-die variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 721-727, San Jose, CA, November 6-10 2005.
- [2599]
- X. Li, P. Li, and
L. T. Pileggi.
Parameterized interconnect order reduction with explicit-and-implicit
multi-parameter moment matching for inter/intra-die variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 806-812, San Jose, CA, November 6-10 2005.
- [2600]
- H. Li, J. Fan, Z. Qi,
S. X.-D. Tan, L. Wu, Y. Cai, and X. Hong.
Partitioning-based approach to fast on-chip decouping capacitor budgeting and
minimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2402-2412, November 2006.
- [2601]
- H. Li, W.-Y. Yin, and
J.-F. Mao.
Comments on "modeling of metallic carbon-nanotube interconnects for circuit
simulations and a comparison with cu interconnects for sealed technologies".
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):3042-3044, December 2006.
- [2602]
- H. Li, C. E. Zemke,
G. Manetas, V. I. Okhmatovski, E. Rosenbaum, and A. C. Cangellaris.
An automated and efficient substrate noise analysis tool.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(3):454-468, March 2006.
- [2603]
- P. Li, L. T. Pileggi,
M. Asheghi, and R. Chandra.
IC thermal simulation and modeling via efficient multigrid-based approaches.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1763-1776, September 2006.
- [2604]
- X. Li, J. Le, and
L. T. Pileggi.
Projection-based statistical analysis of full-chip leakage power with
non-log-normal distributions.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
103-108, San Francisco, CA, July 24-28 2006.
- [2605]
- F. Li, Y. Lin, and
L. He.
Field programmability of supply voltages for FPGA power reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):752-764, April 2007.
- [2606]
- X. Li,
P. Gopalakrishnan, Y. Xu, and L. T. Pileggi.
Robust analog/RF circuit design with projection-based performance modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):2-15, January 2007.
- [2607]
- X. Li, J. Le,
P. Gopalakrishnan, and L. T. Pileggi.
Asymptotic probability extraction for nonnormal performance distributions.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):16-37, January 2007.
- [2608]
- X. Li, B. Taylor,
Y.-T. Chien, and L. T. Pileggi.
Adaptive post-silicon tuning for analog circuits: concept, analysis and
optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 450-457, San Jose, CA, November 5-8 2007.
- [2609]
- Y.-T. Li, Z. Bai,
Y. Su, and X. Zeng.
Parameterized model order reduction via a two-directional arnoldi process.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 868-873, San Jose, CA, November 5-8 2007.
- [2610]
- T. Li, W. Zhang, and
Z. Yu.
Full-chip leakage analysis in nano-scale technologies: mechanisms, variation
sources, and verification.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
594-599, Anaheim, CA, June 8-13 2008.
- [2611]
- X. Li, J. Le,
M. Celik, and L. T. Pileggi.
Defining statistical timing sensitivity for logic circuits with large-scale
process and environmental variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(6):1041-1054, June 2008.
- [2612]
- X. Li, Y. Zhan, and
L. T. Pileggi.
Quadratic statistical MAX approximation for parametric yield estimation of
analog/RF integrated circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(5):831-843, May 2008.
- [2613]
- Y.-T. Li, Z. Bai,
Y. Su, and X. Zeng.
Model order reduction of parameterized interconnect networks via a
two-directional arnoldi process.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(9):1571-1582, September 2008.
- [2614]
- B. Li, N. Chen, and
U. Schlichtmann.
Timing model extraction for sequential circuits considering process variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 333-343, San Jose, CA, November 2-5 2009.
- [2615]
- K. S.-M. Li, C.-L. Lee,
C. Su, and J.-E. Chen.
A unified detection scheme for crosstalk effects in interconnection bus.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):306-311, February 2009.
- [2616]
- X. Li, R. R. Rutenbar,
and R. D. Blanton.
Virtual probe: a statistically optimal framework for minimum-cost silicon
characterization of nanoscale integrated circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 433-440, San Jose, CA, November 2-5 2009.
- [2617]
- B. Li, N. Chen, and
U. Schlichtmann.
Fast statistical timing analysis of latch-controlled circuits for arbitrary
clock periods.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 524-531, San Jose, CA, November 7-11 2010.
- [2618]
- X. Li, C. C. McAndrew,
W. Wu, S. Chaudhry, J. Victory, and G. Gildenblat.
Statistical modeling with the PSP MOSFET model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):599-606, April 2010.
- [2619]
- B. Li, N. Chen, and
U. Schlichtmann.
Fast statistical timing analysis for circuits with post-silicon tunable clock
buffers.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 111-117, San Jose, CA, November 7-10 2011.
- [2620]
- B. Li, P. S.
McLaughlin, J. P. Bickford, P. Habitz, D. Netrabile, and T. Sullivan.
Statistical evaluation of electromigration reliability at chip level.
IEEE Transactions on Device and Materials Reliability, 11(1):86-91,
March 2011.
- [2621]
- S. Li, K. Chen, J.-H.
Ahn, J. B. Brockman, and N. P. Jouppi.
CACTI-P: architecture-level modeling for SRAM-based structures with
advanced leakage reduction techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 694-701, San Jose, CA, November 7-10 2011.
- [2622]
- X.-C. Li, J.-F. Mao,
and M. Swaminathan.
Transient analysis of CMOS-gate-driven RLGC interconnects based on FDTD.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(4):574-583, April 2011.
- [2623]
- Y. Li, H. Schneider,
F. Schnabel, R. Thewes, and D. Schmitt-Landsiedel.
DRAM yield analysis and optimization by a statistical design approach.
IEEE Transactions on Circuits and Systems, 58(12):2906-2918, December
2011.
- [2624]
- Z. Li,
R. Balasubramanian, F. Liu, and S. Nassif.
2011 TAU power grid simulation contest: benchmark suite and results.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 478-481, San Jose, CA, November 7-10 2011.
- [2625]
- B. Li, N. Chen, and
U. Schlichtmann.
Statistical timing analysis for latch-controlled circuits with reduced
iterations and graph transformations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(11):1670-1683, November 2012.
- [2626]
- Z. Li, M. Mohamed,
X. Chen, E. Dudley, K. Meng, L. Shang, A. R. Mickelson, R. Joseph,
M. Vachharajani, B. Schwartz, and Y. Sun.
Reliability modeling and management of nanophotonic on-chip networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(1):98-111, January 2012.
- [2627]
- B. Li, N. Chen, Y. Xu,
and U. Schlichtmann.
On timing model extraction and hierarchical statistical timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(2):367-380, February 2013.
- [2628]
- Y. Li, P. Chow,
J. Jiang, M. Zhang, and S. Wei.
Software/handware parallel long-period random number generation framework based
on the WELL method.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1054-1059, May 2014.
- [2629]
- D.-A. Li,
M. Marek-Sadowska, and S. R. Nassif.
A method for improving power grid resilience to electromigration-caused via
failures.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(1):118-130, January 2015.
- [2630]
- D.-A. Li,
M. Marek-Sadowska, and S. R. Nassif.
T-VEMA: a temperature- and variation-aware electromigration power grid
analysis tool.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(10):2327-2331 K electromigration (EM), jL product, process variation,
thermal analysis, October 2015.
- [2631]
- X. Li, F. Yang, D. Wu,
Z. Zhou, and X. Zeng.
MOS table models for fast and accurate simulation of analog and mixed-signal
circuits using efficient oscillation-diminishing interpolations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(9):1481-1494, September 2015.
- [2632]
- S. Li, L. Liu, P. Gu,
C. Xu, and Y. Xie.
Nvsim-CAM: a circuit-level simulator for emerging nonvolatile memory based
content-addressable memory.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [2633]
- S. Li, Y. Wang,
W. Wen, Y. Wang, Y. Chen, and H. Li.
A data locality-aware design framework for reconfigurable sparse matrix-vector
multiplication kernel.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [2634]
- D. Li, K. Zhang,
A. Guliani, and S. Ogrenci-Memik.
Adaptive thermal management for 3d ics with stacked DRAM caches.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [2635]
- H. Li, X. Wang, J. Xu,
Z. Wang, R. K. V. Maeda, Z. Wang, P. Yang, L. H. K. Duong, and Z. Wang.
Energy-efficient power delivery system paradigms for many core processors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(3):449-462, March 2017.
- [2636]
- B. Li, A. Kim,
P. McLaughlin, B. Linder, and C. Christiansen.
Electromigration characteristics of power grid like structures.
In IEEE International Reliability Physics Symposium (IRPS), pages
4F.3.1-5, Burlingame, CA, March 11-15 2018.
- [2637]
- H. Li, Z. Tian,
R. K. V. Maeda, X. Chen, J. Feng, and J. Xu.
Co-manage power delivery and consumption for manycore systems using
reinforcement learning.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [2638]
- J. Li and J. Draper.
Accelerating soft-error-rate (SER) estimation in the presence of single event
transients.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [2639]
- P.-C. Li and I. N. Hajj.
Computer-aided redesign of VLSI circuits for hot-carrier reliability.
IEEE Transactions on Computer-Aided Design, 15(5):453-464, May
1996.
- [2640]
- Y. Li and J. Henkel.
A framework for estimating and minimizing energy dissipation of embedded
HW/SW systems.
In IEEE/ACM 35th Design Automation Conference, pages 188-193, San
Francisco, CA, June 15-19 1998.
- [2641]
- D.-A. Li and
M. Marek-Sadowska.
Variation-aware electromigration analysis of power/ground networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 571-576, San Jose, CA, November 7-10 2011.
- [2642]
- J. C.-M. Li and E. J.
McCluskey.
Diagnosis of resistive-open and stuck-open defects in digital CMOS ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(11):1748-1759, November 2005.
- [2643]
- P. Li and L. T. Pileggi.
Compact reduced-order modeling of weakly nonlinear analog and RF circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(2):184-203, February 2005.
- [2644]
- T. Li and S. S. Sapatnekar.
Stress-aware performance evaluation of 3d-stacked wide I/O drams.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 645-650, Irvine CA, November 13-16 2017.
- [2645]
- Z. Li and C.-J. R. Shi.
SILCA: fast-yet-accurate time-domain simulation of VLSI circuits with
strong parasitic coupling effects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 793-799, San Jose, CA, November 9-13 2003.
- [2646]
- P. Li and W. Shi.
Model order reduction of linear networks with massive ports via
frequency-dependent port packing.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
267-272, San Francisco, CA, July 24-28 2006.
- [2647]
- Z. Li and C.-J. R. Shi.
A quasi-newton preconditioned newton-krylov method for robust and efficient
time-domain simulation of integrated circuits with strong parasitic
couplings.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2868-2881, December 2006.
- [2648]
- Z. Li and C.-J. R. Shi.
SILCA: SPICE-accurate iterative linear-centric analysis for efficient
time-domain simulation of VLSI circuits with strong parasitic couplings.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(6):1087-1103, June 2006.
- [2649]
- J.-R. Li and J. White.
Efficient model reduction of interconnect via approximate system gramians.
In IEEE/ACM International Conference on Computer-Aided Design, pages
380-383, San Jose, CA, November 7-11 1999.
- [2650]
- T. Li and Z. Yu.
Statistical analysis of full-chip leakage power considering junction tunneling
leakage.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 99-102,
San Diego, CA, June 4-8 2007.
- [2651]
- P. Li.
Power grid simulation via efficient sampling-based sensitivity analysis and
hierarchical symbolic relaxation.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
664-669, Anaheim, CA, June 13-17 2005.
- [2652]
- P. Li.
Variational analysis of large power grids by exploring statistical sampling
sharing and spatial locality.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 645-651, San Jose, CA, November 6-10 2005.
- [2653]
- P. Li.
Statistical sampling-based parametric analysis of power grids.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2852-2867, December 2006.
- [2654]
- X. Li.
Finding deterministic solution from underdetermined equation: large-scale
performance modeling by least angle regression.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
364-369, San Francisco, CA, July 26-31 2009.
- [2655]
- X. Li.
Finding deterministic solution from underdetermined equation: large-scale
performance variability modeling of analog/RF circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1661-1668, November 2010.
- [2656]
- P. Li.
Design analysis of IC power delivery.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 664-666, San Jose, CA, November 5-8 2012.
- [2657]
- B. Li.
Statistical timing analysis and criticality computation for circuits with
post-silicon clock tuning elements.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(11):1784-1797, November 2015.
- [2658]
- X. Liang,
K. Turgay, and D. Brooks.
Architectural power models for SRAM and CAM structures based on hybrid
analytical/empirical techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 824-830, San Jose, CA, November 5-8 2007.
- [2659]
- Y. Liang, W. T.
Tang, R. Zhao, M. Lu, H. P. Huynh, and R. S. M. Goh.
Scale-free sparse matrix-vector multiplication on many-core architectures.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(12):2106-2119, December 2017.
- [2660]
- X. Liang and D. Brooks.
Microarchitecture parameter selection to optimize system performance under
process variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 429-436, San Jose, CA, November 5-9 2006.
- [2661]
- Y. Liang and D. Chen.
Clusred: clustering and network reduction based probabilistic optimal power
flow analysis for large-scale smart grids.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [2662]
- H. Liao, W. W-M Dai,
R. Wang, and F-Y Chang.
S-parameter based macro model of distributed-lumped networks using
exponentially decayed polynomial function.
In ACM/IEEE Design Automation Conference, pages 726-731, Dallas, TX,
June 14-18 1993.
- [2663]
- W. Liao, J. M.
Basile, and L. He.
Leakage power modeling and reduction with data reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 714-719, San Jose, CA, November 10-14 2002.
- [2664]
- W. Liao, J. M.
Basile, and L. He.
Microarchitecture-level leakage reduction with data retention.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1324-1328, November 2005.
- [2665]
- W. Liao, L. He, and
K. M. Lepak.
Temperature and supply voltage aware performance and power modeling at
microarchitecture level.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):1042-1053, July 2005.
- [2666]
- K.-Y. Liao, C.-Y.
Chang, and J.-C.-M. Li.
A parallel test pattern generation algorithm to meet multiple quality
objectives.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(11):1767-1772, November 2011.
- [2667]
- S. Liao, Z. Li,
X. Lin, Q. Qiu, Y. Wang, and B. Yuan.
Energy-efficient, high-performance, highly-compressed deep neural network
design using block-circulant matrices.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 458-465, Irvine CA, November 13-16 2017.
- [2668]
- H.-T. Liaw and C.-S. Lin.
On the OBDD-representation of general boolean functions.
IEEE Transactions on Computers, 41(6):661-664, June 1992.
- [2669]
- D. Lidsky and J. M.
Rabaey.
Early power exploration - a world wide web application.
In 33rd Design Automation Conference, pages 27-32, Las Vegas, NV,
June 3-7 1996.
- [2670]
- L. W. Liebmann
and R. O. Topaloglu.
Design and technology co-optimization near single-digit nodes.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 582-585, San Jose, CA, November 2-6 2014.
- [2671]
- B. K. Liew, N. W.
Cheung, and C. Hu.
Electromigration interconnect lifetime under AC and pulse DC stress.
In IEEE International Reliability Physics Symposium, pages 215-219,
1989.
- [2672]
- B. K. Liew, P. Fang,
N. W. Cheung, and C. Hu.
Reliability simulator for interconnect and intermetallic contact
electromigration.
In IEEE 28th International Reliability Physics Symposium, pages
111-118, New Orleans, LA, March 27-29 1990.
- [2673]
- M. R. Lightner and
G. D. Hachtel.
Implication algorithms for MOS switch-level functional macromodeling,
implication and testing.
In IEEE 19th Design Automation Conference, pages 691-698, Las Vegas,
NV, June 1982.
- [2674]
- Y. J. Lim, K-I. Son,
H-J. Park, and M. Soma.
A statistical approach to the estimation of delay-dependent switching activity
in CMOS combinational circuits.
In 33rd Design Automation Conference, pages 445-450, Las Vegas, NV,
June 3-7 1996.
- [2675]
- D. Lim, J.-W. Lee,
B. Gassend, G. E. Suh, M. van Dijk, and S. Devadas.
Extracting secret keys from integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(10):1200-1205, October 2005.
- [2676]
- S.-K. Lim, X. Zhao,
and M. Scheuermann.
Analysis of DC current crowding in through-silicon-vias and its impact on
power integrity in 3-D ics.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
157-162, San Francisco, CA, June 3-7 2012.
- [2677]
- A. Lim and Y-M. Chee.
Graph partitioning using tabu search.
In IEEE International Symposium on Circuits and Systems, pages
1164-1167, June 1991.
- [2678]
- Y. J. Lim and M. Soma.
Statistical estimation of delay-dependent switching activities in embedded
CMOS combinational circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
5(3):309-319, September 1997.
- [2679]
- L.-H. Lim and J. Weare.
Fast randomized iteration: diffusion monte carlo through the lens of numerical
linear algebra.
SIAM Review, 59(3):547-587, September 2017.
- [2680]
- S. Lin, E. S. Kuh, and
M. Marek-Sadowska.
Stepwise equivalent conductance circuit simulation technique.
IEEE Transactions on Computer-Aided Design, 12(5):672-683, May
1993.
- [2681]
- J-Y. Lin, T-C. Liu,
and W-Z. Shen.
A cell-based power estimation in CMOS combinational circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
304-309, San Jose, CA, November 6-10 1994.
- [2682]
- J.-Y. Lin, W.-Z. Shen,
and J.-Y. Jou.
A power modeling and characterization method for the CMOS standard cell
library.
In IEEE/ACM International Conference on Computer-Aided Design, pages
400-404, San Jose, CA, November 10-14 1996.
- [2683]
- J-Y Lin, W-Z Shen, and
J-Y Jou.
A power modeling and characterization method for macrocells using structure
information.
In IEEE/ACM International Conference on Computer-Aided Design, pages
502-506, San Jose, CA, November 9-13 1997.
- [2684]
- T. Lin, E. Acar, and
L. Pileggi.
h-gamma: An RC delay metric based on a gamma distribution approximation of
the homogeneous response.
In IEEE/ACM International Conference on Computer-Aided Design, pages
19-25, San Jose, CA, November 8-12 1998.
- [2685]
- J.-Y. Lin, W.-Z. Shen,
and J.-Y. Jou.
A structure-oriented power modeling technique for macrocells.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(3):380-391, September 1999.
- [2686]
- T. Lin, M. W. Beattie,
and L. T. Pileggi.
On the efficacy of simplified 2d on-chip inductance models.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
757-762, New Orleans, LA, June 10-14 2002.
- [2687]
- Y. Lin, F. Li, and
L. He.
Circuits and architectures for field programmable gate array with configurable
supply voltage.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(9):1035-1047, September 2005.
- [2688]
- Y. Lin, Y. Hu, L. He,
and V. Raghunat.
An efficient chip-level time slack allocation algorithm for dual-vdd FPGA
power reduction.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 168-173, Tegernsee, Germany, October 4-6 2006.
- [2689]
- S. Lin, H. Yang, and
R. Luo.
A novel gamma.d/n RLCG transmission line model considering complex RC(L)
loads.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(5):970-977, May 2007.
- [2690]
- H.-P. Lin, J.-H. R.
Jiang, and R.-R. Lee.
To SAT or not to SAT: Ashenhurst decomposition in a large scale.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 32-37, San Jose, CA, November 10-13 2008.
- [2691]
- M.-P.-H. Lin, C.-C.
Hsu, and Y.-T. Chang.
Post-placement power optimization with multi-bit flip-flops.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(12):1870-1882, December 2011.
- [2692]
- P.-C.-K. Lin,
A. Mandal, and S. Khatri.
Boolean satisfiability using noise based logic.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1256-1257, San Francisco, CA, June 3-7 2012.
- [2693]
- C.-C. Lin,
A. Chakrabarti, and N. K. Jha.
Optimized quantum gate library for various physical machine descriptions.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(11):2055-2068, November 2013.
- [2694]
- H. Lin, P. Li, and
C. J. Myers.
Verification of digitally-intensive analog circuits via kernel ridge regression
and hybrid reachability analysis.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2695]
- I.-C. Lin, C.-H. Lin,
and K.-H. Li.
Leakage and aging optimization using transmission gate-based technique.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):87-99, January 2013.
- [2696]
- T. Lin, C. Chu,
J. R. Shinnerl, I. Bustany, and I. Nedelchev.
POLAR: placement based on novel rough legalization and refinement.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 357-362, San Jose, CA, November 18-21 2013.
- [2697]
- X. Lin, Y. Wang, and
M. Pedram.
Joint sizing and adaptive independent gate control for finfet circuits
operating in multiple voltage regimes using the logical effort method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 444-449, San Jose, CA, November 18-21 2013.
- [2698]
- H.-T. Lin, Y.-L.
Chuang, Z.-H. Yang, and T.-Y. Ho.
Pulsed-latch utilization for clock-tree power optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(4):721-733, April 2014.
- [2699]
- I.-C. Lin, K.-H. Li,
C.-H. Lin, and K.-C. Wu.
NBTI and leakage reduction using ILP-based approach.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(9):2034-2038, September 2014.
- [2700]
- L. Lin, Y. Saad, and
C. Yang.
Approximating spectral densities of large matrices.
SIAM Review, 58(1):34-65, March 2016.
- [2701]
- J.-M. Lin, T.-T.
Chen, Y.-F. Chang, W.-Y. Chang, Y.-T. Shyu, Y.-J. Chang, and J.-M. Lu.
A fast thermal-aware fixed-outline floor planning methodology based on
analytical models.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [2702]
- J.-M. Lin, J.-S.
Syu, and I-R. Chen.
Macro-aware row-style power delivery network design for better routability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [2703]
- S.-C. Lin and K. Banerjee.
An electrothermally-aware full-chip substrate temperature gradient evaluation
methodology for leakage dominant technologies with implications for power
estimation and hot-spot management.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 568-574, San Jose, CA, November 5-9 2006.
- [2704]
- S.-C. Lin and K. Banerjee.
A design-specific and thermally-aware methodology for trading-off power and
performance in leakage-dominant CMOS technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(11):1488-1498, November 2008.
- [2705]
- S. Lin and N. Chang.
Challenges in power-ground integrity.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 651-654, San Jose, CA, November 4-8 2001.
- [2706]
- I-J. Lin and Y.-W. Chang.
An efficient algorithm for statistical circuit optimization using lagrangian
relaxation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 119-124, San Jose, CA, November 5-8 2007.
- [2707]
- Y. Lin and E. Gad.
Formulation of the obreshkov-based transient circuit simulator in the presence
of nonlinear memory elements.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(1):86-94, January 2015.
- [2708]
- M. Lin and A. El Gamal.
A low-power field-programmable gate array routing fabric.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(10):1481-1494, October 2009.
- [2709]
- Y. Lin and L. He.
Leakage efficient chip-level dual vdd assignment with time slack allocation for
FPGA power reduction.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
720-725, Anaheim, CA, June 13-17 2005.
- [2710]
- Y. Lin and L. He.
Dual-vdd interconnect with chip-level time slack allocation for FPGA power
reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2023-2034, October 2006.
- [2711]
- Y. Lin and L. He.
Statistical dual-vdd assignment for FPGA interconnect power reduction.
Design, Automation and Test in Europe (DATE-07), pages 636-641, April
16-20 2007.
- [2712]
- H.-M. Lin and J.-Y. Jou.
On computing the minimum feedback vertex set of a directed graph by contraction
operations.
IEEE Transactions on Computer-Aided Design, 19(3):295-307, March
2000.
- [2713]
- P.-C.-K. Lin and S. Khatri.
Application of logic synthesis to the understanding and cure of genetic
diseases.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
734-740, San Francisco, CA, June 3-7 2012.
- [2714]
- S. Lin and E. Kuh.
Transient simulation of lossy interconnect.
In 29th ACM/IEEE Design Automation Conference, pages 81-86, Anaheim,
CA, June 8-12 1992.
- [2715]
- H. Lin and P. Li.
Classifying circuit performance using active-learning guided support vector
machines.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 187-194, San Jose, CA, November 5-8 2012.
- [2716]
- H. Lin and P. Li.
Relevance vector and feature machine for statistical analog circuit
characterization and built-in self-test optimization.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [2717]
- S.-H. Lin and M.-P.-H. Lin.
More effective power-gated circuit optimization with multi-bit retention
registers.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 213-217, San Jose, CA, November 2-6 2014.
- [2718]
- J.-M. Lin and C.-C. Lin.
Placement density aware power switch planning methodology for power gating
designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(5):766-777, May 2015.
- [2719]
- B. Lin and H. De Man.
Low-power driven technology mapping under timing constraints.
In International Workshop on Logic Synthesis, pages 9a-1 -- 9a-16,
1993.
- [2720]
- T-M. Lin and C. A. Mead.
Signal delay in general RC networks.
IEEE Transactions on Computer-Aided Design, CAD-3(4):331-349, October
1984.
- [2721]
- T.-M. Lin and C. A. Mead.
A hierarchical timing simulation model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, CAD-5(1):188-197, January 1986.
- [2722]
- R.-B. Lin and C.-M. Tsai.
Theoretical analysis of bus-invert coding.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):929-935, December 2002.
- [2723]
- C.-A. Lin and C.-H. Wu.
Second-order approximations for RLC trees.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(7):1124-1128, July 2004.
- [2724]
- C. Lin and H. Zhou.
Retiming for wire pipelining in system-on-chip.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 215-220, San Jose, CA, November 9-13 2003.
- [2725]
- C. Lin and H. Zhou.
Wire retiming as fixpoint computation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(12):1340-1348, December 2005.
- [2726]
- M.-B. Lin.
On the design of fast large fan-in CMOS multiplexers.
IEEE Transactions on Computer-Aided Design, 19(8):963-967, August
2000.
- [2727]
- J.-F. Lin.
Low-power pulse-triggered flip-flop design based on a signal feed-through
scheme.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(1):181-185, January 2014.
- [2728]
- B. Linares-Barranco and T. Serrano-Gotarredonna.
On an efficient CAD implementation of the distance term in pelgrom's mismatch
model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(8):1534-1538, August 2007.
- [2729]
- M. Linderman and
M. Leeser.
Simulation of digital circuits in the presence of uncertainty.
In IEEE/ACM International Conference on Computer-Aided Design, pages
248-251, San Jose, CA, November 6-10 1994.
- [2730]
- A. Ling, D. P.
Singh, and S. D. Brown.
FPGA technology mapping: a study of optimality.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
427-432, Anaheim, CA, June 13-17 2005.
- [2731]
- A. C. Ling, D. P.
Singh, and S. D. Brown.
FPGA PLB architecture evaluation and area optimization techniques using
boolean satisfiability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(7):1196-1210, July 2007.
- [2732]
- D. D. Ling,
C. Visweswariah, P. Feldmann, and S. Abbaspour.
A moment-based effective characterization waveform for static timing analysis.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 19-24,
San Francisco, CA, July 26-31 2009.
- [2733]
- L. Lingappan, S. Ravi, and N. K. Jha.
Satisfiability-based test generation for nonseparable RTL controller-datapath
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(3):544-557, March 2006.
- [2734]
- L. Lintereur.
Challenges and potential for incorporating model-based design in medical device
development.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [2735]
- J.-J. Liou,
A. Krstic, Y.-M. Jiang, and K.-T. Cheng.
Path selection and pattern generation for dynamic timing analysis considering
power supply noise effects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 493-496, San Jose, CA, November 5-9 2000.
- [2736]
- J.-J. Liou, K.-T.
Cheng, S. Kundu, and A. Krstic.
Fast statistical timing analysis by probabilistic event propagation.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
661-666, Las Vegas, NV, June 18-22 2001.
- [2737]
- J.-J. Liou,
A. Krstic, L.-C. Wang, and K.-T. Cheng.
False-path-aware statistical timing analysis and efficient path selection for
delay testing and timing validation.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
566-569, New Orleans, LA, June 10-14 2002.
- [2738]
- L. Lipsky and S. C. Seth.
Signal probabilities in AND-OR trees.
IEEE Transactions on Computers, 38(11):1558-1563, November 1989.
- [2739]
- R. Lisanke,
F. Brglez, A. J. Degeus, and D. Gregory.
Testability-driven random test-pattern generation.
IEEE Transactions on Computer-Aided Design, CAD-6(6):1082-1087,
November 1987.
- [2740]
- S. Little,
D. Walter, C. Myers, R. Thacker, and T. Yoneda.
Verification of analog/mixed-signal circuits using labeled hybrid petri nets.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(4):617-630, April 2011.
- [2741]
- S. Liu, M. Pedram, and
A. M. Despain.
A fast state assignment procedure for large fsms.
In 32nd Design Automation Conference, pages 327-332, San Francisco,
CA, June 12-16 1995.
- [2742]
- Y. Liu, L. T. Pileggi,
and A. J. Strojwas.
ftd: An exact frequency to time domain conversion for reduced order RLC
interconnect models.
In IEEE/ACM 35th Design Automation Conference, pages 469-472, San
Francisco, CA, June 15-19 1998.
- [2743]
- X. Liu, M. C.
Papaefthymiou, and E. G. Friedman.
Maximizing performance by retiming and clock skew scheduling.
In ACM/IEEE Design Automation Conference, pages 231-236, 1999.
- [2744]
- Y. Liu, L. T.
Pileggi, and A. J. Strojwas.
Model order-reduction of RC(L) interconnect including variational analysis.
In Design Automation Conference, pages 201-206, New Orleans, LA, June
21-25 1999.
- [2745]
- Y. Liu, S. R. Nassif,
L. T. Pileggi, and A. J. Strojwas.
Impact of interconnect variations on the clock skew of a gigahertz processor.
In Design Automation Conference, pages 168-171, Los Angeles, CA, June
5-9 2000.
- [2746]
- Y. Liu, L. T. Pileggi,
and A. J. Strojwas.
ftd: Frequency to time domain conversion for reduced-order interconnect
simulation.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(4):500-506, April 2001.
- [2747]
- F. Liu, C. Kashyap,
and C. J. Alpert.
A delay metric for RC circuits based on the weibull distribution.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 620-624, San Jose, CA, November 10-14 2002.
- [2748]
- J. Liu, S. Zhou,
H. Zhu, and C.-K. Cheng.
An algorithmic approach for generic parallel adders.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 734-740, San Jose, CA, November 9-13 2003.
- [2749]
- F. Liu, C. Kashyap,
and C. J. Alpert.
A delay metric for RC circuits based on the weibull distribution.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(3):443-447, March 2004.
- [2750]
- M. Liu, W.-S. Wang,
and M. Orshansky.
Leakage power reduction by dual-vth designs under probabilistic analysis of vth
variation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 2-7, Newport Beach, CA, August 9-11 2004.
- [2751]
- Q. Liu, B. Hu, and
M. Marek-Sadowska.
Individual wire-length prediction with appreciation to timing-driven placement.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1004-1014, October 2004.
- [2752]
- Q.-H. Liu, C. Cheng,
and H. Z. Massoud.
The special grid method: a novel fast schrodinger-equation solver for
semiconductor nanodevice simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1200-1208, August 2004.
- [2753]
- X. Liu, Y. Peng, and
M. C. Papaefthymiou.
Practical repeater insertion for low power: what repeater library do we need.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 30-35,
San Diego, CA, June 7-11 2004.
- [2754]
- P. Liu, Z. Qi,
H. Li, L. Jin, W. Wu, S. X.-D. Tan, and J. Yang.
Fast thermal simulation for architecture level dynamic thermal management.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 639-644, San Jose, CA, November 6-10 2005.
- [2755]
- P. Liu, S. X.-D.
Tan, H. Li, Z. Qi, J. Kong, B. McGaughly, and L. He.
An efficient method for terminal reduction of interconnect circuits considering
delay variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 821-826, San Jose, CA, November 6-10 2005.
- [2756]
- H.-Y. Liu, C.-W.
Lin, S.-J. Chou, W.-T. Tu, C.-H. Liu, Y.-W. Chang, and S.-Y. Kuo.
Current path analysis for electrostatic discharge protection.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 510-515, San Jose, CA, November 5-9 2006.
- [2757]
- X. Liu, Y. Peng, and
M. C. Papaefthymiou.
Practical repeater insertion for low power: what repeater library do we need?
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):917-924, May 2006.
- [2758]
- Z. Liu, B. W.
McGaughy, and J.-Z. Ma.
Design tools for reliability analysis.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
182-187, San Francisco, CA, July 24-28 2006.
- [2759]
- H.-Y. Liu, W.-P.
Lee, and Y.-W. Chang.
A provably good approximation algorithm for power optimization using multiple
supply voltages.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
887-890, San Diego, CA, June 4-8 2007.
- [2760]
- P. Liu, S. X.-D.
Tan, B. McGaughy, L. Wu, and L. He.
Termmerg: an efficient terminal-reduction method for interconnect circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(8):1382-1392, August 2007.
- [2761]
- J.-H. Liu, Z.-Y.
Jiang, L. Chen, and C. C.-P. Chen.
Singular value decomposition based spatial correlation extraction for VLSI
DFM applications.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 80-85, Monterey, CA,
February 25-26 2008.
- [2762]
- J.-H. Liu, M.-F.
Tsai, L. Chen, and C.-C.-P. Chen.
Accurate and analytical statistical spatial correlation modeling for VLSI
DFM applications.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
694-697, Anaheim, CA, June 8-13 2008.
- [2763]
- S. Liu, G. Chen,
T.-T. Jing, L. He, T. Zhang, R. Dutta, and X.-L. Hong.
Topological routing to maximize routability for package substrate.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
566-569, Anaheim, CA, June 8-13 2008.
- [2764]
- Y.-F. Liu, B. Wang,
M. Xu, X. Liu, J.-Z. Chen, and M. Desmith.
Correlation of on-die capacitance for power delivery network.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 123-126, San Jose, CA, October 27-29 2008.
- [2765]
- T.-T. Liu, L. P.
Alarcon, M. D. Pierson, and J. M. Rabaey.
Asynchronous computing in sense amplifier-based pass transistor logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(7):883-892, July 2009.
- [2766]
- J.-H. Liu, M.-F.
Tsai, L. Chen, and C.-C.-P. Chen.
Accurate and analytical statistical spatial correction modeling based on
singular value decomposition for VLSI DFM applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):580-589, April 2010.
- [2767]
- S. Liu, Y. Zhang,
S. O. Memik, and G. Memik.
An approach for adaptive DRAM temperature and power management.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(4):684-688, April 2010.
- [2768]
- X.-X. Liu, H. Yu,
and S. X.-D. Tan.
A robust periodic arnoldi shooting algorithm for efficient analysis of
large-scale RF/MM ics.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
573-578, Anaheim, CA, June 13-18 2010.
- [2769]
- X.-X. Liu, H. Wang,
and S.-X.-D. Tan.
Parallel power grid analysis using preconditioned GMRES solver on CPU-GPU
platforms.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 561-568, San Jose, CA, November 18-21 2013.
- [2770]
- B. Liu, H. Li,
Y. Chen, X. Li, T. Huang, Q. Wu, and M. Barnell.
Reduction and IR-drop compensations techniques for reliable neuromorphic
computing systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 63-70, San Jose, CA, November 2-6 2014.
- [2771]
- S.-S.-Y. Liu, R.-G.
Luo, S. Aroonsantidecha, C.-Y. Chin, and H.-M. Chen.
Fast thermal aware placement with accurate thermal anaylsis based on green
function.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(6):1404-1415, June 2014.
- [2772]
- W.-H. Liu, M.-S.
Chang, and T.-C. Wang.
Floorplanning and signal assignment for silicon interposer-based 3d ics.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [2773]
- J. Liu, D.-C. Juan,
and Y. Shi.
Effective CAD research in the sea of papers.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 781-785, Austin, TX, November 2-6 2015.
- [2774]
- X. Liu, S. Sun,
P. Zhou, X. Li, and H. Qian.
A statistical methodology for noise sensor placement and full-chip voltage map
generation.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [2775]
- X.-X. Liu, H. Yu, and
S.-X.-D. Tan.
A GPU-accelerated parallel shooting algorithms for analysis of radio
frequency and microwave circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(3):480-492, March 2015.
- [2776]
- X. Liu, S. Sun,
X. Li, H. Qian, and P. Zhou.
Machine learning for noise sensor placement and full-chip voltage emergency
detection.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(3):421--, March 2017.
- [2777]
- Y. Liu, L. Wei,
B. Luo, and Q. Xu.
Fault injection attack on deep neural network.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 131-138, Irvine CA, November 13-16 2017.
- [2778]
- C.-W. Liu and Y.-W. Chang.
Power/ground network and floorplan cosynthesis for fast design convergence.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):693-704, April 2007.
- [2779]
- F-J Liu and C-K Cheng.
Extending moment computation to 2-port circuit representations.
In IEEE/ACM 35th Design Automation Conference, pages 473-476, San
Francisco, CA, June 15-19 1998.
- [2780]
- C.-C. Liu and C.-K. Cheng.
Low-power and high-speed interconnect using serial passive compensation.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 68-73, Monterey, CA,
February 25-26 2008.
- [2781]
- J. Liu and P. H. Chou.
Optimizing model transition sequences in idle intervals for component-level and
system-level energy minimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 21-28, San Jose, CA, November 7-11 2004.
- [2782]
- F. Liu and P. Feldmann.
MAISE: An interconnect simulation engine for timing and noise analysis.
In IEEE International Conference on Quality Electronic Design (ISQED),
pages 621-626, San Jose, CA, March 17-19 2008.
- [2783]
- F. Liu and P. Feldmann.
A time-unrolling method to compute sensitivity of dynamic systems.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [2784]
- F. Liu and B. R. Hodges.
Dynamic river network simulation at large scale.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
723-728, San Francisco, CA, June 3-7 2012.
- [2785]
- Q. Liu and
M. Marek-Sadowska.
Pre-layout wire length and congestion estimation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
582-587, San Diego, CA, June 7-11 2004.
- [2786]
- F. Liu and S. Ozev.
Statistical test development for analog circuits under high process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(8):1465-1477, August 2007.
- [2787]
- X. Liu and M. C.
Papaefthymiou.
A markov chain sequence generator for power macromodeling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 404-411, San Jose, CA, November 10-14 2002.
- [2788]
- X. Liu and M. C.
Papaefthymiou.
A markov chain sequence generator for power macromodeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(7):1048-1062, July 2004.
- [2789]
- X. Liu and M. C.
Papaefthymiou.
Hype: hybrid power estimation for IP-based system-on-chip.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):1089-1103, July 2005.
- [2790]
- Q. Liu and S. S.
Sapatnekar.
Confidence scalable post-silicon statistical delay prediction under process
variations.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
497-502, San Diego, CA, June 4-8 2007.
- [2791]
- Q. Liu and S. S.
Sapatnekar.
A framework for scalable postsilicon statistical delay prediction under process
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(8):1201-1212, August 2008.
- [2792]
- Q. Liu and S. S.
Sapatnekar.
Capturing post-silicon variations using a representative critical path.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(2):211-222, February 2010.
- [2793]
- B. Liu and S. X.-D. Tan.
Minimum decoupling capacitor insertion in VLSI power/ground supply networks
by semidefinite and linear programs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(11):1284-1287, November 2007.
- [2794]
- J.-B. Liu and A. Veneris.
Incremental fault diagnosis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(2):240-251, February 2005.
- [2795]
- H. Liu and N. Wong.
Autonomous volterra algorithm for steady-state analysis of nonlinear circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):858-868, June 2013.
- [2796]
- X. Liu and Q. Xu.
Interconnection fabric design for tracing signals in post-silicon validation.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
352-357, San Francisco, CA, July 26-31 2009.
- [2797]
- F. Liu.
An efficient method for statistical circuit simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 719-724, San Jose, CA, November 5-8 2007.
- [2798]
- F. Liu.
A general framework for spatial correlation modeling in VLSI design.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
817-822, San Diego, CA, June 4-8 2007.
- [2799]
- F. Liu.
How to construct spatial correlation models: a mathematical approach.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 106-111, Austin,
Texas, February 26-27 2007.
- [2800]
- Y. Liu.
Dynamically resilient and agile fine-grained replication configuration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 786-793, Austin, TX, November 2-6 2015.
- [2801]
- P. Liy, D. J. Liljay,
W. Qianz, K. Bazargany, and M. Riedely.
The synthesis of complex arithmetic computation on stochastic bit streams using
sequential logic.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 480-487, San Jose, CA, November 5-8 2012.
- [2802]
- R. P. LLopis,
R. J. H. Koopman, H. G. Kerkhoff, and J. A. Braat.
A performance analysis tool for performance-driven micro-cell generation.
In European Conference on Design Automation, pages 576-580, February
1991.
- [2803]
- R. P. Llopis and
K. Goossens.
The petrol approach to high-level power estimation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 130-132, Monterey, CA, August 10-12 1998.
- [2804]
- R. P. Llopis and
M. Sachdev.
Low power, testable dual edge triggered flip-flops.
In International Symposium on Low Power Electronics and Design, pages
341-345, Monterey, CA, August 12-14 1996.
- [2805]
- J. R. Lloyd and
J. Kitchin.
The electromigration failure distribution: The fine-line case.
Journal of Applied Physics, 69(4):2117-2127, February 1991.
- [2806]
- J. R. Lloyd.
Electromigration and mechanical stress.
Microelectronics Engineering, 49:51-64, 1999.
- [2807]
- J. R. Lloyd.
Black's law revisited - nucleation and growth in electromigration failure.
Microelectronics Reliability, 47:1468-1472, September 2007.
- [2808]
- C-Y. Lo, H. N. Nham, and
A. K. Bose.
A data structure for MOS circuits.
In IEEE 20th Design Automation Conference, pages 619-624, Miami
Beach, FL, June 27-29 1983.
- [2809]
- C. F. Van Loan.
Computing integrals involving the matrix exponential.
IEEE Transactions on Automatic Control, AC-23(3):395-404, June
1978.
- [2810]
- J. Long, J.-C. Ku,
S. O. Memik, and Y. I. Ismail.
A self-adjusting clock tree architecture to cope with temperature variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 75-82, San Jose, CA, November 5-8 2007.
- [2811]
- J. Long, J.-C. Ku,
S. O. Memik, and Y. Ismail.
SACTA: a self-adjusting clock tree architecture for adapting to
thermal-induced delay variation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(9):1323-1336, September 2010.
- [2812]
- J. Long, D. Li,
S. O. Memik, and S. Ulgen.
Theory and analysis for optimization of on-chip thermoelectric cooling systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1628-1632, October 2013.
- [2813]
- C. Long and L. He.
Distributed sleep transistor network for power reduction.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
181-186, Anaheim, CA, June 2-6 2003.
- [2814]
- C. Long and L. He.
Distributed sleep transistor network for power reduction.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(9):937-946, September 2004.
- [2815]
- J. Long and S. O. Memik.
Automated design of self-adjusting pipelines.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
211-216, Anaheim, CA, June 8-13 2008.
- [2816]
- D. E. Long.
The design of a cache-friendly BDD library.
In IEEE/ACM International Conference on Computer-Aided Design, pages
639-645, San Jose, CA, November 8-12 1998.
- [2817]
- D. Lorenz,
M. Barke, and U. Schlichtmann.
Aging analysis at gate and macro cell level.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 77-84, San Jose, CA, November 7-11 2010.
- [2818]
- K. K. Low and S. W.
Director.
A new methodology for the design centering of IC fabrication processes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 10(7):895-903, July 1991.
- [2819]
- K. S. Lowe and P. G. Gulak.
Gate sizing and buffer insertion for optimizing performance in power
constrained bicmos circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
216-219, Santa Clara, CA, November 7-11 1993.
- [2820]
- K. S. Lowe and P. G. Gulak.
A joint gate sizing and buffer insertion method for optimizing delay and power
in CMOS and bicmos combinational logic.
IEEE Transactions on Computer-Aided Design, 17(5):419-434, May
1998.
- [2821]
- Y.-H. Lu, L. Benini, and
G. De Micheli.
Dynamic frequency scaling with buffer insertion for mixed workloads.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(11):1284-1305, November 2002.
- [2822]
- Z. Lu, W. Huang,
J. Lach, M. Stan, and K. Skadron.
Interconnect lifetime prediction under dynamic stress for reliability-aware
design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 327-334, San Jose, CA, November 7-11 2004.
- [2823]
- X. Lu, Z. Li, W. Qiu,
D. M. H. Walker, and W. Shi.
Longest-path selection for delay test under process variation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(12):1924-1929, December 2005.
- [2824]
- P.-F. Lu, N. Cao,
L. Sigal, P. Woltgens, R. Robertazzi, and D. Heidel.
A pulsed low-voltage swing latch for reduced power dissipation in
high-frequency microprocessors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 85-88, Tegernsee, Germany, October 4-6 2006.
- [2825]
- Z. Lu, W. Huang, M. R.
Stan, K. Skadron, and J. Lach.
Interconnect lifetime prediction for reliability-aware systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(2):159-172, February 2007.
- [2826]
- Y. Lu, L. Shang,
H. Zhou, H. Zhu, F. Yang, and X. Zeng.
Statistical reliability analysis under process variation and aging effects.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
514-519, San Francisco, CA, July 26-31 2009.
- [2827]
- Y. Lu, H. Zhou,
L. Shang, and X. Zeng.
Multicore parallelization of min-cost flow for CAD applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(10):1546-1557, October 2010.
- [2828]
- S.-L. Lu, T. Karnik,
G. Srinivasa, K.-Y. Chao, D. Carmean, and J. Held.
Scaling the "memory wall".
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 271-272, San Jose, CA, November 5-8 2012.
- [2829]
- S.-K. Lu, H.-H. Huang,
J.-L. Huang, and P. Ning.
Synergistic reliability and yield enhancement techniques for embedded srams.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):165-169, January 2013.
- [2830]
- J. Lu, P.Chen, C.-C.
Chang, L. Sha, D.-J.-H. Huang, C.-C. Teng, and C.-K. Cheng.
eplace: electrostatics based placement using nesterov's method.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [2831]
- C.-P. Lu, I.-H.-R Jiang,
and C.-H. Hsu.
Gasstation: power and area efficient buffering for multiple power domain
design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 861-866, Austin, TX, November 2-6 2015.
- [2832]
- N. Lu and I. N. Hajj.
A hierarchical based approach for coupling aware delay analysis of
combinational logic blocks.
In 7th IEEE International Conference on Electronics, Circuits and
Systems, pages 1012-1015, Beirut, Lebanon, December 17-19 2000.
- [2833]
- N. Lu and I. N. Hajj.
A fast coupling aware delay estimation scheme based on simplified circuit
model.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 133-138, San Jose, CA, March 26-28 2001.
- [2834]
- R. Lu and C.-K. Koh.
SAMBA-bus: a high performance bus architecture for system-on-chips.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 8-12, San Jose, CA, November 9-13 2003.
- [2835]
- Y. Lu and H. Zhou.
Efficient design space exploration for component-based system design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 466-472, San Jose, CA, November 5-8 2012.
- [2836]
- J. T. Ludwig,
S. H. Nawab, and A. Chandrakasan.
Low power filtering using approximate processing for DSP applications.
In IEEE Custom Integrated Circuits Conference, pages 185-188, Santa
Clara, CA, May 1-4 1995.
- [2837]
- F. Luellau,
T. Hoepken, and E. Barke.
A technology independent block extraction algorithm.
In IEEE 21st Design Automation Conference, pages 610-615, 1984.
- [2838]
- J. Luo, L. Zhong,
Y. Fei, and N.-K. Jha.
Register binding-based RTL power management for control-flow intensive
designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1175-1183, August 2004.
- [2839]
- Y. Luo, J. Yu,
J. Yang, and L. Bhuyan.
Low power network processor design using clock gating.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
712-715, Anaheim, CA, June 13-17 2005.
- [2840]
- J. Luo, S. Sinha,
Q. Su, J. Kawa, and C. Chiang.
An IC manufacturing yield model considering intra-die variations.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
749-754, San Francisco, CA, July 24-28 2006.
- [2841]
- J. Luo, N. K. Jha, and
L.-S. Peh.
Simultaneous dynamic voltage scaling processors and communication links in
real-time distributed embedded systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(4):427-437, April 2007.
- [2842]
- P.-W. Luo, J.-E. Chen,
C.-L. Wey, L.-C. Cheng, J.-J. Chen, and W.-C. Wu.
Impact of capacitance correlation on yield enhancement of mixed-signal/analog
integrated circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(11):2097-2101, November 2008.
- [2843]
- Y. Luo,
K. Chakrabarty, and T.-Y. Ho.
Error recovery in cyberphysical digital microfluidic biochips.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):59-72, January 2013.
- [2844]
- S. Luo and Z.-D. Chen.
Extraction of causal time-domain network parameters from their band-limited
frequency-domain counterparts using rational functions.
IEEE Transactions on Circuits and Systems, 52(6):1205-1210, June
2005.
- [2845]
- C. Lursinsap and
D. Gajski.
An optimal power routing for top-down design architecture.
In IEEE International Conference on Computer-Design, pages 345-348,
1987.
- [2846]
- A. Lvov and U. Finkler.
Exact basic geometric operations on arbitrary angle polygons using only fixed
size integer coordinates.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 494-498, San Jose, CA, November 10-13 2008.
- [2847]
- W.-L. Lyu, F. Yang,
C.-H. Yan, D. Zhou, and X. Zeng.
Multi-objective bayesian optimization for analog/RF circuit synthesis.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [2848]
- C.-G. Lyuh and T. Kim.
High-level synthesis for low power based on network flow method.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):364-375, June 2003.
- [2849]
- S. Rao M. and S. K. Nandy.
Power minimization using control generated clocks.
In Design Automation Conference, pages 794-799, Los Angeles, CA, June
5-9 2000.
- [2850]
- W. m. Hwu, S. Ryoo,
S.-Z. Ueng, J. H. Kelm, I. Gelado, S. S. Stone, R. E. Kidd, S. S. Baghsorkhi,
A. A. Mahesri, S. C. Tsao, N. Navarro, S. S. Lumetta, M. I. Frank, and S. J.
Patel.
Implicitly parallel programming models for thousand-vore microprocessors.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
754-759, San Diego, CA, June 4-8 2007.
- [2851]
- D. Ma, J. Wang, and
P. Vozqua.
Adaptive on-chip power supply with robust one-cycle control technique.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 394-399, Tegernsee, Germany, October 4-6 2006.
- [2852]
- J. D. Ma and R. A. Rutenbar.
Interval-valued reduced order statistical interconnect modeling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 460-467, San Jose, CA, November 7-11 2004.
- [2853]
- J.-D. Ma and R. A. Rutenbar.
Fast interval-valued statistical modeling of interconnect and effective
capacitance.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(4):710-724, April 2006.
- [2854]
- J. D. Ma and R. A. Rutenbar.
Interval-valued reduced-order statistical interconnect modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(9):1602-1613, September 2007.
- [2855]
- Q. Ma and E. F.-Y. Young.
Network flow-based power optimization under timing constraints in MSV-driven
floorplanning.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 1-8, San Jose, CA, November 10-13 2008.
- [2856]
- Q. Ma and E. F. Y. Young.
Multivoltage floorplan design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):607-617, April 2010.
- [2857]
- F. Maamari and
J. Rajski.
A reconvergent fanout analysis for efficient exact fault simulation of
combinational circuits.
In IEEE 18th International Fault Tolerant Computing Symposium, pages
122-126, June 1988.
- [2858]
- M. Maasoumy and A. Sangiovanni-Vincentelli.
Buildings to grid integration: a dynamic contract approach.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 473-478, Austin, TX, November 2-6 2015.
- [2859]
- L. Macchiarulo, E. Macii, and M. Poncino.
Low-energy encoding for deep-submicron address buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 176-181, Huntington Beach, California, August 6-7
2001.
- [2860]
- E. Macii,
M. Pedram, and F. Somenzi.
High-level power modeling, estimation, and optimization.
In 34th Design Automation Conference, pages 504-511, Anaheim, CA,
June 9-13 1997.
- [2861]
- A. Macii,
E. Macii, M. Poncino, and R. Scarsi.
Stream synthesis for efficient power simulation based on spectral transforms.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 30-35, Monterey, CA, August 10-12 1998.
- [2862]
- E. Macii,
M. Pedram, and F. Somenzi.
High-level power modeling, estimation, and optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 17(11):1061-1079, November 1998.
- [2863]
- A. Macii,
E. Macii, M. Poncino, and R. Scarsi.
Stream synthesis for efficient power simulation based on spectral techniques.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(3):417-426, June 2001.
- [2864]
- E. Macii and M. Poncino.
Predicting the functional complexity of combinational circuits by symbolic
spectral analysis of boolean functions.
In European Design Automation Conference, pages 294-299, 1996.
- [2865]
- C. MacInnes.
The use of small pivot perturbation in circuit analysis.
IEEE Transactions on Computer-Aided Design, 10(11):1441-1446,
November 1991.
- [2866]
- D. MacMillen, M. Butts, R. Camposano, D. Hill, and T. W.
Williams.
An industrial view of electronic design automation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1428-1448, December 2000.
- [2867]
- R. Macys and
S. McCormick.
A new algorithm for computing the "effective capacitance" in deep sub-micron
circuits.
In IEEE Custom Integrated Circuits Conference, pages 313-316, Santa
Clara, CA, May 11-14 1998.
- [2868]
- C. Madigan and
V. Bulovic.
Organic electronic device modeling at the nanoscale.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 832-833, San Jose, CA, November 5-9 2006.
- [2869]
- P. Maffezzoni and A. Brambilla.
Study of statistical approaches to the solution of linear discrete and integral
problems.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(9):1153-1161, September 2003.
- [2870]
- P. Maffezzoni and A. Brambilla.
Statistical approach to derive an electrical port model of capacitively coupled
interconnects.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(4):797-807, April 2004.
- [2871]
- Nir Magen, Avinoam
Kolodny, Uri Weiser, and Nachum Shamir.
Interconnect-power dissipation in a microprocessor.
In ACM/IEEE International Workshop on System-Level Interconnect Prediction
(SLIP-04), pages 7-13, February 14-15 2004.
- [2872]
- M. Magerl,
V. Ceperic, and A. Baric.
Echo state networks for black-box modeling of integrated circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(8):1309-1317, August 2016.
- [2873]
- M. Maggio,
A. Chandrakasan, A. Agarwal, Y. Sinangil, M. Sinangil, S. Devadas, E. Lau,
G. Kurian, J. Holt, H. Hoffman, S. Neuman, and J. Miller.
Self-aware computing in the angstrom processor.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
259-264, San Francisco, CA, June 3-7 2012.
- [2874]
- B. Magnhagen.
Practical experience from signal probability simulation of digital designs.
In IEEE 14th Design Automation Conference, pages 216-219, 1977.
- [2875]
- V. Mahalingam, N. Ranganathan, and J. E. Harlow, III.
A novel approach for variation aware power minimization during gate sizing.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 174-179, Tegernsee, Germany, October 4-6 2006.
- [2876]
- V. Mahalingam, N. Ranganathan, and J. E. Harlow.
A fuzzy optimization approach for variation aware power minimization during
gate sizing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(8):975-984, August 2008.
- [2877]
- H. Mahawar,
V. Sarin, and W. Shi.
A solenoidal basis method for efficient inductance extraction.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
751-756, New Orleans, LA, June 10-14 2002.
- [2878]
- A. Maheshwari, W. Burleson, and R. Tessier.
Trading off transient fault tolerance and power consumption in deep submicron
(DSM) VLSI circuits.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(3):299-311, March 2004.
- [2879]
- A. Maheshwari and W. Burleson.
Differential current-sensing for on-chip interconnects.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1321-1329, December 2004.
- [2880]
- Z. Mahmood,
S. Grivet-Talocia, A. Chinea, G. C. Clalfiore, and L. Daniel.
Efficient localization methods for passivity enforcement of linear dynamical
models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(9):1328-1341, September 2014.
- [2881]
- H. Mahmoodi,
V. Tirumalashetty, M. Cooke, and K. Roy.
Ultra low-power clocking scheme using energy recovery and clock gating.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(1):33-44, January 2009.
- [2882]
- M. R. Mahmoodi and
D. Strukov.
An ultra-low energy internally analog, externally digital vector-matrix
multiplier based on NOR flash memory technology.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [2883]
- H. Mahmoodi-Meimand and K. Roy.
Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design
style.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(3):495-503, March 2004.
- [2884]
- A. G. Mahmutoglu
and A. Demir.
Modeling and analysis of nonstationary low-frequency noise in circuit
simulators: enabling non monte carlo techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 309-315, San Jose, CA, November 2-6 2014.
- [2885]
- A. G. Mahmutoglu
and A. Demir.
Non-monte carlo analysis of low-frequency noise: exposition of intricate
nonstationary behavior and comparision with legacy models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(11):1825-1835, November 2016.
- [2886]
- A. Majumdar,
W.-Y. Chen, and J. Guo.
Hold time validation on silicon and the relevance of hazards in timing
analysis.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
326-331, San Francisco, CA, July 24-28 2006.
- [2887]
- A. Majumdar and
S. B. K. Vrudhula.
Analysis of signal probability in logic circuits using stochastic models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
1(3):365-379, September 1993.
- [2888]
- W.-K. Mak and C. Chu.
Rethinking the wirelength benefit of 3-D integration.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(12):2346-2351, December 2012.
- [2889]
- T. Makimoto and
Y. Sakai.
Evolution of low power electronics and its future applications.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 2-5, Seoul, Korea, August 25-27 2003.
- [2890]
- E. Malavasi,
S. Zancella, and M. Cao.
Impact analysis of process variability on clock skew.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 129-132, San Jose, CA, March 18-21 2002.
- [2891]
- J. S. Malik,
A. Hemani, J. N. Malik, B. Silmane, and N. D. Gohar.
Revisiting central limit theorem: accurate gaussian random number generation in
VLSI.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(5):842-855, May 2015.
- [2892]
- S. Malik.
Analysis of cyclic combinational circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
618-625, Santa Clara, CA, November 7-11 1993.
- [2893]
- C. H. Malley and
M. Dieudonne.
Logic verification methodology for powerpc microprocessors.
In 32nd Design Automation Conference, pages 234-240, San Francisco,
CA, June 12-16 1995.
- [2894]
- W. Maly, P. K. Nag,
and P. Nigh.
Testing oriented analysis of CMOS ics with opens.
In IEEE International Conference on Computer-Aided Design, pages
344-347, Santa Clara, CA, Nov. 7-10 1988.
- [2895]
- W. Maly, Y.-W. Lin,
and M. Marek-Sadowska.
OPC-free and minimally irregular IC design style.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
954-957, San Diego, CA, June 4-8 2007.
- [2896]
- M. Mamidipaka, D. Hirschberg, and N. Dutt.
Low power address encoding using self-organizing lists.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 188-193, Huntington Beach, California, August 6-7
2001.
- [2897]
- M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir.
IDAP: a tool for high level power estimation of custom array structures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 113-119, San Jose, CA, November 9-13 2003.
- [2898]
- M. N.
Mamidipaka, D. S. Hirschberg, and N. D. Dutt.
Adaptive low-power address encoding techniques using self-organizing lists.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(5):827-834, October 2003.
- [2899]
- M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir.
IDAP: a tool for high-level power estimation of custom array structures.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1361-1369, September 2004.
- [2900]
- P. Manfredi,
D. V. Ginste, D. De Zutter, and F. G. Canavero.
On the passivity of polynomial chaos-based augmented models for stochastic
circuits.
IEEE Transactions on Circuits and Systems, 60(11):2998-3007, November
2013.
- [2901]
- O. L.
Mangasarian and T.-H. Shiau.
Variable complexity norm maximization problem.
SIAM Journal on Algebraic and Discrete Methods, 7(3):455-461,
1986.
- [2902]
- H. Mangassarian, A. Veneris, S. Safarpour, F. N. Najm, and M. S.
Abadir.
Maximum circuit activity estimation using pseudo-boolean satisfiability.
Design, Automation and Test in Europe (DATE-07), pages 1538-1543,
April 16-20 2007.
- [2903]
- H. Mangassarian, A. Veneris, D. E. Smith, and S. Safarpour.
Debugging with dominance: on-the-fly RTL debug solution implications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 587-594, San Jose, CA, November 7-10 2011.
- [2904]
- H. Mangassarian, A. Veneris, and F. N. Najm.
Maximum circuit activity estimation using pseudo-boolean satisfiability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(2):271-284, February 2012.
- [2905]
- M. Mani, A. Devgan,
and M. Orshansky.
An efficient algorithm for statistical minimization of total power under timing
yield constraints.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
309-314, Anaheim, CA, June 13-17 2005.
- [2906]
- M. Mani, A. Devgan,
M. Orshansky, and Y. Zhan.
A statistical algorithm for power- and timing-limited parametric yield
optimization of large integrated circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(10):1790-1802, October 2007.
- [2907]
- S. Manne,
A. Pardo, R. I. Bahar, G. D. Hachtel, F. Somenzi, E. Macii, and M. Poncino.
Computing the maximum power cycles of a sequential circuit.
In 32nd Design Automation Conference, pages 23-28, San Francisco, CA,
June 12-16 1995.
- [2908]
- V. Manohararajah, S. D. Brown, and Z. G. Vranesic.
Heuristics for area minimization in LUT-based FPGA technology mapping.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2331-2340, November 2006.
- [2909]
- M. M. Mansour and
A. Mehrotra.
Reduced-order modeling based on PRONY's and SHANK's methods via the
bilinear transformation.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 299-304, San Jose, CA, March 24-26 2003.
- [2910]
- W. Mao and M. D. Ciletti.
Correlation-reduced scan-path design to improve delay fault coverage.
In 28th ACM/IEEE Design Automation Conference, pages 73-79, San
Francisco, CA, June 17-21 1991.
- [2911]
- T. E. Marchok,
A. El-Maleh, W. Maly, and J. Rajski.
A complexity analysis of sequential ATPG.
IEEE Transactions on Computer-Aided Design, 15(11):1409-1423,
November 1996.
- [2912]
- R. Marculescu, D. Marculescu, and M. Pedram.
Switching activity analysis considering spatiotemporal correlations.
In IEEE/ACM International Conference on Computer-Aided Design, pages
294-299, San Jose, CA, November 6-10 1994.
- [2913]
- D. Marculescu, R. Marculescu, and M. Pedram.
Information theoretic measures of energy consumption at register transfer
level.
In ACM/IEEE International Symposium on Low Power Design, pages 81-86,
Dana Point, CA, April 23-26 1995.
- [2914]
- R. Marculescu, D. Marculescu, and M. Pedram.
Efficient power estimation for highly correlated input streams.
In 32nd Design Automation Conference, pages 628-634, San Francisco,
CA, June 12-16 1995.
- [2915]
- D. Marculescu, R. Marculescu, and M. Pedram.
Information theoretic measures for power analysis.
IEEE Transactions on Computer-Aided Design, 15(6):599-610, June
1996.
- [2916]
- D. Marculescu, R. Marculescu, and M. Pedram.
Stochastic sequential machine synthesis targeting constrained sequence
generation.
In 33rd Design Automation Conference, pages 696-701, Las Vegas, NV,
June 3-7 1996.
- [2917]
- D. Marculescu, R. Marculescu, and M. Pedram.
Sequence compaction for probabilistic analysis of finite-state machines.
In 34th Design Automation Conference, pages 12-15, Anaheim, CA, June
9-13 1997.
- [2918]
- R. Marculescu, D. Marculescu, and M. Pedram.
Composite sequence compaction for finite-state machines using block entropy and
high-order markov models.
In 1997 International Symposium on Low Power Electronics and Design,
pages 190-195, Monterey, CA, August 18-20 1997.
- [2919]
- R. Marculescu, D. Marculescu, and M. Pedram.
Hierarchical sequence compaction for power estimation.
In 34th Design Automation Conference, pages 570-575, Anaheim, CA,
June 9-13 1997.
- [2920]
- D. Marculescu, R. Marculescu, and M. Pedram.
Theoretical bounds for switching activity analysis in finite-state machines.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 36-41, Monterey, CA, August 10-12 1998.
- [2921]
- R. Marculescu, D. Marculescu, and M. Pedram.
Probabilistic modeling of dependencies during switching activity analysis.
IEEE Transactions on Computer-Aided Design of Circuits and Systems,
17(2):73-83, February 1998.
- [2922]
- R. Marculescu, D. Marculescu, and M. Pedram.
Non-stationary effects in trace-driven power analysis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 133-138, San Diego, CA, August 16-17 1999.
- [2923]
- R. Marculescu, D. Marculescu, and M. Pedram.
Sequence compaction for power estimation: Theory and practice.
IEEE Transactions on Computer-Aided Design, 18(7):973-993, July
1999.
- [2924]
- D. Marculescu, R. Marculescu, and M. Pedram.
Theoretical bounds for switching activity analysis in finite-state machines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):335-339, June 2000.
- [2925]
- D. Marculescu, D. Stamoulis, and E. Cai.
Hardware-aware machine learning: modeling and optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [2926]
- D. Marculescu and
S. Garg.
System-level process-driven variability analysis for single and multi
voltage-frequency island systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 541-546, San Jose, CA, November 5-9 2006.
- [2927]
- R. Marculescu and D. Marculescu.
Does Q=mc2? (on the relationship between quality in electronic design and the
model of colloidal computing).
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 451-457, San Jose, CA, March 18-21 2002.
- [2928]
- D. Marculescu.
Profile-driven code execution for low power dissipation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 253-255, Italy, July 26-27 2000.
- [2929]
- S. K. Marella,
S. V. Kumar, and S. S. Sapatnekar.
A holistic analysis of circuit timing variations in 3d-ics with thermal and
TSV-induced stress considerations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 317-324, San Jose, CA, November 5-8 2012.
- [2930]
- G. Mariani,
G. Palermo, V. Zaccaria, and C. Silvano.
OSCAR: an optimization methodology exploiting spatial correlation in
multicore design spaces.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(5):740-753, May 2012.
- [2931]
- E. Maricau and
G. Gielen.
Efficient variability-aware NBTI and hot carrier circuit reliability
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(12):1884-1893, December 2010.
- [2932]
- P. N. Marinos.
Derivation of minimal complete sets of test-input sequences using boolean
differences.
IEEE Transactions on Computers, C-20(1):25-32, January 1971.
- [2933]
- C. A. Marinov and
C. Budianu.
Iteratively improved bounds for RC circuits.
IEEE Transactions on Circuits and Systems - I: Fundamental Theory and
Applications, 45(6):663-666, June 1998.
- [2934]
- C. A. Marinov
and P. Neittaanmaki.
A theory of electrical circuits with resistively coupled distributive
structures: delay time predicting.
IEEE Transactions on Circuits and Systems, 35(2):173-183, February
1988.
- [2935]
- I. L. Markov,
J. Hu, and M.-C. Kim.
Progress and challenges in VLSI placement research.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 275-282, San Jose, CA, November 5-8 2012.
- [2936]
- D. Markovic,
B. Nikolic, and R. W. Brodersen.
Analysis and design of low-energy flip-flops.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 52-55, Huntington Beach, California, August 6-7 2001.
- [2937]
- G. Markowsky.
Bounding signal probabilities in combinational circuits.
IEEE Transactions on Computers, C-36(10):1247-1251, October 1987.
- [2938]
- J. P.
Marques-Silva and K. A. Sakallah.
Boolean satisfiability in electronic design automation.
In Design Automation Conference, pages 675-680, Los Angeles, CA, June
5-9 2000.
- [2939]
- H. Martin,
G. Di. Natale, and L. Entrena.
Towards a dependable true random number generator with self-repair
capabilities.
IEEE Transactions on Circuits and Systems, Part I: Regular Papers,
65(1):247-256, January 2018.
- [2940]
- A. J. Martin.
Towards an energy complexity of computation.
Information Processing Letters, 77:181-187, 2001.
- [2941]
- K. W. Martin.
Complex signal processing is not complex.
IEEE Transactions on Circuits and Systems, 51(9):1823-1836, September
2004.
- [2942]
- G. Martin.
Overview of the mpsoc design challenge.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
274-279, San Francisco, CA, July 24-28 2006.
- [2943]
- A. M. Martinez.
Quick estimation of transient currents in CMOS integrated circuits.
IEEE Journal of Solid-State Circuits, 24(2):520-531, April 1989.
- [2944]
- K. Mase.
Comments on "A measure of computation work" and "logical network cost and
entropy".
IEEE Transactions on Computers, C-27(1):94-95, January 1978.
- [2945]
- D. Maslov, G. W.
Dueck, and D. M. Miller.
Fredkin/toffoli templates for reversible logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 256-261, San Jose, CA, November 9-13 2003.
- [2946]
- K. Masselos,
P. Merakos, S. Theoharis, T. Stouraitis, and C. E. Goutis.
Power efficient data path synthesis of sum-of-products computation.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):446-450, June 2003.
- [2947]
- Y. Masuda,
M. Hashimoto, and T. Onoye.
Performance evaluation of software-based error detection mechanisms for
localizing electrical timing failures under dynamic supply noise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 315-322, Austin, TX, November 2-6 2015.
- [2948]
- P. Mateti and N. Deo.
On algorithms for enumerating all circuits of a graph.
SIAM Journal on Computing, 5(1):90-99, March 1976.
- [2949]
- T. Mattson and
M. Wrinn.
Parallel programming: can we PLEASE get it right this time?
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages 7-11,
Anaheim, CA, June 8-13 2008.
- [2950]
- P. M. Maurer.
The inversion algorithm for digital simulation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
258-261, San Jose, CA, November 6-10 1994.
- [2951]
- P. M. Maurer.
The inversion algorithm for digital simulation.
IEEE Transactions on Computer-Aided Design, 16(7):762-769, July
1997.
- [2952]
- P. M. Maurer.
Event driven simulation without loops or conditionals.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 23-26, San Jose, CA, November 5-9 2000.
- [2953]
- P. M. Maurer.
Efficient event-driven simulation by exploiting the output observability of
gate clusters.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(11):1471-1486, November 2003.
- [2954]
- P. Maurine,
M. Rezzoug, N. Azemard, and D. Auvergne.
Transition time modeling in deep submicron CMOS.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(11):1352-1363, November 2002.
- [2955]
- K. Mayaram,
D. C. Lee, S. Moinian, D. Rich, and J. Roychowdhury.
Overview of computer-aided analysis tools for RFIC simulation: algorithms,
features, and limitations.
In IEEE 1997 Custom Integrated Circuits Conference, pages 505-512,
Santa Clara, CA, May 5-8 1997.
- [2956]
- K. Mayaram.
Output voltage analysis for the MOS colpitts oscillator.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 47(2):260-263, February 2000.
- [2957]
- P. S. Maybeck.
Stochastic Models, Estimation and Control (Vol. 1).
Academic Press, New York, NY, 1979.
- [2958]
- P. S. Maybeck.
Stochastic Models, Estimation and Control (Vol. 2).
Academic Press, New York, NY, 1979.
- [2959]
- C. C. McAndrew.
Statistical modeling for circuit simulation.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 357-362, San Jose, CA, March 24-26 2003.
- [2960]
- C. C. McAndrew.
Statistical modeling for circuit simulation.
In IEEE International Symposium on Quality Electronic Design (ISQED),
San Jose, CA, March 24-26 2003.
- [2961]
- E. McCluskey.
Logic Design Principles.
Prentice Hall, Englewood Cliffs, NJ, 1986.
- [2962]
- T. McConaghy and
G. G. E. Gielen.
Globally reliable variation-aware sizing of analog intergated circuits via
response surfaces and structural homotopy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(11):1627-1640, November 2009.
- [2963]
- S. McCormick and
J. Allen.
Waveform moment methods for improved interconnection analysis.
In 27th ACM/IEEE Design Automation Conference, pages 406-412,
Orlando, FL, June 24-28 1990.
- [2964]
- C. B. McDonald and
R. E. Bryant.
Symbolic functional and timing verification of transistor-level circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
526-530, San Jose, CA, November 7-11 1999.
- [2965]
- C. B. McDonald and
R. E. Bryant.
CMOS circuit verification with symbolic switch-level timing simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(3):458-474, March 2001.
- [2966]
- C. B. McDonald
and R. E. Bryant.
Computing logic-stage delays using circuit simulation and symbolic elmore
analysis.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
283-288, Las Vegas, NV, June 18-22 2001.
- [2967]
- C. B. McDonald
and R. E. Bryant.
A symbolic simulation-based methodology for generating black-box timing models
of custom macrocells.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 501-506, San Jose, CA, November 4-8 2001.
- [2968]
- M. C.
McFarland, A. C. Parker, and P. Camposano.
The high-level synthesis of digital systems.
In Proceedings of the IEEE, pages 301-318, February 1990.
- [2969]
- P. McGeer and
R. Brayton.
Efficient algorithms for computing the longest viable path in a combinational
network.
In 25th ACM/IEEE Design Automation Conference, pages 561-567, Las
Vegas, NV, June 25-29 1989.
- [2970]
- P. McGeer and
R. Brayton.
Timing analysis in precharge/unate networks.
In 27th ACM/IEEE Design Automation Conference, pages 124-129,
Orlando, FL, June 24-28 1990.
- [2971]
- P. C. McGeer and R. K.
Brayton.
Integrating functional and temporal domains in logic design.
Kluwer Academic Publishers, Boston, MA, 1991.
- [2972]
- R. McGowen.
Adaptive designs for power and thermal optimization.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 118-121, San Jose, CA, November 6-10 2005.
- [2973]
- C. McMullen and
J. Shearer.
Prime implicants, minimum covers, and the complexity of logic simplification.
IEEE Transactions on Computers, C-35(8):761-762, August 1986.
- [2974]
- L. McMurchie and
C. Sechen.
WTA - waveform-based timing analysis for deep submicron circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 625-631, San Jose, CA, November 10-14 2002.
- [2975]
- R. McNaughton
and H. Yamada.
Regular expressions and state graphs for automata.
IRE Transactions on Electronic Computers, EC-9(1):39-47, March
1960.
- [2976]
- J. W. McPherson
and P. B. Ghate.
A methodology for the calculation of continuous DC electromigration
equivalents from transient current waveforms.
The Electrochemical Society, Proc. Symp. on Electromigration of
Metals, pages 64-74, October 7-12 1984.
- [2977]
- J. W. McPherson.
Stress dependent activation energy.
In IEEE 24th International Reliability Physics Symposium (IRPS), pages
12-18, New York, NY, 1986.
- [2978]
- J. W. McPherson.
Scaling-induced reductions in CMOS reliability margins and the escalating
need for increased design-in reliability efforts.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 123-130, San Jose, CA, March 26-28 2001.
- [2979]
- J. W. McPherson.
Reliability challenges for 45nm and beyond.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
176-181, San Francisco, CA, July 24-28 2006.
- [2980]
- J.W. McPherson.
Reliability Physics and Engineering.
Springer, New York, NY, 2010.
- [2981]
- C. Mead and L. Conway.
Introduction to VLSI Systems.
Addison-Wesley Publishing Company, 1979.
- [2982]
- H. Mecha,
M. Fernandez, F. Tirado, J. Septien, D. Mozos, and K. Olcoz.
A method for area estimation of data-path in high level synthesis.
IEEE Transactions on Computer-Aided Design, 15(2):258-265, February
1996.
- [2983]
- G. Medeiros-Ribeiro, J. H. Nickel, and J.-J. Yang.
Progress in CMOS-memristor integration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 246-249, San Jose, CA, November 7-10 2011.
- [2984]
- W. Meeker, Jr. and
L. Escobar.
Pitfalls of accelerated testing.
IEEE Transactions on Reliability, 47(2):114-118, June 1998.
- [2985]
- P. K. Meher.
Extended sequential logic for synchronous circuit optiimization and its
applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(4):469-477, April 2009.
- [2986]
- R. Mehra,
L. Guerra, and J. Rabaey.
Exploiting locality for low-power design.
In IEEE 1996 Custom Integrated Circuits Conference, pages 401-404,
San Diego, CA, May 5-8 1996.
- [2987]
- R. Mehra, L. M.
Guerra, and J. M. Rabaey.
A partitioning scheme for optimizing interconnect power.
IEEE Journal of Solid State Circuits, 32(3):433-443, March 1997.
- [2988]
- R. Mehra and J. Rabaey.
Behavioral level power estimation and exploration.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
197-202, Napa, CA, April 24-27 1994.
- [2989]
- R. Mehra and J. Rabaey.
Exploiting regularity for low-power design.
In IEEE/ACM International Conference on Computer-Aided Design, pages
166-172, San Jose, CA, November 10-14 1996.
- [2990]
- V. Mehrotra,
S. L. Sam, D. Boning, A. Chandrakasan, R. Vallishayee, and S. Nassif.
A methodology for modeling the effects of systematic within-die interconnect
and device variations on circuit performance.
In Design Automation Conference, pages 172-175, Los Angeles, CA, June
5-9 2000.
- [2991]
- A. Mehrotra and
A. Somani.
A robust and efficient harmonic balance (HB) using direct solution of HB
jacobian.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
370-375, San Francisco, CA, July 26-31 2009.
- [2992]
- A. Mehrotra.
Noise analysis of phase-locked loops.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 277-282, San Jose, CA, November 5-9 2000.
- [2993]
- A. Mehrotra.
Noise analysis of phase-locked loops.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(9):1309-1316, September 2002.
- [2994]
- H. Mehta, R. M.
Owens, and M. J. Irwin.
Energy characterization based on clustering.
In 33rd Design Automation Conference, pages 702-707, Las Vegas, NV,
June 3-7 1996.
- [2995]
- H. Mehta, R. M.
Owens, M. J. Irwin, R. Chen, and D. Ghosh.
Techniques for low energy software.
In 1997 International Symposium on Low Power Electronics and Design,
pages 72-75, Monterey, CA, August 18-20 1997.
- [2996]
- V. J. Mehta,
M. Marek-Sadowska, K.-H. Tsai, and J. Rajski.
Diagnosis of delay defects and delay variations.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 92-97, Monterey, CA,
February 25-26 2008.
- [2997]
- T. Mei,
J. Roychowdhury, T. S. Coffey, S. A Hutchinson, and D. M. Day.
Robust, stable time-domain methods for solving mpdes of fast/slow systems.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
848-853, San Diego, CA, June 7-11 2004.
- [2998]
- T. Mei,
J. Roychowdhury, T. S. Coffey, S. A. Hutchinson, and D. M. Day.
Robust, stable time-domain methods for solving mpdes of fast/slow systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(2):226-239, February 2005.
- [2999]
- T. Mei, H. Thornquist,
E. Keiter, and S. Hutchinson.
Structure preserving reduced-order modeling of linear periodic time-varying
systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 361-366, San Jose, CA, November 7-10 2011.
- [3000]
- P. C. H. Meier,
R. A. Rutenbar, and L. R. Carley.
Exploring multiplier architecture and layout for low power.
In IEEE 1996 Custom Integrated Circuits Conference, pages 513-516,
San Diego, CA, May 5-8 1996.
- [3001]
- M. Meijer,
F. Pessolano, and J. Pineda de Gyvez.
Technology exploration for adaptive power and frequency scaling in 90nm CMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 14-19, Newport Beach, CA, August 9-11 2004.
- [3002]
- I. Meilijson and
A. Nadas.
Convex majorization with an application to the length of critical paths.
Journal of Applied Probability, 16(3):671-677, September 1979.
- [3003]
- J. D. Meindl.
A history of low power electronics: how it began and where it's headed.
In 1997 International Symposium on Low Power Electronics and Design,
pages 149-151, Monterey, CA, August 18-20 1997.
- [3004]
- S. Mele and M. Favalli.
A SAT based test generation method for delay fault testing of macro based
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(4):631-635, April 2011.
- [3005]
- M. Menezes,
R. Baldick, and L. T. Pileggi.
A sequential quadratic programming approach to concurrent gate and wire sizing.
IEEE Transactions on Computer-Aided Design, 16(8):867-881, August
1997.
- [3006]
- N. Menezes,
C. Kashyap, and C. Amin.
A true electrical cell model for timing, noise, and power grid verification.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
462-467, Anaheim, CA, June 8-13 2008.
- [3007]
- Y. Meng,
T. Sherwood, and R. Kastner.
Leakage power reduction of embedded memories on fpgas through location
assignment.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
612-617, San Francisco, CA, July 24-28 2006.
- [3008]
- X. Meng, R. Saleh,
and K. Arabi.
Layout of decoupling capacitors in IP blocks for 90-nm CMOS.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(11):1581-1588, November 2008.
- [3009]
- K.-H. Meng,
V. Shukla, and E. Rosenbaum.
Full-component modeling and simulating of charged device model ESD.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(7):1105-1113, July 2016.
- [3010]
- K. Meng and R. Joseph.
Process variation aware cache leakage management.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 262-267, Tegernsee, Germany, October 4-6 2006.
- [3011]
- S. Meninger,
J. O. Mur-Miranda, R. Amirtharajah, A. Chandrakasan, and J. H. Lang.
Vibration-to-electric energy conversion.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(1):64-76, February 2001.
- [3012]
- T. Menkad and
A. Dounavis.
Resistive coupling-based waveform relaxataion algorithm for analysis of
interconnect circuits.
IEEE Transactions on Circuits and Systems I: Regular Papers,
64(7):1877-1890, July 2017.
- [3013]
- P. Mercati,
R. Ayoub, M. Kishinevsky, E. Samson, M. Beuchat, F. Paterna, and T. S.
Rosing.
Multi-variable dynamic power management for the GPU subsystem.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [3014]
- P. Mercati,
F. Paterna, A. Bartolini, L. Benini, and T. S. Rosing.
WARM: workload-aware reliability management in linux/android.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(9):1557-1570, September 2017.
- [3015]
- M. R. Mercer.
Logic elements for universally testable circuits.
In IEEE International Test Conference, pages 493-497, Sept. 8-11
1986.
- [3016]
- D. Messerman, A. Gershtein, S. Goldenberg, and V. Tsipenyuk.
Advanced modeling techniques for accurate transistor-level timing analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 55-60, Austin, Texas,
February 26-27 2007.
- [3017]
- P. Metzgen and
D. Nancekievill.
Multiplexer restructuring for FPGA implementation cost reduction.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
421-426, Anaheim, CA, June 13-17 2005.
- [3018]
- A. V. Mezhiba and
E. G. Friedman.
Inductive characteristics of power distribution grids in high speed integrated
circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 316-321, San Jose, CA, March 18-21 2002.
- [3019]
- A. V. Mezhiba and
E. G. Friedman.
Inductive properties of high-performance power distribution grids.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):762-776, December 2002.
- [3020]
- A. V. Mezhiba and
E. G. Friedman.
Impedance characteristics of power distribution grids in nanoscale integrated
circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(11):1148-1155, November 2004.
- [3021]
- A. V. Mezhiba and
E. G. Friedman.
Scaling trends of on-chip power distribution noise.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):386-394, April 2004.
- [3022]
- N. Mi, S. X.-D.Tan,
P. Liu, J. Cui, Y. Cai, and X. Hong.
Stochastic extended krylov subspace method for variational analysis of on-chip
power grid networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 48-53, San Jose, CA, November 5-8 2007.
- [3023]
- N. Mi, J. Fan, S. X.-D.
Tan, Y. Cai, and Y. Hong.
Statistical analysis of on-chip power delivery networks considering lognormal
leakage current variations with spatial correlation.
IEEE Transactions on Circuits and Systems, 55(7):2064-2075, August
2008.
- [3024]
- N. Mi, S. X.-D. Tan,
Y. Cai, and X. Hong.
Fast variational analysis of on-chip power grids by stochastic extended krylov
subspace method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(11):1996-2006, November 2008.
- [3025]
- X. Mi, D. Mandal,
V. Sathe, B. Bakkologlu, and J.-S. Seo.
Fully-integrated switched-capacitor voltage regulator with on-chip
current-sensing and workload optimization in 32nm SOI CMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 371-376, Rome, Italy, July 22-24 2015.
- [3026]
- J. Miao, K. He,
A. Gerstlauer, and M. Orshansky.
Modeling and synthesis of quality-energy optimal approximate adders.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 728-735, San Jose, CA, November 5-8 2012.
- [3027]
- G. Micheli.
Reliable communication in systems on chips.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 77-77,
San Diego, CA, June 7-11 2004.
- [3028]
- P. Miettinen, M. Honkala, J. Roos, and M. Valtonen.
Partmor: partitioning-based realizable model-order reduction method for RLC
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(3):374-387, March 2011.
- [3029]
- P. Miettinen, M. Honkala, J. Roos, and M. Valtonen.
Sparsification of dense capacitive coupling of interconnect models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1955-1959, October 2013.
- [3030]
- F. Milano and
M. Anghel.
Impact of time delays on power system stability.
IEEE Transactions on Circuits and Systems, 59(4):889-900, April
2012.
- [3031]
- P. Miliozzi,
I. Vassiliou, E. Charbon, E. Malavasi, and A. L. Sangiovanni-Vincentelli.
Use of sensitivities and generalized substrate models in mixed-signal IC
design.
In 33rd Design Automation Conference, pages 227-232, Las Vegas, NV,
June 3-7 1996.
- [3032]
- I. R. Miller,
J. E. Freund, and R. Johnson.
Probability and Statistics for Engineers.
Prentice-Hall, Inc., Englewood Cliffs, NJ, 4th edition, 1990.
- [3033]
- G. Miller,
B. Bhattarai, Y.-C. Hsu, J. Dutt, X. Chen, and G. Bakewell.
A method to leverage pre-silicon collateral and analysis for post-silicon
testing and validation.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
575-578, San Diego, CA, June 5-9 2011.
- [3034]
- R. E. Miller.
Formal analysis and synthesis of bilateral switching networks.
IRE Transactions on Electronic Computers, pages 231-244, September
1958.
- [3035]
- Raymond E. Miller.
Switching Theory, volume 2.
John Wiley and Sons, New York, NY, 1965.
- [3036]
- D. M. Miller.
An improved method for computing a generalized spectral coefficient.
IEEE Transactions on Computer-Aided Design, 17(3):233-238, March
1998.
- [3037]
- P. Milliozzi, L. Carloni, E. Charbon, and A. L.
Sangiovanni-Vincentelli.
SUBWAVE: A methodology for modeling digital substrate noise injection.
In IEEE 1996 Custom Integrated Circuits Conference, pages 385-388,
San Diego, CA, May 5-8 1996.
- [3038]
- O. Milter and
A. Kolodny.
Crosstalk noise reduction in synthesized digital logic circuits.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(6):1153-1158, December 2003.
- [3039]
- K.-S. Min, K. Kanda,
and T. Sakurai.
Row-by-row dynamic source-line voltage control (RRDSV) scheme for two orders
of magnitude leakage current reduction of sub-1-V-VDD SRAM's.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 66-71, Seoul, Korea, August 25-27 2003.
- [3040]
- K.-S. Min, H.-D.
Choi, H.-Y. Choi, H. Kawaguchi, and T. Sakurai.
Leaking-suppressed clock-gating circuit with zigzag super cut-off CMOS
(ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-v-vdd lsis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(4):430-435, April 2006.
- [3041]
- P. Min, H. Yi,
J. Song, S. Baeg, and S. Park.
Efficient interconnect test patterns for crosstalk and static faults.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2605-2608, November 2006.
- [3042]
- S-I Minato and G. De
Micheli.
Finding all simple disjunctive decompositions using irredundant sum-of-products
forms.
In IEEE/ACM International Conference on Computer-Aided Design, pages
111-117, San Jose, CA, November 8-12 1998.
- [3043]
- E. Mintarno,
J. Skaf, R. Zheng, J. B. Velamala, Y. Cao, S. Boyd, R. W. Dutton, and
S. Mitra.
Self-tuning for maximized lifetime energy-efficiency in the presence of circuit
aging.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(5):760-773, May 2011.
- [3044]
- M. Miranda,
P. Roussel, L. Brusamarello, and G. Wirth.
Statistical characterization of standard cells using design of experiments with
response surface modeling.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
77-82, San Diego, CA, June 5-9 2011.
- [3045]
- A. Mishchenko, S. Chatterjee, and R. Brayton.
DAG-aware AIG rewriting a fresh look at combinational logic synthesis.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
532-535, San Francisco, CA, July 24-28 2006.
- [3046]
- A. Mishchenko, J.-S. Zhang, S. Sinha, J. R. Burch, R. Brayton,
and M. Chrzanowska-Jeske.
Using simulation and satisfiability to compute flexibilities in boolean
networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):743-755, May 2006.
- [3047]
- A. Mishchenko, R. Brayton, and S. Chatterjee.
Boolean factoring and decomposition of logic networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 38-44, San Jose, CA, November 10-13 2008.
- [3048]
- A. Mishchenko
and R. K. Brayton.
A theory of non-deterministic networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 709-716, San Jose, CA, November 9-13 2003.
- [3049]
- A. Mishchenko
and R. K. Brayton.
A theory of nondeterministic networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(6):977-999, June 2006.
- [3050]
- A. Mishchenko
and T. Sasao.
Large-scale SOP minimization using decomposition and functional properties.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
149-154, Anaheim, CA, June 2-6 2003.
- [3051]
- A. Mishchenko.
Fast computation of symmetries in boolean functions.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(11):1588-1593, November 2003.
- [3052]
- V. Mishra,
P. Jain, S. K. Marella, and S. S. Sapatnekar.
Incorporating the role of stress on electromigration in power grids with via
arrays.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [3053]
- V. Mishra and S. S.
Sapatnekar.
The impact of electromigration in copper interconnects on power grid integrity.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [3054]
- V. Mishra and
S. S. Sapatnekar.
Probabilistic wire resistance degradation due to electromigration in power
grids.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(4):628-640, April 2017.
- [3055]
- N. Miskov-Zivanov, J. R. Faeder, C. J. Myers, and H. M. Sauro.
Modeling and design automation of biological circuits and systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 291-293, San Jose, CA, November 5-8 2012.
- [3056]
- N. Miskov-Zivanov and D. Marculescu.
Circuit reliability analysis using symbolic techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2638-2649, December 2006.
- [3057]
- N. Miskov-Zivanov and D. Marculescu.
Formal modeling and reasoning for reliability analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
531-536, Anaheim, CA, June 13-18 2010.
- [3058]
- J. N. Mistry,
J. Myers, B. M. Al-Hashimi, D. Flynn, J. Biggs, and G. V. Merrett.
Active mode subclock power gating.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(9):1898-1908, September 2014.
- [3059]
- A. Mitev,
D. Ganesan, D. Shanmugasundaram, Y. Cao, and J.-M. Wang.
A robust finite-point based gate model considering process variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 692-697, San Jose, CA, November 5-8 2007.
- [3060]
- A. Mitev,
M. Marefat, D. Ma, and J.-M. Wang.
Principle hessian direction based parameter reduction with process variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 632-637, San Jose, CA, November 5-8 2007.
- [3061]
- A. Mitev,
M. Marefat, D. Ma, and J.-M. Wang.
Principle hessian direction-based parameter reduction for interconnect networks
with process variation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(9):1337-1347, September 2010.
- [3062]
- S. Mitra, R. A.
Rutenbar, L. R. Carley, and D. J. Allstot.
A methodology for rapid estimation of substrate-coupled switching noise.
In IEEE Custom Integrated Circuits Conference, pages 129-132, Santa
Clara, CA, May 1-4 1995.
- [3063]
- S. Mitra,
T. Karnik, N. Seifert, and M. Zhang.
Logic soft errors in sub-65nm technologies design and CAD challenges.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 2-4,
Anaheim, CA, June 13-17 2005.
- [3064]
- S. Mitra, S. A.
Seshia, and N. Nicolici.
Post-silicon validation opportunities, challenges and recent advances.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
12-17, Anaheim, CA, June 13-18 2010.
- [3065]
- R. S. Mitra.
Strategies for mainstream usage of formal verification.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
800-805, Anaheim, CA, June 8-13 2008.
- [3066]
- T. Mitsuhashi and
E. S. Kuh.
Power and ground network topology optimization for cell based vlsis.
In 29th ACM/IEEE Design Automation Conference, pages 524-529,
Anaheim, CA, June 8-12 1992.
- [3067]
- G. Mittal, D. C.
Zaratsky, X. Tang, and P. Banerjee.
Automatic translation of software binaries onto fpgas.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
389-394, San Diego, CA, June 7-11 2004.
- [3068]
- K. Miyase and
S. Kajihara.
XID: don't care identification of test patterns for combinational circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(2):321-326, February 2004.
- [3069]
- M. Miyazaki,
H. Tanaka, G. Ono, T. Nagano, and N. Ohkubo.
Electric-energy generation using variable-capacitive resonator for power-free
LSI: efficient analysis and fundamental experiment.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 193-198, Seoul, Korea, August 25-27 2003.
- [3070]
- L. Mizrukhin, J. Huey, and S. Mehta.
Prediction of product yield distributions from wafer parametric mesurements of
CMOS circuits.
IEEE Transactions on Semiconductor Manufacturing, 5(2):88-93, May
1992.
- [3071]
- F. Mo and R. K. Brayton.
Whirlpool plas: A regular logic structure and their synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 543-549, San Jose, CA, November 10-14 2002.
- [3072]
- F. Mo and R. Brayton.
PLA-based regular structures and their synthesis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(6):723-729, June 2003.
- [3073]
- B. C.
Mochocki, X.-S. Hu, and G. Quan.
A unified approach to variable voltage scheduling for nonideal DVS
processors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1370-1377, September 2004.
- [3074]
- H. D. Mogal,
H. Qian, S. S. Sapatnekar, and K. Bazargan.
Clustering based pruning for statistical criticality computation under process
variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 340-343, San Jose, CA, November 5-8 2007.
- [3075]
- H. D. Mogal,
H. Qian, S. S. Sapatnekar, and K. Bazargan.
Fast and accurate statistical criticality computation under process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(3):350-363, March 2009.
- [3076]
- V. Mohan,
T. Bunker, L. Grupp, S. Gurumurthi, M. R. Stan, and S. Swanson.
Modeling power consumption of NAND flash memories using flashpower.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(7):1031-1044, July 2013.
- [3077]
- C. R. Mohan and
P. P. Chakrabarti.
A new approach for factorizing fsms.
In IEEE/ACM International Conference on Computer-Aided Design, pages
698-701, San Jose, CA, November 6-10 1994.
- [3078]
- K. Mohanram and
J. Guo.
Graphene nanoribbon fets: technology exploration and CAD.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 412-415, San Jose, CA, November 10-13 2008.
- [3079]
- S. P. Mohanty
and N. Ranganathan.
A framework for energy and transient power reduction during behavioral
synthesis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(6):562-572, June 2004.
- [3080]
- M. Mohiyuddin, A. Prakash, A. Aziz, and W. Wolf.
Synthesizing interconnect-efficient low density parity check codes.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
488-491, San Diego, CA, June 7-11 2004.
- [3081]
- N. N.
Mojumder, S. Mukhopadhyay, J.-J. Kim, C.-T. Chuang, and K. Roy.
Self-repairing SRAM using on-chip detection and compensation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(1):75-84, January 2010.
- [3082]
- M. E. Mokari and
W. Patience.
Calculation of noise parameters by direct matrix analysis.
In 1991 IEEE International Symposium on Circuits and Systems, pages
2343-2346, June 1991.
- [3083]
- C. Moler and C. F. Van
Loan.
Nineteen dubious ways to compute the exponential of a matrix.
SIAM Review, 20(4):801-836, October 1978.
- [3084]
- C. Moler and C. F. Van
Loan.
Nineteen dubious ways to compute the exponential of a matrix, twenty-five years
later.
SIAM Review, 45(1):3-49, 2003.
- [3085]
- A. Mondal and
P. P. Chakrabarti.
Reasoning about timing behavior of digital circuits using symbolic event
propagation and temporal logic.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1793-1814, September 2006.
- [3086]
- W. S. Mong and J. Zhu.
A retargetable micro-architecture simulator.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
752-757, Anaheim, CA, June 2-6 2003.
- [3087]
- W.-S. Mong and J. Zhu.
Dynamosim: a trace-based dynamically compiled instruction set simulator.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 131-136, San Jose, CA, November 7-11 2004.
- [3088]
- F. Montagna,
A. Rahimi, S. Benatti, D. Rossi, and L. Benini.
PULP-HD: accelerating brain-inspired high-dimensional computing on a
parallel ultra-low power platform.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [3089]
- J. Monteiro,
S. Devadas, and A. Ghosh.
Retiming sequential circuits for low power.
In IEEE International Conference on Computer-Aided Design, pages
398-402, Santa Clara, CA, 1993.
- [3090]
- J. Monteiro,
S. Devadas, B. Lin, C-Y. Tsui, and M. Pedram.
Exact and approximate methods of switching activity estimation in sequential
logic circuits.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
117-122, Napa, CA, April 24-27 1994.
- [3091]
- J. Monteiro,
S. Devadas, P. Ashar, and A. Mauskar.
Scheduling techniques to enable power management.
In 33rd Design Automation Conference, pages 349-352, Las Vegas, NV,
June 3-7 1996.
- [3092]
- J. Monteiro,
S. Devadas, A. Ghosh, K. Keutzer, and J. White.
Estimation of average switching activity in combinational logic circuits using
symbolic simulation.
IEEE Transactions on Computer-Aided Design, 16(1):121-127, January
1997.
- [3093]
- J. Monteiro, S. Devadas, and A. Gosh.
Sequential logic optimization for low power using input-disabling
precomputation architectures.
IEEE Transactions on Computer-Aided Design, 17(3):279-284, March
1998.
- [3094]
- J. Monteiro and
S. Devadas.
A methodology for efficient estimation of switching activity in sequential
logic circuits.
In 31st ACM/IEEE Design Automation Conference, pages 12-17, San
Diego, CA, June 6-10 1994.
- [3095]
- J. Monteiro and
S. Devadas.
Techniques for the power estimation of sequential logic circuits under
user-specified input sequences and programs.
In ACM/IEEE International Symposium on Low Power Design, pages 33-38,
Dana Point, CA, April 23-26 1995.
- [3096]
- J. C. Monteiro
and A. L. Oliveira.
Finite state machine decomposition for low power.
In IEEE/ACM 35th Design Automation Conference, pages 758-763, San
Francisco, CA, June 15-19 1998.
- [3097]
- J. C. Monteiro
and A. L. Oliveira.
Implicit FSM decomposition applied to low-power design.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):560-565, October 2002.
- [3098]
- J. C. Garcia Montesdeoca, J. A. Montiel-Nelson, and
S. Nooshabadi.
CMOS driver-receiver pair for low-swing signaling for low energy on-chip
interconnects.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):311-316, February 2009.
- [3099]
- C. W. Moon,
H. Kriplani, and K. P. Belkhale.
Timing model extraction of hierarchical blocks by graph reduction.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
152-157, New Orleans, LA, June 10-14 2002.
- [3100]
- C. W. Moon and R. K.
Brayton.
Elimination of dynamic hazards by factoring.
In 30th ACM/IEEE Design Automation Conference, pages 7-13, Dallas,
Texas, June 14-18 1993.
- [3101]
- S.-J. Moon and A. C.
Cangellaris.
Passivity enforcement via quadratic programming for element-by-element rational
function approximation of passive network matrices.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 203-206, San Jose, CA, October 27-29 2008.
- [3102]
- A. Morgenshtein, A. Fish, and I. A. Wagner.
Gate-diffusion input (GDI): a power-efficient method for digital
combinatorial circuits.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):566-581, October 2002.
- [3103]
- A. Morgenshtein, E. G. Friedman, R. Ginosar, and A. Kolodny.
Unified logical effort - a method for delay evaluation and minimization in
logic paths with RC interconnect.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(5):689-696, May 2010.
- [3104]
- C. A. Moritz,
T. Wang, P. Narayanan, M. Leuchtenburg, Y. Guo, C. Dezan, and M. Bennaser.
Fault-tolerant nanoscale processors on semiconductor nanowire grids.
IEEE Transactions on Circuits and Systems, 54(11):2422-2437, November
2007.
- [3105]
- P. B. Morton and W. Dai.
Crosstalk noise estimation for noise management.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
659-664, New Orleans, LA, June 10-14 2002.
- [3106]
- A. Moshovos,
B. Falsafi, F. N. Najm, and N. Azizi.
A case for asymmetric-cell cache memories.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(7):877-881, July 2005.
- [3107]
- A. Moshovos.
Checkpointing alternatives for high performance, power-aware processors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 318-321, Seoul, Korea, August 25-27 2003.
- [3108]
- H. Mostafa,
M. Anis, and M. Elmasry.
Novel timing yield improvement circuits for high-performance low-power wide
fan-in dynamic OR gates.
IEEE Transactions on Circuits and Systems, 58(8):1785-1797, August
2011.
- [3109]
- H. Mostafa,
M. H. Anis, and M. Elmasry.
Analytical soft error models accounting for die-to-die and within-die
variations in sub-threshold SRAM cells.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(2):182-195, February 2011.
- [3110]
- H. Mostafa,
M. Anis, and M. Elmasry.
Statistical SRAM read access yield improvement using negative capacitance
circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(1):92-101, January 2013.
- [3111]
- K. Motohashi.
The prospects of next generation television - japans initiative to 2020 -.
In 20th Asia and South Pacific Design Automation Conference, pages
677-679, Chiba/Tokyo, Japan, January 19-22 2015.
- [3112]
- M. Mottaghi-Dastjerdi, A. Afzali-Kusha, and M. Pedram.
BZ-FAD: a low-power low-area multiplier based on shift-and-add
architecture.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):302-306, February 2009.
- [3113]
- Z. Moudallal and
F. N. Najm.
Generating circuit current constraints to guarantee power grid safety.
In 20th Asia and South Pacific Design Automation Conference, pages
358-365, Chiba/Tokyo, Japan, January 19-22 2015.
- [3114]
- Z. Moudallal and
F. N. Najm.
Generating current budgets to guarantee power grid safety.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(11):1914-1927, November 2016.
- [3115]
- Z. Moudallal and
F. N. Najm.
Generating current constraints to guarantee RLC power grid safety.
ACM Transactions on Design Automation of Electronic Systems (TODAES),
22(4):66:1-66:39, June 2017.
- [3116]
- Z. Moudallal and
F. N. Najm.
Power scheduling with active power grids.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 466-473, Irvine, CA, November 13-16 2017.
- [3117]
- Z. Moudallal and
F. N. Najm.
Power scheduling with active RC power grids.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
27(2):444-457, February 2019.
- [3118]
- V. Mrazek, S. S.
Sarwar, L. Sekanina, Z. Vasicek, and K. Roy.
Design of power-efficient approximate multipliers for approximate artificial
neural networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [3119]
- S.-P. Mu, W.-H. Chang,
M.-C.-T. Chao, Y.-M. Wang, M.-T. Chang, and M.-H. Tsai.
Statistical methodology to identify optimal placement of on-chip process
monitors for predicting fmax.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [3120]
- Z. Mu.
Discussing impedance distribution with multiple stimulating sources in power
distribution system design and simulation.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 103-106, San Jose, CA, October 27-29 2008.
- [3121]
- T. Mudge.
Power: A first-class architectural design constraint.
IEEE Computer, pages 52-58, April 2001.
- [3122]
- E. I. Muehldorf
and A. D. Savkar.
LSI logic testing - an overview.
IEEE Transactions on Computers, C-30(1):1-17, January 1981.
- [3123]
- E. I. Muehldorf
and T. W. Williams.
Analysis of the switching behavior of combinational logic networks.
In IEEE International Test Conference, pages 379-390, Nov. 15-18
1982.
- [3124]
- D. Mueller-Gritschneder, U. Sharif, and U. Schlichtmann.
Performance and accuracy in soft-error resilience evaluation using the
multi-level processor simulator ETISS-ML.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [3125]
- M. L. Mui,
K. Banerjee, and A. Mehrotra.
Power supply optimization in sub-130 nm leakage dominant technologies.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 409-414, San Jose, CA, March 22-24 2004.
- [3126]
- M.-L. Mui,
K. Banerjee, and A. Mehrotra.
Supply and power optimization in leakage-dominant technologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(9):1362-1371, September 2005.
- [3127]
- T. Mukherjee, G. K. Fedder, D. Ramaswamy, and J. White.
Emerging simulation approaches for micromachined devices.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1572-1589, December 2000.
- [3128]
- P. Mukherjee, G.-P. Fang, R. Burt, and P. Li.
Automatic stability checking for large linear analog integrated circuits.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
304-309, San Diego, CA, June 5-9 2011.
- [3129]
- S. Mukherjee and
S. Roy.
Nearly-2-SAT solutions for segmented-channel routing.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(1):128-140, January 2016.
- [3130]
- T. Mukherjee.
Design automation issues for biofluidic microchips.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 463-470, San Jose, CA, November 6-10 2005.
- [3131]
- S. Mukhopadhyay, C. Neau, R. T. Cakici, A. Agarwal, C. H. Kim,
and K. Roy.
Gate leakage reduction for scaled devices using transistor stacking.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):716-730, August 2003.
- [3132]
- S. Mukhopadhyay, A. Raychowdhury, and K. Roy.
Accurate estimation of total leakage current in scaled CMOS logic circuits
based on compact current modeling.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
169-174, Anaheim, CA, June 2-6 2003.
- [3133]
- S. Mukhopadhyay, H. Mahmoodi, and K. Roy.
Statistical design and optimization of SRAM cell for yield enhancement.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 10-13, San Jose, CA, November 7-11 2004.
- [3134]
- S. Mukhopadhyay, H. Mahmoodi, and K. Roy.
Modeling of failure probability and statistical design of SRAM array for
yield enhancement in nanoscaled CMOS.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(12):1859-1880, December 2005.
- [3135]
- S. Mukhopadhyay, A. Raychowdhury, and K. Roy.
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits
based on device geometry and doping profile.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):363-381, March 2005.
- [3136]
- S. Mukhopadhyay, S. Bhunia, and K. Roy.
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS
logic circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(8):1486-1495, August 2006.
- [3137]
- S. Mukhopadhyay, K. Kim, C.-T. Chuang, and K. Roy.
Modeling and analysis of leakage currents in double-gate technologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2052-2061, October 2006.
- [3138]
- S. Mukhopadhyay and K. Roy.
Modeling and estimation of total leakage current in nano-scaled CMOS devices
considering the effect of parameter variation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 172-175, Seoul, Korea, August 25-27 2003.
- [3139]
- A. Mukhopadhyay.
Complete sets of logic primitives.
In A. Mukhopadhyay, editor, Recent Developments in Switching Theory,
pages 1-26. Academic Press, New York, NY, 1971.
- [3140]
- S. Mukhopadhyay.
A generic data-driven nonparametric framework for variability analysis of
integrated circuits in nanometer technologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(7):1038-1046, July 2009.
- [3141]
- A. V. Mule, E. N.
Glytsis, T. K. Gaylord, and J. D. Meindl.
Electrical and optical clock distribution networks for gigascale
microprocessors.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):582-594, October 2002.
- [3142]
- R. S. Muller and
Theodore Kamins.
Device Electronics for Integrated Circuits.
John Wiley & Sons, 1986.
- [3143]
- D. E. Muller.
Treatment of transition signals in electronic switching circuits by algebraic
methods.
IRE Transactions on Electronic Computers, EC-8(3):401, September
1959.
- [3144]
- T. Munakata,
S. Sinha, and W. L. Ditto.
Chaos computing: implementation of fundamental logical gates by chaotic
elements.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(11):1629-1633, November 2002.
- [3145]
- H. Murata and E. S. Kuh.
Sequence-pair based placement method for hard/soft/pre-placed modules.
In ACM/IEEE International Symposium on Physical Design, pages
167-172, Monterey, CA, April 6-8 1998.
- [3146]
- R. Murgai, R. K.
Brayton, and A. Sangiovanni-Vincentelli.
On clustering for minimum delay/area.
In IEEE International Conference on Computer-Aided Design, pages 6-9,
Santa Clara, CA, November 11-14 1991.
- [3147]
- R. Murgai, R. K.
Brayton, and A. Sangiovanni-Vincentelli.
Decomposition of logic functions for minimum transition activity.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
33-38, Napa, CA, April 24-27 1994.
- [3148]
- R. Murgai,
M. Fujita, and A. Oliveira.
Using complementation and resequencing to minimize transitions.
In IEEE/ACM 35th Design Automation Conference, pages 694-697, San
Francisco, CA, June 15-19 1998.
- [3149]
- T. Murgan,
M. Momeni, A. Garcia Ortiz, and M. Glesner.
A high-level compact pattern-dependent delay model for high-speed
point-to-point interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 323-328, San Jose, CA, November 5-9 2006.
- [3150]
- B. Murmann and
W. Xiong.
Design of analog circuits using organic field-effect transistors.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 504-507, San Jose, CA, November 7-11 2010.
- [3151]
- Saburo Muroga.
Logic Design and Switching Theory.
John Wiley & Son, New York, NY, 1979.
- [3152]
- A. K.
Murugavel, N. Ranganathan, R. Chandramouli, and S. Chavali.
Least-square estimation of average power in digital CMOS circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(1):55-58, February 2002.
- [3153]
- A. K.
Murugavel and N. Ranganathan.
Petri net modeling of gate and interconnect delays for power estimation.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
455-460, New Orleans, LA, June 10-14 2002.
- [3154]
- A. K.
Murugavel and N. Ranganathan.
A game theoretic approach for power optimization during behavioral synthesis.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(6):1031-1043, December 2003.
- [3155]
- A. K.
Murugavel and N. Ranganathan.
Petri net modeling of gate and interconnect delays for power estimation.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(5):921-927, October 2003.
- [3156]
- A. Mutlu, J. Le,
R. Molina, and M. Celik.
A parametric approach for handling local variation effects in timing analysis.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
126-129, San Francisco, CA, July 26-31 2009.
- [3157]
- M. Mutyam.
Selective shielding: a crosstalk-free bus encoding technique.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 618-621, San Jose, CA, November 5-8 2007.
- [3158]
- M. Mutyam.
Fibonacci codes for crosstalk avoidance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(10):1899-1903, October 2012.
- [3159]
- G. Nabaa,
N. Azizi, and F. N. Najm.
An adaptive FPGA architecture with process variation compensation and reduced
leakage.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
624-629, San Francisco, CA, July 24-28 2006.
- [3160]
- G. Nabaa and F. N. Najm.
Minimization of delay sensitivity to process induced voltage threshold
variations.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 171-174, Quebec City, Quebec, June 19-22 2005.
- [3161]
- A. Nabavi-Lishi and N. Rumin.
Delay and bus current evaluation in CMOS logic circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
198-203, Santa Clara, CA, November 8-12 1992.
- [3162]
- K. Nabors, T-T
Fang, H-W Chang, K. S. Kundert, and J. K. White.
Lumped interconnect models via gaussian quadrature.
In 34th Design Automation Conference, pages 40-45, Anaheim, CA, June
9-13 1997.
- [3163]
- K. Nabors and J. White.
Fastcap: A multipole accelerated 3-D capacitance extraction program.
IEEE Transactions on Computer-Aided Design, 10(11):1447-1459,
November 1991.
- [3164]
- J. A. Nachlas,
C. R. Cassady, and K. F. Rooney.
Hazard-function implications of stochastic-deterioration and distributed-defect
concentrations.
In Annual Reliability and Maintainability Symposium, pages 213-216,
Washington, DC, January 16-19 1995.
- [3165]
- S. Nadarajah and
S. Kotz.
Exact distribution of the max/min of two gaussian random variables.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(2):210-212, February 2008.
- [3166]
- A. Nadas.
Probabilistic PERT.
IBM Journal of Research and Development, 23(3):339-347, May 1979.
- [3167]
- A. Nadas.
Random critical paths.
In IEEE International Symposium on Circuits and Systems, pages 32-35,
1980.
- [3168]
- A. Naeemi,
Y. Joshi, F. Fedorov, P. Kohl, and J. D. Meindl.
The urgency of deep sub-ambient cooling for gigascale integration.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 171-174, Austin, TX, May 9 - 11 2005.
- [3169]
- A. Naeemi and J. D.
Meindl.
Physical models for electron transport in graphene nanoribbons and their
junctions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 400-405, San Jose, CA, November 10-13 2008.
- [3170]
- S. Naffziger, T. Grutkowski, and B. Stackhouse.
The implementation of a 2-core, multi-threaded itanium family processor.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 43-48, Austin, TX, May 9 - 11 2005.
- [3171]
- M. Nagata.
On-chip measurements complementary to design flows for integrity in socs.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
400-403, San Diego, CA, June 4-8 2007.
- [3172]
- B. Nagy and M. Matolcsi.
Algorithm for positive realization of transfer functions.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(5):699-702, May 2003.
- [3173]
- A. Nahir,
M. Dusanapudi, S. Kapoor, K. Reick, W. Roesner, K.-D. Schubert, K. Sharp, and
G. Wetli.
Post-silicon validation of the IBM power8 processor.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [3174]
- M. H. Najafi,
D. J. Lilja, and M. Riedel.
Deterministic methods for stochastic computing using low-discrepancy sequences.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [3175]
- F. Najm, R. Burch,
P. Yang, and I. Hajj.
CREST - A current estimator for CMOS circuits.
In IEEE International Conference on Computer-Aided Design, pages
204-207, Santa Clara, CA, Nov. 7-10 1988.
- [3176]
- F. Najm, I. Hajj,
and P. Yang.
Computation of bus current variance for reliability estimation of VLSI
circuits.
In IEEE International Conference on Computer-Aided Design, pages
202-205, Santa Clara, CA, November 5-9 1989.
- [3177]
- F. Najm, I. Hajj,
and P. Yang.
Electromigration median time-to-failure based on a stochastic current waveform.
In 1989 IEEE International Conference on Computer Design, pages
447-450, Cambridge, MA, October 2-4 1989.
- [3178]
- F. Najm, R. Burch,
P. Yang, and I. Hajj.
Probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Transactions on Computer-Aided Design, 9(4):439-450, April
1990.
- [3179]
- F. Najm, I. Hajj,
and P. Yang.
An extension of probabilistic simulation for reliability analysis of CMOS
VLSI circuits.
IEEE Transactions on Computer-Aided Design, 10(11):1372-1381,
November 1991.
- [3180]
- F. N. Najm,
S. Goel, and I. N. Hajj.
Power estimation in sequential circuits.
In 32nd Design Automation Conference, pages 635-640, San Francisco,
CA, June 12-16 1995.
- [3181]
- F. N. Najm,
N. Menezes, and I. A. Ferzli.
A yield model for integrated circuits and its application to statistical timing
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(3):574-591, March 2007.
- [3182]
- F. Najm and I. Hajj.
The complexity of fault detection in MOS VLSI circuits.
IEEE Transactions on Computer-Aided Design, 9(9):995-1001, September
1990.
- [3183]
- F. Najm and I. Hajj.
Probabilistic simulation of very large scale integrated circuits and systems.
In 1990 Bilkent International Conference on New Trends in Communication,
Control, and Signal Processing, Bilkent University, Ankara, Turkey, July
2-5 1990.
- [3184]
- F. N. Najm and N. Menezes.
Statistical timing analysis based on a timing yield model.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
460-465, San Diego, CA, June 7-11 2004.
- [3185]
- F. N. Najm and M. Y. Zhang.
Extreme delay sensitivity and the worst-case switching activity in VLSI
circuits.
In 32nd Design Automation Conference, pages 623-627, San Francisco,
CA, June 12-16 1995.
- [3186]
- F. Najm.
Transition density, a stochastic measure of activity in digital circuits.
In 28th ACM/IEEE Design Automation Conference, pages 644-649, San
Francisco, CA, June 17-21 1991.
- [3187]
- F. Najm.
Transition density : a new measure of activity in digital circuits.
IEEE Transactions on Computer-Aided Design, 12(2):310-323, February
1993.
- [3188]
- F. Najm.
Improved estimation of the switching activity for reliability prediction in
VLSI circuits.
In IEEE 1994 Custom Integrated Circuit Conference, pages 429-432, San
Diego, CA, May 1-4 1994.
- [3189]
- F. Najm.
A survey of power estimation techniques in VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2(4):446-455, December 1994.
- [3190]
- F. N. Najm.
Low-pass filter for computing the transition density in digital circuits.
IEEE Transactions on Computer-Aided Design, 13(9):1123-1131,
September 1994.
- [3191]
- F. N. Najm.
Feedback, correlation, and delay concerns in the power estimation of VLSI
circuits.
In 32nd Design Automation Conference, pages 612-617, San Francisco,
CA, June 12-16 1995.
- [3192]
- F. N. Najm.
Power estimation techniques for integrated circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
492-499, San Jose, CA, November 5-9 1995.
- [3193]
- F. N. Najm.
Towards a high-level power estimation capability.
In ACM/IEEE International Symposium on Low Power Design, pages 87-92,
Dana Point, CA, April 23-26 1995.
- [3194]
- F. N. Najm.
On the need for statistical timing analysis.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
764-765, Anaheim, CA, June 13-17 2005.
- [3195]
- F. N. Najm.
Circuit Simulation.
John Wiley & Sons, Inc., Hoboken, NJ, 2010.
- [3196]
- F. N. Najm.
Overview of vectorless/early power grid verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 670-677, San Jose, CA, November 5-8 2012.
- [3197]
- F. N. Najm.
Physical design challenges in the chip power distribution network.
In ACM International Symposium on Physical Design 2015, page 101,
Monterey, California, March 29 - April 1 2015.
- [3198]
- S. Nakatake,
K. Sakanushi, Y. Kajitani, and M. Kawakita.
The channeled-BSG: A universal floorplan for simultaneous place/route with
IC applications.
In IEEE/ACM International Conference on Computer-Aided Design, pages
418-425, San Jose, CA, November 8-12 1998.
- [3199]
- Y. Nakatsukasa and R. W. Freund.
Computing fundamental matrix decompositions accurately via the matrix sign
function in two iterations: the power of zolotarev's functions.
SIAM Review, 58(3):461-493, September 2016.
- [3200]
- N. Nakhla,
M. Nakhla, and R. Achar.
Sparse and passive reduction of massively coupled large multiport
interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 622-626, San Jose, CA, November 5-8 2007.
- [3201]
- A. Nalamalpu, S. Srinivasan, and W. P. Burleson.
Boosters for driving long onchip interconnects - design issues, interconnect
synthesis, and comparison with repeaters.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(1):50-62, January 2002.
- [3202]
- G.-J. Nam, S. Reda,
C. J. Alpert, P. G. Villarrubia, and A. B. Kahng.
A fast hierarchical quadratic placement algorithm.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(4):678-691, April 2006.
- [3203]
- A. Namazi,
M. Nourani, and M. Saquib.
A fault-tolerant interconnect mechanism for NMR nanoarchitectures.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(10):1433-1446, October 2010.
- [3204]
- A. Namazi and
M. Nourani.
Distributed voting for fault-tolerant nanoscale systems.
In IEEE International Conference on Computer Design (ICCD-07), pages
568-573, October 2007.
- [3205]
- A. Namazi and
M. Nourani.
Gate-level redundancy: a new design-for-reliability paradigm for
nanotechnologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(5):775-786, May 2010.
- [3206]
- A. Nani and
R. Marculescu.
System-level power/performance analysis for embedded systems design.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
599-604, Las Vegas, NV, June 18-22 2001.
- [3207]
- Simon Napper.
Static timing analysis - a demanding solution.
Electronic Engineering, pages 35-42, January 1996.
- [3208]
- M. Narasimhan and J. Ramanujan.
Improving the computational performance of ILP-based problems.
In IEEE/ACM International Conference on Computer-Aided Design, pages
593-596, San Jose, CA, November 8-12 1998.
- [3209]
- A. Narayan,
J. Jain, M. Fujita, and A. L. Sangiovanni-Vincentelli.
Partitioned robdds - A compact, canonical and efficiently manipulable
representation for boolean functions.
In IEEE/ACM International Conference on Computer-Aided Design, pages
547-554, San Jose, CA, November 10-14 1996.
- [3210]
- U. Narayanan, H. W. Leong, K.-S. Chung, and C. L. Liu.
Low power multiplexer decomposition.
In 1997 International Symposium on Low Power Electronics and Design,
pages 269-274, Monterey, CA, August 18-20 1997.
- [3211]
- U. Narayanan, P. Pan, and C. L. Liu.
Low power logic synthesis under a general delay model.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 209-214, Monterey, CA, August 10-12 1998.
- [3212]
- U. K. Narayanan and
C. L. Liu.
Low power logic synthesis for XOR based circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
570-574, San Jose, CA, November 9-13 1997.
- [3213]
- A. Nardi,
A. Neviani, E. Zanoni, M. Quarantelli, and C. Guardiani.
Impact of unrealistic worst case modeling on the performance of VLSI circuits
in deep submicron CMOS technologies.
IEEE Transactions on Semiconductor Manufacturing, 12(4):396-402,
November 1999.
- [3214]
- A. Nardi,
A. Neviani, and C. Guardiani.
Realistic worst-case modeling by performance level principal component
analysis.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 455-459, San Jose, CA, March 20-22 2000.
- [3215]
- A. Nardi, H. Zeng,
J. L. Garrett, L. Daniel, and A. L. Sangiovanni-Vincentelli.
A methodology for the computation of an upper bound and noise current spectrum
of CMOS switching activity.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 778-785, San Jose, CA, November 9-13 2003.
- [3216]
- A. Nardi,
E. Tuncer, S. Naidu, A. Antonau, S. Gradinaru, T. Lin, and J. Song.
Use of statistical timing analysis on real designs.
Design, Automation and Test in Europe (DATE-07), pages 1605-1610,
April 16-20 2007.
- [3217]
- A. Nardi and A. Armato.
Functional safety methodologies for automotive applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 956-961, Irvine CA, November 13-16 2017.
- [3218]
- S. Narendra,
S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan.
Scaling of stack effect and its application for leakage reduction.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 195-200, Huntington Beach, California, August 6-7
2001.
- [3219]
- S. Narendra,
V. De, S. Borkar, D. Antoniadis, and A. Chandrakasan.
Full-chip sub-threshold leakage power prediction model for sub-0.18um CMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 19-23, Monterey, California, August 12-14 2002.
- [3220]
- E. Naroska,
S.-J. Ruan, U. Schwiegelshohn, and F. Lai.
Optimal permutation and spacing for unbiased random, counter, and instruction
address buses.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 111-114, Quebec City, Quebec, June 19-22 2005.
- [3221]
- E. Naroska,
S.-J. Ruan, and U. Schwiegelshohn.
Simultaneously optimizing crosstalk and power for instruction bus coupling
capacitance using wire pairing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(4):421-425, April 2006.
- [3222]
- H. Naseri and
S. Timarchi.
Low-power and fast full adder by exploring new XOR and XNOR gates.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
26(8):1481-1493, August 2018.
- [3223]
- N. Nassif, M. P.
Desai, and D. H. Hall.
Robust elmore delay models suitable for full chip timing verification of a 600
mhz CMOS microprocessor.
In IEEE/ACM 35th Design Automation Conference, pages 230-235, San
Francisco, CA, June 15-19 1998.
- [3224]
- S. Nassif,
D. Jamsek, A. Devgan, and T. Nguyen.
Timing uncertainty in SOI.
In ACM/IEEE 1999 International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU-99), pages 103-108,
Monterey, CA, March 8-9 1999.
- [3225]
- S. R. Nassif,
D. Boning, and N. Hakim.
The care and feeding of your statistical static timer.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 138-139, San Jose, CA, November 7-11 2004.
- [3226]
- S. R. Nassif and
J. N. Kozhaya.
Fast power grid simulation.
In Design Automation Conference, pages 156-161, Los Angeles, CA, June
5-9 2000.
- [3227]
- S. R. Nassif.
Design for variability in DSM technologies.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 451-454, San Jose, CA, March 20-22 2000.
- [3228]
- S. R. Nassif.
The impact of variability on power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 350-350, Newport Beach, CA, August 9-11 2004.
- [3229]
- S. R. Nassif.
Model to hardware matching for nano-meter scale technologies.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 203-206, Tegernsee, Germany, October 4-6 2006.
- [3230]
- S. R. Nassif.
Power grid analysis benchmarks.
In 13th Asia and South Pacific Design Automation Conference
(ASPDAC-08), pages 376-381, Seoul, Korea, January 21-24 2008.
- [3231]
- K. Natarajan, H. Hanson, S. W. Keckler, C. R. Moore, and
D. Burger.
Microprocessor pipeline energy analysis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 282-287, Seoul, Korea, August 25-27 2003.
- [3232]
- S. Nazarian,
H. Fatemi, and M. Pedram.
Accurate timing and noise analysis for combinational and sequential logic cells
using current source modeling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(1):92-103, January 2011.
- [3233]
- C. Neau and K. Roy.
Optimal body bias selection for leakage improvement and process compensation
over different technology generations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 116-121, Seoul, Korea, August 25-27 2003.
- [3234]
- J. A. Nedler and R. Mead.
A simplex method for function minimization.
Computer Journal, 7:308-313, 1965.
- [3235]
- N. Nedovic and
V. G. Oklobdzija.
Dual-edge triggered storage elements and clocking strategy for low-power
systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(5):577-590, May 2005.
- [3236]
- Wayne Nelson.
Acclerated Testing, Statistical Models, Test Plans, and Data Analyses.
John Wiley & Sons, New York, NY, 1990.
- [3237]
- W. B. Nelson.
A bibliography of accelerated test plans.
IEEE Transactions on Reliability, 54(2):194-197, June 2005.
- [3238]
- W. B. Nelson.
A bibliography of accelerated test plans part II - references.
IEEE Transactions on Reliability, 54(3):370-373, September 2005.
- [3239]
- M. Nemani and F. N.
Najm.
High-level power estimation and the area complexity of boolean functions.
In International Symposium on Low Power Electronics and Design, pages
329-334, Monterey, CA, August 12-14 1996.
- [3240]
- M. Nemani and F. N.
Najm.
Towards a high-level power estimation capability.
IEEE Transactions on Computer-Aided Design, 15(6):588-598, June
1996.
- [3241]
- M. Nemani and F. N.
Najm.
High-level area and power estimation for VLSI circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
114-119, San Jose, CA, November 9-13 1997.
- [3242]
- M. Nemani and F. N.
Najm.
High-level area prediction for power estimation.
In IEEE 1997 Custom Integrated Circuits Conference, pages 483-486,
Santa Clara, CA, May 5-8 1997.
- [3243]
- M. Nemani and F. N. Najm.
Delay estimation of VLSI circuits from a high-level view.
In IEEE/ACM 35th Design Automation Conference, pages 591-594, San
Francisco, CA, June 15-19 1998.
- [3244]
- M. Nemani and F. N. Najm.
High-level area and power estimation for VLSI circuits.
IEEE Transactions on Computer-Aided Design, 18(6):697-713, June
1999.
- [3245]
- M. Nemani and
V. Tiwari.
Macro-driven circuit design methodology for high-performance datapaths.
In Design Automation Conference, pages 661-666, Los Angeles, CA, June
5-9 2000.
- [3246]
- K. Nepal, R. I.
Bahar, B. J. Mundy, W. R. Patterson, and A. Zaslavsky.
Designing logic circuits for probabilistic computation in the presence of
noise.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
485-490, Anaheim, CA, June 13-17 2005.
- [3247]
- K. Neshatpour, W. Burleson, and A. Khajeh.
Enhancing power, performance, and energy efficiency in chip multiprocessors
exploring inverse thermal dependence.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
26(4):778-791, April 2018.
- [3248]
- M. S. Nesro,
L. Sun, and I. M. Elfadel.
Compact modeling of microbatteries using behavioral linearization and
model-order reduction.
In 20th Asia and South Pacific Design Automation Conference, pages
713-718, Chiba/Tokyo, Japan, January 19-22 2015.
- [3249]
- A. R.
Newton and A. L. Sangiovanni-Vincentelli.
Relaxation-based electrical simulation.
IEEE Transactions on Electron Devices, ED-30(9):1184-1207, September
1983.
- [3250]
- A. R. Newton.
Timing, logic, and mixed-mode simulation for large MOS integrated circuits.
In P. Antognetti, D. O. Pederson, and H. De Man, editors, Computer design
aids for VLSI circuits, pages 175-239. Sijthoff & Noordhoff, Alphen
aan de Rijn, The Netherlands; Rockville, MD, USA, 1981.
- [3251]
- H.-T. Ng and D. J. Allstot.
CMOS current steering logic for low-voltage mixed-signal integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
5(3):301-308, September 1997.
- [3252]
- K. Ng.
Challenges in using system-level models for RTL verification.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
812-815, Anaheim, CA, June 8-13 2008.
- [3253]
- E. Ngoya,
J. Rousset, and J. J. Obregon.
Newton-raphson iteration speed-up algorithm for the solution of nonlinear
circuit equations in general-purpose CAD programs.
IEEE Transactions on Computer-Aided Design, 16(6):638-644, June
1997.
- [3254]
- T. Nguyen,
P. Feldmann, S. W. Director, and R. A. Rohrer.
SPECS simulation validation with efficient transient sensitivity.
In IEEE International Conference on Computer-Aided Design, pages
252-255, 1989.
- [3255]
- T. V. Nguyen,
A. Devgan, and A. Sadigh.
Simulation of coupling capacitances using matrix partitioning.
In IEEE/ACM International Conference on Computer-Aided Design, pages
12-18, San Jose, CA, November 8-12 1998.
- [3256]
- D. Nguyen,
A. Davare, M. Orshansky, D. Chinnery, B. Thompson, and K. Keutzer.
Minimization of dynamic and static power through joint assignment of threshold
voltages and sizing optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 158-163, Seoul, Korea, August 25-27 2003.
- [3257]
- T. V. Nguyen and J. Li.
Multipoint pade approximation using a rational block lanczos algorithm.
In IEEE/ACM International Conference on Computer-Aided Design, pages
72-75, San Jose, CA, November 9-13 1997.
- [3258]
- H. T. Nguyen and
Y. Yagil.
A systematic approach to SER estimation and solutions.
In International Reliability Physics Symposium (IRPS), pages 60-70,
Dallas, TX, March 30-April 4 2003.
- [3259]
- M. Ni and S. O. Memik.
Leakage power-aware clock skew scheduling: converting stolen time into leakage
power reduction.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
610-613, Anaheim, CA, June 8-13 2008.
- [3260]
- M. Ni and S. O. Memik.
A fast heuristic algorithm for multidomain clock skew scheduling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(4):630-637, April 2010.
- [3261]
- M. Nicolaidis, N. Achouri, and S. Boutobza.
Dynamic data-bit memory built-in self-repair.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 588-594, San Jose, CA, November 9-13 2003.
- [3262]
- Y.-T. Nieh, S.-H.
Huang, and S.-Y. Hsu.
Minimizing peak current via opposite-phase clock tree.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
182-185, Anaheim, CA, June 13-17 2005.
- [3263]
- M. Niemier,
M. Crocker, X.-S. Hu, and M. Lieberman.
Using CAD to shape experiments in molecular QCA.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 907-914, San Jose, CA, November 5-9 2006.
- [3264]
- M. T. Niemier,
X.-S. Hu, M. Alam, G. Bernstein, W. Porod, M. Putney, and J. DeAngelis.
Clocking structures and power analysis for nanomagnet-based logic devices.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 26-31, Portland, Oregon, August 27-29 2007.
- [3265]
- S. Nikolaidis, E. Karaolis, and E. D. Kyriakis-Bitzaros.
Estimation of signal transition activity in FIR filters implemented by a
MAC architecture.
IEEE Transactions on Computer-Aided Design, 19(1):164-169, January
2000.
- [3266]
- S. Nikolaidis and A. Chatzigeorgiou.
Modeling the transistor chain operation in CMOS gates for short channel
devices.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 46(10):1191-1202, October 1999.
- [3267]
- B. Nikolic,
J.-H. Park, J. Kwak, B. Giraud, Z. Guo, L.-T. Pang, S.-O. Toh, R. Jevtic,
K. Qian, and C. Spanos.
Technology variability from a design perspective.
IEEE Transactions on Circuits and Systems, 58(9):1996-2009, September
2011.
- [3268]
- L. Ning, T. T.
Georgiou, A. Tannenbaum, and S. P. Boyd.
Linear models based on noisy data and the frisch scheme.
SIAM Review, 57(2):167-197, June 2015.
- [3269]
- D. Niu, Y. Chen,
C. Xu, and Y. Xie.
Impact of process variations on emerging memristor.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
877-882, Anaheim, CA, June 13-18 2010.
- [3270]
- M. Nizam, F. N.
Najm, and A. Devgan.
Power grid voltage integrity verification.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 239-244, San Diego, CA, August 8-10 2005.
- [3271]
- V. Nookala,
Y. Chen, D. J. Lilja, and S. S. Sapatnekar.
Microarchitecture-aware floorplanning using a statistical design of experiments
approach.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
579-584, Anaheim, CA, June 13-17 2005.
- [3272]
- T. Nopper,
C. Scholl, and B. Becker.
Computation of minimal counterexamples by using black box techniques and
symbolic methods.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 273-280, San Jose, CA, November 5-8 2007.
- [3273]
- K. Nose, S.-I.
Chae, and T. Sakurai.
Voltage dependent gate capacitance and its impact in estimating power and delay
of CMOS digital circuits with low supply voltage.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 228-230, Italy, July 26-27 2000.
- [3274]
- K. Nose and T. Sakurai.
Analysis and future trend of short-circuit power.
IEEE Transactions on Computer-Aided Design, 19(9):1023-1030,
September 2000.
- [3275]
- W. Noth and R. Kolla.
Node normalization and decomposition in low power technology mapping.
In 1997 International Symposium on Low Power Electronics and Design,
pages 275-280, Monterey, CA, August 18-20 1997.
- [3276]
- B. Nouri, M. S.
Nakhla, and R. Achar.
Optimum order estimation of reduced macromodels based on a geometric approach
for projection-based MOR methods.
IEEE Transactions on Components, Packaging and Manufacturing
Technology, 3(7):1218-1227, July 2013.
- [3277]
- A. Nourivand, C. Wang, and M. O. Ahmad.
A VHDL-based technique for an accurate estimation of leakage power in digital
CMOS circuits.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 47-50, Quebec City, Quebec, June 19-22 2005.
- [3278]
- S. Novakovsky, S. Shyman, and Z. Hanna.
High capacity and automatic functional extraction tool for industrial VLSI
circuit designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 520-525, San Jose, CA, November 10-14 2002.
- [3279]
- M. Nowak and
R. Radojcic.
Are there economic benefits in DFM.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
767-768, Anaheim, CA, June 13-17 2005.
- [3280]
- N. NS, F. Cano,
H. Haznedar, and D. Young.
A practical approach to static signal electromigration analysis.
In IEEE/ACM 35th Design Automation Conference, pages 572-577, San
Francisco, CA, June 15-19 1998.
- [3281]
- N. NS, T. Bonifield,
A. Singh, C. Bittlestone, U. Narasimha, V. Le, and A. Hill.
BEOL variability and impact on RC extraction.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
758-759, Anaheim, CA, June 13-17 2005.
- [3282]
- J. Nyathi and B. Bero.
Logic circuits operating in subthreshold voltages.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 131-134, Tegernsee, Germany, October 4-6 2006.
- [3283]
- K. K. O, K. Kim, B. Floyd,
J. Mehta, H. Yoon, C.-M. Hung, D. Bravo, T. Dickson, X. Guo, R. Li,
N. Trichy, J. Caserta, W. Bomstad, J. Branch, D.-J. Yang, J. Bohorquez,
J. Chen, E.-Y. Seok, L. Gao, A. Sugavanam, J.-J. Lin, S. Yu, C. Cao, M.-H.
Hwang, Y.-P. Ding, S.-H. Hwang, H. Wu, N. Zhang, and J. E. Brewer.
The feasibility of on-chip interconnection using antennas.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 979-984, San Jose, CA, November 6-10 2005.
- [3284]
- A. S. Oates.
Interconnect reliability challenges for technology scaling: A circuit focus.
In IEEE International Interconnect Technology Conference / Advanced
Metallization Conference (IITC/AMC), pages 59-59, San Jose, CA, May
23-26 2016.
- [3285]
- J. Oberg, W. Hu,
A. Irturk, M. Tiwari, T. Sherwood, and R. Kastner.
Theoretical analysis of gate level information flow tracking.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
244-247, Anaheim, CA, June 13-18 2010.
- [3286]
- P. R. O'Brien and
T. L. Savarino.
Modeling the driving-point characteristic of resistive interconnect for
accurate delay estimation.
In IEEE International Conference on Computer-Aided Design, pages
512-515, 1989.
- [3287]
- I. O'Connor,
J. Liu, F. Gaffiot, F. Pregaldiny, C. Lallement, C. Maneux, J. Goguet,
F. Fegonese, T. Zimmer, L. Anghel, T.-T. Dang, and R. Leveugle.
CNTFET modeling and reconfigurable logic-circuit design.
IEEE Transactions on Circuits and Systems, 54(11):2365-2379, November
2007.
- [3288]
- A. Odabasioglu, M. Celik, and L. Pileggi.
PRIMA: passive reduced-order interconnect macromodeling algorithm.
In IEEE/ACM International Conference on Computer-Aided Design, pages
58-65, San Jose, CA, November 9-13 1997.
- [3289]
- A. Odabasioglu, M. Celik, and L. T. Pileggi.
PRIMA: Passive reduced-order interconnect macromodeling algorithm.
IEEE Transactions on Computer-Aided Design, 17(8):645-654, August
1998.
- [3290]
- A. Odabasioglu, M. Celik, and L. T. Pileggi.
Practical considerations for passive reduction of RLC circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
214-219, San Jose, CA, November 7-11 1999.
- [3291]
- K. O'Donoghue, M. P. Kennedy, and P. Forbes.
A fast and simple implementation of chua's oscillator using a "cube-like" chua
diode.
In European Conference on Circuit Theory and Design (ECCTD), pages
II.83-II.86, Cork, Ireland, August 29 - September 2 2005.
- [3292]
- Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye.
Supply noise suppression by triple-well structure.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(4):781-785, April 2013.
- [3293]
- U. Y. Ogras,
R. Marculescu, and D. Marculescu.
Variation-adaptive feedback control for networks-on-chip with multiple clock
domains.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
614-619, Anaheim, CA, June 8-13 2008.
- [3294]
- C. Oh, D. Blaauw,
M. Becer, V. Zolotov, R. Panda, and A. Dasgupta.
Static electromigration analysis for signal interconnects.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 377-382, San Jose, CA, March 24-26 2003.
- [3295]
- K.-I. Oh and L.-S. Kim.
A clock delayed sleep mode domino logic for wide dynamic OR gate.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 176-179, Seoul, Korea, August 25-27 2003.
- [3296]
- N. Ohba and K. Takano.
An soc design methodology using fpgas and embedded microprocessors.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
747-752, San Diego, CA, June 7-11 2004.
- [3297]
- M. Ohlrich,
C. Ebeling, E. Ginting, and L. Sather.
Subgemini: Identifying subcircuits using a fast subgraph isomorphism algorithm.
In 30th ACM/IEEE Design Automation Conference, pages 31-37, Dallas,
Texas, June 14-18 1993.
- [3298]
- S. Y. Ohm, F. J.
Kurdahi, and N. D. Dutt.
A unified lower bound estimation technique for high-level synthesis.
IEEE Transactions on Computer-Aided Design, 16(5):458-472, May
1997.
- [3299]
- M. Ohnishi,
A. Yamada, H. Noda, and T. Kambe.
A method of redundant clocking and power reduction at RT level design.
In 1997 International Symposium on Low Power Electronics and Design,
pages 131-136, Monterey, CA, August 18-20 1997.
- [3300]
- M. Ohring and
L. Kasprzak.
Reliability and Failure of Electronic Materials and Devices.
Academic Press, 2nd edition, 2014.
- [3301]
- K. Okada,
K. Yamaoka, and H. Onodera.
A statistical gate-delay model considering intra-gate variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 908-913, San Jose, CA, November 9-13 2003.
- [3302]
- V. G.
Oklobdzija, B. R. Zeydel, H. O. Dao, S. Mathew, and R. Krishnamurthy.
Comparison of high-performance VLSI adders in the energy-delay space.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):754-758, June 2005.
- [3303]
- V. G.
Oklobdzija and P. G. Kovijanic.
On testability of CMOS-domino logic.
In IEEE 14th International Symposium on Fault-Tolerant Computing,
pages 50-55, Kissimee, FL, June 20-22 1984.
- [3304]
- H. Okuhara,
A. B. Ahmed, J. M. Kuhn, and H. Amano.
Asymmetric body bias control with low-power FD-SOI technologies: modeling
and power optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
26(7):1254-1267, July 2018.
- [3305]
- S. W. Oldridge and
S. J. E. Wilton.
A novel FPGA architecture supporting wide, shallow memories.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):758-762, June 2005.
- [3306]
- G. F.
Oliveira, L. R. Goncalves, M. Brandalero, A. C. S. Beck, and L. Carro.
Employing classification-based algorithms for general-purpose approximate
computing.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [3307]
- M. Olivieri,
F. Pappalardo, and G. Visalli.
Bus-switch coding for reducing power dissipation in off-chip buses.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1374-1377, December 2004.
- [3308]
- M. Olivieri,
G. Scotti, and A. Trifiletti.
A novel yield optimization technique for digital CMOS circuits design by
means of process parameters run-time estimation and body bias active control.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(5):630-638, May 2005.
- [3309]
- M. Olivieri.
Theoretical system-level limits of power dissipation reduction under a
performance constraint in VLSI microprocessor design.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):595-600, October 2002.
- [3310]
- E. Olson and S. M. Kang.
Low-power state assignment for finite state machines.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
63-68, Napa, CA, April 24-27 1994.
- [3311]
- E. Olson and S. M. Kang.
State assignment for low-power FSM synthesis using genetic local search.
In IEEE 1994 Custom Integrated Circuit Conference, pages 140-143, San
Diego, CA, May 1-4 1994.
- [3312]
- F. O'Mahony,
C. P. Yue, M. A. Horowitz, and S. S. Wong.
Design of a 10ghz clock distribution network using coupled standing-wave
oscillators.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
682-687, Anaheim, CA, June 2-6 2003.
- [3313]
- M. Omana,
D. Rossi, F. Fuzzi, C. Metra, C. Tirumurti, and R. Galivanche.
Scalable approach for power droop reduction during scan-based logic BIST.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(1):238-246, January 2017.
- [3314]
- O. Omedes,
M. Robert, and M. Ramdani.
A flexibility aware budgeting for hierarchical flow timing closure.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 261-266, San Jose, CA, November 7-11 2004.
- [3315]
- S. Onaissi,
K. R. Heloue, and F. N. Najm.
Clock skew optimization via wiresizing for timing sign-off covering all process
corners.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
196-201, San Francisco, CA, July 26-31 2009.
- [3316]
- S. Onaissi,
K. R. Heloue, and F. N. Najm.
PSTA-based branch and bound approach to the silicon speedpath isolation
problem.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 217-224, San Jose, CA, November 2-5 2009.
- [3317]
- S. Onaissi,
F. Taraporevala, J. Liu, and F. N. Najm.
A fast approach for static timing analysis covering all PVT corners.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
777-782, San Diego, CA, June 5-9 2011.
- [3318]
- S. Onaissi and F. N.
Najm.
A linear-time approach for static timing analysis covering all process corners.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 217-224, San Jose, CA, November 5-9 2006.
- [3319]
- S. Onaissi and F. N.
Najm.
A linear-time approach for static timing analysis covering all process corners.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(7):1291-1304, July 2008.
- [3320]
- Z.-Z. Oo, X.-C. Wei,
E.-X. Liu, E.-P. Li, and L.-W. Li.
Efficient analysis for multilayer power-ground planes with multiple vias and
signal traces in an advanced electronic package.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 95-98, San Jose, CA, October 27-29 2008.
- [3321]
- M. Oppeneer,
P. Sumant, and A. C. Cangellaris.
Robust iterative finite element solver for multi-terminal power distribution
network resistance extraction.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 181-184, San Jose, CA, October 27-29 2008.
- [3322]
- M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu.
Impact of systematic spatial intra-chip gate length variability on performance
of high-speed digital circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 62-67, San Jose, CA, November 5-9 2000.
- [3323]
- M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu.
Impact of spatial intrachip gate length variability on the performance of
high-speed digital circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(5):544-553, May 2002.
- [3324]
- M. Orshansky, L. Milor, and C. Hu.
Characterization of spatial intrafield gate CD variability, its impact on
circuit performance, and spatial mask-level correction.
IEEE Transactions on Semiconductor Manufacturing, 17(1):2-11,
February 2004.
- [3325]
- M. Orshansky and A. Bandyopadhyay.
Fast statistical timing analysis handling arbitrary delay correlations.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
337-342, San Diego, CA, June 7-11 2004.
- [3326]
- M. Orshansky and
K. Keutzer.
A general probabilistic framework for worst case timing analysis.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
556-561, New Orleans, LA, June 10-14 2002.
- [3327]
- Ortega and
Rheinboldt.
Iterative Solutions of Non-Linear Equations in Several Variables.
Academic Press, New York, NY, 1970.
- [3328]
- J. M. Ortega.
Matrix Theory, A Second Course.
Plenum Press, New York, NY, 1987.
- [3329]
- R. R. Ortiz and J. P.
Knight.
Compatible cell connections for multifamily dynamic logic gates.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):327-340, June 2002.
- [3330]
- K. Otseidu,
T. Jia, J. Bryne, L. Hargrove, and J. Gu.
Design and optimization of edge computing distributed neural processor for
biomedical rehabilitation with sensor fusion.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [3331]
- R. H. J. M. Otten and
R. K. Brayton.
Planning for performance.
In IEEE/ACM 35th Design Automation Conference, pages 122-127, San
Francisco, CA, June 15-19 1998.
- [3332]
- R. H. J. M. Otten and
P. Sravers.
Challenges in physical chip design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 84-91, San Jose, CA, November 5-9 2000.
- [3333]
- R. H. J. M. Otten.
Global wires harmful?
In ACM/IEEE International Symposium on Physical Design, pages
104-109, Monterey, CA, April 6-8 1998.
- [3334]
- R. J. M. Otten.
What is a floorplan?
In International Symposium on Physical Design, pages 201-206, San
Diego, CA, April 9-12 2000.
- [3335]
- H.-C. Ou, H.-C. Chang
Chien, and Y.-W. Chang.
Simultaneous analog placement and routing with current flow and current density
considerations.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [3336]
- B. Ouattara,
L. Doyen, D. Ney, H. Mehrez, and P. Bazargan-Sabet.
Power grid redundant path contribution in system on chip (soc) robustness
against electromigration.
Microelectronics Reliability, 54(9-10):1702-1706, September-October
2014.
- [3337]
- J. K. Ousterhout.
Crystal: A timing analyzer for nmos VLSI circuits.
In 3rd Caltech Conference on VLSI, pages 57-69, 1983.
- [3338]
- J. K. Ousterhout.
Switch-level delay models for digital MOS VLSI.
In IEEE 21st Design Automation Conference, pages 542-548,
Albuquerque, NM, June 24-27 1984.
- [3339]
- J. K. Ousterhout.
A switch-level timing verifier for digital MOS VLSI.
IEEE Transactions on Computer-Aided Design, CAD-4(3):336-349, July
1985.
- [3340]
- D. Overhauser, J. R. Lloyd, S. Rochel, G. Steele, and S. Z.
Hussain.
Full-chip reliability analysis.
Microelectronics Reliability, 38:851-859, 1998.
- [3341]
- D. Overhauser and
I. Hajj.
Multi-level circuit partitioning for switch-level timing simulation.
In IEEE International Symposium on Circuits and Systems, pages
1361-1364, 1988.
- [3342]
- D. Overhauser and
I. Hajj.
Feedback processing in fast timing simulation on a multiprocessor system.
In 32nd Midwest Symposium on Circuit and Systems, pages 466-469,
August 1989.
- [3343]
- D. Overhauser
and R. Saleh.
Evaluating mixed-signal simulators.
In IEEE Custom Integrated Circuits Conference, pages 113-120, Santa
Clara, CA, May 1-4 1995.
- [3344]
- H. Owhadi,
C. Scovel, and T. Sullivan.
On the brittleness of bayesian inference.
SIAM Review, 57(4):566-582, December 2015.
- [3345]
- D. Oyaro and
P. Triverio.
Turbomor-RC: an efficient model order reduction technique for RC networks
with many ports.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(10):1695-1706, October 2016.
- [3346]
- M. M. Ozdal,
S. Burns, and J. Hu.
Gate sizing and device technology selection algorithms for high performance
industrial designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 724-731, San Jose, CA, November 7-10 2011.
- [3347]
- S. Ozoguz and S. Ergun.
A non-autonomous IC chaotic oscillator and its application for random bit
generation.
In European Conference on Circuit Theory and Design (ECCTD), pages
II.165-II.168, Cork, Ireland, August 29 - September 2 2005.
- [3348]
- A. Pacelli.
A local circuit topology for inductive parasitics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 208-214, San Jose, CA, November 10-14 2002.
- [3349]
- C. Pacha, U. Auer,
C. Burwick, P. Glosekotter, A. Brennemann, W. Prost, F. J. Tegude, and K. F.
Goser.
Threshold logic circuit design of parallel adders using resonant tunneling
devices.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(5):558-572, October 2000.
- [3350]
- S. Padmanaban and S. Tragoudas.
Efficient identification of (critical) testable path delay faults using
decision diagrams.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):77-87, January 2005.
- [3351]
- U. Padmanabhan, J. M. Wang, and J. Hu.
Robust clock tree routing in the presence of process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(8):1385-1397, August 2008.
- [3352]
- S. Paek, S.-H. Moon,
W. Shin, J. Sim, and L.-S. Kim.
Powerfield: a transient temperature-to-power technique based on markov random
field theory.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
630-635, San Francisco, CA, June 3-7 2012.
- [3353]
- S. Paek, W. Shin,
J. Sim, and L.-S. Kim.
Powerfield: a probabilistic approach for temperature-to-power conversion based
on markov random field theory.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1509-1519, October 2013.
- [3354]
- S. Pagani, J. J.
Chen, and J. Henkel.
Energy and peak power efficiency analysis for the single voltage approximation
(SVA) scheme.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(9):1415-1428, September 2015.
- [3355]
- S. Paik and Y. Shin.
Multiobjective optimization of sleep vector for zigzag power-gated circuits in
standard cell elements.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
600-605, Anaheim, CA, June 8-13 2008.
- [3356]
- J. Pak, S.-K Lim, and
D. Z. Pan.
Electromigration-aware routing for 3d ics with stress-aware EM modeling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 325-332, San Jose, CA, November 5-8 2012.
- [3357]
- J. Pak, S.-K. Lim, and
D.-Z. Pan.
Electromigration study for multi-scale power/ground vias in TSV-based 3d ics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 379-386, San Jose, CA, November 18-21 2013.
- [3358]
- J. Pak, S. K. Lim, and
D. Z. Pan.
Electromigration study for multiscale power/ground vias in TSV-based 3-D
ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(12):1873-1885, December 2014.
- [3359]
- J. Pak, B. Yu, and
D.-Z. Pan.
Electromigration-aware redundant via insertion.
In 20th Asia and South Pacific Design Automation Conference, pages
544-549, Chiba/Tokyo, Japan, January 19-22 2015.
- [3360]
- E. Pakbaznia, F. Fallah, and M. Pedram.
Charge recycling in MTCMOS circuits: concept and analysis.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 97-102,
San Francisco, CA, July 24-28 2006.
- [3361]
- E. Pakbaznia, F. Fallah, and M. Pedram.
Sizing and placement of charge recycling transistor in MTCMOS circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 791-796, San Jose, CA, November 5-8 2007.
- [3362]
- E. Pakbaznia, F. Fallah, and M. Pedram.
Charge recylcing in power-gated CMOS circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1798-1811, October 2008.
- [3363]
- K. Palem and
A. Lingamneni.
What to do about the end of moore's law, probably!
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
924-929, San Francisco, CA, June 3-7 2012.
- [3364]
- G. A.
Paleologo, L. Benini, A. Bogliolo, and G. De Micheli.
Policy optimization for dynamic power management.
In IEEE/ACM 35th Design Automation Conference, pages 182-187, San
Francisco, CA, June 15-19 1998.
- [3365]
- I. Palit, Q. Lou,
N. Acampora, J. Nahas, M. Niemier, and X.-S. Hu.
Analytically modeling power and performance of a CNN system.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 186-193, Austin, TX, November 2-6 2015.
- [3366]
- M. Palla,
J. Bargfrede, S. Eggersglus, W. Anheier, and R. Drechsler.
Timing arc based logic analysis for false noise reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 225-230, San Jose, CA, November 2-5 2009.
- [3367]
- G. Palumbo,
D. Pappalardo, and M. Gaibotti.
Charge-pump circuits: power consumption optimization.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(11):1535-1542, November 2002.
- [3368]
- G. Palumbo,
M. Pennisi, and M. Alioto.
A simple circuit approach to reduce delay variatons in domino logic gates.
IEEE Transactions on Circuits and Systems, 59(10):2292-2300, October
2012.
- [3369]
- G. Palumbo and M. Poli.
Propagation delay model of a current driven RC chain for an optimized design.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(4):572-575, April 2003.
- [3370]
- D. Pamunuwa, S. Elassaad, and H. Tenhunen.
Analytic modeling of interconnects for deep sub-micron circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 835-842, San Jose, CA, November 9-13 2003.
- [3371]
- D. Pamunuwa, L.-R. Zheng, and H. Tenhunen.
Maximizing throughput over parallel wire structures in the deep submicrometer
regime.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(2):224-243, April 2003.
- [3372]
- D. Pamunuwa,
S. Elassaad, and H. Tenhunen.
Modeling delay and noise in arbitrarily coupled RC trees.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(11):1725-1739, November 2005.
- [3373]
- Z. Pan, Y. Cai,
S. X.-D. Tan, Z. Luo, and X. Hong.
Transient analysis of on-chip power distribution networks using equivalent
circuit modeling.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 63-68, San Jose, CA, March 22-24 2004.
- [3374]
- D.-Z. Pan, B. Yu, and
J.-R. Gao.
Design for manufacturing with emerging nanolithography.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1453-1472, October 2013.
- [3375]
- D. Z. Pan and M. D.-F. Wong.
Manufacturability-aware physical layout optimizations.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 149-153, Austin, TX, May 9 - 11 2005.
- [3376]
- R. Panda,
A. Dharchoudhury, T. Edwards, J. Norton, and D. Blaauw.
Migration: A new technique to improve synthesized designs through incremental
customization.
In IEEE/ACM 35th Design Automation Conference, pages 388-391, San
Francisco, CA, June 15-19 1998.
- [3377]
- R. Panda,
D. Blaauw, R. Chaudhry, V. Zolotov, B. Young, and R. Ramaraju.
Model and analysis for combined package and on-chip power grid simulation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 179-184, Italy, July 26-27 2000.
- [3378]
- R. Panda,
S. Sundareswaran, and D. Blaauw.
On the interaction of power distribution network with substrate.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 388-393, Huntington Beach, California, August 6-7
2001.
- [3379]
- R. Panda,
S. Sundareswaran, and D. Blaauw.
Impact of low-impedance substrate on power supply integrity.
IEEE Design & Test of Computers, pages 16-22, May-June 2003.
- [3380]
- P. R. Panda and N. D. Dutt.
Low-power memory mapping through reducing address bus activity.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(3):309-320, September 1999.
- [3381]
- R. Panda and F. N. Najm.
Technology decomposition for low-power synthesis.
In IEEE Custom Integrated Circuits Conference, pages 627-630, Santa
Clara, CA, May 1-4 1995.
- [3382]
- R. Panda and F. N. Najm.
Technology-dependent transformations for low-power synthesis.
In 34th Design Automation Conference, pages 650-655, Anaheim, CA,
June 9-13 1997.
- [3383]
- P. P. Pande, R.-G.
Kim, W. Choi, Z. Chen, D. Marculescu, and R. Marculescu.
The (low) power of less wiring: enabling energy efficiency in many-core
platforms through wireless noc.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 165-169, Austin, TX, November 2-6 2015.
- [3384]
- V. S. Pandit and W.-H.
Ryu.
Mutli-GHZ modeling and characterization of on-chip power delivery network.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 115-118, San Jose, CA, October 27-29 2008.
- [3385]
- Y. Pang and K. Radecka.
Optimizing imprecise fixed-point arithmetic circuits specified by taylor series
through arithmetic transform.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
397-402, Anaheim, CA, June 8-13 2008.
- [3386]
- J. Pangjun and
S. S. Sapatnekar.
Low-power clock distribution using multiple voltages and reduced swings.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):309-318, June 2002.
- [3387]
- B. M. Pangrle.
On the complexity of connectivity binding.
IEEE Transactions on Computer-Aided Design, 10(11):1460-1465,
November 1991.
- [3388]
- P. Pant, V. De, and
A. Chatterjee.
Device-circuit optimization for minimal energy and power consumption in CMOS
random logic networks.
In 34th Design Automation Conference, pages 403-408, Anaheim, CA,
June 9-13 1997.
- [3389]
- P. Pant, V. K. De,
and A. Chatterjee.
Simultaneous power supply, threshold voltage, and transistor size optimization
for low-power operation of CMOS circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(4):538-545, December 1998.
- [3390]
- P. Pant, R. K. Roy,
and A. Chatterjee.
Dual-threshold voltage assignment with transistor sizing for low power CMOS
circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(2):390-394, April 2001.
- [3391]
- M. D. Pant, P. Pant,
and D. S. Wills.
On-chip decoupling capacitor optimization using architectural level prediction.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):319-326, June 2002.
- [3392]
- S. Pant, D. Blaauw,
V. Zolotov, S. Sundareswaran, and R. Panda.
Vectorless analysis of supply noise induced delay variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 184-191, San Jose, CA, November 9-13 2003.
- [3393]
- S. Pant, D. Blaauw,
V. Zolotov, S. Sundareswaran, and R. Panda.
A stochastic approach to power grid analysis.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
171-176, San Diego, CA, June 7-11 2004.
- [3394]
- S. Pant and D. Blaauw.
Static timing anaylsis considering power supply variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 365-371, San Jose, CA, November 6-10 2005.
- [3395]
- S. Pant and E. Chiprout.
Power grid physics and implications for CAD.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
199-204, San Francisco, CA, July 24-28 2006.
- [3396]
- S. Panth,
K. Samadi, Y. Du, and S.-K. Lim.
Tier-partitioning for power delivery vs cooling tradeoff in 3d VLSI for
mobile applications.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [3397]
- H. Panzer,
T. Wolf, and B. Lohmann.
A strictly dissipative state space representation of second order systems.
Automatisierungstechnik, 60(12):392-396, July 2012.
- [3398]
- C. Papachristou, M. Spinning, and M. Nourani.
An effective power management scheme for RTL design.
In 33rd Design Automation Conference, pages 337-342, Las Vegas, NV,
June 3-7 1996.
- [3399]
- C. A. Papachristou, M. Nourani, and M. Spining.
A multiple clocking scheme for low-power RTL design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
7(2):266-276, June 1999.
- [3400]
- E. Papadopoulou.
Net-aware critical area extraction for opens in VLSI circuits via
higher-order voronoi diagrams.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(5):704-717, May 2011.
- [3401]
- M. C.
Papaefthymiou and K. H. Randall.
TIM: A timing package for two-phase, level-clocked circuitry.
In ACM/IEEE Design Automation Conference, pages 497-502, 1993.
- [3402]
- A. Papoulis and
S. U. Pillai.
Probability, Random Variables, and Stochastic Processes.
McGraw-Hill, Boston, MA, 4th edition, 2002.
- [3403]
- Athanasios Papoulis.
The Fourier Integral and its Applications.
McGraw-Hill Book Company, Inc., 1962.
- [3404]
- A. Papoulis.
Probability, Random Variables, and Stochastic Processes.
McGraw-Hill, Inc., New York, NY, 2nd edition, 1984.
- [3405]
- K. Parashar,
D. Menard, R. Rocher, O. Sentieys, D. Novo, and F. Catthoor.
Fast performance evaluation of fixed-point systems with un-smooth operators.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 9-16, San Jose, CA, November 7-11 2010.
- [3406]
- K. N.
Parashar, D. Menard, and O. Sentieys.
A polynomial time algorithm for solving the word-length optimization problem.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 638-645, San Jose, CA, November 18-21 2013.
- [3407]
- A. Pardo, R. I.
Bahar, S. Manne, P. Feldmann, G. D. Hachtel, and F. Somenzi.
CMOS dynamic power estimation based on collapsible current source transistor
modeling.
In ACM/IEEE International Symposium on Low Power Design, pages
111-116, Dana Point, CA, April 23-26 1995.
- [3408]
- A. Parihar,
N. Shukla, M. Jerry, S. Dattay, and A. Raychowdhury.
Connecting spectral techniques for graph coloring and eigen properties of
coupled dynamics: a pathway for solving ombinatorial optimizations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 800-804, Irvine CA, November 13-16 2017.
- [3409]
- S. Park,
A. Savvides, and M. Srivastava.
Battery capacity measurement and analysis using lithium coin cell battery.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 382-387, Huntington Beach, California, August 6-7
2001.
- [3410]
- J. Park,
K. Muhammad, and K. Roy.
Efficient modeling of 1/fa noise using multirate process.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1247-1256, July 2006.
- [3411]
- S. Park,
A. Shrivastava, N. Dutt, A. Nicolau, Y. Paek, and E. Earlie.
Register file power reducing using bypass sensitive compiler.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(6):1155-1159, June 2008.
- [3412]
- Y.-J. Park, P. Jain,
and S. Krishnan.
New electromigration validation: via node vector method.
In 2010 IEEE International Reliability Physics Symposium (IRPS), pages
698-704, Anaheim, CA, May 2-6 2010.
- [3413]
- S.-Y. Park and N.-I. Cho.
Fixed-point error analysis of CORDIC processor based on the variance
propagation formula.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(3):573-583, March 2004.
- [3414]
- K. P. Parker and
E. J. McCluskey.
Probabilistic treatment of general combinational networks.
IEEE Transactions on Computers, C-24:668-670, June 1975.
- [3415]
- D. Stott Parker, Jr.
Conditions for the optimality of the huffman algorithm.
SIAM Journal on Computing, 9(3):470-488, August 1980.
- [3416]
- J. Parkhurst, N. Sherwani, S. Maturi, D. Ahrams, and
E. Chiprout.
SRC physical design top ten problems.
In 1999 International Symposium on Physical Design, pages 55-58,
Monterey, CA, April 12-14 1999.
- [3417]
- J. Parkhurst, J. Darringer, and B. Grundmann.
From single core to multi-core: preparing for a new exponential.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 67-72, San Jose, CA, November 5-9 2006.
- [3418]
- S. Parter.
The use of linear graphs in gauss elimination.
SIAM Review, 3(2):119-130, April 1961.
- [3419]
- G. Parthasarathy, M. K. Iyer, K.-T. Cheng, and F. Brewer.
RTL SAT simplification by boolean and interval arithmetic reasoning.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 297-302, San Jose, CA, November 6-10 2005.
- [3420]
- E. Pastor and
J. Cortadella.
Polynomial algorithms for the synthesis of hazard-free circuits from signal
transition graphs.
In IEEE/ACM International Conference on Computer-Aided Design, pages
250-254, Santa Clara, CA, November 7-11 1993.
- [3421]
- K. Patel, W. Lee,
and M. Pedram.
Minimizing power dissipation during write operation to register files.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 183-188, Portland, Oregon, August 27-29 2007.
- [3422]
- K. N. Patel and I. L.
Markov.
Error-correction and crosstalk avoidance in DSM busses.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1076-1080, October 2004.
- [3423]
- M. Pathak,
J. Pak, D.-Z. Pan, and S.-K. Lim.
Electromigration modeling and full-chip reliability analysis for BEOL
interconnect in TSV-based 3dics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 555-562, San Jose, CA, November 7-10 2011.
- [3424]
- D. Pathak,
H. Homayoun, and I. Savidis.
Smart grid on chip: work load-balanced on-chip power delivery.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(9):2538-2551, September 2017.
- [3425]
- J. Pathak,
B. Hunt, M. Girvan, Z. Lu, and E. Ott.
Model-free prediction of large spatiotemporally chaotic systems from data: A
reservoir computing approach.
Physical Review Letters, 120(2):024102/1-5, January 2018.
- [3426]
- A. Pathania,
V. Venkatramani, M. Shafique, T. Mitra, and J. Henkel.
Optimal greedy algorithm for many-core scheduling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(6):1054-1058, June 2017.
- [3427]
- N. Patil, J. Deng,
H.-S. P. Wong, and S. Mitra.
Automated design of misaligned-carbon-nanotube-immune circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
958-961, San Diego, CA, June 4-8 2007.
- [3428]
- N. Patil, A. Lin,
J. Zhang, H.-S. P. Wong, and S. Mitra.
Digital VLSI logic technology using carbon nanotube fets: frequently asked
questions.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
304-309, San Francisco, CA, July 26-31 2009.
- [3429]
- A. Patil,
N. Shanbhag, E. Pop, H.-S.-P. Wong, S. Mitra, J. Rabaey, J. Weldon,
L. Pileggi, S. Manipatruni, D. Nikonov, and I. Young.
A systems approach to computing in beyond CMOS fabrics.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [3430]
- P. Patra and
U. Narayanan.
Automated phase assignment for the synthesis of low power domino circuits.
In Design Automation Conference, pages 379-384, New Orleans, LA, June
21-25 1999.
- [3431]
- G. A.
Patterson, J. Sune, and E. Miranda.
Voltage-driven hystersis model for resistive switching: SPICE modeling and
circuit applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(12):2044-2051, December 2017.
- [3432]
- R. Patti.
3d integrated circuits: designing in a new dimension.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 274, San Jose, CA, November 5-8 2012.
- [3433]
- B. C. Paul, K. Kang,
H. Kufluoglu, M. A. Alam, and K. Roy.
Negative bias temperature instability: estimation and design for improved
reliability of nanoscale circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):743-751, April 2007.
- [3434]
- D. Paul, N. M.
Nakhla, R. Achar, and M. S. Nakhla.
Parallel algorithm for analysis of high-speed interconnects.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 191-194, San Jose, CA, October 27-29 2008.
- [3435]
- D. Paul, M. S.
Nakhla, R. Achar, and N. M. Nakhla.
Parallel circuit simulation via binary link formulations (pvb).
IEEE Transactions on Components, Packaging and Manufacturing
Technology, 3(5):768-782, May 2013.
- [3436]
- D. Paul, R. Achar,
M. S. Nakhla, and N. M. Nakhla.
Addressing partitioning issues in parallel circuit simulation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(12):2713-2723, December 2014.
- [3437]
- A. Paul, S.-P. Park,
D. Somasekhar, Y.-M. Kim, N. Borkar, U. R. Karpuzcu, and C.-H. Kim.
System-level power analysis of a multicore multipower domain processor with
on-chip voltage regulators.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(12):3468-3476, December 2016.
- [3438]
- P. Pavan,
L. Larcher, M. Cuozzo, P. Zuliani, and A. Conte.
A complete model of e2prom memory cells for circuit simulations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(8):1072-1079, August 2003.
- [3439]
- A. Peano,
L. Ramini, M. Gavanelli, M. Nonato, and D. Bertozzi.
Design technology for fault-free and maximally-parallel wavelength-routed
optical networks-on-chip.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [3440]
- M. Pecht, F. R.
Nash, and J. H. Lory.
Understanding and solving the real reliability assurance problems.
In Annual Reliability and Maintainability Symposium, pages 159-161,
Washington, DC, January 16-19 1995.
- [3441]
- M. G. Pecht and F. R. Nash.
Predicting the reliability of electronic equipment.
In Proceedings of the IEEE, pages 990-1004, July 1994.
- [3442]
- D. O. Pederson.
A historical review of circuit simulation.
IEEE Transactions on Circuits and Systems, CAS-31(1):103-111, January
1984.
- [3443]
- M. Pedram,
R. Bushroe, R. Camposano, G. De Micheli, A. Domic, C-P Hsu, and M. Jackson.
Panel: physical design and synthesis: merge or die!
In 34th Design Automation Conference, pages 238-239, Anaheim, CA,
June 9-13 1997.
- [3444]
- M. Pedram and B. T.
Preas.
Interconnection analysis for standard cell layouts.
IEEE Transactions on Computer-Aided Design, 18(10):1512-1519, October
1999.
- [3445]
- M. Pedram and Y. Wang.
Design automation methodology and tools for superconductive electronics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [3446]
- M. Pedram and Q. Wu.
Design considerations for battery-powered electronics.
In Design Automation Conference, pages 861-866, New Orleans, LA, June
21-25 1999.
- [3447]
- M. Pedram and Q. Wu.
Battery-powered digital CMOS design.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):601-607, October 2002.
- [3448]
- M. Pedram.
Power minimization in IC design: principles and applications.
ACM Transactions on Design Automation of Electronic Systems,
1(1):3-56, January 1996.
- [3449]
- M. Pedram.
Energy-efficient datacenters.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(10):1465-1484, October 2012.
- [3450]
- A. Peiravi and
M. Asyaei.
Current-comparison-based domino: new low-leakage high-speed domino circuit for
wide fan-in gates.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(5):934-943, May 2013.
- [3451]
- M. J. M.
Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers.
Matching properties of MOS transistors.
IEEE Journal of Solid-State Circuits, 24(5):1433-1440, October
1989.
- [3452]
- P. Penfield,
Jr. and J. Rubinstein.
Signal delay in RC tree networks.
In IEEE 18th Design Automation Conference, pages 613-617, 1981.
- [3453]
- H. Peng, K. Rouz,
M. Borah, and C.-K. Cheng.
Parallel full-chip transient simulation at transistor level.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 239-242, San Jose, CA, October 27-29 2008.
- [3454]
- H.-K. Peng, C. H.-P.
Wen, and J. Bhadra.
On soft error rate analysis of scaled CMOS designs - a statistical
perspective.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 157-163, San Jose, CA, November 2-5 2009.
- [3455]
- Y. Peng, B.-W. Ku,
Y. Park, K.-I. Park, S.-J. Jang, J.-S. Choi, and S.-K. Lim.
Design, packaging, and architectural policy co-optimization for DC power
integrity in 3d DRAM.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [3456]
- S. Peng, H. Zhou,
T. Kim, H.-B. Chen, and S. X.-D. Tan.
Physics-based compact TDDB modelss for low-k BEOL copper interconnects with
time-varying voltage stressing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
26(2):239-248, February 2018.
- [3457]
- Z. Peng, X. Chen,
C. Xu, N. Jing, X. Liang, C. Lu, and L. Jiang.
Axnet: approximate computing using an end-to-end trainable neural network.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [3458]
- Y. Peng and X. Liu.
An efficient low-power repeater-insertion scheme.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2726-2736, December 2006.
- [3459]
- C. S. Petrie and
J. A. Connelly.
A noise-based IC random number generator for applications in cryptography.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 47(5):615-621, May 2000.
- [3460]
- P. Petrov and
A. Orailoglu.
Low-power insturction bus encoding for embedded processors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(8):812-826, August 2004.
- [3461]
- O. Peyran,
Z. Zeng, and W. Zhuang.
Area optimization of delay-optimized sturctures using intrinsic constraint
graphs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):888-906, June 2004.
- [3462]
- T. Pfingsten, D. J. L. Herrmann, and C. E. Rasmussen.
Model-based design analysis and yield optimization.
IEEE Transactions on Semiconductor Manufacturing, 19(4):475-486,
November 2006.
- [3463]
- J. Phillips,
L. Daniel, and L. Miguel Silveira.
Guaranteed passive balancing transformations for model order reduction.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages 52-57,
New Orleans, LA, June 10-14 2002.
- [3464]
- J. R.
Phillips, L. Daniel, and L. M. Silveira.
Guaranteed passive balancing transformations for model order reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(8):1027-1041, August 2003.
- [3465]
- J. R. Phillips
and L. M. Silveira.
Poor man's TBR: a simple model reduction scheme.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):43-55, January 2005.
- [3466]
- J. R. Phillips.
Variational interconnect analysis via PMTBR.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 872-879, San Jose, CA, November 7-11 2004.
- [3467]
- M. W. Phyu, K. Fu,
W.-L. Goh, and K.-S. Yeo.
Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(1):1-9, January 2011.
- [3468]
- C. Piguet, J.-M.
Masgonty, S. Cserveny, C. Arm, and P.-D. Pfister.
Low-power low-voltage library cells and memories.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 1521-1524, St. Julian, Malta, September 2-5 2001.
- [3469]
- C. Piguet,
C. Schuster, and J.-L. Nagel.
Optimizing architecture activity and logic depth for static and dynamic power
reduction.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 41-44, Montreal, Quebec, June 20-23 2004.
- [3470]
- L. Pileggi,
H. Schmit, A. J. Strojwas, P. Gopalakrishnan, V. Kheterpal, A. Koorapaty,
C. Patel, V. Rovner, and K. Y. Tong.
Exploring regular fabrics to optimize the performance cost trade-off.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
782-787, Anaheim, CA, June 2-6 2003.
- [3471]
- L. Pileggi.
Coping with RC(L) interconnect design headaches.
In IEEE/ACM International Conference on Computer-Aided Design, pages
246-253, San Jose, CA, November 5-9 1995.
- [3472]
- L. Pileggi.
Timing metrics for physical design of deep submicron technologies.
In ACM/IEEE International Symposium on Physical Design, pages 28-33,
Monterey, CA, April 6-8 1998.
- [3473]
- L. Pileggi.
Timing metrics for physical design of deep submicron technologies.
In International Symposium on Physical Design, pages 28-33, Monterey,
CA, 1998.
- [3474]
- L. Pileggi.
Achieving timing closure for giga-scale IC designs.
In ACM/IEEE 1999 International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU-99), pages 25-28,
Monterey, CA, March 8-9 1999.
- [3475]
- L. Pillage,
X. Huang, and R. Rohrer.
Asymptotic waveform evaluation for circuits containing floating nodes.
In IEEE International Symposium on Circuits and Systems, pages
613-616, 1990.
- [3476]
- L. T. Pillage and
R. A. Rohrer.
Asymptotic waveform evaluation for timing analysis.
IEEE Transactions on Computer-Aided Design, 9(4):352-366, April
1990.
- [3477]
- J. C. G.
Pimentel, E. Gad, and S. Roy.
High-order A-stable and L-stable state-space discrete modeling of
continuous systems.
IEEE Transactions on Circuits and Systems, 59(2):346-359, February
2012.
- [3478]
- A. Pinar and C. L. Liu.
Power invariant vector sequence compaction.
In IEEE/ACM International Conference on Computer-Aided Design, pages
473-476, San Jose, CA, November 8-12 1998.
- [3479]
- R. Pino, H. Li,
Y. Chen, M. Hu, and B. Liu.
Statistical memristor modeling and case study in neuromorphic computing.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
585-590, San Francisco, CA, June 3-7 2012.
- [3480]
- N. Pippenger.
Information theory and the complexity of boolean functions.
Mathematical Systems Theory, 10:129-167, 1977.
- [3481]
- Sergio Pissanetsky.
Sparse Matrix Technology.
Academic Press Inc., Orlando, FL, 1984.
- [3482]
- G. Poddar,
K. Chakrabarty, and S. Banerjee.
Control of chaos in DC-DC converters.
IEEE Transactions on Circuits and Systems - I: Fundamental Theory and
Applications, 45(6):672-676, June 1998.
- [3483]
- R. Pokala.
Thermal analysis in SPICE.
In IEEE International Conference on Computer-Aided Design, pages
256-259, 1989.
- [3484]
- F. J. Pollack.
New microarchitecture challenges in the coming generations of CMOS process
technologies.
In ACM/IEEE 32nd Annual International Symposium on Microarchitecture
(MICRO-32), page 2, Haifa, Israel, November 16-18 1999.
- [3485]
- I. Pomeranz and
S. M. Reddy.
Transparent scan: a new approach to test generation and test compaction for
scan circuits that incorporates limited scan operations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(12):1663-1670, December 2003.
- [3486]
- I. Pomeranz and
S. M. Reddy.
Transparent DFT: a design for testability and test generation approach for
synchronous sequential circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(6):1170-1175, June 2006.
- [3487]
- I. Pomeranz and
S. M. Reddy.
Double-single stuck-at faults: a delay fault model for synchronous sequential
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(3):426-432, March 2009.
- [3488]
- I. Pomeranz and
S. M. Reddy.
Random test generation with input cube avoidance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(1):45-54, January 2009.
- [3489]
- I. Pomeranz and
S. M. Reddy.
TOV: sequential test generation by ordering of test vectors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(3):454-465, March 2010.
- [3490]
- I. Pomeranz.
Invariant states and redundant logic in synchronous sequential circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(6):1171-1175, June 2007.
- [3491]
- I. Pomeranz.
Subsets of primary input vectors in sequential test generation for single
stuck-at faults.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(10):1579-1583, October 2011.
- [3492]
- T. Pompl,
C. Schlunder, M. Hommel, H. Nielen, and J. Schneider.
Practical aspects of reliability analysis for IC designs.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
193-198, San Francisco, CA, July 24-28 2006.
- [3493]
- D. Ponomarev, G. Kucuk, O. Ergin, and K. Ghose.
Power efficient comparators for long arguments in superscalar processors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 378-383, Seoul, Korea, August 25-27 2003.
- [3494]
- M. Popovich,
E. G. Friedman, R. M. Secareanu, and O. L. Hartin.
Efficient placement of distributed on-chip decoupling capacitors in nanoscale
ics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 811-816, San Jose, CA, November 5-8 2007.
- [3495]
- M. Popovich, E. G. Friedman, R. M. Secareanu, and O. L. Hartin.
Efficient distributed on-chip decoupling capacitors for nanoscale ics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(12):1717-1721, December 2008.
- [3496]
- M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny.
On-chip power distribution grids with multiple supply voltages for
high-performance integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(7):908-921, July 2008.
- [3497]
- M. Popovich, M. Sotman, A. Kolodny, and E. G. Friedman.
Effective radii of on-chip decoupling capacitors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(7):894-906, July 2008.
- [3498]
- M. Popovich and
E. G. Friedman.
Decoupling capacitors for multi-voltage power distribution systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(3):217-228, March 2006.
- [3499]
- S. Popovych,
H.-H. Lai, C.-M. Wang, Y.-L. Li, W.-H. Liu, and T.-C. Wang.
Density-aware detailed placement with instant legalization.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [3500]
- S. Posluszny, N. Aoki, D. Boerstler, P. Coulman, S. Dhong,
B. Flachs, P. Hofstee, N. Kojima, O. Kwon, K. Lee, D. Meltzer, K. Nowka,
J. Park, J. Peter, J. Silberman, O. Takahashi, and P. Villarrubia.
"timing closure by design," A high frequency microprocessor design
methodology.
In Design Automation Conference, pages 712-717, Los Angeles, CA, June
5-9 2000.
- [3501]
- G. Posser,
V. Mishra, P. Jain, R. Reis, and S. S. Sapatnekar.
A systematic approach for analyzing and optimizing cell-internal signal
electromigration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 486-491, San Jose, CA, November 2-6 2014.
- [3502]
- G. Posser,
V. MIshra, P. Jain, R. Reis, and S. S. Sapatnekar.
Cell-internal electromigration: analysis and pin placement based optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(2):220-231, February 2016.
- [3503]
- A. Pothen, H. D.
Simon, and K-P Liou.
Partitioning sparse matrices with eigenvectors of graphs.
SIAM J. Matrix Anal. Appl., 11(3):430-452, July 1990.
- [3504]
- M. Potkonjak, D. Chen, P. Kalla, and S. P. Levitan.
DA vision 2015: from here to eternity.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 271-277, Austin, TX, November 2-6 2015.
- [3505]
- M. Potkonjak.
Synthesis of trustable ics using untrusted CAD tools.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
633-634, Anaheim, CA, June 13-18 2010.
- [3506]
- B. Potts,
R. Hokinson, W. Kang, J. Riley, D. Doman, F. Cano, N. S. Nagaraj, and
N. Durrant.
Enabling DIR (designing-in reliability) throught CAD capabilities.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 151-156, San Jose, CA, March 20-22 2000.
- [3507]
- M. Powell, S.-H.
Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar.
Gated-vdd: A circuit technique to reduce leakage in deep-submicron cache
memories.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 90-95, Italy, July 26-27 2000.
- [3508]
- M. Powell, S.-H.
Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar.
Reducing leakage in a high-performance deep-submicron instruction cache.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(1):77-89, February 2001.
- [3509]
- S. R. Powell and P. M.
Chau.
Estimating power dissipation of VLSI signal processing chips: The PFA
technique.
In VLSI Signal Processing IV, pages 250-259. IEEE, 1991.
- [3510]
- D. K. Pradhan,
M. Chatterjee, M. V. Swarna, and W. Kunz.
Gate-level synthesis for low-power using new transformations.
In International Symposium on Low Power Electronics and Design, pages
297-300, Monterey, CA, August 12-14 1996.
- [3511]
- M. R. Prasad,
P. Chong, and K. Keutzer.
Why is ATPG easy?
In Design Automation Conference, pages 22-28, New Orleans, LA, June
21-25 1999.
- [3512]
- S. C. Prasad and K. Roy.
Circuit optimization for minimization of power consumption under delay
constraint.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
15-20, Napa, CA, April 24-27 1994.
- [3513]
- R. J. Pratap,
P. Sen, C. E. Davis, R. Mukhophdhyay, G. S. May, and J. Laskar.
Neurogenetic design centering.
IEEE Transactions on Semiconductor Manufacturing, 19(2):173-182, May
2006.
- [3514]
- Preparata and Yeh.
Introduction to Discrete Structures.
Addison-Wesley Publishing Company, 1973.
- [3515]
- E. J. Prinz.
The zen of nonvolatile memories.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
815-820, San Francisco, CA, July 24-28 2006.
- [3516]
- S. Priyadarshi, C. S. Saunders, N. M. Kriplani, H. Demircioglu,
W. R. Davis, P. D. Franzon, and M. B. Steer.
Parallel transient simulation of multiphysics circuits using delay-based
partitioning.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(10):1522-1535, October 2012.
- [3517]
- Y. Pu, J. P. de Gyvez,
H. Corporaal, and Y. Ha.
VT balancing and device sizing towards high yield of sub-threshold static
logic gates.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 355-358, Portland, Oregon, August 27-29 2007.
- [3518]
- Y. Pu, X. Zhang,
J. Huang, A. Muramatsu, M. Nomura, K. Hirairi, H. Takata, T. Sakurabayashi,
S. Miyano, M. Takamiya, and T. Sakurai.
Misleading energy and performance claims in sub/near threshold digital systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 625-631, San Jose, CA, November 7-11 2010.
- [3519]
- A. Puggelli,
T. Welp, A. Kuehlmann, and A. Sangiovanni-Vincentelli.
Are logic synthesis tools robust?
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
633-638, San Diego, CA, June 5-9 2011.
- [3520]
- R. Puri,
A. Bjorksten, and T. E. Rosser.
Logic optimization by output phase assignment in dynamic logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
2-8, San Jose, CA, November 10-14 1996.
- [3521]
- R. Puri, L. Stok,
J. Cohn, D. Kung, D. Pan, D. Sylvester, A. Srivastava, and S. Kulkarni.
Pushing ASIC performance in a power envelope.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
788-793, Anaheim, CA, June 2-6 2003.
- [3522]
- R. Puri, L. Stok,
and S. Bhattacharya.
Keeping hot chips cool.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
285-288, Anaheim, CA, June 13-17 2005.
- [3523]
- R. Puri and C. T. Chuang.
Hysteresis effect in floating-body partially-depleted SOI CMOS domino
circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 223-228, San Diego, CA, August 16-17 1999.
- [3524]
- R. Puri.
Minimizing power under performance constraint.
In International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 159-163, Austin, TX, May 17-20 2004.
- [3525]
- R. Puri.
Application driven high level design in the era of heterogeneous computing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 71, San Jose, CA, November 2-6 2014.
- [3526]
- Z. Qi, H. Yu, P. Liu,
S. X.-D. Tan, and L. He.
Wideband passive multiport model order reduction and realization of RLCM
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(8):1496-1509, August 2006.
- [3527]
- J. Qian, S. Pullela,
and L. Pillage.
Modeling the "effective capacitance" for the RC interconnect of CMOS gates.
IEEE Transactions on Computer-Aided Design, 13(12):1526-1535,
December 1994.
- [3528]
- H. Qian, S. R.
Nassif, and S. S. Sapatnekar.
Random walks in a supply network.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 93-98,
Anaheim, CA, June 2-6 2003.
- [3529]
- H. Qian, J. N.
Kozhaya, S. R. Nassif, and S. S. Sapatnekar.
A chip-level electrostatic discharge simulation strategy.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 315-318, San Jose, CA, November 7-11 2004.
- [3530]
- H. Qian, S. R.
Nassif, and S. S. Sapatnekar.
Early-stage power grid analysis for uncertain working modes.
In ACM International Symposium on Physical Design (ISPD-04), pages
132-137, Phoenix, AZ, April 18-21 2004.
- [3531]
- H. Qian, S. R.
Nassif, and S. S. Sapatnekar.
Early-stage power grid analysis for uncertain working modes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(5):676-682, May 2005.
- [3532]
- H. Qian, S. R.
Nassif, and S. S. Sapatnekar.
Power grid analysis using random walks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(8):1204-1224, August 2005.
- [3533]
- W. Qian, M. D.
Riedel, H. Zhou, and J. Bruck.
Transforming probabilities with combinational logic.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(9):1279-1292, September 2011.
- [3534]
- W. Qian, C. Wang,
P. Li, D. J. Lilja, K. Bazargan, and M. D. Riede.
An efficient implementation of numerical integration using logical computation
on stochastic bit streams.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 156-162, San Jose, CA, November 5-8 2012.
- [3535]
- H. Qian and S. S.
Sapatnekar.
Hierarchical random-walk algorithms for power grid analysis.
In IEEE/ACM Asia and South Pacific Design Automation Conference
(ASP-DAC), pages 499-504, Yokohama, Japan, January 27-30 2004.
- [3536]
- H. Qian and S. S.
Sapatnekar.
A hybrid linear equation solver and its application in quadratic placement.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 905-909, San Jose, CA, November 6-10 2005.
- [3537]
- H. Qian and S. S.
Sapatnekar.
Fast poisson solvers for thermal analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 698-702, San Jose, CA, November 7-11 2010.
- [3538]
- Z. Qin and C.-K. Cheng.
Realizable parasitic reduction using generalized Y-delta transformation.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
220-225, Anaheim, CA, June 2-6 2003.
- [3539]
- Q. Qiu, Q. Wu,
M. Pedram, and C.-S. Ding.
Cycle-accurate macro-models for RT-level power analysis.
In 1997 International Symposium on Low Power Electronics and Design,
pages 125-130, Monterey, CA, August 18-20 1997.
- [3540]
- Q. Qiu, Q. Wu, and
M. Pedram.
Maximum power estimation using the limiting distributions of extreme order
statistics.
In IEEE/ACM 35th Design Automation Conference, pages 684-689, San
Francisco, CA, June 15-19 1998.
- [3541]
- Q. Qiu, Q. Wu, and
M. Pedram.
Stochastic modeling of a power-managed system: construction and optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 194-199, San Diego, CA, August 16-17 1999.
- [3542]
- Q. Qiu, Q. Wu, and
M Pedram.
Dynamic power management of complex systems using generalized stochastic petri
nets.
In Design Automation Conference, pages 352-356, Los Angeles, CA, June
5-9 2000.
- [3543]
- Q. Qiu, Y. Tan, and
Q. Wu.
Stochastic modeling and optimization for robust power management in a partially
observable system.
Design, Automation and Test in Europe (DATE-07), pages 779-784, April
16-20 2007.
- [3544]
- X. Qiu,
M. Marek-Sadowska, and W. P. Maly.
Characterizing vesfet-based ics with CMOS-oriented EDA infrastructure.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(4):495-506, April 2014.
- [3545]
- Q. Qiu and M. Pedram.
Dynamic power management based on continuous-time markov decision processes.
In Design Automation Conference, pages 555-561, New Orleans, LA, June
21-25 1999.
- [3546]
- G. Qu, N. Kawabe,
K. Usami, and M. Potkonjak.
Function-level power estimation methodology for microprocessors.
In Design Automation Conference, pages 810-813, Los Angeles, CA, June
5-9 2000.
- [3547]
- G. Qu and L. Yuan.
Design THINGS for the internet of things - an EDA perspective.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 411-416, San Jose, CA, November 2-6 2014.
- [3548]
- N. T. Quach,
N. Takagi, and M. J. Flynn.
Systematic IEEE rounding method for high-speed floating-point multipliers.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):511-521, May 2004.
- [3549]
- J. M. Rabaey,
C. Chu, P. Hoang, and M. Potkonjak.
Fast prototyping of datapath-intensive architectures.
IEEE Design & Test of Computers, 8(2):40-51, June 1991.
- [3550]
- J. M. Rabaey,
M. Potkonjak, F. Koushanfar, S.-F. Li, and T. Tuan.
Challenges and opportunities in broadband and wireless communication designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 76-82, San Jose, CA, November 5-9 2000.
- [3551]
- J. M. Rabaey.
Exploring the power dimension.
In IEEE 1996 Custom Integrated Circuits Conference, pages 215-220,
San Diego, CA, May 5-8 1996.
- [3552]
- J. M. Rabaey.
System-level power estimation and optimization - challenges and perspectives.
In 1997 International Symposium on Low Power Electronics and Design,
pages 158-160, Monterey, CA, August 18-20 1997.
- [3553]
- D. Rabe and W. Nebel.
Short circuit power consumption of glitches.
In International Symposium on Low Power Electronics and Design, pages
125-128, Monterey, CA, August 12-14 1996.
- [3554]
- M. O. Rabin.
Probabilistic algorithms.
In J. F. Traub, editor, Algorithms and Complexity, pages 21-39.
Academic Press, Inc., New York, NY, 1976.
- [3555]
- E. Rachlin and J. E.
Savage.
Nanowire addressing with randomized-contact decoders.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 735-742, San Jose, CA, November 5-9 2006.
- [3556]
- R. M. P. Rad and
M. Tehranipoor.
A new hybrid FPGA with nanoscale clusters and CMOS routing.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
727-730, San Francisco, CA, July 24-28 2006.
- [3557]
- V. Raghavan and
R. A. Rohrer.
AWE-right.
In Custom Integrated Circuit Conference (CICC-93), 1993.
- [3558]
- T. Ragheb and
Y. Massoud.
On the modeling of resistance in graphene nanoribbon (GNR) for future
interconnect applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 593-597, San Jose, CA, November 10-13 2008.
- [3559]
- A. Raghunathan, S. Dey, and N. K. Jha.
Glitch analysis and reduction in register transfer level power optimization.
In 33rd Design Automation Conference, pages 331-336, Las Vegas, NV,
June 3-7 1996.
- [3560]
- A. Raghunathan, S. Dey, and N. K. Jha.
Register-transfer level estimation techniques for switching activity and power
consumption.
In IEEE/ACM International Conference on Computer-Aided Design, pages
158-165, San Jose, CA, November 10-14 1996.
- [3561]
- A. Raghunathan, S. Dey, N. K. Jha, and K. Wakabayashi.
Controller re-specification to minimize switching activity in controller/data
path circuits.
In International Symposium on Low Power Electronics and Design, pages
301-304, Monterey, CA, August 12-14 1996.
- [3562]
- A. Raghunathan, S. Dey, N. K. Jha, and K. Wakabayashi.
Power management techniques for control-flow intensive designs.
In 34th Design Automation Conference, pages 429-434, Anaheim, CA,
June 9-13 1997.
- [3563]
- A. Raghunathan, S. Dey, and N. K. Jha.
Register transfer level power optimization with emphasis on glitch analysis and
reduction.
IEEE Transactions on Computer-Aided Design, 18(8):1114-1131, August
1999.
- [3564]
- V. Raghunathan, S. Ravi, A. Raghunathan, and G. Lakshminarayana.
Transient power management through high-level synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 545-552, San Jose, CA, November 4-8 2001.
- [3565]
- A. Raghunathan, S. Dey, and N. K. Jha.
High-level marco-modeling and estimation techniques for switching activity and
power consumption.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):538-557, August 2003.
- [3566]
- A. Raghunathan, S. Dey, and V. Kozhikkottu.
Recovery-based design for variation-tolerant socs.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
826-833, San Francisco, CA, June 3-7 2012.
- [3567]
- V. Raghunathan
and P.-H. Chou.
Design and power management of energy harvesting embedded systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 369-374, Tegernsee, Germany, October 4-6 2006.
- [3568]
- A. Rahman and
V. Polavarapuv.
Evaluation of low-leakage design techniques for field-programmable gate arrays.
In ACM/SIGDA International Symposium on Field Programmable Gate
Arrays, pages 23-30, Monterey, CA, February 22-24 2004.
- [3569]
- A.-M. Rahmani,
M.-H. Haghbayan, A. Kanduri, A. Y. Weldezion, P. Liljeberg, J. Plosila,
A. Jantsch, and H. Tenhunen.
Dynamic power management for many-core platforms in the dark silicon era: a
multi-objective control approach.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 219-224, Rome, Italy, July 22-24 2015.
- [3570]
- A. M. Rahmani,
M.-H. Haghbayan, A. Miele, P. Liljeberg, A. Jantsch, and H. Tenhunen.
Reliability-aware runtime power management for many-core systems in the dark
silicon era.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(2):427-440, February 2017.
- [3571]
- S. Rai, S. Srinivasa,
P. Cadareanu, X. Yin, X.-S. Hu, P.-E. Gaillardon, V. Narayanan, and A. Kumar.
Emerging reconfigurable nanotechnologies: can they support future electronics?
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [3572]
- R. Raimi and J. Abraham.
Detecting false timing paths: experiments on powerpc microprocessors.
In Design Automation Conference, pages 737-741, New Orleans, LA, June
21-25 1999.
- [3573]
- Gordon Raisbeck.
Information Theory.
The MIT Press, Cambridge, MA, 1963.
- [3574]
- S. Raj, S. B. K.
Vrudhula, and J. Wang.
A methodology to improve timing yield in the presence of process variations.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
448-453, San Diego, CA, June 7-11 2004.
- [3575]
- S. Raja, F. Varadi,
M. Becer, and J. Geada.
Transistor level gate modeling for accurate and fast timing, noise, and power
analysis.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
456-461, Anaheim, CA, June 8-13 2008.
- [3576]
- T. Raja, V. D.
Agrawal, and M. L. Bushnell.
Variable input delay CMOS logic for low power design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(10):1534-1545, October 2009.
- [3577]
- A. Rajaram,
B. Lu, W. Guo, R. Mahapatra, and J. Hu.
Analytical bound for unwanted clock skew due to wire width variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 401-406, San Jose, CA, November 9-13 2003.
- [3578]
- A. Rajaram,
J. Hu, and R. Mahapatra.
Reducing clock skew variability via cross links.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 18-23,
San Diego, CA, June 7-11 2004.
- [3579]
- A. Rajaram,
J. Hu, and R. Mahapatra.
Reducing clock skew variability via crosslinks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(6):1176-1182, June 2006.
- [3580]
- A. Rajaram,
B. Lu, J. Hu, R. Mahapatra, and W. Guo.
Analytical bound for unwanted clock skew due to wire width variation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1869-1876, September 2006.
- [3581]
- R. Rajaraman and
D. F. Wong.
Optimum clustering for delay minimization.
IEEE Transactions on Computer-Aided Design, 14(12):1490-1495,
December 1995.
- [3582]
- S. Rajgopal and
G. Mehta.
Experiences with simulation-based schematic-level current estimation.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
9-14, Napa, CA, April 24-27 1994.
- [3583]
- M. Raji and B. Ghavami.
Soft error rate reduction of combinational circuits using gate sizing in the
presence of process variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(1):247-260, January 2017.
- [3584]
- R. Rajkumar,
I. Lee, L. Sha, and J. Stankovic.
Cyber-physical systems: the next computing revolution.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
731-736, Anaheim, CA, June 13-18 2010.
- [3585]
- J. Rajski and
J. Vasudevamurthy.
The testability-preserving concurrent decomposition and factorization of
boolean expressions.
IEEE Transactions on Computer-Aided Design, 11(6):778-793, June
1992.
- [3586]
- A. Rak and G. Cserey.
Macromodeling of the memristor in SPICE.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):632-641, April 2010.
- [3587]
- D. Rakhmatov
and S. B. K. Vrudhula.
Time-to-failure estimation for batteries in portable electronic systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 88-91, Huntington Beach, California, August 6-7 2001.
- [3588]
- D. Ramachandran, S. Irani, and R. K. Gupta.
An analysis of system level power management algorithms and their effects on
latency.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(3):291-305, March 2002.
- [3589]
- C. Ramachandran and F. J. Kurdahi.
Combined topological and functionality-based delay estimation using a
layout-driven approach for high-level applications.
IEEE Transactions on Computer-Aided Design, 13(12):1450-1460,
December 1994.
- [3590]
- V. Ramachandran.
Algorithmic aspects of MOS VLSI switch-level simulation with race
detection.
IEEE Transactions on Computers, C-35(5):462-475, May 1986.
- [3591]
- A. Ramalingam, A. K. Singh, S. R. Nassif, G.-J. Nam,
M. Orshansky, and D.-Z. Pan.
An accurate sparse matrix based framework for statistical static timing
analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 231-236, San Jose, CA, November 5-9 2006.
- [3592]
- A. Ramalingam, G. V. Devarayanadurg, and D. Z. Pan.
Accurate power grid analysis with behavioral transistor network modeling.
In ACM International Symposium on Physical Design (ISPD-07), pages
43-50, Austin, TX, March 18-21 2007.
- [3593]
- A. Ramalingam, A. K. Singh, S. R. Nassif, M. Orshansky, and
D. Z. Pan.
Accurate waveform modeling using singular value decomposition with applications
to timing analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 67-72, Austin, Texas,
February 26-27 2007.
- [3594]
- A. Ramalingam, A. K. Singh, S. R. Nassif, M. Orshansky, and
D. Z. Pan.
Accurate waveform modeling using singular value decomposition with applications
to timing analysis.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
148-153, San Diego, CA, June 4-8 2007.
- [3595]
- D. Ramanathan, S. Irani, and R. Gupta.
Latency effects of system level power management algorithms.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 350-355, San Jose, CA, November 5-9 2000.
- [3596]
- S. S. Ramani and
S. Bhanja.
Any-time probabilistic switching model using bayesian networks.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 86-89, Newport Beach, CA, August 9-11 2004.
- [3597]
- B. Ramkumar and
H. M. Kittur.
Low-power and area-efficient carry select adder.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):371-375, February 2012.
- [3598]
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj.
Achievable bounds on signal transition activity.
In IEEE/ACM International Conference on Computer-Aided Design, pages
126-129, San Jose, CA, November 9-13 1997.
- [3599]
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj.
Analytical estimation of signal transition activity from word-level statistics.
IEEE Transactions on Computer-Aided Design, 16(7):718-733, July
1997.
- [3600]
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj.
Analytical estimation of transition activity from word-level signal statistics.
In 34th Design Automation Conference, pages 582-587, Anaheim, CA,
June 9-13 1997.
- [3601]
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj.
Decorrelating (DECOR) transformations for low-power adaptive filters.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 250-255, Monterey, CA, August 10-12 1998.
- [3602]
- S. Ramprasad, I. N. Hajj, and F. N. Najm.
An optimization technique for dual-output domino logic.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 258-260, San Diego, CA, August 16-17 1999.
- [3603]
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj.
A coding framework for low-power address and data busses.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
7(2):212-221, June 1999.
- [3604]
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj.
Information-theoretic bounds on average signal transition activity.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(3):359-368, September 1999.
- [3605]
- S. Ramprasad, I. N. Hajj, and F. N. Najm.
A technique for improving dual-output domino logic.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(4):508-511, August 2002.
- [3606]
- S. Ramprasath and V. Vasudevan.
On the computation of criticality in statistical timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 172-179, San Jose, CA, November 5-8 2012.
- [3607]
- S. Ramprasath and V. Vasudevan.
Statistical criticality computation using the circuit delay.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(5):717-727, May 2014.
- [3608]
- S. Ramprasath and V. Vasudevan.
An efficient algorithm for statistical timing yield optimization.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [3609]
- Y. Ran, A. Kondratyev,
K.-T. Tseng, Y. Watanabe, and M. Marek-Sadowska.
Eliminating false positives in corsstalk noise analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(9):1406-1419, September 2005.
- [3610]
- Y. Ran and
M. Marek-Sadowska.
Via-configurable routing architectures and fast design mappability estimation
for regular fabrics.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 25-32, San Jose, CA, November 6-10 2005.
- [3611]
- V. Rao, J. Soreff,
T. Brodnax, and R. Mains.
Einstlt: Transistor level timing with einstimer.
In ACM/IEEE 1999 International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU-99), pages 1-6,
Monterey, CA, March 8-9 1999.
- [3612]
- R. Rao,
A. Srivastava, D. Blaauw, and D. Sylvester.
Statistical estimation of leakage current considering inter- and intra-die
process variation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 84-89, Seoul, Korea, August 25-27 2003.
- [3613]
- R. M. Rao, J. L.
Burns, A. Devgan, and R. B. Brown.
Efficient techniques for gate leakage estimation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 100-103, Seoul, Korea, August 25-27 2003.
- [3614]
- R. M. Rao, F. Liu,
J. L. Burns, and R. B. Brown.
A heuristic to determine low leakage sleep state vectors for CMOS
combinational circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 689-692, San Jose, CA, November 9-13 2003.
- [3615]
- R. Rao, A. Agarwal,
D. Sylvester, R. Brown, K. Nowka, and S. Nassif.
Approaches to run-time and standby mode leakage reduction in global buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 188-193, Newport Beach, CA, August 9-11 2004.
- [3616]
- R. Rao,
A. Srivastava, D. Blaauw, and D. Sylvester.
Statistical analysis of subthreshold leakage current for VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(2):131-139, February 2004.
- [3617]
- R. R. Rao,
A. Devgan, D. Blaauw, and D. Sylvester.
Parametric yield estimation considering leakage variability.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
442-447, San Diego, CA, June 7-11 2004.
- [3618]
- R. R. Rao, H. S.
Deogun, D. Blaauw, and D. Sylvester.
Bus encoding for total power reduction using a leakage-aware buffer
configuration.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(12):1376-1383, December 2005.
- [3619]
- R. R. Rao,
D. Blaauw, and D. Sylvester.
Soft error reduction in combinational logic using gate resizing and flipflop
selection.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 502-509, San Jose, CA, November 5-9 2006.
- [3620]
- R. R. Rao, A. Devgan,
D. Blaauw, and D. Sylvester.
Analytical yield prediction considering leakage/performance correlation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1685-1695, September 2006.
- [3621]
- W. Rao,
A. Orailoglu, and R. Karri.
Topology aware mapping of logic functions onto nanowire-based crossbar
architectures.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
723-726, San Francisco, CA, July 24-28 2006.
- [3622]
- R. R. Rao, K. Chopra,
D. T. Blaauw, and D. M. Sylvester.
Computing the soft error rate of a combinational logic circuit using
parameterized descriptors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(3):468-479, March 2007.
- [3623]
- V. Rao, D. Sinha,
N. Srimal, and P. K. Maurya.
Statistical path tracing in timing graphs.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [3624]
- R. Rao and S. Vrudhula.
Energy-optimal speed control of a generic device.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2737-2746, December 2006.
- [3625]
- N. Narayana Rao.
Elements of Engineering Electromagnetics.
Prentice Hall, Inc., Englewood Cliffs, NJ, 1986.
- [3626]
- V. B. Rao.
Delay analysis of the distributed RC line.
In 32nd Design Automation Conference, pages 370-375, San Francisco,
CA, June 12-16 1995.
- [3627]
- G. Rappitsch, E. Seebacher, M. Kocher, and E. Stadlober.
SPICE modeling of process variation using location depth corner models.
IEEE Transactions on Semiconductor Manufacturing, 17(2):201-213, May
2004.
- [3628]
- A. Rastogi,
W. Chen, and S. Kundu.
On estimating impact of loading effect on leakage current in sub-65nm scaled
CMOS circuits based on newton-raphson method.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
712-715, San Diego, CA, June 4-8 2007.
- [3629]
- C. L.
Ratzlaff, S. Pullela, and L. T. Pillage.
Modeling the RC-interconnect effects in a hierarchical timing analyzer.
In IEEE 1992 Custom Integrated Circuits Conference, pages
15.6.1-15.6.4, May 1992.
- [3630]
- K. Ravi and F. Somenzi.
High-density reachability analysis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
154-158, San Jose, CA, November 5-9 1995.
- [3631]
- C. Ravishankar, J. H. Anderson, and A. Kennings.
FPGA power reduction by guarded evaluation considering logic architecture.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(9):1305-1318, September 2012.
- [3632]
- S. Ray.
Transportation security in the era of autonomous vehicles: challenges and
practice.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 1020-1024, Irvine CA, November 13-16 2017.
- [3633]
- A. Raychowdhury, S. Mukhopadhyay, and K. Roy.
A circuit-compatible model of ballistic carbon nanotube field-effect
transistors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(10):1411-1420, October 2004.
- [3634]
- A. Raychowdhury, B. C. Paul, S. Bhunia, and K. Roy.
Computing with subthreshold leakage: device/circuit/architecture co-design for
ultralow-power subthreshold operation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1213-1224, November 2005.
- [3635]
- A. Raychowdhury and K. Roy.
Modeling of metallic carbon-nanotube interconnects for circuit simulations and
a comparison with cu interconnects for scaled technologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):58-65, January 2006.
- [3636]
- A. Raychowdhury and K. Roy.
Carbon nanotube electronics: design of high-performance and low-power digital
circuits.
IEEE Transactions on Circuits and Systems, 54(11):2391-2401, November
2007.
- [3637]
- A. Raychowdhury.
Spin torque devices in embedded memory: model studies and design space
exploration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 572-575, San Jose, CA, November 18-21 2013.
- [3638]
- A. Raychowhury, X. Fong, Q. Chen, and K. Roy.
Analysis of super cut-off transistors for ultralow power digital logic
circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 2-7, Tegernsee, Germany, October 4-6 2006.
- [3639]
- B. Reagen,
U. Gupta, L. Pentecost, P. Whatmough, S.-K. Lee, N. Mulholl, D. Brooks, and
G.-Y. Wei.
Ares: a framework for quantifying the resilience of deep neural networks.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [3640]
- S. M. Reddy,
V. D. Agrawal, and S. K. Jain.
A gate level model for CMOS combinational logic circuits with application to
fault detection.
In IEEE 21st Design Automation Conference, pages 504-509,
Albuquerque, NM, June 25-27 1984.
- [3641]
- S. M. Reddy,
M. K. Reddy, and V. D. Agrawal.
Robust tests for stuck-open faults in CMOS combinational logic circuits.
In IEEE 14th International Symposium on Fault Tolerant Computing,
pages 44-49, Kissimee, FL, June 20-22 1984.
- [3642]
- M. K. Reddy, S. M.
Reddy, and P. Agrawal.
Transistor level test generation for MOS circuits.
In IEEE 22nd Design Automation Conference, pages 825-828, 1985.
- [3643]
- S. M. Reddy and M. K.
Reddy.
Testable realizations for FET stuck-open faults in CMOS combinational logic
circuits.
IEEE Transactions on Computers, C-35(8):742-754, August 1986.
- [3644]
- T. L. Reed.
Using the taguchi method of parameter design for improving product reliability.
In Tutorial Notes, Annual Reliability and Maintainability Symposium,
Washington, DC, January 16-19 1995.
- [3645]
- S. Rehman,
W. El-Harouni, M. Shafique, A. Kumar, and J. Henkel.
Architectural-space exploration of approximate multipliers.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [3646]
- A. Reimer,
A. Schulz, and W. Nebel.
Modelling macromodules for high-level dynamic power estimation of FPGA-based
digital designs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 151-154, Tegernsee, Germany, October 4-6 2006.
- [3647]
- E. M.
Reingold, J. Nievergelt, and N. Deo.
Combinatorial algorithms, theory and practice.
Prentice-Hall, Inc., Englewood Cliffs, NJ, 1977.
- [3648]
- T. Reis and R. Stykel.
PABTEC: passivity-preserving balanced truncation for electrical circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(9):1354-1367, September 2010.
- [3649]
- T. Rejimon,
K. Lingasubramanian, and S. Bhanja.
Probabilistic error modeling for nano-domain logic circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(1):55-65, January 2009.
- [3650]
- T. Rejimon and
S. Bhanja.
A timing-aware probabilistic model for single-event-upset analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(10):1130-1139, October 2006.
- [3651]
- L. Ren, X. Chen,
Y. Wang, C. Zhang, and H. Yang.
Sparse LU factorization for parallel circuit simulation on GPU.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1125-1130, San Francisco, CA, June 3-7 2012.
- [3652]
- P. Ren, M. Lis, M.-H.
Cho, K.-S. Shim, C. W. Fletcher, O. Khan, N. Zheng, and S. Devadas.
Hornet: a cycle-level multicore simulator.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(6):890-903, June 2012.
- [3653]
- P. Rezvani,
A. H. Ajami, M. Pedram, and H. Savoj.
LEOPARD: A logical effort-based fanout optimizer for area and delay.
In IEEE/ACM International Conference on Computer-Aided Design, pages
516-519, San Jose, CA, November 7-11 1999.
- [3654]
- P. Rezvani and
M. Pedram.
A fanout optimization algorithm based on the effort delay model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(12):1671-1678, December 2003.
- [3655]
- J-K Rho, F. Somenzi,
and C. Pixley.
Minimum length synchronizing sequences of finite state machine.
In 30th ACM/IEEE Design Automation Conference, pages 463-468, Dallas,
Texas, June 14-18 1993.
- [3656]
- M. S. Riazi and
F. Koushanfar.
Privacy-preserving deep learning and inference.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [3657]
- S. E. Rich, M. J.
Parker, and J. Schwartz.
Reducing the frequency gap between ASIC and custom designs: A custom
perspective.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
432-437, Las Vegas, NV, June 18-22 2001.
- [3658]
- R. Rithe, S. Chou,
J. Gu, A. Wang, S. Datla, G. Gammie, D. Buss, and A. Chandrakasan.
The effect of random dopant fluctuations on logic timing at low voltage.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(5):911-924, May 2012.
- [3659]
- J. Rius.
IR-drop in on-chip power distribution networks of ics with nonuniform power
consumption.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(3):512-522, March 2013.
- [3660]
- J. Rius.
Supply noise and impedance of on-chip power distribution networks in ics with
nonuniform power consumption and interblock decoupling capacitors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(6):993-1004, June 2015.
- [3661]
- J. Rizo-Morente, M. Casas-Sanchez, and C. J. Bleakley.
Dynamic current modeling at the instruction level.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 95-100, Tegernsee, Germany, October 4-6 2006.
- [3662]
- V. Rizzoli,
D. Masotti, F. Mastri, and E. Montanari.
System-oriented harmonic-balance algorithms for circuit-level simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(2):256-269, February 2011.
- [3663]
- E. Roa, W.-H. Chen,
and B. Jung.
Material implication in CMOS: a new kind of logic.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1254-1255, San Francisco, CA, June 3-7 2012.
- [3664]
- W. Robinett,
P. J. Kuekes, and R. S. Williams.
Defect tolerance based on coding and series replication in transistor-logic
demultiplexer circuits.
IEEE Transactions on Circuits and Systems, 54(11):2410-2421, November
2007.
- [3665]
- G. Robins,
J. Huang, and J. Lach.
A methodology for energy-quality tradeoff using imprecise hardware.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
504-509, San Francisco, CA, June 3-7 2012.
- [3666]
- S. H. Robinson and
J. P. Shen.
Towards a switch-level test pattern generation program.
In IEEE International Conference on Computer-Aided Design, pages
39-41, Santa Clara, CA, Nov. 18-21 1985.
- [3667]
- S. Rochel and N. S.
Nagaraj.
Full-chip signal interconnect analysis for electromigration reliability.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 337-340, San Jose, CA, March 20-22 2000.
- [3668]
- P. Rodman.
Forest vs trees: where's the slack.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
267-267, San Diego, CA, June 7-11 2004.
- [3669]
- R. Rodriguez, J. H. Stathis, and B. P. Linder.
Modeling and experimental verification of the effect of gate oxide breakdown on
CMOS inverters.
In International Reliability Physics Symposium (IRPS), pages 11-16,
Dallas, TX, March 30-April 4 2003.
- [3670]
- A. Rogachev,
L. Wan, and D. Chen.
Temperature aware statistical static timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 103-110, San Jose, CA, November 7-10 2011.
- [3671]
- B. Rohfleisch, A. Kolbl, and B. Wurth.
Reducing power dissipation after technology mapping by structural
transformations.
In 33rd Design Automation Conference, pages 789-794, Las Vegas, NV,
June 3-7 1996.
- [3672]
- R. Rohrer.
Fully automated network design by digital computer: preliminary considerations.
In Proceedings of the IEEE, pages 1929-1939, November 1967.
- [3673]
- R. A. Rohrer.
Circuit partitioning simplified.
IEEE Transactions on Circuits and Systems, 35(1):2-5, January
1988.
- [3674]
- D. R. Rolston,
D. M. Gross, G. W. Roberts, and D. V. Plant.
A distributed synchronized clocking method.
IEEE Transactions on Circuits and Systems, 52(8):1597-1607, August
2005.
- [3675]
- J. Rommes and
W. H. A. Schilders.
Efficent methods for large resistor networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(1):28-39, January 2010.
- [3676]
- P. Rong and M. Pedram.
Battery-aware power management based on markovian decision processes.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 707-713, San Jose, CA, November 10-14 2002.
- [3677]
- P. Rong and M. Pedram.
An analytical model for predicting the remaining battery capacity of
lithium-ion batteries.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(5):441-451, May 2006.
- [3678]
- P. Rong and M. Pedram.
Battery-aware power management based on markovian decision processes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1337-1349, July 2006.
- [3679]
- G. S. Rose, M. M.
Ziegler, and M. R. Stan.
Large-signal two-terminal device model for nanoelectronic circuit analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(11):1201-1208, November 2004.
- [3680]
- J. Rosenfeld
and E. G. Friedman.
Design methodology for global resonant H-tree clock distribution networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(2):135-148, February 2007.
- [3681]
- J. Rosenfeld
and E. G. Friedman.
Quasi-resonant interconnects: a low power, low latency design methodology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):181-193, February 2009.
- [3682]
- A. Rosenthal.
Computing the reliability of complex networks.
SIAM Journal on Applied Mathematics, 32(2):384-393, March 1977.
- [3683]
- T. S. Rosing,
K. Mihic, and G. De Micheli.
Power and reliability management of socs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(4):391-403, April 2007.
- [3684]
- T. Roska.
Cellular wave computers and CNN technology - a soc architecture with xk
processors and sensor arrays.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 557-564, San Jose, CA, November 6-10 2005.
- [3685]
- Sheldon Ross.
Stochastic Processes.
John Wiley & Sons, New York, NY, 1983.
- [3686]
- J. L. Rossello and
J. Segura.
Power-delay modeling of dynamic CMOS gates for circuit optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 494-499, San Jose, CA, November 4-8 2001.
- [3687]
- J. L. Rossello and
J. Segura.
Charge-based analytical model for the evaluation of power consumption in
submicron CMOS buffers.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(4):433, April 2002.
- [3688]
- D. Rossi, A. K.
Nieuwland, S. V. E. S. van Dijk, R. P. Kleihorst, and C. Metra.
Power consumption of fault tolerant busses.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(5):542-553, May 2008.
- [3689]
- D. Rossi, J. M.
Cazeaux, M. Omana, C. Metra, and A. Chatterjee.
Accurate linear model for SET critical charge estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(8):1161-1166, August 2009.
- [3690]
- D. Rossi,
V. Tenentes, S. Yang, S. Khursheed, and B. M. Al-Hashimi.
Reliable power gating with NBTI aging benefits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(8):2735-2744, August 2016.
- [3691]
- J. P. Roth, W. G.
Bouricius, and P. R. Schneider.
Programmed algorithms to compute tests to detect and distinguish between
failures in logic circuits.
IEEE Transactions on Electronic Computers, EC-16(5):71-84, October
1967.
- [3692]
- J. P. Roth, V. G.
Oklobdzija, and J. F. Beetem.
Test generation for FET switching circuits.
In IEEE International Test Conference, pages 59-62, 1984.
- [3693]
- J. P. Roth.
Algebraic topological methods for the synthesis of switching systems I.
Transactions of the American Mathematical Society, 88(2):301-326,
July 1958.
- [3694]
- J. P. Roth.
Diagnosis of automata failure: a calculus and a method.
IBM Journal of Research and Development, 10(4):278-291, July 1966.
- [3695]
- John Paul Roth.
Computer Logic, Testing, and Verification.
Computer Science Press, Inc., Potomac, MD, 1980.
- [3696]
- P. W. K. Rothemund.
Design of DNA origami.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 471-478, San Jose, CA, November 6-10 2005.
- [3697]
- F. Rouatbi,
B. Haroun, and A. J. Al-Khalili.
Power estimation tool for sub-micron CMOS VLSI circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
204-209, Santa Clara, CA, November 8-12 1992.
- [3698]
- B. D.
Rouhani, M. S. Riazi, and F. Koushanfar.
Deepsecure: scalable provably-secure deep learning.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [3699]
- B. D.
Rouhani, M. Samragh, M. Javaheripi, T. Javidi, and F. Koushanfar.
Assured deep learning: practical defense against adversarial attacks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [3700]
- S. Roy, H. Arts, and
P. Banerjee.
Powerdrive: A fast, canonical power estimator for driving synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
601-606, San Jose, CA, November 8-12 1998.
- [3701]
- A. Roy, N. Mahmoud,
and M. H. Chowdhury.
Effects of coupling capacitance and inductance on delay uncertainty and clock
skew.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
184-187, San Diego, CA, June 4-8 2007.
- [3702]
- S. Roy, W. Chen,
C. C.-P. Chen, and Y. H. Hu.
Numerically convex forms and their application in gate sizing.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(9):1637-1647, September 2007.
- [3703]
- S. Roy, P. P.
Chakrabarti, and P. Dasgupta.
Satisfiability models for maximum transition power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(8):941-951, August 2008.
- [3704]
- K. Roy, J. P.
Kulkarni, and S. K. Gupta.
Device/circuit interactions at 22nm technology node.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 97-102,
San Francisco, CA, July 26-31 2009.
- [3705]
- A. Roy, J. Xu, and
M. H. Chowdhury.
Analysis of the impacts of signal slew and skew on the behavior of coupled
RLC interconnects for different switching patterns.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):338-342, February 2010.
- [3706]
- K. Roy, M. Sharad,
D. Fan, and K. Yogendra.
Exploring boolean and non-boolean computing with spin torque devices.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 576-580, San Jose, CA, November 18-21 2013.
- [3707]
- S. Roy, M. Choudhury,
R. Puri, and D.-Z. Pan.
Polynomial time algorithm for area and power efficient adder synthesis in
high-performance designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(5):820-831, May 2016.
- [3708]
- S. Roy and P. Banerjee.
An algorithm for converting floating-point computations to fixed-point in
MATLAB based FPGA design.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
484-487, San Diego, CA, June 7-11 2004.
- [3709]
- S. Roy and
K. Chakraborty.
Predicting timing violations through instruction-level path sensitization
analysis.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1074-1081, San Francisco, CA, June 3-7 2012.
- [3710]
- S. Roy and A. Dounavis.
Closed-form delay and crosstalk models for RLC on-chip interconnects using a
matrix rational approximation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(10):1481-1492, October 2009.
- [3711]
- S. Roy and A. Dounavis.
Efficient delay and crosstalk modeling of RLC interconnects using delay
algebraic equations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(2):342-346, February 2011.
- [3712]
- S. C. Dutta Roy and
S. Minocha.
On the evaluation of a matrix polynomial.
IEEE Transactions on Circuits and Systems - I, 39(7):567-570, July
1992.
- [3713]
- K. Roy and S. Prasad.
SYCLOP: Synthesis of CMOS logic for low power applications.
In IEEE International Conference on Computer Design, pages 464-467,
1992.
- [3714]
- K. Roy and S. C. Prasad.
Circuit activity based logic synthesis for low power reliable operations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
1(4):503-513, December 1993.
- [3715]
- D. Roy.
Discrete rayleigh distribution.
IEEE Transactions on Reliability, 53(2):255-260, June 2004.
- [3716]
- P. Royannez,
H. Mair, F. Dahan, M. Wagner, M. Streeter, L. Bouetel, J. Blasquez,
H. Clasen, S. Semino, J. Dong, D. Scott, B. Pitts, C. Raibaut, and U. Ko.
A design platform for 90-nm leakage reduction techniques.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
549-550, Anaheim, CA, June 13-17 2005.
- [3717]
- J. S. Roychowdhury, A. R. Newton, and D. O. Pederson.
Simulating lossy interconnect with high frequency nonidealities in linear time.
In 29th ACM/IEEE Design Automation Conference, pages 75-80, Anaheim,
CA, June 8-12 1992.
- [3718]
- J. Roychowdhury and R. Melville.
Delivering global DC convergence for large mixed-signal circuits via
homotopy/continuation methods.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):66-78, January 2006.
- [3719]
- J. Roychowdhury.
Micro-photonic interconnects: characteristics, possibilities and limitations.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
574-575, San Diego, CA, June 4-8 2007.
- [3720]
- G. M. Royer.
A monte carlo procedure for potential theory problems.
IEEE Transactions on Microwave Theory and Techniques,
MTT-19(10):813-818, October 1971.
- [3721]
- N. Rubanov.
Subislands: The probabilistic match assignment algorithm for subcircuit
recgonition.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(1):26-38, January 2003.
- [3722]
- N. Rubanov.
High-performance subcircuit recognition method based on the nonlinear graph
optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2353-2363, November 2006.
- [3723]
- N. Rubanov.
A general framework to perform the MAX/MIN operations in parameterized
statistical timing analysis using information theoretic concepts.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(7):1011-1019, July 2011.
- [3724]
- J. Rubenstein, P. Penfield, Jr., and M. A. Horowitz.
Signal delay in RC tree networks.
IEEE Transactions on Computer-Aided Design, CAD-2(3):202-211, July
1983.
- [3725]
- A. Rubio,
N. Itazaki, X. Xu, and K. Kinoshita.
An approach to the analysis and detection of crosstalk faults in digital VLSI
circuits.
IEEE Transactions on Computer-Aided Design, 13(3):387-395, March
1994.
- [3726]
- Sergiu Rudeanu.
Boolean Functions and Equations.
North Holland Publishing Company, American Elsevier Publishing Co. Inc., New
York, NY, 1974.
- [3727]
- J. C. Rudell,
J-J Ou, R. S. Narayanaswami, G. Chien, J. A. Weldon, L. Lin, K-C Tsai,
L. Tee, K. Khoo, D. Au, T. Robinson, D. Gerna, M. Otsuka, and P. R. Gray.
Rcent developments in high integration multi-standard CMOS transceivers for
personal communication systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 149-154, Monterey, CA, August 10-12 1998.
- [3728]
- R. Rudell.
Dynamic variable ordering for ordered binary decision diagrams.
In IEEE/ACM International Conference on Computer-Aided Design, pages
42-47, Santa Clara, CA, November 7-11 1993.
- [3729]
- R. Rudell.
Tutorial: Design of a logic synthesis system.
In 33rd Design Automation Conference, pages 191-196, Las Vegas, NV,
June 3-7 1996.
- [3730]
- A. E. Ruehli,
N. Kulasza, and J. Pivnichny.
Inductance of nonstraight conductors close to a ground return plane.
IEEE Transactions on Microwave Theory and Techniques, pages 706-708,
August 1975.
- [3731]
- A. E. Ruehli,
C. Paul, and J. Garrett.
Inductance calculations using partial inductances and macromodels.
In IEEE International Symposium on Electromagnetic Compatibility
(EMC), pages 23-28, Atlanta, GA, August 1995.
- [3732]
- A. E. Ruehli and
J. Hayes.
Nonlinear circuit solver with linear interconnect load.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 195-198, San Jose, CA, October 27-29 2008.
- [3733]
- A. E. Ruehli.
Inductance calculations in a complex integrated circuit environment.
IBM Journal of Research and Development, 16(5):470-481, September
1972.
- [3734]
- A. E. Ruehli.
Survey of computer-aided electrical analysis of integrated circuit
interconnections.
IBM Journal of Research and Development, 23(6):626-639, November
1979.
- [3735]
- R. A. Rutenbar and
J. M. Cohn.
Layout tools for analog ics and mixed-signal socs: A survey.
In International Symposium on Physical Design, pages 76-83, San
Diego, CA, April 9-12 2000.
- [3736]
- R. A. Rutenbar.
Analog circuit and layout synthesis revisited.
In ACM International Symposium on Physical Design 2015, page 83,
Monterey, California, March 29 - April 1 2015.
- [3737]
- Y. Ryu and T. Kim.
Clock buffer polarity assignment combined with clock tree generation for
power/ground noise minimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 416-419, San Jose, CA, November 10-13 2008.
- [3738]
- N. Ryzhenko and
S. Burns.
Standard cell routing via boolean satisfiability.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
603-612, San Francisco, CA, June 3-7 2012.
- [3739]
- Y. Saad and M. H. Schultz.
GMRES: A generalized minimal residual algorithm for solving nonsymmetric
linear systems.
SIAM Journal on Scientific and Statistical Computing, 7:856-869, July
1986.
- [3740]
- Y. Saad.
Iterative Methods for Sparse Linear Systems.
SIAM, Philadelphia, PA, 2003.
- [3741]
- M. M. Sabry,
A. Sridhar, J. Meng, A. K. Coskun, and D. Atienza.
Greencool: an energy-efficient liquid cooling design technique for 3-D mpsocs
via channel width modulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(4):524-537, April 2013.
- [3742]
- D. Sacchetto, M. De Marchi, G. DeMicheli, and Y. Leblebici.
Alternative design methodologies for the next generation logic switch.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 231-234, San Jose, CA, November 7-10 2011.
- [3743]
- S. Sadasivam, Z. Chen, J. Lee, and R. Jain.
Invited: efficient reinforcement learning for automating human decision-making
in soc design.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [3744]
- S. Safarpour, A. Veneris, G. Baeckler, and R. Yuan.
Efficient SAT-based boolean matching for FPGA technology mapping.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
466-471, San Francisco, CA, July 24-28 2006.
- [3745]
- S. Safarpour and
A. Veneris.
Automated design debugging with abstraction and refinement.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(10):1597-1608, October 2009.
- [3746]
- E. Safi,
A. Moshovos, and A. Veneris.
L-CBF: a low-power, fast counting bloom filter architecture.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 250-255, Tegernsee, Germany, October 4-6 2006.
- [3747]
- E. Safi, P. Akl,
A. Moshovos, and A. Veneris.
On the latency, energy and area of checkpointed, superscalar register alias
tables.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 379-382, Portland, Oregon, August 27-29 2007.
- [3748]
- E. Safi,
A. Moshovos, and A. Veneris.
L-CBF: a low-power, fast counting bloom filter architecture.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(6):628-638, June 2008.
- [3749]
- M. Saint-Laurent, V. G. Oklobdzija, S. S. Singh, and
M. Swaminathan.
Optimal sequencing energy allocation for CMOS integrated systems.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 194-199, San Jose, CA, March 18-21 2002.
- [3750]
- M. Saint-Laurent, B. Mohammad, and P. Bassett.
A 65-nm pulsed latch with a single clocked transistor.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 347-350, Portland, Oregon, August 27-29 2007.
- [3751]
- M. Saint-Laurent.
A model for interlevel coupling noise in multilevel interconnect structures.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(5):834-844, May 2007.
- [3752]
- Karem A.
Sakallah, Yao-Tsung Yen, and Steve S. Greenberg.
The meyer model revisited: explaining and correcting the charge
non-conservation problem.
In IEEE International Conference on Computer-Aided Design, pages
204-207, Santa Clara, CA, Nov. 9-12 1987.
- [3753]
- K. A.
Sakallah, T. N. Mudge, and O. A. Olukotun.
Analysis and design of latch-controlled synchronous digital circuits.
In 27th ACM/IEEE Design Automation Conference, pages 111-117,
Orlando, FL, June 24-28 1990.
- [3754]
- K. A.
Sakallah, T. N. Mudge, and O. A. Olukotun.
Analysis and design of latch-controlled synchronous digital circuits.
IEEE Transactions on Computer-Aided Design, 11(3):322-333, March
1992.
- [3755]
- T. Sakamoto,
T. Yamada, M. Mukuno, Y. Matsushita, Y. Harada, and H. Yasuura.
Power analysis techniques for soc with improved wiring models.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 259-262, Monterey, California, August 12-14 2002.
- [3756]
- K. Sakanushi, S. Nakatake, and Y. Kajitani.
The multi-BSG: stochastic approach to an optimum packing of
convex-rectilinear blocks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
267-274, San Jose, CA, November 8-12 1998.
- [3757]
- K. Sakanushi, Y. Kajitani, and D. P. Mehta.
The quarter-state-sequence floorplan representation.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(3):376-386, March 2003.
- [3758]
- C. M. Sakkas.
Potential distribution and multi-terminal dc resistance computations for LSI
technology.
IBM Journal of Research and Development, 23(6):640-651, November
1979.
- [3759]
- T. Sakurai,
S. Kobayashi, and M. Noda.
Simple expressions for interconnection delay, coupling and crosstalk in
VLSI's.
In 1991 IEEE International Symposium on Circuits and Systems, pages
2375-2378, June 1991.
- [3760]
- T. Sakurai,
B. Lin, and A. R. Newton.
Fast simulated diffusion: an optimization algorithm for multiminimum problems
and its application to MOSFET model parameter extraction.
IEEE Transactions on Computer-Aided Design, 11(2):228-234, February
1992.
- [3761]
- T. Sakurai,
H. Kawaguchi, and T. Kuroda.
Low-power CMOS design through vth control and low-swing circuits.
In 1997 International Symposium on Low Power Electronics and Design,
pages 1-6, Monterey, CA, August 18-20 1997.
- [3762]
- T. Sakurai and
A. Richard Newton.
Delay analysis of series-connected MOSFET circuits.
IEEE Journal of Solid-State Circuits, 26(2):122-131, February
1991.
- [3763]
- T. Sakurai.
Approximation of wiring delay in MOSFET LSI.
IEEE Journal of Solid-State Circuits, SC-18(4):418-426, August
1983.
- [3764]
- T. Sakurai.
Closed-form expressions for interconnection delay, coupling, and crosstalk in
VLSI's.
IEEE Transactions on Electron Devices, 40(1):118-124, January
1993.
- [3765]
- T. Sakurai.
Low-power and high-speed VLSI design with low supply voltage through
cooperation between levels.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 445-450, San Jose, CA, March 18-21 2002.
- [3766]
- T. Sakurai.
Minimizing power across multiple technology and design levels.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 24-27, San Jose, CA, November 10-14 2002.
- [3767]
- A. Saldanha.
Functional timing optimization.
In IEEE/ACM International Conference on Computer-Aided Design, pages
539-543, San Jose, CA, November 7-11 1999.
- [3768]
- R. A. Saleh,
B. A. A. Antao, and J. Singh.
Multilevel and mixed-domain simulation of analog circuits and systems.
IEEE Transactions on Computer-Aided Design, 15(1):68-82, January
1996.
- [3769]
- R. Saleh,
D. Overhauser, and S. Taylor.
Full-chip verification of UDSM designs.
In IEEE/ACM International Conference on Computer-Aided Design, pages
453-460, San Jose, CA, November 8-12 1998.
- [3770]
- R. Saleh, S. Z.
Hussain, S. Rochel, and D. Overhauser.
Clock skew verification in the presence of IR-drop in the power distribution
network.
IEEE Transactions on Computer-Aided Design, 19(6):635-644, June
2000.
- [3771]
- S. Salerno,
A. Bocca, E. Macii, and M. Poncino.
Limited intra-word transition codes: an energy-efficient bus encoding for LCD
display interfaces.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 206-211, Newport Beach, CA, August 9-11 2004.
- [3772]
- E. Salman,
A. Dasdan, F. Taraporevala, K. Kucukcakar, and E. G. Friedman.
Exploiting setup-hold interdependence in static timing analyis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(6):1114-1125, June 2007.
- [3773]
- E. Salman, E. G.
Friedman, R. M. Secareanu, and O. L. Hartin.
Worst case power/ground noise estimation using an equivalent transition time
for resonance.
IEEE Transactions on Circuits and Systems, 56(5):997-1004, May
2009.
- [3774]
- A. Salz and M. Horowitz.
IRSIM: An incremental MOS switch-level simulator.
In 26th ACM/IEEE Design Automation Conference, pages 173-178, Las
Vegas, NV, June 25-29 1989.
- [3775]
- A. Sama,
M Balakrishnan, and J. F. M. Theeuwen.
Speeding up power estimation of embedded software.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 191-196, Italy, July 26-27 2000.
- [3776]
- S. B. Samaan.
The impact of device parameter variations on the frequency and performance of
VLSI chips.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 343-346, San Jose, CA, November 7-11 2004.
- [3777]
- S. K. Samal,
S. Panth, K. Samadi, M. Saedi, Y. Du, and S.-K. Lim.
Fast and accurate thermal modeling and optimization for monolithic 3d ics.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [3778]
- S. K. Samal,
K. Samadi, P. Kamal, Y. Du, and S.-K. Lim.
Full chip impact study of power delivery network designs in monolithic 3d ics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 565-572, San Jose, CA, November 2-6 2014.
- [3779]
- S. K. Samal,
K. Samadi, P. Kamal, Y. Du, and S.-K. Lim.
Full chip impact study of power delivery network designs in gate-level
monolithic 3-D ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(6):992-1003, June 2017.
- [3780]
- R. Samanta,
G. Venkataraman, N. Shah, and J. Hu.
Elastic timing scheme for power-efficient and robust performance.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 92-97, Austin, Texas,
February 26-27 2007.
- [3781]
- R. Samanta,
G. Venkataraman, and J. Hu.
Clock buffer polarity assignment for power noise reduction.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(6):770-780, June 2009.
- [3782]
- M. Sami, D. Sciuto,
C. Silvano, and V. Zaccaria.
An instruction-level energy model for embedded VLIW architectures.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(9):998-1010, September 2002.
- [3783]
- C. Sanchez-Lopez, F. V. Fernandesz, E. Tlelo-Cuautle, and
S.-X.-D. Tan.
Pathological element-based active device models and their application to
symbolic analysis.
IEEE Transactions on Circuits and Systems, 58(6):1382-1395, June
2011.
- [3784]
- I. W. Sandberg.
Causality and the impulse response scandal.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(6):810-811, June 2003.
- [3785]
- M. Saneei,
A. Afzali-Kusha, and Z. Navabi.
Sign bit reduction encoding for low power applications.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
214-217, Anaheim, CA, June 13-17 2005.
- [3786]
- J. V.
Sanghavi, R. K Ranjan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
High performance BDD package by exploiting memory hierarchy.
In 33rd Design Automation Conference, pages 635-640, Las Vegas, NV,
June 3-7 1996.
- [3787]
- A. Sangiovanni-Vincentelli, L. Carloni, F. De Bernardinis, and
M. Sgroi.
Benefits and challenges for platform-based design.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
409-414, San Diego, CA, June 7-11 2004.
- [3788]
- A. L.
Sangiovanni-Vincentelli.
Circuit simulation.
In P. Antognetti, D. O. Pederson, and H. De Man, editors, Computer Design
Aids for VLSI Circuits, pages 19-112. Sijthoff & Noordhoff, Alphen aan
den Rijn, The Netherlands; Rockville, MD, USA, 1981.
- [3789]
- S. S.
Sapatnekar and W. Chuang.
Power vs. delay in gate sizing: conflicting objectives?
In IEEE/ACM International Conference on Computer-Aided Design, pages
463-466, San Jose, CA, November 5-9 1995.
- [3790]
- S. Sapatnekar and
H. Su.
Analysis and optimization of power grids.
IEEE Design & Test of Computers, pages 7-15, May-June 2003.
- [3791]
- S. S. Sapatnekar.
A timing model incorporating the effect of crosstalk on delay and its
application to optimal channel routing.
IEEE Transactions on Computer-Aided Design, 19(5):550-559, May
2000.
- [3792]
- N. Saraf and
K. Bazargan.
Sequential logic to transform probabilities.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 732-738, San Jose, CA, November 18-21 2013.
- [3793]
- D. Saraswat,
R. Achar, and M. Nakhla.
Circuit simulation of s-parameter based interconnects via passive macromodels.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 309-312, Montreal, Quebec, June 20-23 2004.
- [3794]
- D. Saraswat,
R. Achar, and M. S. Nakhla.
Global passivity enforcement algorithm for macromodels of interconnect
subnetowrks characterized by tabulated data.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(7):819-832, July 2005.
- [3795]
- O. Sarbishei, M. Tabandeh, B. Alizadeh, and M. Fujita.
A formal approach for debugging arithmetic circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(5):742-754, May 2009.
- [3796]
- H. K. Sarin and A. J.
McNelly.
A power modeling and characterization method for logic simulation.
In IEEE Custom Integrated Circuits Conference, pages 363-366, Santa
Clara, CA, May 1-4 1995.
- [3797]
- A. Sarkar,
S. Lin, and K. Wang.
A methodology for analysis and verification of power gated circuits with
correlated results.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 351-354, Portland, Oregon, August 27-29 2007.
- [3798]
- S. Sarkar,
A. Biswas, A. S. Dhar, and R. M. Rao.
Adaptive bus encoding for transition reduction on off-chip buses with
dynamically varying switching characteristics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(11):3057-3066, November 2017.
- [3799]
- M. Sarrafzadeh, F. Dabiri, R. Jafari, T. Massey, and
A. Nahapetan.
Low power light-weight embedded systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 207-212, Tegernsee, Germany, October 4-6 2006.
- [3800]
- D. Sarta,
D. Trifone, and G. Ascia.
A data dependent approach to instruction level power estimation.
In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages
182-190, Como, Italy, March 4-5 1999.
- [3801]
- T. Sasao.
On the numbers of variables to represent sparse logic functions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 45-51, San Jose, CA, November 10-13 2008.
- [3802]
- T. Sassao and
M. Matsuura.
BDD representation for incompletely specified multiple-output logic functions
and its applications to functional decomposition.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
373-378, Anaheim, CA, June 13-17 2005.
- [3803]
- S. Sastry and J-I. Pi.
An investigation into statistical properties of partitioning and floorplanning
problems.
In 26th ACM/IEEE Design Automation Conference, pages 382-387, Las
Vegas, NV, June 25-29 1989.
- [3804]
- A. Sathanur, L. Benini, A. Macii, E. Macii, and M. Poncino.
Fast computation of discharge current upper bounds for clustered power gating.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(1):146-151, January 2011.
- [3805]
- A. Sathanur, L. Benini, A. Macii, E. Macii, and M. Poncino.
Row-based power-gating: a novel sleep transistor insertion methodology for
leakage power optimization in nanometer CMOS circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(3):469-482, March 2011.
- [3806]
- V. S. Sathe, M. C.
Papaefthymiou, and C. H. Ziesler.
A ghz-class charge recovery logic.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 91-94, San Diego, CA, August 8-10 2005.
- [3807]
- H. Sathyamurthy, S. S. Sapatnekar, and J. P. Fishburn.
Speeding up pipelined circuits through a combination of gate sizing and clock
skew optimization.
IEEE Transactions on Computer-Aided Design of Circuits and Systems,
17(2):173-182, February 1998.
- [3808]
- T. Sato, Y. Cao,
K. Agarwal, D. Sylvester, and C. Hu.
Bidirectional closed-form transformation between on-chip coupling noise
waveforms and interconnect delay-change curves.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(5):560-572, May 2003.
- [3809]
- J. H.
Satyanarayana and K. Parhi.
HEAT: Hierarchical energy analysis tool.
In 33rd Design Automation Conference, pages 9-14, Las Vegas, NV, June
3-7 1996.
- [3810]
- J. H.
Satyanarayana and K. K. Parhi.
Theoretical analysis of word-level switching activity in the presence of
glitching and correlation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(2):148-159, April 2000.
- [3811]
- S. Sauter,
D. Schmitt-Landsiedel, R. Thewes, and W. Weber.
Effect of parameter variations at chip and wafer level on clock skews.
IEEE Transactions on Semiconductor Manufacturing, 13(4):395-400,
November 2000.
- [3812]
- I. Savidis,
B. Vaisband, and E. G. Friedman.
Experimental analysis of thermal coupling in 3-D integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(10):2077-2089, October 2015.
- [3813]
- J. Savir, G. S.
Ditlow, and P. H. Bardell.
Random pattern testability.
IEEE Transactions on Computers, C-33(1):79-90, January 1984.
- [3814]
- J. Savir and W. H.
McAnney.
Random pattern testability of delay faults.
In IEEE International Test conference, pages 263-273, Sept. 8-11
1986.
- [3815]
- J. Savir and J. P. Roth.
Testing for, and distinguishing between failures.
In IEEE 12th International Symposium on Fault-Tolerant Computing,
pages 165-172, June 1982.
- [3816]
- P. Saxena and S. Gupta.
On integrating power and signal routing for shield count minimization in
congested regions.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(4):437-445, April 2003.
- [3817]
- B. Schaeffer.
Product transformation and heuristic EXOR-AND-OR logic synthesis of
incompletely specified functions.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(11):1831-1841, November 2017.
- [3818]
- B. C. Schafer and
T. Kim.
Hotspots elimination and temperature flattening in VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(11):1475-1487, November 2008.
- [3819]
- B. C. Schafer.
Probabilistic multiknob high-level synthesis design space exploration
acceleration.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(3):394-406, March 2016.
- [3820]
- M. Schaffner, F. K. Gurkaynak, A. Smolic, H. Kaeslin, and
L. Benini.
An aapproximate computing technique for reducing the complexity of a
direct-solver for sparse linear systems in real-time video processing.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [3821]
- L. Scheffer and
E. Nequist.
Why interconnect prediction doesn't work.
In International Workshop on System-Level Interconnect Prediction,
pages 139-144, San Diego, CA, April 8-9 2000.
- [3822]
- L. Scheffer.
The convergence of structured custom and ASIC designs.
In IEEE Custom Integrated Circuits Conference, pages 23-27, Santa
Clara, CA, May 1-4 1995.
- [3823]
- L. K. Scheffer.
CAD implications of new interconnect technologies.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
576-581, San Diego, CA, June 4-8 2007.
- [3824]
- L. K. Scheffer.
Design tools for artificial nervous systems.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
717-722, San Francisco, CA, June 3-7 2012.
- [3825]
- J. Scheible and
J. Lienig.
Automation of analog IC layout - challenges and solutions.
In ACM International Symposium on Physical Design 2015, pages 33-40,
Monterey, California, March 29 - April 1 2015.
- [3826]
- W. E. Schiesser.
Computational Mathematics in Engineering and Applied Science: ODEs, DAEs,
and PDEs.
Taylor & Francis, 1993.
- [3827]
- E. Schmidt,
G. von Colln, L. Kruse, F. Theeuwen, and W. Nebel.
Memory power models for multilevel power estimation and optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(2):106-109, April 2002.
- [3828]
- M. Schmidt,
H. Kinzelbach, and U. Schichtmann.
Variational waveform propagation for accurate statistical timing analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 20-25, Monterey, CA,
February 25-26 2008.
- [3829]
- P. H.
Schneider, U. Schlichtmann, and B. Wurth.
Fast power estimation of large circuits.
IEEE Design & Test of Computers, 13(1):70-78, Spring 1996.
- [3830]
- E. Schneider, S. Holst, X. Wen, and H.-J. Wunderlich.
Data-parallel simulation for fast and accurate timing validation of CMOS
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 17-23, San Jose, CA, November 2-6 2014.
- [3831]
- P. H.
Schneider and S. Krishnamoorthy.
Effects of correlations on accuracy of power analysis - an experimental study.
In International Symposium on Low Power Electronics and Design, pages
113-116, Monterey, CA, August 12-14 1996.
- [3832]
- P. H.
Schneider and U. Schlichtmann.
Decomposition of boolean functions for low power based on a new power
estimation technique.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
123-128, Napa, CA, April 24-27 1994.
- [3833]
- P. R. Schneider.
On the necessity to examine D-chains in diagnostic test generation - an
example.
IBM Journal of Research and Development, 11:114, January 1967.
- [3834]
- A. Schottl.
A reliability model of a system with dependent components.
IEEE Transactions on Reliability, 45(2):267-273, June 1996.
- [3835]
- M. J. Schulte,
A. A. Sinkar, H. RezaGhasemi, and N.-S. Kim.
Cost-effective power delivery to support per-core voltage domains for
power-constrained processors.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
56-61, San Francisco, CA, June 3-7 2012.
- [3836]
- S. C. Schwartz and
Y. S. Yeh.
On the distribution function and moments of power sums with log-normal moments.
The Bell System Technical Journal, 61(7):1441-1462, September
1982.
- [3837]
- D. Scott, S. Tang,
S. Zhao, and M. Nandakumar.
Device physics impact on low leakage, high speed DSP design techniques.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 349-354, San Jose, CA, March 18-21 2002.
- [3838]
- R. M.
Secareanu, S. Warner, S. Seabridge, C. Burke, J. Becerra, T. E. Watrobski,
C. Morton, W. Staub, T. Tellier, I. S. Kourtev, and E. G. Friedman.
Substrate coupling in digital circuits in mixed-signal smart-power systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(1):67-78, January 2004.
- [3839]
- C-J. Seger.
A bounded delay race model.
In IEEE International Conference on Computer-Aided Design, pages
130-133, 1989.
- [3840]
- F. F. Sellers,
Jr., M. Y. Hsiao, and L. W. Bearnson.
Analyzing errors with the boolean difference.
IEEE Transactions on Computers, C-17(7):676-683, July 1968.
- [3841]
- S. Sen.
Channel-adaptive zero-margin & process-adaptive self-healing communication
circuits/systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 80-85, San Jose, CA, November 2-6 2014.
- [3842]
- E. Seneta.
Non-Negative Matrices and Markov Chains.
Springer-Verlag, New York, NY, 1981.
- [3843]
- M. Sengupta,
S. Saxena, L. Daldoss, G. Kramer, S. Minehane, and J. Cheng.
Application specific worst case corners using response surfaces and statistical
models.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 351-356, San Jose, CA, March 22-24 2004.
- [3844]
- M. Sengupta,
S. Szxena, L. Daldoss, G. Kramer, S. Minehane, and J. Cheng.
Application-specific worst case corners using response surfaces and statistical
models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(9):1372-1380, September 2005.
- [3845]
- D. Sengupta and
R. Saleh.
Generalized power-delay metrics in deep submicron CMOS designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):183-189, January 2007.
- [3846]
- D. Sengupta and
R. Saleh.
Application-driven floorplan-aware voltage island design.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
155-160, Anaheim, CA, June 8-13 2008.
- [3847]
- D. Sengupta and
R. A. Saleh.
Application-driven voltage-island partitioning for low-power system-on-chip
design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(3):316-326, March 2009.
- [3848]
- D. Sengupta and
S. S. Sapatnekar.
Rescale: recalibrating sensor circuits for aging and lifetime estimation under
BTI.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 492-497, San Jose, CA, November 2-6 2014.
- [3849]
- R. Senthinathan, G. Tubbs, and M. Schuelein.
Negative feedback influence on simultaneously switching CMOS outputs.
In IEEE 1988 Custom Integrated Circuits Conference, pages
5.4.1-5.4.5, Rochester, NY, May 16-19 1988.
- [3850]
- J.-S. Seo,
D. Sylvester, D. Blaauw, H. Kaul, and R. Krishnamurthy.
A robust edge encoding technique for energy-efficient multi-cycle interconnect.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 68-73, Portland, Oregon, August 27-29 2007.
- [3851]
- Y.-H. Seo and D.-W. Kim.
A new VLSI architecture of parallel multiplier - accumulator based on radix-2
modified booth algorithm.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):201-208, February 2010.
- [3852]
- M. Seok, S. Hanson,
D. Sylvester, and D. Blaauw.
Analysis and optimization of sleep modes in subthreshold circuit design.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
694-699, San Diego, CA, June 4-8 2007.
- [3853]
- M. Seok.
Decoupling capacitor design strategy for minimizing supply noise of ultra low
voltage circuits.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
968-973, San Francisco, CA, June 3-7 2012.
- [3854]
- J. Seomun,
J. Kim, and Y. Shin.
Skewed flip-flop transformation for minimizing leakage in sequential circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
103-106, San Diego, CA, June 4-8 2007.
- [3855]
- J. Seomun, J.-H.
Kim, and Y. Shin.
Skewed flip-flop and mixed vt gates for minimizing leakage in sequential
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(11):1956-1968, November 2008.
- [3856]
- J. Seomun,
I. Shin, and Y. Shin.
Synthesis and implementation of active mode power gating circuits.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
487-492, Anaheim, CA, June 13-18 2010.
- [3857]
- G. Servel and
D. Deschacht.
On-chip crosstalk evaluation between adjacent interconnections.
In 7th IEEE International Conference on Electronics, Circuits and
Systems, pages 827-830, Beirut, Lebanon, December 17-19 2000.
- [3858]
- S. A. Seshia and
A. Rakhlin.
Game-theoretic timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 575-582, San Jose, CA, November 10-13 2008.
- [3859]
- S. C. Seth, L. Pan,
and V. D. Agrawal.
Predict - probabilistic estimation of digital circuit testability.
In IEEE 15th International Symposium on Fault-Tolerant Computing,
pages 220-225, Ann Arbor, MI, June 19-21 1985.
- [3860]
- S. C. Seth and V. D.
Agrawal.
Cutting chip-testing costs.
IEEE Spectrum, pages 38-45, April 1985.
- [3861]
- M. Severson,
K. Yuen, and Y. Du.
Not so fast my friend: Is near-threshold computing the answer for power
reduction of wireless devices?
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1160-1162, San Francisco, CA, June 3-7 2012.
- [3862]
- K. Sewell,
T. Mudge, D. Blaauw, D. Sylvester, N. Pinckney, R. Dreslinski, and D. Fick.
Assessing the performance limits of parallelized near-threshold computing.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1143-1148, San Francisco, CA, June 3-7 2012.
- [3863]
- A. Shacham,
K. Bergman, and L. P. Carloni.
The case for low-power photonic networks on chip.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
132-135, San Diego, CA, June 4-8 2007.
- [3864]
- O. Shacham,
M. Wachs, A. Danowitz, S. Galal, J. Brunhaver, W. Qadeer,
S. Sankaranarayanan, A. Vassilliev, S. Richardson, and M. Horowitz.
Avoiding game over: bringing design to the next level.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
623-629, San Francisco, CA, June 3-7 2012.
- [3865]
- M. Shafique,
S. Garg, J. Henkel, and D. Marculescu.
The EDA challenges in the dark silicon era.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [3866]
- M. Shafique and
J. Henkel.
Mitigating the power density and temperature problems in the nano-era.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 176-177, Austin, TX, November 2-6 2015.
- [3867]
- S. Shah,
A. Srivastava, D. Sharma, D. Sylvester, D. Blaauw, and V. Zolotov.
Discrete vt assignment and gate sizing using a self-snapping continuous
formulation.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 705-712, San Jose, CA, November 6-10 2005.
- [3868]
- S. Shah, P. Gupta,
and A. Kahng.
Standard cell library optimization for leakage reduction.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
983-986, San Francisco, CA, July 24-28 2006.
- [3869]
- K. Shahookar
and P. Mazumder.
A genetic approach to standard cell placement using meta-genetic parameter
optimization.
IEEE Transactions on Computer-Aided Design, 9(5):500-512, May
1990.
- [3870]
- M. Shahriari and
F. Najm.
A gate-level timing model for SOI circuits.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 795-798, St. Julian, Malta, September 2-5 2001.
- [3871]
- N. Shanbhag,
K. Soumyanath, and S. Martin.
Reliable low-power design in the presence of deep submicron noise.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 295-302, Italy, July 26-27 2000.
- [3872]
- N. R.
Shanbhag, R. A. Abdallah, R. Kumar, and D. L. Jones.
Stochastic computation.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
859-864, Anaheim, CA, June 13-18 2010.
- [3873]
- N. R. Shanbhag.
Lower bounds on power-dissipation for DSP algorithms.
In International Symposium on Low Power Electronics and Design, pages
43-48, Monterey, CA, August 12-14 1996.
- [3874]
- N. Shanbhag.
Reliable and energy-efficient digital signal processing.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
830-835, New Orleans, LA, June 10-14 2002.
- [3875]
- N. R. Shanbhag.
A communication-theoretic design paradigm for reliable socs.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 76-76,
San Diego, CA, June 7-11 2004.
- [3876]
- L. Shang, L.-S.
Peh, and N. K. Jha.
Powerherd: a distributed scheme for dynamically satisfying peak-power
constraints in interconnection networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):92-110, January 2006.
- [3877]
- D. Shang,
A. Yakovlev, A. Koelmans, D. Sokolov, and A. Bystrov.
Registers for phase difference based logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(6):720-724, June 2007.
- [3878]
- L. Shannon and P. Chow.
SIMPPL: an adaptable soc framework using a programmable controller IP
interface to facilitate design reuse.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(4):377-390, April 2007.
- [3879]
- C. E. Shannon.
A symbolic analysis of relay and switching circuits.
AIEE Transactions, 57:713-723, 1938.
- [3880]
- M. Shao, D. F. Wong,
Y. Gao, L.-P. Yuan, and H. Cao.
Shaping interconnect for uniform current density.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 254-259, San Jose, CA, November 10-14 2002.
- [3881]
- M. J. Sharifi and
D. Baharepour.
A multiloop and full amplitude hysteresis model for molecular electronics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(2):187-196, February 2016.
- [3882]
- M. Sharifkhani and M. Sachdev.
A low power SRAM architecture based on segmented virtual grounding.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 256-261, Tegernsee, Germany, October 4-6 2006.
- [3883]
- M. Sharifkhani and M. Sachdev.
Segmented virtual ground architecture for low-power embedded SRAM.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(2):196-205, February 2007.
- [3884]
- S. Sharifsadeh, J. R. Koehler, A. B. Owen, and J. D. Shott.
Using simulators to model transmitted variability in IC manufacturing.
IEEE Transactions on Semiconductor Manufacturing, 2(3):82-93, August
1989.
- [3885]
- J. Sharkey,
A. Buyuktosunoglu, and P. Bose.
Evaluating design tradeoffs in on-chip power management for cmps.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 44-49, Portland, Oregon, August 27-29 2007.
- [3886]
- M. Shatzkes and
J. R. Lloyd.
A model for conductor failure considering diffusion concurrently with
electromigration resulting in a current exponent of 2.
Journal of Applied Physics, 59(11):3890-3893, June 1986.
- [3887]
- A. Shayan,
X. Hu, H. Peng, M. Popovich, W. Zhang, C.-K. Cheng, Lew C.-E., and X. Chen.
3d power distribution network co-design for nanoscale stacked silicon ics.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 11-14, San Jose, CA, October 27-29 2008.
- [3888]
- A. Shebaita,
C. Amin, F. Dartu, and Y. I. Ismail.
Expanding the frequency range of AWE via time shifting.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 935-938, San Jose, CA, November 6-10 2005.
- [3889]
- A. Shebaita,
D. Petranovic, and Y. I. Ismail.
Importance of volume discretization of single and coupled interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 119-126, San Jose, CA, November 5-9 2006.
- [3890]
- A. Shebaita,
D. Petranovic, and Y. I. Ismail.
Including inductance in static timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 686-691, San Jose, CA, November 5-8 2007.
- [3891]
- A. Shebaita,
D. Das, D. Petranovic, and Y. Ismail.
A noval moment based framework for accurate and efficient static timing
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(8):1258-1262, August 2011.
- [3892]
- B. N. Sheehan.
ENOR: Model order reduction of RLC circuits using nodal equations for
efficient factorization.
In Design Automation Conference, pages 17-21, New Orleans, LA, June
21-25 1999.
- [3893]
- B. N. Sheehan.
TICER: Realizable reduction of extracted RC circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
200-203, San Jose, CA, November 7-11 1999.
- [3894]
- B. N. Sheehan.
Osculating thevenin model for predicting delay and slew of capacitively
characterized cells.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
866-869, New Orleans, LA, June 10-14 2002.
- [3895]
- B. N. Sheehan.
Branch merge reduction of RLCM networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 658-664, San Jose, CA, November 9-13 2003.
- [3896]
- B. Sheehan.
Realizable reduction of RC networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(8):1393-1407, August 2007.
- [3897]
- A. T. Sheikh,
A. H. El-Maleh, M. E. S. Elrabaa, and S. M. Salt.
A fault tolerance technique for combinational circuits based on
selective-transistor redundancy.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(1):224-237, January 2017.
- [3898]
- R. S. Shelar,
S. S. Sapatnekar, P. Saxena, and X. Wang.
A predictive distributed congestion metric with application to technology
mapping.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(5):696-710, May 2005.
- [3899]
- R. S. Shelar and
M. Patyra.
Impact of local interconnects on timing and power in a high performace
microprocessor.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1623-1627, October 2013.
- [3900]
- J. H. Shelly and D. R.
Tryon.
Statistical techniques of timing verification.
In IEEE 20th Design Automation Conference, pages 396-402, 1983.
- [3901]
- J. P. Shen, W. Maly,
and F. J. Ferguson.
Inductive fault analysis of MOS integrated circuits.
Design and Test of Computers, pages 13-26, December 1985.
- [3902]
- A. Shen, A. Ghosh,
S. Devadas, and K. Keutzer.
On average power dissipation and random pattern testability of CMOS
combinational logic networks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
402-407, Santa Clara, CA, November 8-12 1992.
- [3903]
- A. Shen, S. Devadas,
and A. Ghosh.
Probabilistic manipulation of boolean functions using free boolean diagrams.
IEEE Transactions on Computer-Aided Design, 14(1):86-95, January
1995.
- [3904]
- R. Shen, S. X.-D.
Tan, J. Cui, W. Yu, Y. Cai, and G.-S. Chen.
Variational capacitance extraction and modeling based on orthogonal polynomial
method.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(11):1556-1566, November 2010.
- [3905]
- R. Shen, S. X.-D.
Tan, and J. Xiong.
A linear algorithm for full-chip statistical leakage power analysis considering
weak spatial correlation.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
481-486, Anaheim, CA, June 13-18 2010.
- [3906]
- W. Shen, Y. Cai,
X. Hong, and J. Hu.
An effective gated clock tree design based on activity and register aware
placement.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(12):1639-1648, December 2010.
- [3907]
- C. Shen, H. Choi,
S. Chakraborty, and M. Srivastava.
Towards a rich sensing stack for iot devices.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 424-427, San Jose, CA, November 2-6 2014.
- [3908]
- N. V. Shenoy and
W. Nicholls.
An efficient routing database.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
590-595, New Orleans, LA, June 10-14 2002.
- [3909]
- K. L. Shepard,
V. Narayanan, P. C. Elmendorf, and G. Zheng.
Global harmony: coupled noise analysis for full-chip RC interconnect
networks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
139-146, San Jose, CA, November 9-13 1997.
- [3910]
- K. L.
Shepard, V. Narayanan, and R. Rose.
Harmony: Static noise analysis of deep submicron digital integrated circuits.
IEEE Transactions on Computer-Aided Design, 18(8):1132-1150, August
1999.
- [3911]
- K. L. Shepard,
I. Meric, and P. Kim.
Characterization and modeling of graphene field-effect devices.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 406-411, San Jose, CA, November 10-13 2008.
- [3912]
- K. L. Shepard and D.-J.
Kim.
Body-voltage estimation in digital PD-SOI circuits and its application to
static timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
531-538, San Jose, CA, November 7-11 1999.
- [3913]
- K. L. Shepard and D.-J.
Kim.
Static noise analysis for digital integrated circuits in partially-depleted
silicon-on-insulator technology.
In Design Automation Conference, pages 239-242, Los Angeles, CA, June
5-9 2000.
- [3914]
- K. L. Shepard and D.-J.
Kim.
Body-voltage estimation in digital PD-SOI circuits and its application to
static timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(7):888-901, July 2001.
- [3915]
- K. L. Shepard and
D. N. Maynard.
Variability and yield improvement: rules, models and characterization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 834-835, San Jose, CA, November 5-9 2006.
- [3916]
- K. L. Shepard and
V. Narayanan.
Noise in deep submicron digital design.
In IEEE/ACM International Conference on Computer-Aided Design, pages
524-531, San Jose, CA, November 10-14 1996.
- [3917]
- K. L. Shepard.
Design methodologies for noise in digital integrated circuits.
In IEEE/ACM 35th Design Automation Conference, pages 94-99, San
Francisco, CA, June 15-19 1998.
- [3918]
- K. L. Shepard.
CAD issues for CMOS VLSI design in SOI.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 105-110, San Jose, CA, March 26-28 2001.
- [3919]
- K. Sheth,
E. Sarto, and J. McGrath.
The importance of adopting a package-aware chip design flow.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
853-856, San Francisco, CA, July 24-28 2006.
- [3920]
- G. Shi, B. Hu, and
C.-J. R. Shi.
On symbolic model order reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1257-1272, July 2006.
- [3921]
- J. Shi, S. X.-D. Tan,
and J. Fan.
Pattern-based iterative method for extreme large power/ground analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):680-692, April 2007.
- [3922]
- Y. Shi, J. Xiong,
C. Liu, and L. He.
Efficient decoupling capacitance budgeting considering operation and process
variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 803-810, San Jose, CA, November 5-8 2007.
- [3923]
- Y. Shi, J. Xiong,
C. Liu, and L. He.
Efficient decoupling capacitance budgeting considering operation and process
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(7):1253-1263, July 2008.
- [3924]
- J. Shi, Y. Cai,
W. Hou, L. Ma, S. X.-D. Tan, P.-H. Ho, and X. Wang.
GPU friendly fast poisson solver for structured power grid network analysis.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
178-183, San Francisco, CA, July 26-31 2009.
- [3925]
- B. Shi, Y. Zhang, and
A. Srivastava.
Dynamic thermal management under soft thermal constraints.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(11):2045-2054, November 2013.
- [3926]
- W. Shi, M. B.
Alawieh, X. Li, H. Yu, N. Arechiga, and N. Tomatsu.
Efficient statistical validation of machine learning systems for autonomous
driving.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 1-8, Austin, TX, November 7-10 2016.
- [3927]
- C. Shi and R. W.
Brodersen.
Automated fixed-point data-type optimization tool for signal processing and
communication systems.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
478-483, San Diego, CA, June 7-11 2004.
- [3928]
- Y. Shi and L. He.
Modeling and design for beyond-the-die power integrity.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 411-416, San Jose, CA, November 7-11 2010.
- [3929]
- K. Shi and D. Howard.
Challenges in sleep transistor design and implementation in low-power designs.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
113-116, San Francisco, CA, July 24-28 2006.
- [3930]
- X. Shi and N. Nicolici.
On-chip generation of uniformly distributed constrained-random stimuli for
post-silicon validation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 808-815, Austin, TX, November 2-6 2015.
- [3931]
- X. Shi and N. Nicolici.
On-chip cube-based constrained-random stimuli generation for post-silicon
validation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(7):1012-1025, July 2016.
- [3932]
- G. Shi and C.-J. R. Shi.
Model order reduction by dominant subspace projection: Error bound, subspace
computation, and circuit applications.
IEEE Transactions on Circuits and Systems I: Regular Papers,
52(5):975-993, May 2005.
- [3933]
- C. Shi and K. Zhang.
A robust approach for timing verification.
In IEEE International Conference on Computer-Aided Design, pages
56-59, Nov. 9-12 1987.
- [3934]
- C. Shi and K. Zhang.
Tree relaxation : a new iterative solution method for linear equations.
In IEEE International Conference on Circuits and Systems, pages
2355-2358, 1988.
- [3935]
- G. Shi.
A simple implementation of determinant decision diagram.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 70-76, San Jose, CA, November 7-11 2010.
- [3936]
- G. Shi.
Graph-pair decision diagram construction for topological symbolic circuit
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(2):275-288, February 2013.
- [3937]
- M-C. Shiau and C-Y. Wu.
The signal delay in interconnection lines considering the effect of
small-geometry CMOS inverters.
IEEE Transactions on Circuits and Systems, 37(3):420-425, March
1990.
- [3938]
- H.-C. Shih, P.-W.
Luo, J.-C. Yeh, S.-Y. Lin, D.-M. Kwai, S.-L. Lu, A. Schaefer, and C.-W. Wu.
Dart: a component-based DRAM area, power, and timing modeling tool.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(9):1356-1369, September 2014.
- [3939]
- H-C. Shih and J. A.
Abraham.
Transistor-level test generation for physical failures in CMOS circuits.
In IEEE 23rd Design Automation Conference, pages 243-249, 1986.
- [3940]
- B. Shim, S. R.
Sridhara, and N. R. Shanbhag.
Reliable low-power digital signal processing via reduced precision redundancy.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):497-510, May 2004.
- [3941]
- B. Shim and N. R.
Shanblag.
Energy-efficient soft error-tolerant digital signal processing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(4):336-348, April 2006.
- [3942]
- H. Shimada,
H. Ando, and T. Shimada.
Pipeline stage unification: a low-energy consumption, technique for future
mobile processors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 326-329, Seoul, Korea, August 25-27 2003.
- [3943]
- K. Shimazaki, S. Hirano, and H. Tsujikawa.
An EMI-noise analysis on LSI design with impedance estimation.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 169-174, San Jose, CA, March 18-21 2002.
- [3944]
- Y. Shimda and
K. Sakurai.
A new accurate yield prediction method for system-LSI embedded memories.
IEEE Transactions on Semiconductor Manufacturing, 16(3):436-445,
August 2003.
- [3945]
- T. Shimokawa and
M. Liao.
Goodness-of-fit tests for type-I extreme-value and 2-parameter weibull
distributions.
IEEE Transactions on Reliability, 48(1):79-86, March 1999.
- [3946]
- Y. Shin, S-I Chae,
and K. Choi.
Partial bus-invert coding for power optimization of system level bus.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 127-129, Monterey, CA, August 10-12 1998.
- [3947]
- Y. Shin, S.-I.
Chae, and K. Choi.
Partial bus-invert coding for power optimization of application-specific
systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(2):377-383, April 2001.
- [3948]
- Y. Shin, K. Choi,
and Y.-H. Chang.
Narrow bus encoding for low-power DSP systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(5):656-660, October 2001.
- [3949]
- Y. Shin, S. Paik,
and H.-O. Kim.
Semicustom design of zigzag power-gated circuits in standard cell elements.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(3):327-339, March 2009.
- [3950]
- S. Shin, K. Kim, and
S.-M. Kang.
Compact models for memristors based on charge-flux constitutive relationships.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):590-598, April 2010.
- [3951]
- S. Shin, K. Kim, and
S.-M. Kang.
Resistive computing: memristors-enabled signal multiplication.
IEEE Transactions on Circuits and Systems, 60(5):1241-1249, May
2013.
- [3952]
- I. Shin, J.-J. Kim,
Y.-S. Lin, and Y. Shin.
One-cycle correction of timing errors in pipelines with standard clocked
elements.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(2):600-612, February 2016.
- [3953]
- D. Shin and K. Choi.
Low power high level synthesis by increasing data correlation.
In 1997 International Symposium on Low Power Electronics and Design,
pages 62-67, Monterey, CA, August 18-20 1997.
- [3954]
- Y. Shin and T. Sakurai.
Coupling-driven bus design for low-power application specific systems.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
750-753, Las Vegas, NV, June 18-22 2001.
- [3955]
- Y. Shin and T. Sakurai.
Estimation of power distribution in VLSI interconnects.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 370-375, Huntington Beach, California, August 6-7
2001.
- [3956]
- Y. Shin and T. Sakurai.
Power distribution analysis of VLSI interconnects using model order
reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(6):739-745, June 2002.
- [3957]
- K. Shinkai,
M. Hashimoto, A. Kurokawa, and T. Onoye.
A gate delay model focusing on current fluctuation over wide-range of process
and environmental variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 47-53, San Jose, CA, November 5-9 2006.
- [3958]
- C. G. Shirley.
A defect model of reliability.
In International Reliability Physics Symposium, pages 3.1-3.56, Las
Vegas, NV, April 1995.
- [3959]
- P. P.
Shirvani, N. Saxena, and E. J. McCluskey.
Common-mode failures in redundant VLSI systems: A survey.
IEEE Transactions on Reliability, 49(3):377-387, September 2000.
- [3960]
- W.-T. Shiue and
C. Chakrabarti.
Memory exploration for low power, embedded systems.
In Design Automation Conference, pages 140-145, New Orleans, LA, June
21-25 1999.
- [3961]
- H. Shojaei and
A. Davoodi.
Trace signal selection to enhance timing and logic visibility in post-silicon
validation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 168-172, San Jose, CA, November 7-11 2010.
- [3962]
- M. Shoji.
CMOS Digital Circuit Technology.
Prentice-Hall, Englewood Cliffs, NJ, 1987.
- [3963]
- G. Shomalnasab
and L. Zhang.
New analytic model of coupling and substrate capacitance in nanometer
technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(7):1268-1280, July 2015.
- [3964]
- M. Shoniker,
O. Oleynikov, B. Cockburn, J. Han, M. Rana, and W. Pedrycz.
Automatic selection of process corner simulations for faster design
verification.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 37(6):1312-1316, June 2018.
- [3965]
- IU. A. Shreider and
N. P. Buslenko et al.
The Monte Carlo Method.
Pergamon Press, New York, NY, 1966.
- [3966]
- A. Shrestha,
K. Ahmed, Y. Wang, D. P. Widemann, A. T. Moody, B. C. Van Essen, and Q. Qiu.
A spike-based long short-term memory on a neurosynaptic processor.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 631-637, Irvine CA, November 13-16 2017.
- [3967]
- Y.-T. Shyu, J.-M.
Lin, C.-P. Huang, C.-W. Lin, Y.-Z. Lin, and S.-J. Chang.
Effective and efficient approach for power reduction by using multi-bit
flip-flops.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(4):624-635, April 2013.
- [3968]
- Y.-T. Shyu, J.-M.
Lin, C.-C. Lin, C.-P. Huang, and S.-I. Chang.
An efficient and effective methodology to control turn-on sequence of power
switches for power-gating designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(10):1730-1743, October 2016.
- [3969]
- J. Siebert,
J. Collier, and R. Amirtharajah.
Self-timed circuits for energy harvesting AC power supplies.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 315-318, San Diego, CA, August 8-10 2005.
- [3970]
- B. K. Sikdar,
N. Ganguly, and P. P. Chaudhuri.
Generation of test patterns without prohibited pattern set.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(12):1650-1660, December 2004.
- [3971]
- L. G. De Silva,
J. R. Philips, and L. M. Silveira.
Efficient computation of the exact worst-delay corner.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 7-12, Austin, Texas,
February 26-27 2007.
- [3972]
- J. M. S. Silva,
J. R. Phillips, and L. M. Silveira.
Efficient simulation of power grids.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(10):1523-1532, October 2010.
- [3973]
- J. P. M. Silva and
K. Sakallah.
GRASP - A new search algorithm for satisfiability.
In IEEE/ACM International Conference on Computer-Aided Design, pages
220-227, San Jose, CA, November 10-14 1996.
- [3974]
- L. M.
Silveira, J. K. White, H. Neto, and L. Vidigal.
On exponential fitting for circuit simulation.
IEEE Transactions on Computer-Aided Design, 11(5):566-574, May
1992.
- [3975]
- L. M.
Silveira, M. Kamon, and J. White.
Efficient reduced-order modeling of frequency-dependent coupling inductances
associated with 3-D interconnect structures.
In 32nd ACM/IEEE Design Automation Conference, pages 376-380, June
1995.
- [3976]
- L. M.
Silveira, M. Kamon, I. Elfadel, and J. White.
A coordinate-transformed arnoldi algorithm for generating guaranteed stable
reduced-order models of RLC circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
288-294, San Jose, CA, November 10-14 1996.
- [3977]
- L. M. Silveira
and J. R. Phillips.
Exploiting input information in a model reduction algorithm for massively
coupled parasitic networks.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
385-388, San Diego, CA, June 7-11 2004.
- [3978]
- P. Silver, J. C.
Anderson, and R. Murray.
Joint DAC/IWBDA special session engineering biology: fundamentals and
applications.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
220-221, Anaheim, CA, June 13-18 2010.
- [3979]
- H. Sim,
S. Kenzhegulov, and J. Lee.
DPS: dynamic precision scaling for stochastic computing-based deep neural
networks.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [3980]
- V. Simoncini.
Computational methods for linear matrix equations.
SIAM Review, 58(3):377-441, September 2016.
- [3981]
- H. Simonis,
N. Nguyen, and M. Dincbas.
Verification of digital circuits using CHIP.
In G. J. Milne, editor, The Fusion of Hardware Design and
Verification, pages 421-442. Elsevier Science Publishers B.V.
(North-Holland), 1988.
- [3982]
- T. Simunic,
L. Benini, and G. De Micheli.
Cycle-accurate simulation of energy consumption in embedded systems.
In Design Automation Conference, pages 867-873, New Orleans, LA, June
21-25 1999.
- [3983]
- T. Simunic,
S. P. Boyd, and P. Glynn.
Managing power consumption in netowrks on chips.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(1):96-107, January 2004.
- [3984]
- E. Singerman, Y. Abarbanel, and S. Baartmans.
Transaction based pre-to-post silicon validation.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
564-568, San Diego, CA, June 5-9 2011.
- [3985]
- D. Singh, J. M.
Rabaey, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, and T. J. Mozdzen.
Power conscious CAD tools and methodologies: A perspective.
In Proceedings of the IEEE, pages 570-593, April 1995.
- [3986]
- A. Singh,
J. Tharian, and J. Plusquellic.
Path delay estimation using power supply transient signals: a comparative study
using fourier and wavelet analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 748-753, San Jose, CA, November 9-13 2003.
- [3987]
- A. K. Singh,
M. Mani, and M. Orshansky.
Statistical technology mapping for parametric yield.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 511-518, San Jose, CA, November 6-10 2005.
- [3988]
- D. P. Singh,
V. Manohararajah, and S. D. Brown.
Incremental retiming for FPGA physical synthesis.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
433-438, Anaheim, CA, June 13-17 2005.
- [3989]
- J. Singh,
V. Nookala, Z.-Q. Luo, and S. Sapatnekar.
Robust gate sizing by geometric programming.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
315-320, Anaheim, CA, June 13-17 2005.
- [3990]
- H. Singh,
K. Agarwal, D. Sylvester, and K. J. Nowka.
Enhanced leakage reduction techniques using intermediate strength power gating.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(11):1215-1224, November 2007.
- [3991]
- J. Singh, Z.-Q.
Luo, and S. S. Sapatnekar.
A geometric programming-based worst case gate sizing method incorporating
spatial correlation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):295-308, February 2008.
- [3992]
- A. K. Singh,
M. Lok, K. Ragab, C. Caramanis, and M. Orshansky.
An algorithm for exploiting modeling error statistics to enable robust analog
optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 62-69, San Jose, CA, November 7-11 2010.
- [3993]
- A. K. Singh,
K. Ragab, M. Lok, C. Caramanis, and M. Orshansky.
Predictable equation-based analog optimization based on eplicit capture of
modeling error statistics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(10):1485-1498, October 2012.
- [3994]
- R. Singh and N. Bhat.
An offset compensation techniques for latch type sense amplifiers in high-speed
low-power srams.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(6):652-657, June 2004.
- [3995]
- A. Singh and P. Li.
On behavioral model equivalence checking for large analog/mixed signal systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 55-61, San Jose, CA, November 7-11 2010.
- [3996]
- M. Singh and S. M.
Nowick.
Synthesis for logical initializability of synchronous finite-state machines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(5):542-557, October 2000.
- [3997]
- J. Singh and S. S.
Sapatnekar.
Congestion-aware topology optimization of structured power/ground networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(5):683-695, May 2005.
- [3998]
- J. Singh and
S. Sapatnekar.
Statistical timing analysis with correlated non-gaussian parameters using
independent component analysis.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
155-160, San Francisco, CA, July 24-28 2006.
- [3999]
- J. Singh and S. S.
Sapatnekar.
Partition-based algorithm for power grid design using locality.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(4):664-677, April 2006.
- [4000]
- J. Singh and S. S.
Sapatnekar.
A scalable statistical static timing analyzer incorporating correlated
non-gaussian and gaussian parameter variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(1):160-173, January 2008.
- [4001]
- K. J. Singh and
P. A. Subrahmanyam.
Extracting RTL models from transistor netlists.
In IEEE/ACM International Conference on Computer-Aided Design, pages
11-17, San Jose, CA, November 5-9 1995.
- [4002]
- V. Singh.
Lithography at 14nm and beyond: choices and challenges.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), page 459,
San Diego, CA, June 5-9 2011.
- [4003]
- V. Singhal,
C. Pixley, A. Aziz, and R. K. Brayton.
Theory of safe replacements for sequential circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(2):249-265, February 2001.
- [4004]
- R. Singhal,
G. Choi, and R. Mahapatra.
Information theoretic approach to address delay and reliability in long on-chip
interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 310-314, San Jose, CA, November 5-9 2006.
- [4005]
- R. Singhal,
G. Choi, and R. N. Mahapatra.
Data handling limits of on-chip interconnects.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(6):707-713, June 2008.
- [4006]
- K. Singhal and
V. Visvanathan.
Statistical device models for worst case files and electrical test data.
IEEE Transactions on Semiconductor Manufacturing, 12(4):470-484,
November 1999.
- [4007]
- A. Singhee,
C.-F. Fang, J.-D. Ma, and R. A. Rutenbar.
Probabilistic interval-valued computation: toward a practical surrogate for
statistics inside CAD tools.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
167-172, San Francisco, CA, July 24-28 2006.
- [4008]
- A. Singhee,
C.-F. Fang, J.-D. Ma, and R. A. Rutenbar.
Probabilistic interval-valued computation: toward a practical surrogate for
statistics inside CAD tools.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(12):2317-2330, December 2008.
- [4009]
- A. Singhee,
S. Singhal, and R. A. Rutenbar.
Practical, fast monte carlo statistical static timing analysis: why and how.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 190-195, San Jose, CA, November 10-13 2008.
- [4010]
- A. Singhee and
P. Castalino.
Pareto sampling: choosing the right weights by derivative pursuit.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
913-916, Anaheim, CA, June 13-18 2010.
- [4011]
- A. Singhee and
R. A. Rutenbar.
Beyond low-order statistical response surfaces: latent variable regression for
efficient, highly nonlinear fitting.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
256-261, San Diego, CA, June 4-8 2007.
- [4012]
- A. Singhee and
R. A. Rutenbar.
From finance to flip-flops: a study of fast quasi-monte carlo methods from
computational finance applied to statistical circuit analysis.
In IEEE International Symposium on Quality Electronic Design (ISQED),
San Jose, CA, March 26-28 2007.
- [4013]
- A. Singhee and
R. A. Rutenbar.
Why quasi-monte carlo is better than monte carlo or latin hypercube sampling
for statistical circuit analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1763-1776, November 2010.
- [4014]
- A. Sinha, A. Wang,
and A. P. Chandrakasan.
Algorithmic transforms for efficient energy scalable computation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 31-36, Italy, July 26-27 2000.
- [4015]
- S. Sinha,
A. Mishchenko, and R. K. Brayton.
Topologically constrained logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 679-686, San Jose, CA, November 10-14 2002.
- [4016]
- A. Sinha,
N. Ickes, and A. P. Chandrakasan.
Instruction level and operating system profiling for energy exposed software.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(6):1044-1057, December 2003.
- [4017]
- D. Sinha, N. V.
Shenoy, and H. Zhou.
Statistical gate sizing for timing yield optimization.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 1037-1041, San Jose, CA, November 6-10 2005.
- [4018]
- D. Sinha,
D. Khalil, Y. I. Ismail, and H. Zhou.
A timing dependent power estimation framework considering coupling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 401-407, San Jose, CA, November 5-9 2006.
- [4019]
- D. Sinha, N. V.
Shenoy, and H. Zhou.
Statistical timing yield optimization by gate sizing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(10):1140-1146, October 2006.
- [4020]
- D. Sinha, H. Zhou,
and N. V. Shenoy.
Advances in computation of the maximum of a set of gaussian random variables.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(8):1522-1533, August 2007.
- [4021]
- D. Sinha,
A. Rubin, C. Visweswariah, F. Borkam, G. Schaeffer, and S. Abbaspour.
Feasible aggressor-set identification under constraints for maximum coupling
noise.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(7):1096-1100, July 2009.
- [4022]
- D. Sinha,
C. Visweswariah, N. Venkateswaran, J. Xiong, and V. Zolotov.
Reversible statistical max/min operation: concept and applications to timing.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1067-1073, San Francisco, CA, June 3-7 2012.
- [4023]
- D. Sinha,
V. Zolotov, J. Hu, S. K. Raghunathan, A. Bhanji, and C. M. Casey.
Generation and use of statistical timing macro-models considering slew and load
variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [4024]
- D. Sinha,
V. Zolotov, S. K. Raghunathan, M. H. Wood, and K. Kalafala.
Practical statistical static timing analysis with current source models.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [4025]
- A. Sinha and A. P.
Chandrakasan.
Jouletrack - A web based tool for software energy profiling.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
220-225, Las Vegas, NV, June 18-22 2001.
- [4026]
- D. Sinha and H. Zhou.
Gate sizimg for crosstalk reduction under timing constraints by lagrangian
relaxation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 14-19, San Jose, CA, November 7-11 2004.
- [4027]
- D. Sinha and H. Zhou.
A unified framework for statistical timing analysis with coupling and multiple
input switching.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 837-843, San Jose, CA, November 6-10 2005.
- [4028]
- D. Sinha and H. Zhou.
Statistical timing analysis with coupling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2965-2975, December 2006.
- [4029]
- A. Sinkar,
T. Park, and N.-S. Kim.
Clamping virtual supply voltage of power-gated circuits for active leakage
reduction and gate-oxide reliability improvement.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(3):580-588, March 2013.
- [4030]
- S. Sirichotiyakul, T. Edwards, C. Oh, J. Zuo, A. Dharchoudhury,
R. Panda, and D. Blaauw.
Stand-by power minimization through simultaneous threshold voltage selection
and circuit sizing.
In Design Automation Conference, pages 436-441, New Orleans, LA, June
21-25 1999.
- [4031]
- S. Sirichotiyakul, D. Blaauw, C. Oh, R. Levy, V. Zolotov, and
J. Zuo.
Driver modeling and alignment for worst-case delay noise.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
720-725, Las Vegas, NV, June 18-22 2001.
- [4032]
- S. Sirichotiyakul, T. Edwards, C. Oh, R. Panda, and D. Blaauw.
Duet: An accurate leakage estimation and optimization tool for dual-vt
circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(2):79-90, April 2002.
- [4033]
- D. Sitaram,
Y. Zheng, and K. L. Shepard.
Full-chip, three-dimensional, shapes-based RLC extraction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):711-727, May 2004.
- [4034]
- M. Sivaraman
and A. J. Strojwas.
Timing analysis based on primitive path delay fault identification.
In IEEE/ACM International Conference on Computer-Aided Design, pages
182-189, San Jose, CA, November 9-13 1997.
- [4035]
- M. Sivaraman
and A. J. Strojwas.
Primitive path delay faults: identification and their use in timing analysis.
IEEE Transactions on Computer-Aided Design, 19(11):1347-1362,
November 2000.
- [4036]
- D. Skias, Th.
Haniotakis, Y. Tsiatouhas, and A. Arapoyanni.
A state assignment algorithm for finite state machines.
In 7th IEEE International Conference on Electronics, Circuits and
Systems, pages 823-825, Beirut, Lebanon, December 17-19 2000.
- [4037]
- I. Skliarova and
A. B. Ferrari.
A software/reconfigurable hardware SAT solver.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):408-419, April 2004.
- [4038]
- N. J. A. Sloane.
On finding the paths though a network.
The Bell System Technical Journal, 51(2):371-390, February 1972.
- [4039]
- A. Smith,
A. Veneris, M. Fahim Ali, and A. Viglas.
Fault diagnosis and logic debugging using boolean satisfiability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(10):1606-1621, October 2005.
- [4040]
- D. Smith.
Delving into deep submicron.
Integrated System Design, pages 15-22, February 1995.
- [4041]
- G. Smith.
Platform based design: does it answer the entire soc challenge.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
407-407, San Diego, CA, June 7-11 2004.
- [4042]
- R. Smunyahirun
and E.-L. Tan.
Derivation of the most energy-efficient source functions by using calculus of
variations.
IEEE Transactions on Circuits and Systems, 63(4):494-502, April
2016.
- [4043]
- T. Smy and P. Gunupudi.
Robust simulation of opto-electronic systems by alternating complex envelope
representations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(7):1139-1143, July 2012.
- [4044]
- E. S. Snyder,
A. Kapoor, and C. Anderson.
The impact of statistics on hot-carrier lifetime estimates of n-channel
MOSFETS.
In B. Vasquez, A. Sabnis, K. P. MacWilliams, and J. C. S. Woo, editors,
Microelectronics Manufacturing and Reliability, Proc. SPIE 1802,
pages 180-187. SPIE - The International Society for Optical Engineering,
Bellingham, WA, 1992/93.
- [4045]
- I. M. Sobol.
A Primer for the Monte Carlo Method.
CRC Press, Boca Raton, FL, 1994.
- [4046]
- H. Soeleman,
K. Roy, and B. C. Paul.
Robust subthreshold logic for ultra-low power operation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(1):90-99, February 2001.
- [4047]
- H. Soleimani, A. Abmadi, and M. Bavandpour.
Biologically inspired spiking neurons: piecewise linear models and digital
implementation.
IEEE Transactions on Circuits and Systems, 59(12):2991-3004, December
2012.
- [4048]
- A. Solomatnikov, D. Somasekhar, N. Sirisantana, and K. Roy.
Skewed CMOS: noise-tolerant high-performance low-power static circuit family.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(4):469-476, August 2002.
- [4049]
- P. M. Solomon.
A comparison of semiconductor devices for high-speed logic.
In Proceedings of the IEEE, pages 489-510, May 1982.
- [4050]
- A. K. Somani,
U. R. Sandadi, D. W. Twigg, and T. C. Sharma.
An efficient decomposition technique for markov-chain analysis.
In Annual Reliability and Maintainability Symposium, pages 465-469,
Washington, DC, January 16-19 1995.
- [4051]
- K. Son and M. Soma.
Dynamic life-estimation of CMOS ics in real operating environment: precise
electrical method and MLE.
IEEE Transactions on Reliability, 46(1):31-37, March 1997.
- [4052]
- H.-Y. Song,
K. Nepal, R. I. Bahar, and J. Grodstein.
Timing analysis for full-custom circuits using symbolic DC formulations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1815-1830, September 2006.
- [4053]
- Q. Song, F. Liu,
J. Cao, and W. Yu.
Pinning-controllability analysis of complex networks: an m-matrix approach.
IEEE Transactions on Circuits and Systems, 59(11):2692-2701, November
2012.
- [4054]
- Y. Song, H. Yu, and
S. M. Pudukotai DinakarRao.
Reachability-based robustness verification and optimization of SRAM dynamic
stability under process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(4):585-598, April 2014.
- [4055]
- W. S. Song and L. A.
Glasser.
Power distribution techniques for VLSI circuits.
IEEE Journal of Solid-State Circuits, SC-21(1):150-156, February
1986.
- [4056]
- G. Sorkin.
Asymptotically perfect trivial global routing: a stochastic analysis.
IEEE Transactions on Computer-Aided Design, 6(5):820-827, September
1987.
- [4057]
- P. P.
Sotiriadis, T. Konstantakopoulos, and A. Chandrakasan.
Analysis and implementation of charge recycling for deep sub-micron buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 364-369, Huntington Beach, California, August 6-7
2001.
- [4058]
- P. P.
Sotiriadis and A. Chandrakasan.
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron
technologies.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 322-327, San Jose, CA, November 5-9 2000.
- [4059]
- P. P.
Sotiriadis and A. P. Chandrakasan.
A bus energy model for deep submicron technology.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):341-350, June 2002.
- [4060]
- P. P.
Sotiriadis and A. P. Chandrakasan.
Bus energy reduction by transition pattern coding using a detailed deep
submicrometer bus model.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(10):1280-1295, October 2003.
- [4061]
- K.-C. Sou,
A. Megretski, and L. Daniel.
A quasi-convex optimization approach to parameterized model order reduction.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
933-938, Anaheim, CA, June 13-17 2005.
- [4062]
- K.-C. Sou,
A. Megretski, and L. Daniel.
Bounding l2 gain system error generated by approximations of the nonlinear
vector field.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 879-886, San Jose, CA, November 5-8 2007.
- [4063]
- K. C. Sou,
A. Megretski, and L. Daniel.
A quasi-convex optimization approach to parameterized model order reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(3):456-469, March 2008.
- [4064]
- A. Sridhar,
A. Vincenzi, M. Ruggiero, and D. Atienza.
Neural network-based thermal simulation of integrated circuits on gpus.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(1):23-36, January 2012.
- [4065]
- A. Sridhar,
Y. Madhour, D. Atienza, T. Brunschwiler, and J. Thome.
STEAM: a fast compact thermal model for two-phase cooling of integrated
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 256-263, San Jose, CA, November 18-21 2013.
- [4066]
- S. R.
Sridhara, G. Balamurugan, and N. R. Shanbhag.
Joint equalization and coding for on-chip bus communication.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(3):314-318, March 2008.
- [4067]
- S. R. Sridhara
and N. R. Shanbhag.
Coding for system-on-chip networks: a unified framework.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
103-106, San Diego, CA, June 7-11 2004.
- [4068]
- S. Sridhara and
N. R. Shanbhag.
Coding for system-on-chip networks: a unified framework.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):655-667, June 2005.
- [4069]
- S. R. Sridhara
and N. R. Shanbhag.
A low-power bus design using joint repeater insertion and coding.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 99-102, San Diego, CA, August 8-10 2005.
- [4070]
- S. R. Sridhara
and N. R. Shanbhag.
Coding for reliable on-chip buses: a class of fundamental bounds and practical
codes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(5):977-982, May 2007.
- [4071]
- H. C.
Srinivasaiah and N. Bhat.
Mixed-mode simulation approach to characterize the circuit delay sensitivity to
implant dose variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(6):742-747, June 2003.
- [4072]
- A. Srinivasan, G. D. Huber, and D. P. LaPotin.
Accurate area and delay estimation from RTL descriptions.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(1):168-172, March 1998.
- [4073]
- S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir,
Y. Xie, and M. J. Irwin.
Improving soft-error tolerance of FPGA configuration bits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 107-110, San Jose, CA, November 7-11 2004.
- [4074]
- S. Srinivasan and K. Sarpatwari.
Flaw: FPGA lifetime awareness.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
630-635, San Francisco, CA, July 24-28 2006.
- [4075]
- T. Sripramong
and C. Toumazou.
The invention of CMOS amplifiers using genetic programming and current-flow
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(11):1237-1252, November 2002.
- [4076]
- M. B.
Srivastava, A. P. Chandrakasan, and R. W. Brodersen.
Predictive system shutdown and other architectural techniques for energy
efficient programmable computation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
4(1):42-55, March 1996.
- [4077]
- A. Srivastava, R. Bai, D. Blaauw, and D. Sylvester.
Modeling and analysis of leakage power considering within-die process
variations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 64-67, Monterey, California, August 12-14 2002.
- [4078]
- A. Srivastava, R. Kastner, C. Chen, and M. Sarrafzadeh.
Timing driven gate duplication.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(1):42-51, January 2004.
- [4079]
- A. Srivastava, D. Sylvester, and D. Blaauw.
Power minimization using simultaneous gate sizing, dual-vdd and dual-vth
assignment.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
783-787, San Diego, CA, June 7-11 2004.
- [4080]
- A. Srivastava, D. Sylvester, and D. Blaauw.
Statistical optimization of leakage power considering process variations using
dual-vth and sizing.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
773-778, San Diego, CA, June 7-11 2004.
- [4081]
- A. Srivastava, S. Shah, K. Agarwal, D. Sylvester, D. Blaauw, and
S. Director.
Accurate and efficient gate-level parametric yield estimation considering
correlated variations in leakage power and performance.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
535-540, Anaheim, CA, June 13-17 2005.
- [4082]
- A. Srivastava, T. Kachru, and D. Sylvester.
Low-power-design space exploration considering process variation using robust
optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):67-79, January 2007.
- [4083]
- A. Srivastava, K. Chopra, S. Shah, D. Sylvester, and D. Blaauw.
A novel approach to perform gate-level yield analysis and optimization
considering correlated variations in power and performance.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):272-285, February 2008.
- [4084]
- N. Srivastava and K. Banerjee.
Performance analysis of carbon nanotube interconnects for VLSI applications.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 383-390, San Jose, CA, November 6-10 2005.
- [4085]
- M. Srivastava and M. Potkonjak.
Power optimization in programmable processors and ASIC implementations of
linear systems: transformation-based approach.
In 33rd Design Automation Conference, pages 343-348, Las Vegas, NV,
June 3-7 1996.
- [4086]
- S. Srivastava and J. Roychowdhury.
Interdependent latch setup/hold time characterization via euler-newton curve
tracing on state-transition equations.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
136-141, San Diego, CA, June 4-8 2007.
- [4087]
- S. Srivastava and J. Roychowdhury.
Rapid and accurate latch characterization via direct newton solution of
setup/hold times.
Design, Automation and Test in Europe (DATE-07), pages 1006-1011,
April 16-20 2007.
- [4088]
- S. Srivastava and J. Roychowdhury.
Independent and interdependent latch setup/hold time characterization via
newton-raphson solution and euler curve tracking of state-transition
equations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(5):817-830, May 2008.
- [4089]
- A. Srivastava and M. Sarrafzadeh.
Predictabilitly: definition, analysis, and optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 118-121, San Jose, CA, November 10-14 2002.
- [4090]
- A. Srivastava and D. Sylvester.
A general framework for probabilistic low-power design space exploration
considering process variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 808-813, San Jose, CA, November 7-11 2004.
- [4091]
- A. Srivastava and D. Sylvester.
Minimizing total power by simultaneous vdd/vth assignment.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):665-677, May 2004.
- [4092]
- A. Srivastava.
Simultaneous vt selection and assignment for leakage optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 146-151, Seoul, Korea, August 25-27 2003.
- [4093]
- G. I. Stamoulis.
A monte-carlo approach for the accurate and efficient estimation of average
transition probabilities in sequential logic circuits.
In IEEE 1996 Custom Integrated Circuits Conference, pages 221-224,
San Diego, CA, May 5-8 1996.
- [4094]
- M. R. Stan and W. P.
Burleson.
Limited-weight codes for low-power I/O.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
209-214, Napa, CA, April 24-27 1994.
- [4095]
- M. R. Stan and W. P.
Burleson.
Bus-invert coding for low power I/O.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
3(1):49-58, March 1995.
- [4096]
- M. R. Stan and W. P.
Burleson.
Two-dimensional codes for low power.
In International Symposium on Low Power Electronics and Design, pages
335-340, Monterey, CA, August 12-14 1996.
- [4097]
- M. R. Stan and W. P.
Burleson.
Low-power encodings for global communication in CMOS VLSI.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
5(4):444-455, December 1997.
- [4098]
- T. Stanion and
C. Sechen.
Maximum projections of don't care conditions in a boolean network.
In IEEE International Conference on Computer-Aided Design, pages
674-679, Santa Clara, CA, 1993.
- [4099]
- P. Stanley-Marbell and M. S. Hsiao.
Fast, flexible cycle-accurate energy estimation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 141-146, Huntington Beach, California, August 6-7
2001.
- [4100]
- C. H. Stapper.
Modeling of integrated circuit defect sensitivities.
IBM Journal of Research and Development, 27(6):549-557, November
1983.
- [4101]
- D. Stark and
M. Horowitz.
Analyzing CMOS power supply networks using ariel.
In 25th ACM/IEEE Design Automation Conference, pages 460-464,
Anaheim, CA, June 12-15 1988.
- [4102]
- D. Stark and
M. Horowitz.
Techniques for calculating currents and voltages in VLSI power supply
networks.
IEEE Transactions on Computer-Aided Design, 9(2):126-132, February
1990.
- [4103]
- G. Steele,
D. Overhauser, S. Rochel, and S. Z. Hussain.
Full-chip verification methods for DSM power distribution systems.
In IEEE/ACM 35th Design Automation Conference, pages 744-749, San
Francisco, CA, June 15-19 1998.
- [4104]
- S. Steinhorst
and L. Hedrich.
Trajectory-directed discrete state space modeling for formal verification of
nonlinear analog circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 202-209, San Jose, CA, November 5-8 2012.
- [4105]
- P. Stephan,
R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
Combinational test generation using satisfiability.
IEEE Transactions on Computer-Aided Design, 15(9):1167-1176,
September 1996.
- [4106]
- I. Stevanovic and C. C. McAndrew.
Corrections to "quadratic backward propagation of variance for nonlinear
statistical circuit modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(12):1896-1896, December 2009.
- [4107]
- I. Stevanovic and C. C. McAndrew.
Quadratic backward propagation of variance for nonlinear statistical circuit
modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(9):1428-1432, September 2009.
- [4108]
- K. S. Stevens and
F. Dartu.
Algorithms for MIS vector generation and pruning.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 408-414, San Jose, CA, November 5-9 2006.
- [4109]
- T. Stohr, M. Alt,
A. Hetzel, and J. Koehl.
Analysis, reduction and avoidance of crosstalk on VLSI chips.
In ACM/IEEE International Symposium on Physical Design, pages
211-218, Monterey, CA, April 6-8 1998.
- [4110]
- V. Stojanovic, V. G. Oklobdzija, and R. Bajwa.
A unified approach in the analysis of latches and flip-flops for low-power
systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 227-232, Monterey, CA, August 10-12 1998.
- [4111]
- T. Stojanovski and L. Kocarev.
Chaos-based random number generators - part I: Analysis.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(3):281-289, March 2001.
- [4112]
- T. Stojanovski and L. Kocarev.
Chaos-based random number generators - part II: Practical realizations.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(3):382-385, March 2001.
- [4113]
- V. Stopjakova, P. Malosek, M. Matej, V. Nagy, and M. Margala.
Defect detection in analog and mixed circuits by neural networks using wavelet
analysis.
IEEE Transactions on Reliability, 54(3):441-448, September 2005.
- [4114]
- M. Storace and O. De
Feo.
Piecewise-linear approximation of nonlinear dynamical systems.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(4):830-842, April 2004.
- [4115]
- H.-G.
Stratigopoulos and S. Mir.
Analog test metrics estimates with PPM accuracy.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 241-247, San Jose, CA, November 7-11 2010.
- [4116]
- Ben G. Streetman.
Solid State Electronic Devices.
Prentice Hall, Inc., Englewood Cliffs, NJ, 1995.
- [4117]
- A. Strojwas,
T. Jhaveri, V. Rovner, and L. T. Pileggi.
Creating an affordable 22nm node using design-lithography co-optimization.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 95-96,
San Francisco, CA, July 26-31 2009.
- [4118]
- A. G. M.
Strollo, E. Napoli, and C. Cimino.
Analysis of power dissipation in double edge-triggered flip-flops.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(5):624-629, October 2000.
- [4119]
- A. G. M.
Strollo, D. De Caro, E. Napoli, and N. Petra.
A novel high-speed sense-amplifier-based flip-flop.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1266-1274, November 2005.
- [4120]
- D. Stroobandt
and F. J. Kurdahi.
On the characterization of multi-point nets in electronic design.
In IEEE Eighth Great Lakes Symposium on VLSI, pages 344-350,
Lafayette, LA, February 19-21 1998.
- [4121]
- M. A. Styblinski
and M. Huang.
Drift reliability optimization in IC design: generalized formulation and
practical examples.
IEEE Transactions on Computer-Aided Design, 12(8):1242-1252, August
1993.
- [4122]
- S-L. Su, V. B. Rao, and
T. N. Trick.
A simple and accurate node reduction technique for interconnect modeling in
circuit extraction.
In IEEE International Conference on Computer-Aided Design, pages
270-273, 1986.
- [4123]
- H.-P. Su, A. C.-H. Wu,
and Y.-L. Lin.
A timing-driven soft-macro placement and resynthesis method in interaction with
chip floorplanning.
IEEE Transactions on Computer-Aided Design, 18(4):475-483, April
1999.
- [4124]
- H. Su, K. H. Gala, and
S. S. Sapatnekar.
Fast analysis and optimization of power/ground networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 477-480, San Jose, CA, November 5-9 2000.
- [4125]
- P. Su, S. K. H. Fung,
W. Liu, and C. Hu.
Studying the impact of gate tunneling on dynamic behaviors of
partially-depleted SOI CMOS using BSIMPD.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 487-491, San Jose, CA, March 18-21 2002.
- [4126]
- Q. Su, A V.
Balakrishnan, and C.-K. Koh.
A factorization-based framework for passivity-preserving model order reduction
of RLC systems.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages 40-45,
New Orleans, LA, June 10-14 2002.
- [4127]
- H. Su, E. Acar, and
S. R. Nassif.
Power grid reduction based on algebraic multigrid principles.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
109-112, Anaheim, CA, June 2-6 2003.
- [4128]
- H. Su, K. H. Gala, and
S. S. Sapatnekar.
Analysis and optimization of structured power/ground networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(11):1533-1544, November 2003.
- [4129]
- H. Su, F. Liu,
A. Devgan, E. Acar, and S. Nassif.
Full chip leakage estimation considering power supply and temperature
variations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 78-83, Seoul, Korea, August 25-27 2003.
- [4130]
- H. Su, S. S.
Sapatnekar, and S. R. Nassif.
Optimal decoupling capacitor sizing and placement for standard-cell layout
designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(4):428-436, April 2003.
- [4131]
- H. Su, J. Hu, S. S.
Sapatnekar, and S. R. Nassif.
A methodology for the simultaneous design of supply and signal networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(12):1614-1624, December 2004.
- [4132]
- Y. Su, J. Wang,
X. Zeng, Z. Bai, C. Chiang, and D. Zhou.
SAPOR: second-order arnoldi method for passive order reduction of RCS
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 74-79, San Jose, CA, November 7-11 2004.
- [4133]
- H. Su, D. Widiger,
C. Kashyap, F. Liu, and B. Krauter.
A noise-driven effective capacitance method with fast embedded noise rule
calculation for functional noise analysis.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
186-189, Anaheim, CA, June 13-17 2005.
- [4134]
- F. Su, K. Chakrabarty,
and R. B. Fair.
Microfluidics-based biochips: technology issues, implementation platforms, and
design-automation challenges.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(2):211-223, February 2006.
- [4135]
- J. Su, T. Tu, and L. He.
A quantum annealing approach for boolean satisfiability problem.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [4136]
- B.-Y. Su and Y.-W. Chang.
An exact jumper insertion algorithm for antenna effect avoidance/fixing.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
325-328, Anaheim, CA, June 13-17 2005.
- [4137]
- Y. Su and W. Rao.
Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping
and morphing simultaneously.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 456-462, San Jose, CA, November 7-10 2011.
- [4138]
- J. S. Suehle and H. A.
Schafft.
Current density dependence of electromigration t50 enhancement due to pulsed
operation.
In IEEE 28th International Reliability Physics Symposium, pages
106-110, New Orleans, LA, March 27-29 1990.
- [4139]
- D. S.
Sugiharto, C. Y. Yang, H. Le, and J. E. Chung.
Beating the heat.
IEEE Circuits and Devices Magazine, 14(5):43-51, September 1998.
- [4140]
- A. Suissa,
O. Romain, J. Denoulet, K. Hachicha, and P. Garda.
Empirical method based on neural networks for analog power modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(5):839-844, May 2010.
- [4141]
- V. Sukharev,
X. Huang, H.-B. Chen, and S.-X.-D. Tan.
IR-drop based electromigration assessment: parametric failure chip-scale
analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 428-433, San Jose, CA, November 2-6 2014.
- [4142]
- V. Sukharev,
X. Huang, and X.-D. Tan.
Electromigration induced stress evolution under alternate current and pulse
current loads.
Journal of Applied Physics, 118(3), July 21 2015.
- [4143]
- V. Sukharev,
A. Kteyan, and X. Huang.
Postvoiding stress evolution in confined metal lines.
IEEE Transactions on Device and Materials Reliability (TDMR),
16(1):50-60, March 2016.
- [4144]
- V. Sukharev,
A. Kteyan, J.-H. Choy, S. Chatterjee, and F. N. Najm.
Theoretical predictions of EM-induced degradation in test-structures and
on-chip power grids with analytical and numerical analysis.
In IEEE International Reliability Physics Symposium (IRPS), page 6B.5,
Monterey, CA, April 2-6 2017.
- [4145]
- V. Sukharev and F. N.
Najm.
Electromigration check: where the design and reliability methodologies meet.
IEEE Transactions on Device and Materials Reliability (TDMR),
18(4):498-507, December 2018.
- [4146]
- V. Sukharev.
Physically based simulation of electromigration-induced degradation mechanisms
in dual-inlaid copper interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(9):1326-1335, September 2005.
- [4147]
- V. Sukharev.
Beyond black's equation: Full-chip EM/SM assessment in 3d IC stack.
Microelectronic Engineering, 120:99-105, May 25 2014.
- [4148]
- A. K.
Sultania, D. Sylvester, and S. S. Sapatnekar.
Tradeoffs between gate oxide leakage and delay for dual tox circuits.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
761-766, San Diego, CA, June 7-11 2004.
- [4149]
- A. K.
Sultania, D. Sylvester, and S. S. Sapatnekar.
Gate oxide leakage and delay tradeoffs for dual-tox circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(12):1362-1375, December 2005.
- [4150]
- M. Sumita,
S. Sakiyama, M. Kinoshita, Y. Araki, Y. Ikeda, and K. Fukuoka.
Mixed body-bias technologies with fixed vt and ids generation circuits.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 233-234, Austin, TX, May 9 - 11 2005.
- [4151]
- M. Sumita.
High resolution body bias techniques for reducing the impacts of leakage
current and parasitic bipolar.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 203-208, San Diego, CA, August 8-10 2005.
- [4152]
- S.-Z. Sun, D. H. C.
Du, and H.-C. Chen.
Efficient timing analysis for CMOS circuits considering data dependent
delays.
IEEE Transactions on Computer-Aided Design, 17(6):546-552, June
1998.
- [4153]
- K. Sun, Q. Zhou,
K. Mohanram, and D. C. Sorensen.
Parallel domain decomposition for simulation of large-scale power grids.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 54-59, San Jose, CA, November 5-8 2007.
- [4154]
- J. Sun, J. Li, D. Ma,
and J. M. Wang.
Chebyshev affine-arithmetic-based parametric yield prediction under limited
descriptions of uncertainty.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1852-1865, October 2008.
- [4155]
- X. Sun, P. Nuzzo,
C.-C. Wu, and A. Sangiovanni-Vincentelli.
Contract-based system-level composition for analog circuits.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
605-610, San Francisco, CA, July 26-31 2009.
- [4156]
- P. Sun, X. Li, and
M.-Y. Ting.
Efficient incremental analysis of on-chip power grid via sparse approximation.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
676-681, San Diego, CA, June 5-9 2011.
- [4157]
- J. Sun, P. Gupta,
and J. Roveda.
A new uncertainty budgeting based method for robust analog/mixed-signal design.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
529-535, San Francisco, CA, June 3-7 2012.
- [4158]
- S. Sun, M. Monga,
P. H. Jones, and J. Zambreno.
An I/O bandwidth-sensitive sparse matrix-vector multiplication engine on
fpgas.
IEEE Transactions on Circuits and Systems, 59(1):113-123, January
2012.
- [4159]
- S. Sun, X. Li, H. Liu,
K. Luo, and B. Gu.
Fast statistical analysis of rate circuit failure events via scaled-sigma
sampling for high-dimensional variation space.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(7):1096-1109, July 2015.
- [4160]
- Z. Sun, E. Demircan,
M. D. Shroff, T. Kim, X. Huang, and S.-X.-D. Tan.
Voltage-based electromigration immortality check for general multi-branch
interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [4161]
- S. Sun and X. Li.
Fast statistical analysis of rare circuit failure events via subset simulation
in high-dimensional variation space.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 324-331, San Jose, CA, November 2-6 2014.
- [4162]
- S. Sun and X. Li.
Fast statistical analysis of rare failure events for memory circuits in
high-dimensional variation space.
In 20th Asia and South Pacific Design Automation Conference, pages
302-307, Chiba/Tokyo, Japan, January 19-22 2015.
- [4163]
- V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi.
Fast and exact transistor sizing based on iterative relaxation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(5):568-581, May 2002.
- [4164]
- V. Sundararajan and K. K. Parhi.
Low power synthesis of dual threshold voltage CMOS VLSI circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 139-144, San Diego, CA, August 16-17 1999.
- [4165]
- K. Sundaresan and N. R. Mohapatra.
An analysis of timing violations due to spatially distributed thermal effects
in global wires.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
515-520, San Diego, CA, June 4-8 2007.
- [4166]
- R. Sundblad and
C. Svensson.
Fully dynamic switch-level simulation of CMOS circuits.
IEEE Transactions on Computer-Aided Design, CAD-6(2):282-289, March
1987.
- [4167]
- D. C. Suresh,
B. Agrawal, and W. Najjar.
A tunable bus encoder for off-chip data buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 319-322, San Diego, CA, August 8-10 2005.
- [4168]
- O. Suvak and A. Demir.
Computing quadratic approximations for the isochrons of oscillators: a general
theory and advanced numerical methods.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 397-402, San Jose, CA, November 2-5 2009.
- [4169]
- C. Svensson and
A. Alvandpour.
Low power and low voltage CMOS digital circuit techniques.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 7-10, Monterey, CA, August 10-12 1998.
- [4170]
- C. Svensson and
D. Liu.
A power estimation tool and prospects of power savings in CMOS VLSI chips.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
171-176, Napa, CA, April 24-27 1994.
- [4171]
- V. Swaminathan and K. Chakrabarty.
Generalized network flow techniques for dynamic voltage scaling in hard
real-time systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 21-25, San Jose, CA, November 9-13 2003.
- [4172]
- V. Swaminathan and K. Chakrabarty.
Network flow techniques for dynamic voltage scaling in hard real-time systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(10):1385-1398, October 2004.
- [4173]
- D. Sylvester and
K. Keutzer.
Getting to the bottom of deep sub-micron.
In IEEE/ACM International Conference on Computer-Aided Design, pages
203-211, San Jose, CA, November 8-12 1998.
- [4174]
- D. Sylvester and
K. Keutzer.
Getting to the bottom of deep submicron II: A global wiring paradigm.
In 1999 International Symposium on Physical Design, pages 193-200,
Monterey, CA, April 12-14 1999.
- [4175]
- D. Sylvester and
K. Keutzer.
A global wiring paradigm for deep submicron design.
IEEE Transactions on Computer-Aided Design, 19(2):242-252, February
2000.
- [4176]
- S. M. Sze.
VLSI Technology.
McGraw-Hill Book Company, New York, NY, 1983.
- [4177]
- J. Sztipanovits, T. Bapty, S. Neema, X. Koutsoukos, and
E. Jackson.
Design tool chain for cyber-physical systems: lessons learned.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4178]
- H. Szu and R. Hartley.
Fast simulated annealing.
Physics Letters A, 122(3,4):157-162, June 8 1987.
- [4179]
- T. H.
Szymanski, H. Wu, and A. Gourgy.
Power complexity of multiplexer-based optoelectronic crossbar switches.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(5):604-617, May 2005.
- [4180]
- T. G. Szymanski.
Leadout: a static timing analyzer for MOS circuits.
In IEEE International Conference on Computer-Aided Design, pages
130-133, Santa Clara, CA, Nov. 11-13 1986.
- [4181]
- A. Tabbara,
R. K. Brayton, and A. R. Newton.
Retiming for DSM with area-delay trade-offs and delay constraints.
In Design Automation Conference, pages 725-730, New Orleans, LA, June
21-25 1999.
- [4182]
- M. Tachibana, S. Kurosawa, R. Nojima, N. Kojima, M. Yamada,
T. Mitsushashi, and N. Goto.
Power and area optimization by reorganizing CMOS complex gate circuits.
In ACM/IEEE International Symposium on Low Power Design, pages
155-160, Dana Point, CA, April 23-26 1995.
- [4183]
- D. Tadesse,
D. Sheffield, E. Lenge, R. I. Bahar, and J. Grodstein.
Accurate timing analysis using SAT and pattern-dependent delay models.
Design, Automation and Test in Europe (DATE-07), pages 1018-1023,
April 16-20 2007.
- [4184]
- M. Tadeusiewicz.
A method for finding bounds on all the dc solutions of transistor circuits.
IEEE Transactions on Circuits and Systems - I, 39(7):557-564, July
1992.
- [4185]
- P. Tafertshofer, A. Ganz, and K. J. Antreich.
IGRAINE - an implication graph-based engine for fast implication,
justification, and propagation.
IEEE Transactions on Computer-Aided Design, 19(8):907-927, August
2000.
- [4186]
- M. B. Tahoori.
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 668-672, San Jose, CA, November 6-10 2005.
- [4187]
- M. B. Tahoori.
Application-independent defect-tolerant crossbar nano-archiectures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 730-734, San Jose, CA, November 5-9 2006.
- [4188]
- A. Tajalli and
Y. Leblebici.
Design trade-offs in ultra-low-power digital nanoscale CMOS.
IEEE Transactions on Circuits and Systems, 58(9):2189-2200, September
2011.
- [4189]
- H. Takahashi, K. J. Keller, K. T. Le, K. K. Saluja, and
Y. Takamatsu.
A method for reducing the target fault list of crosstalk faults in synchronous
sequential circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(2):252-263, February 2005.
- [4190]
- S. Takahashi, Y. Yoshida, and S. Tsukiyama.
A gaussian mixture model for statistical timing analysis.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
110-115, San Francisco, CA, July 26-31 2009.
- [4191]
- Y. Takashima.
Analytical placement for rectilinear blocks.
In 20th Asia and South Pacific Design Automation Conference, pages
220-225, Chiba/Tokyo, Japan, January 19-22 2015.
- [4192]
- K. Takeuchi,
K. Yanagisawa, T. Sato, K. Sakamoto, and S. Hojo.
Probabilistic crosstalk delay estimation for asics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1377-1383, September 2004.
- [4193]
- K. Takeuchi,
M. Shimada, T. Sato, Y. Katsuki, H. Yoshikawa, and H. Matsushita.
Spatial distribution measurement of dynamic voltage drop caused by pulse and
periodic injection of spot noise.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(1):164-168, January 2013.
- [4194]
- E. Talpes and
D. Marculescu.
Toward a multiple clock/voltage island design style for power-aware processors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(5):591-603, May 2005.
- [4195]
- K. H. Tam, Y. Yu,
L. He, T. T. Jing, and X. Zhang.
Dual-vdd buffer insertion for power reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(8):1498-1502, August 2008.
- [4196]
- W.-C. Tam and S. Blanton.
To DFM or not to DFM?
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
65-70, San Diego, CA, June 5-9 2011.
- [4197]
- R. Tamhankar, S. Murali, S. Stergiou, A. Pullini, F. Angiolini,
L. Benini, and G. De Micheli.
Timing-error-tolerant network-on-chip design methodology.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(7):1297-1310, July 2007.
- [4198]
- Y. Tamiya,
Y. Matsunaga, and M. Fujita.
LP based cell selection with constraints of timing, area and power
consumption.
In IEEE/ACM International Conference on Computer-Aided Design, pages
378-381, San Jose, CA, November 6-10 1994.
- [4199]
- X.-D. Tan, C.-J. R.
Shi, D. Lungeanu, J.-C. Lee, and L.-P. Yuan.
Reliability-constrained area optimization of VLSI power/ground networks via
sequence of linear programmings.
In Design Automation Conference, pages 78-83, New Orleans, LA, June
21-25 1999.
- [4200]
- T. K. Tan,
A. Raghunathan, G. Lakshminarayana, and N. K. Jha.
High-level software energy macro-modeling.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
605-610, Las Vegas, NV, June 18-22 2001.
- [4201]
- T. K. Tan,
A. Raghunathan, G. Lakshminarayana, and N. K. Jha.
High-level energy macromodeling of embedded software.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(9):1037-1050, September 2002.
- [4202]
- S. X.-D. Tan,
C.-J. R. Shi, and J.-C. Lee.
Reliability-constrained area optimization of VLSI power/ground networks via
sequence of linear programmings.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(12):1678-1684, December 2003.
- [4203]
- X.-D. Tan and C.-J. R. Shi.
Fast power/ground network optimization based on equivalent circuit modeling.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
550-554, Las Vegas, NV, June 18-22 2001.
- [4204]
- S. X.-D. Tan and C.-J. R. Shi.
Efficient very large scale integration power/ground network sizing based on
equivalent circuit modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(3):277-284, March 2003.
- [4205]
- S. X.-D. Tan and C.-J. R. Shi.
Efficient approximation of symbolic expressions for analog behavioral modeling
and analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):907-918, June 2004.
- [4206]
- S. X.-D. Tan.
A general s-domain hierarchical network reduction algorithm.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 650-657, San Jose, CA, November 9-13 2003.
- [4207]
- S. X.-D. Tan.
A general hierarchical circuit modeling and simulation algorithm.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):418-434, March 2005.
- [4208]
- H.-A. Tanaka,
A. Hasegawa, H. Mizuno, and T. Endo.
Synchronizability of distributed clock oscillators.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(9):1271-1278, September 2002.
- [4209]
- X. Tang, V. K. De,
and J. D. Meindl.
Effects of random MOSFET parameter fluctuations on total power consumption.
In International Symposium on Low Power Electronics and Design, pages
233-236, Monterey, CA, August 12-14 1996.
- [4210]
- L. C. Tang, Y. Lu,
and E. P. Chew.
Mean residual life of lifetime distributions.
IEEE Transactions on Reliability, 48(1):73-78, March 1999.
- [4211]
- Z. Tang, N. Chang,
S. Lin, W. Xie, O. S. Nakagawa, and L. He.
Instruction prediction for step power reduction.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 211-216, San Jose, CA, March 26-28 2001.
- [4212]
- S. Tang,
S. Narendra, and V. De.
Temperature and process invariant MOS-based reference current generation
circuits for sub-1v operation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 199-204, Seoul, Korea, August 25-27 2003.
- [4213]
- X. Tang, H. Zhou,
and P. Banerjee.
Leakage power optimization with dual-vth library in high-level synthesis.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
202-207, Anaheim, CA, June 13-17 2005.
- [4214]
- X. Tang, R. Tian,
and M.-D.-F. Wong.
Minimizing wire length in floorplanning.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1744-1783, September 2006.
- [4215]
- X. Tang, X. Yuan,
and M. S. Gray.
Practical method for obtaining a feasible integer solution in hierarchical
layout optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 99-104, San Jose, CA, November 5-8 2007.
- [4216]
- Q. Tang, A. Zjajo,
M. Berkelaar, and N. van der Meijs.
RDE-based transistor-level gate simulation for statistical static timing
analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
787-792, Anaheim, CA, June 13-18 2010.
- [4217]
- Q. Tang,
J. Rodriguez, A. Zjajo, M. Berkelaar, and N. van der Meijs.
Statistical transistor-level timing analysis using direct random differential
equation solver.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(2):210-223, February 2014.
- [4218]
- Q. Tang, A. Zjajo,
M. Berkelaar, and N. van der Meijs.
Considering crosstalk effects in statistical timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(2):318-322, February 2014.
- [4219]
- K. T. Tang and E. G.
Friedman.
Simultaneous switching noise in on-chip CMOS power distribution networks.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(4):487-493, August 2002.
- [4220]
- A. Tang and N. K. Jha.
Genfin: genetic algorithm-based multiobjective statistical logic circuit
optimization using incremental statistical analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(3):1126-1139, March 2016.
- [4221]
- T. K. Tang and M. S.
Nakhla.
Analysis of high-speed VLSI interconnects using the asymptotic waveform
evaluation technique.
IEEE Transactions on Computer-Aided Design, 11(3):341-352, March
1992.
- [4222]
- W. C. Tang.
Overview of microelectromechanical systems and design processes.
In 34th Design Automation Conference, pages 670-673, Anaheim, CA,
June 9-13 1997.
- [4223]
- Y. Tanji and H. Asai.
Closed-form expressions of distributed RLC interconnects for analysis of
on-chip inductance effects.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
810-813, San Diego, CA, June 7-11 2004.
- [4224]
- D. Tannir.
Direct sensitivity analysis of nonlinear distortation in RF circuits using
multidimensional moments.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(3):321-331, March 2015.
- [4225]
- J. Tao, H. Yu,
D. Zhou, Y. Su, X. Zeng, and X. Li.
Correlated rare failure analysis via asymptotic probability evaluation.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [4226]
- A. Taparia,
B. Banerjee, and T. R. Viswanathan.
Power-supply noise reduction using active inductors in mixed-signal systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(11):1960-1968, November 2011.
- [4227]
- R. A. Tapia, J. E.
Dennis, Jr., and J. P. Schafermeyer.
Inverse, shifted inverse, and rayleigh quotient iteration as newton's method.
SIAM Review, 60(1):3-55, March 2018.
- [4228]
- S. Tarafdar,
M. Leeser, and Z. Yin.
Integrating floorplanning in data-transfer based high-level synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
412-417, San Jose, CA, November 8-12 1998.
- [4229]
- R. Tarjan.
Depth-first search and linear graph algorithms.
SIAM Journal On Computing, 1(2):146-160, June 1972.
- [4230]
- R. E. Tarjan.
A unified approach to path problems.
Journal of the Association for Computing Machinery, 28(3):577-593,
July 1981.
- [4231]
- Robert Tarjan.
Data Structures and Network Algorithms.
Society for Industrial and Applied Mathematics (SIAM), 1983.
- [4232]
- S. Tasiran and
A. Demir.
Smart monte carlo for yield estimation.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-06), San Jose, CA, February 27-28
2006.
- [4233]
- B. Taskin and I. S.
Kourtev.
Linearization of the timing analysis and optimization of level-sensitive
digital synchronous circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(1):12-27, January 2004.
- [4234]
- Y. Taur.
CMOS design near the limit of scaling.
IBM J. Res. & Dev., 46(2/3):213-222, March-May 2002.
- [4235]
- V. Tavsandogiu.
Decomposition of the nodal conductance matrix of a planar resistive grid and
derivation of its eigenvalues and eigenvectors using the kronecker product
and sum with application to CNN image filters.
IEEE Transactions on Circuits and Systems I: Regular Papers,
63(12):2169-2179, December 2016.
- [4236]
- B. F. Tawadros and
R. S. Guindi.
State assignment for low-leakage finite state machines.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 115-118, Quebec City, Quebec, June 19-22 2005.
- [4237]
- S. A. Tawfik and
V. Kursun.
Dual supply voltages and dual clock frequencies for lower clock power and
suppressed temperature-gradient-induced clock skew.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(3):347-355, March 2010.
- [4238]
- C. N. Taylor,
S. Dey, and Y. Zhao.
Modeling and minimization of interconnect energy dissipation in nanometer
technologies.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
754-757, Las Vegas, NV, June 18-22 2001.
- [4239]
- R. R. Taylor and
H. Schmit.
Creating a power-aware structured ASIC.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 74-77, Newport Beach, CA, August 9-11 2004.
- [4240]
- M. Taylor.
Is dark silicon useful?
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1131-1136, San Francisco, CA, June 3-7 2012.
- [4241]
- C.-K. Teh, M. Hamada,
T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki.
Conditional data mapping flip-flops for low-power and high-performance systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(12):1379-1383, December 2006.
- [4242]
- S. Teja and J. P.
Kulkarni.
Soft-FET: phase transition material assisted soft switching field effect
transistor for supply voltage droop mitigation.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [4243]
- R. Telichevesky, K. Kundert, I. Elfadel, and J. White.
Fast simulation algorithms for RF circuits.
In IEEE 1996 Custom Integrated Circuits Conference, pages 437-444,
San Diego, CA, May 5-8 1996.
- [4244]
- G. E. Tellez,
A. Farrahi, and M. Sarrafzadeh.
Activity-driven clock design for low power circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
62-65, San Jose, CA, November 5-9 1995.
- [4245]
- C-C. Teng, A. M.
Hill, and S-M. Kang.
Estimation of maximum transition counts at internal nodes in CMOS VLSI
circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
366-370, San Jose, CA, November 5-9 1995.
- [4246]
- C-C. Teng, Y-K.
Cheng, E. Rosenbaum, and S-M. Kang.
Hierarchical electromigration reliability diagnosis.
In 33rd Design Automation Conference, pages 752-757, Las Vegas, NV,
June 3-7 1996.
- [4247]
- C.-C. Teng, Y.-K.
Cheng, E. Rosenbaum, and S.-M. Kang.
item: A temperature-dependent electromigration reliability diagnosis tool.
IEEE Transactions on Computer-Aided Design, 16(8):882-893, August
1997.
- [4248]
- Y.-C. Teng, S. C.
Chin, and J. C. S. Woo.
The impact of SOI mosfets on low power digital circuits.
In 1997 International Symposium on Low Power Electronics and Design,
pages 243-246, Monterey, CA, August 18-20 1997.
- [4249]
- B. Teng and J. H.
Anderson.
Latch-based performance optimization for field-programmable gate arrays.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(5):667-680, May 2013.
- [4250]
- Y. Teng and B. Taskin.
Frequency-centric resonant rotary clock distribution network design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 742-749, San Jose, CA, November 2-6 2014.
- [4251]
- H. Tennakoon and
C. Sechen.
Gate sizing using lagrangian relaxation combined with a fast gradient-based
pre-processing step.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 395-402, San Jose, CA, November 10-14 2002.
- [4252]
- H. Tennakoon and
C. Sechen.
Nonconvex gate delay modeling and delay optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(9):1583-1594, September 2008.
- [4253]
- R. A. Thakker,
C. Santhe, M. S. Baghini, and M. B. Patil.
A table-based approach to study the impact of process variations on finfet
circuit performance.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):627-631, April 2010.
- [4254]
- A. Thayse and M. Davio.
Boolean differential calculus and its application to switching theory.
IEEE Transactions on Computers, C-22(4):409-420, April 1973.
- [4255]
- A. Thayse.
Transient analysis of logical networks applied to hazard detection.
Philips Research Reports, 25(5):261-336, October 1970.
- [4256]
- A. Thayse.
Boolean differential calculus.
Philips Research Reports, 26:229-246, June 1971.
- [4257]
- A. Thayse.
A fast algorithm for the proper decomposition of boolean functions.
Philips Research Reports, 27:140-150, April 1972.
- [4258]
- A. Thayse.
A variational diagnosis method for stuck-faults in combinatorial networks.
Philips Research Reports, 27:82-98, February 1972.
- [4259]
- D. B. Thomlas and
W. Luk.
The LUT-SR family of uniform random number generators for FPGA
architectures.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(4):761-770, April 2013.
- [4260]
- S. Thompson,
P. Packan, and M. Bohr.
MOS scaling: transistor challenges for the 21st century.
Intel Technology Journal, pages 1-19, Q3 1998.
- [4261]
- S. K. Thompson.
Sampling.
John Wiley & Sons, Inc., New York, NY, 2nd edition, 2002.
- [4262]
- J. Thong and
N. Nicolici.
A novel optimal single constant multiplication algorithm.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
613-616, Anaheim, CA, June 13-18 2010.
- [4263]
- J. Thong and
N. Nicolici.
FPGA acceleration of enhanced boolean constraint propagation for SAT
solvers.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 234-241, San Jose, CA, November 18-21 2013.
- [4264]
- J. Thong and
N. Nicolici.
SAT solving using FPGA-based heterogeneous computing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 232-239, Austin, TX, November 2-6 2015.
- [4265]
- H. K.
Thornquist, E. R. Keiter, R. J. Hoekstra, D. M. Day, and E. G. Boman.
A parallel preconditioning strategy for efficient transistor-level circuit
simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 410-417, San Jose, CA, November 2-5 2009.
- [4266]
- M. A. Thornton and
V. S. S. Nair.
Efficient calculation of spectral coefficients and their applications.
IEEE Transactions on Computer-Aided Design, 14(11):1328-1341,
November 1995.
- [4267]
- T. Thorp, G. Yee,
and C. Sechen.
Domino logic synthesis using complex static gates.
In IEEE/ACM International Conference on Computer-Aided Design, pages
242-247, San Jose, CA, November 8-12 1998.
- [4268]
- T. J. Thorp, G. S.
Yee, and C. M. Sechen.
Design and synthesis of dynamic circuits.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
11(1):141-149, February 2003.
- [4269]
- B. Thudi and D. Blaauw.
Non-iterative switching window computation for delay-noise.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
390-395, Anaheim, CA, June 2-6 2003.
- [4270]
- M. W. Tian and C.-J. R. Shi.
Worst case tolerance analysis of linear analog circuits using sensitivity
bands.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 47(8):1138-1145, August 2000.
- [4271]
- T.-K. Tien, S.-C.
Chang, and T.-K. Tsai.
Crosstalk alleviation for dynamic PLA.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(12):1416-1424, December 2002.
- [4272]
- T.-K. Tien, C.-S.
Tsai, S.-C. Chang, and C. Yeh.
Power minimization for dynamic plas.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(6):616-624, June 2006.
- [4273]
- L. Ting, J. S. May,
W. R. Hunter, and J. W. McPherson.
AC electromigration characterization and modeling of multilayered
interconnections.
In International Reliability Physics Symposium (IRPS), pages 311-316,
1993.
- [4274]
- L. M. Ting, J. S.
May, W. R. Hunter, and J. W. McPherson.
AC electromigration characterization and modeling of multilayered
interconnects.
In International Reliability Physics Symposium (IRPS), pages 311-316,
March 1993.
- [4275]
- V. Tiwari,
P. Ashar, and S. Malik.
Technology mapping for low power.
In 30th ACM/IEEE Design Automation Conference, pages 74-79, Dallas,
TX, June 14-18 1993.
- [4276]
- V. Tiwari,
S. Malik, and A. Wolfe.
Power analysis of embedded software: a first step towards software power
minimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2(4):437-445, December 1994.
- [4277]
- V. Tiwari,
S. Malik, and A. Wolfe.
Power analysis of embedded software: a first step towards software power
minimization.
In IEEE/ACM International Conference on Computer-Aided Design, pages
384-390, San Jose, CA, November 6-10 1994.
- [4278]
- V. Tiwari,
S. Malik, and P. Ashar.
Guarded evaluation: pushing power management to logic synthesis/design.
In ACM/IEEE International Symposium on Low Power Design, pages
221-226, Dana Point, CA, April 23-26 1995.
- [4279]
- V. Tiwari,
S. Malik, and P. Ashar.
Guarded evaluation: pushing power management to logic synthesis/design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 17(10):1051-1060, October 1998.
- [4280]
- V. Tiwari,
D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez.
Reducing power in high performance microprocessors.
In IEEE/ACM 35th Design Automation Conference, pages 732-737, San
Francisco, CA, June 15-19 1998.
- [4281]
- S. K. Tiwary,
A. Gupta, J. R. Phillips, C. Pinello, and R. Zlatanovici.
First steps towards SAT-based formal analog verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 1-8, San Jose, CA, November 2-5 2009.
- [4282]
- S. K. Tiwary and
J. R. Phillips.
WAVSTAN: waveform based variational static timing analysis.
Design, Automation and Test in Europe (DATE-07), pages 1000-1005,
April 16-20 2007.
- [4283]
- S. K. Tiwary and
R. A. Rutenbar.
Faster, parametric trajectory-based macromodels via localized linear
reductions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 876-883, San Jose, CA, November 5-9 2006.
- [4284]
- A. Todri, S.-C.
Chang, and M. Marek-Sadowska.
Electromigration and voltage drop aware power grid optimization for power gated
ics.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 391-394, Portland, Oregon, August 27-29 2007.
- [4285]
- A. Todri,
M. Marek-Sadowska, and S.-C. Chang.
Analysis and optimization of power-gated ics with multiple power gating
configurations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 783-790, San Jose, CA, November 5-8 2007.
- [4286]
- A. Todri,
M. Marek-Sadowska, and J. Kozhaya.
Power supply noise aware workload assignment for multi-core systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 330-337, San Jose, CA, November 10-13 2008.
- [4287]
- A. Todri and
M. Marek-Sadowska.
Power delivery for multicore systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(12):2243-2255, December 2011.
- [4288]
- A. Todri and
M. Marek-Sadowska.
Reliability analysis and optimization of power-gated ics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(3):457-468, March 2011.
- [4289]
- A. Todri-Sanial, S. Kundu, P. Girard, A. Bosio, L. Dilillo, and
A. Virazel.
Globally constrained locally optimized 3-D power delivery networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(10):2131-2144, October 2014.
- [4290]
- A. Todri-Sanial and Y. Cheng.
A study of 3-D power delivery networks with multiple clock domains.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(11):3218-3231, November 2016.
- [4291]
- J. R. Tolbert,
X. Zhao, S. K. Lim, and S. Mukhopadhyay.
Analysis and design of energy and slew aware subthreshold clock systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(9):1349-1358, September 2011.
- [4292]
- Y. Tomita,
N. Iwanishi, R. Yamaguchi, and H. Edamatsu.
Dual threshold delay model for nonlinear device characterization.
In IEEE Custom Integrated Circuits Conference, pages 371-374, Santa
Clara, CA, May 1-4 1995.
- [4293]
- X. Tong, F. F. Wu,
and L. Qi.
Available transfer capability calculation using a smoothing pointwise maximum
function.
IEEE Transactions on Circuits and Systems, 55(2):450-462, February
2008.
- [4294]
- R. O. Topaloglu.
Design with finfets: design rules, patterns, and variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 569-571, San Jose, CA, November 18-21 2013.
- [4295]
- E. A.
Trachtenberg and D. Varma.
A design automation tool for fast, efficient decomposition of logical
functions.
In IEEE International Conference on Computer-Aided Design, pages
70-73, Santa Clara, CA, Nov. 9-12 1987.
- [4296]
- L. N. Trefethen
and J. A. C. Weideman.
The exponentially convergent trapezoidal rule.
SIAM Review, 56(3):385-458, 2014.
- [4297]
- R. Trihy.
Addressing library creation challenges from recent liberty extensions.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
474-479, Anaheim, CA, June 8-13 2008.
- [4298]
- R. Trinchero, P. Manfredi, T. Ding, and I. S. Stievano.
Combined parametric and worst case circuit analysis via taylor models.
IEEE Transactions on Circuits and Systems, 63(7):1067-1078, July
2016.
- [4299]
- A. R. Trivedi and
A. Shylendra.
Ultralow power acoustic feature-scoring using gaussian I-V transistors.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [4300]
- D. R. Tryon, F. M.
Armstrong, and M. R. Reiter.
Statistical failure analysis of system timing.
IBM Journal of Research and Development, 28(4):340-355, July 1984.
- [4301]
- Y-F. Tsai,
D. Duarte, N. Vijaykrishnan, and M. J. Irwin.
Implications of technology scaling on leakage reduction techniques.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
187-190, Anaheim, CA, June 2-6 2003.
- [4302]
- J.-L. Tsai,
D. Baik, C. C.-P. Chen, and K. K. Saluja.
A yield improvement methodology using pre- and post-silicon statistical clock
scheduling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 611-618, San Jose, CA, November 7-11 2004.
- [4303]
- Y.-F. Tsai,
D. Duarte, N. Vijaykrishnan, and M. J. Irwin.
Impact of process scaling on the efficacy of leakage reduction schemes.
In International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 3-11, Austin, TX, May 17-20 2004.
- [4304]
- Y.-F. Tsai, D. E.
Duarte, N. Vijaykrishnan, and M. J. Irwin.
Characterization and modeling of run-time techniques for leakage power
reduction.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(11):1221-1233, November 2004.
- [4305]
- J.-L. Tsai,
L. Zhang, and C. C.-P. Chen.
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 575-581, San Jose, CA, November 6-10 2005.
- [4306]
- K.-L. Tsai, S.-J.
Ruan, L.-W. Chen, F. Lai, and E. Naroska.
Low power dynamic bus encoding for deep sub micron design.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 159-162, Quebec City, Quebec, June 19-22 2005.
- [4307]
- M.-C. Tsai,
D. Zhang, and Z. Tang.
Modeling litho-constrained design layout.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
354-357, San Diego, CA, June 4-8 2007.
- [4308]
- M.-H. Tsai, W.-S.
Ding, H.-Y. Hsieh, and J.-C.-M. Li.
Transient IR-drop anaylsis for at-speed testing using representative random
walk.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(9):1980-1989, September 2014.
- [4309]
- S. Tsai and C.-Y. (Ric)
Huang.
A false-path aware formal static timing analyzer considering simultaneous input
transitions.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 25-30,
San Francisco, CA, July 26-31 2009.
- [4310]
- C.-H. Tsai and S.-M. Kang.
Fast temperature calculation for transient electrothermal simulation by mixed
frequency/time domain thermal power model reduction.
In Design Automation Conference, pages 750-755, Los Angeles, CA, June
5-9 2000.
- [4311]
- C.-H. Tsai and W.-K. Mak.
A fast parallel approach for common path pessimism removal.
In 20th Asia and South Pacific Design Automation Conference, pages
372-377, Chiba/Tokyo, Japan, January 19-22 2015.
- [4312]
- R-S Tsay.
An exact zero-skew clock routing algorithm.
IEEE Transactions on Computer-Aided Design, 12(2):242-249, February
1993.
- [4313]
- J. Tschanz,
S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De.
Comparative delay and energy of single edge-triggered & dual edge-triggered
pulsed flip-flops for high-performance microprocessors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 147-152, Huntington Beach, California, August 6-7
2001.
- [4314]
- J. Tschanz,
K. Bowman, and V. Le.
Variation-tolerant circuits: circuit solutions and techniques.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
762-763, Anaheim, CA, June 13-17 2005.
- [4315]
- J. Tschanz,
K. Bowman, C. Wilkerson, S.-L. Lu, and T. Karnik.
Resilient circuits - enabling energy-efficient performance and reliability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 71-73, San Jose, CA, November 2-5 2009.
- [4316]
- K. Tseng and
M. Horowitz.
False coupling exploration in timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(11):1795-1805, November 2005.
- [4317]
- K. Tseng and V. Kariat.
Static noise analysis with noise windows.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
864-868, Anaheim, CA, June 2-6 2003.
- [4318]
- Y. P. Tsividis.
Operation and Modeling of the MOS Transistor.
McGraw-Hill, 1987.
- [4319]
- C-Y Tsui,
M. Pedram, and A. M. Despain.
Efficient estimation of dynamic power consumption under a real delay model.
In IEEE International Conference on Computer-Aided Design, pages
224-228, Santa Clara, CA, November 7-11 1993.
- [4320]
- C-Y Tsui,
M. Pedram, and A. M. Despain.
Technology decomposition and mapping targeting low power dissipation.
In 30th ACM/IEEE Design Automation Conference, pages 68-73, Dallas,
TX, June 14-18 1993.
- [4321]
- C-Y. Tsui,
M. Pedram, C-A. Chen, and A. M. Despain.
Low power state assignment targeting two- and multi-level logic
implementations.
In IEEE/ACM International Conference on Computer-Aided Design, pages
82-87, San Jose, CA, November 6-10 1994.
- [4322]
- C-Y Tsui,
M. Pedram, and A. M. Despain.
Exact and approximate methods for calculating signal and transition
probabilities in fsms.
In 31st ACM/IEEE Design Automation Conference, pages 18-23, San
Diego, CA, June 6-10 1994.
- [4323]
- C-Y. Tsui,
M. Pedram, and A. M. Despain.
Power efficient technology decomposition and mapping under an extended power
consumption model.
IEEE Transactions on Computer-Aided Design, 13(9):1110-1122,
September 1994.
- [4324]
- C-Y Tsui,
J. Monteiro, M. Pedram, S. Devadas, A. M. Despain, and B. Lin.
Power estimation methods for sequential logic circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
3(3):404-416, September 1995.
- [4325]
- C-Y. Tsui,
R. Marculescu, D. Marculescu, and M. Pedram.
Improving the efficiency of power simulators by input vector compaction.
In 33rd Design Automation Conference, pages 165-168, Las Vegas, NV,
June 3-7 1996.
- [4326]
- C-Y Tsui, K-K Chan,
Q. Wu, C-S Ding, and M. Pedram.
A power estimation framework for designing low power portable video
applications.
In 34th Design Automation Conference, pages 421-424, Anaheim, CA,
June 9-13 1997.
- [4327]
- C.-Y. Tsui,
M. Pedram, and A. M. Despain.
Low-power state assignment targeting two- and multilevel logic implementations.
IEEE Transactions on Computer-Aided Design, 17(12):1281-1291,
December 1998.
- [4328]
- Y. Tsukamoto, K. Nii, S. Imaoka, Y. Oda, S. Ohbayashi,
T. Yoshizawa, H. Makino, K. Ishibashi, and H. Shinohara.
Worst-case analysis to obtain stable read/write DC margin of high density
6t-SRAM-array with local vth variability.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 398-405, San Jose, CA, November 6-10 2005.
- [4329]
- R. H. Tu, E. Rosenbaum,
W. Y. Chan, C. C. Li, E. Minami, K. Quader, P. K. Ko, and C. Hu.
Berkeley reliability tools - BERT.
IEEE Transactions on Computer-Aided Design, 12(10):1524-1534, October
1993.
- [4330]
- S.-W. Tu, Y.-W. Chang,
and J.-Y. Jou.
RLC coupling-aware simulation and on-chip bus encoding for delay reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2258-2275, October 2006.
- [4331]
- W.-P Tu, C.-H Chou,
S.-H. Huang, S.-C. Chang, Y.-T. Nieh, and C.-Y. Chou.
Low-power timing closure methodology for ultra-low voltage designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 697-704, San Jose, CA, November 18-21 2013.
- [4332]
- T. Tuan, A. Rahman,
S. Das, S. Trimberger, and S. Kao.
A 90-nm low-power FPGA for battery-powered applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(2):296-300, February 2007.
- [4333]
- E. Tuncer,
J. Cortadella, and L. Lavagno.
Enabling adaptability through elastic clocks.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 8-10,
San Francisco, CA, July 26-31 2009.
- [4334]
- S. Turgis,
N. Azemard, and D. Auvergne.
Explicit evaluation of short circuit power dissipation for CMOS logic
structures.
In ACM/IEEE International Symposium on Low Power Design, pages
129-134, Dana Point, CA, April 23-26 1995.
- [4335]
- S. Turgis and
D. Auvergne.
A novel macromodel for power estimation in CMOS structures.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 17(11):1090-1098, November 1998.
- [4336]
- B. Tutuianu,
F. Dartu, and L. Pileggi.
An explicit RC-circuit delay approximation based on the first three moments
of the impulse response.
In 33rd Design Automation Conference, pages 611-616, Las Vegas, NV,
June 3-7 1996.
- [4337]
- B. Tutuianu,
R. Baldick, and M. S. Johnstone.
Nonlinear driver models for timing and noise analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(11):1510-1521, November 2004.
- [4338]
- S. Tuuna,
J. Isoaho, and H. Tenhunen.
Analytical model for crosstalk and intersymbol interference in point-to-point
buses.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1400-1411, July 2006.
- [4339]
- S. Tuuna, L.-R.
Zheng, J. Isoaho, and H. Tenhunen.
Modeling of on-chip bus switching current and its impact on noise in power
supply grid.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(6):766-774, June 2008.
- [4340]
- S. Tuuna,
E. Nigussie, J. Isoaho, and H. Tenhunen.
Modelling of energy dissipation in RLC current-model signaling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(6):1146-1155, June 2012.
- [4341]
- A. Tyagi.
Hercules: a power analyzer for MOS VLSI circuits.
In IEEE International Conference on Computer-Aided Design, pages
530-533, Nov. 9-12 1987.
- [4342]
- A. Tyagi.
VLSI design parsing.
In IEEE/ACM International Conference on Computer-Aided Design, pages
30-34, Santa Clara, CA, November 8-12 1992.
- [4343]
- A. Tyagi.
Entropic bounds on FSM switching.
In International Symposium on Low Power Electronics and Design, pages
323-328, Monterey, CA, August 12-14 1996.
- [4344]
- A. Tyagi.
Entropic bounds on FSM switching.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
5(4):456-464, December 1997.
- [4345]
- K. Uchida.
Single-electron devices for ubiquitous and secure computing applications.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
301-303, San Francisco, CA, July 26-31 2009.
- [4346]
- T. Uchino,
F. Minami, T. Mitsuhashi, and N. Goto.
Switching activity analysis using boolean approximation method.
In IEEE/ACM International Conference on Computer-Aided Design, pages
20-25, San Jose, CA, November 5-9 1995.
- [4347]
- T. Uchino,
F. Minami, M. Murakata, and T. Mitsuhashi.
Switching activity analysis for sequential circuits using boolean approximation
method.
In International Symposium on Low Power Electronics and Design, pages
79-84, Monterey, CA, August 12-14 1996.
- [4348]
- T. Uchino and J. Cong.
An interconnect energy model considering coupling effects.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
555-558, Las Vegas, NV, June 18-22 2001.
- [4349]
- T. Uchino and J. Cong.
An interconnect energy model considering coupling effects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(7):763-776, July 2002.
- [4350]
- I. Ukhov, Z. Peng,
M. Bao, and P. Eles.
Steady-state dynamic temperature analysis and reliability optimization for
embedded multiprocessor systems.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
197-204, San Francisco, CA, June 3-7 2012.
- [4351]
- I. Ukhov, P. Eles,
and Z. Peng.
Probabilistic analysis of power and temperature under process variation for
electronic system design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(6):931-944, June 2014.
- [4352]
- I. Ukhov, P. Eles,
and Z. Peng.
Temperature-centric reliability analysis and optimization of electronic systems
under process variation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(11):2417-2430, November 2015.
- [4353]
- I. Ukhov, P. Eles,
and Z. Peng.
Probabilistic analysis of electronic systems via adaptive hierarchical
interpolation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(11):1883-1896, November 2017.
- [4354]
- F. Fatz ul Hassan, W. Vanderbanwhede, and F. Rodriguez-Salazar.
Impact of random dopant flucatuations on the timing characteristics of
flip-flops.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(1):157-161, January 2012.
- [4355]
- M. S. Ullah and M. H.
Chowdhury.
Analytical models of high-speed RLC interconnect delay for complex and real
poles.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(6):1831-1841, June 2017.
- [4356]
- J. Um and T. Kim.
Synthesis of arithmetic circuits considering layout effects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(11):1487-1503, November 2003.
- [4357]
- C. Umans,
T. Villa, and A. L. Sangiovanni-Vincentelli.
Complexity of two-level logic minimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1230-1246, July 2006.
- [4358]
- P. Urard,
A. Maalej, R. Guizzetti, and N. Chawla.
Leveraging sequential equivalence checking to enable system-level to RTL
flows.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
816-821, Anaheim, CA, June 8-13 2008.
- [4359]
- K. Usami,
K. Nogami, M. Igarashi, F. Minami, Y. Kawasaki, T. Ishikawa, M. Kanazawa,
T. Aoki, M. Takano, C. Mizuno, M. Ichida, S. Sonoda, M. Takahashi, and
N. Hatanaka.
Automated low-power technique exploiting multiple supply voltages applied to a
media processor.
In IEEE 1997 Custom Integrated Circuits Conference, pages 131-134,
Santa Clara, CA, May 5-8 1997.
- [4360]
- K. Usami,
N. Kawabe, M. Koizumi, K. Seta, and T. Furusawa.
Automated selected multi-threshold design for ultra-low standby applications.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 202-206, Monterey, California, August 12-14 2002.
- [4361]
- K. Usami and
M. Horowitz.
Clustered voltage scaling technique for low-power design.
In ACM/IEEE International Symposium on Low Power Design, pages 3-8,
Dana Point, CA, April 23-26 1995.
- [4362]
- M. Vadizadeh, M. Fathipour, and A. Amid.
A novel nanoscale tunnel FET structure for increasing on/off current ratio.
In IEEE 20th International Conference on Microelectronics (ICM), pages
344-347, Sharjah, UAE, December 14-17 2008.
- [4363]
- K. Vaidyanathan, L. Liebmann, A. Strojwas, and L. Pileggi.
Sub-20 nm design technology co-optimization for standard cell logic.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 124-131, San Jose, CA, November 2-6 2014.
- [4364]
- A. Valentian, O. Thomas, A. Vladimirescu, and A. Amara.
Modeling subthreshold SOI logic for static timing analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(6):662-670, June 2004.
- [4365]
- L. G. Valiant.
The complexity of enumeration and reliability problems.
SIAM Journal on Computing, 8(3):410-421, August 1979.
- [4366]
- J. P. A. van der Wagt.
Tunneling-based SRAM.
In Proceedings of the IEEE, pages 571-595, April 1999.
- [4367]
- A. J.
van Genderen and N. P. van der Meijs.
Extracting simple but accurate RC models for VLSI interconnect.
In IEEE International Conference on Circuits and Systems, pages
2351-2354, 1988.
- [4368]
- M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels, and
I. Bolsens.
High-level simulation of substrate noise generation including power supply
noise coupling.
In Design Automation Conference, pages 446-451, Los Angeles, CA, June
5-9 2000.
- [4369]
- V. M. van
Santen, H. Amrouch, J. Martin-Martinez, M. Nafria, and J. Henkel.
Designing guardbands for instantaneous aging effects.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [4370]
- A. Vandecappelle, M Miranda, E. Brockmeyer, F. Catthoor, and
D. Verkest.
Global multimedia system design exploration using accurate memory organization
feedback.
In Design Automation Conference, pages 327-332, New Orleans, LA, June
21-25 1999.
- [4371]
- L. Vandenberghe, S. Boyd, and A. El Gamal.
Optimizing dominant time constant in RC circuits.
IEEE Transactions on Computer-Aided Design of Circuits and Systems,
17(2):110-125, February 1998.
- [4372]
- J. R.
Vanderhaegen and R. W. Brodersen.
Automated design of operational transconductance amplifiers using reversed
geometric programming.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
133-138, San Diego, CA, June 7-11 2004.
- [4373]
- P. Vanoostende, P. Six, and H. J. DeMan.
DARSI: RC data reduction.
IEEE Transactions on Computer-Aided Design, 10(4):493-500, April
1991.
- [4374]
- P. Vanoostende, P. Six, and H. J. De Man.
PRITI: Estimation of maximal currents and current derivatives in complex
CMOS circuits using activity waveforms.
In European Design Automation Conference (EDAC), pages 347-353,
1993.
- [4375]
- B. K. S.
V. L. Varaprasad, L. M. Patnaik, H. S. Jamadagni, and V. K. Agrawal.
A new ATPG technique (expotan) for testing analog circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):189-196, January 2007.
- [4376]
- G. V.
Varatkar, S. Narayanan, N. R. Shanbhag, and D. L. Jones.
Stochastic networked computation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(10):1421-1432, October 2010.
- [4377]
- G. V. Varatkar
and N. R. Shanbhag.
Energy-efficient motion estimation using error-tolerance.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 113-118, Tegernsee, Germany, October 4-6 2006.
- [4378]
- Richard S. Varga.
Matrix Iterative Analysis.
Prentice-Hall, Englewood Cliffs, NJ, 1962.
- [4379]
- A. Varma,
B. Bowhill, J. Crop, C. Gough, B. Griffith, D. Kingsley, and K. Sistla.
Power management in the intel xeon e5 v3.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 371-376, Rome, Italy, July 22-24 2015.
- [4380]
- V. Vashishtha, M. Vangala, and L. T. Clark.
Asap7 predictive design kit development and cell design technology
co-optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 978-984, Irvine CA, November 13-16 2017.
- [4381]
- D. Vasilyev and
J. White.
A more reliable reduction algorithm for behavioral model extraction.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 813-820, San Jose, CA, November 6-10 2005.
- [4382]
- A. Vassighi,
A. Kashavarzi, S. Narendra, G. Schrom, Y. Ye, S. Lee, G. Chrysler,
M. Sachdev, and V. De.
Design optimizations for microprocessors at low temperature.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 2-5,
San Diego, CA, June 7-11 2004.
- [4383]
- H. J. M. Veendrick.
Short-circuit dissipation of static CMOS circuitry and its impact on the
design of buffer circuits.
IEEE Journal of Solid-State Circuits, SC-19(4):468-473, August
1984.
- [4384]
- V. Veeramachaneni, A. Tyagi, and S. Rajgopal.
Re-encoding for low power state assignment of fsms.
In ACM/IEEE International Symposium on Low Power Design, pages
173-178, Dana Point, CA, April 23-26 1995.
- [4385]
- V. Veetil,
D. Sylvester, and D. Blaauw.
Critically aware latin hypercube sampling for efficient statistical timing
analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 24-30, Austin, Texas,
February 26-27 2007.
- [4386]
- V. Veetil,
D. Sylvester, and D. Blaauw.
Fast and accurate waveform analysis with current source models.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 73-79, Austin, Texas,
February 26-27 2007.
- [4387]
- V. Veetil,
D. Sylvester, and D. Blaauw.
Efficient monte carlo based incremental statistical timing analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 7-13, Monterey, CA,
February 25-26 2008.
- [4388]
- V. Veetil,
D. Sylvester, and D. Blaauw.
Efficient monte carlo based incremental statistical timing analysis.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
676-681, Anaheim, CA, June 8-13 2008.
- [4389]
- V. Veetil,
D. Sylvester, D. Blaauw, S. Shah, and S. Rochel.
Efficient smart sampling based full-chip leakage analysis for intra-die
variation considering state dependence.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
154-159, San Francisco, CA, July 26-31 2009.
- [4390]
- V. Veetil,
Y.-H. Chang, D. Sylvester, and D. Blaauw.
Efficient smart monte carlo based SSTA on graphics processing units with
improved resource utilization.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
793-798, Anaheim, CA, June 13-18 2010.
- [4391]
- V. Veetil,
D. Sylvester, and D. Blaauw.
A lower bound computation method for evaluation of statistical design
techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 562-569, San Jose, CA, November 7-11 2010.
- [4392]
- F. Veirano,
L. Naviner, and F. Silveira.
Optimum nmos/pmos imbalance for energy efficient digital circuits.
IEEE Transactions on Circuits and Systems I: Regular Papers,
64(12):3081-3091, December 2017.
- [4393]
- J. B.
Velamala, V. Ravi, and Y. Cao.
Failure diagnosis of asymmetric aging under NBTI.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 428-433, San Jose, CA, November 7-10 2011.
- [4394]
- J. B.
Velamala, K. Sutaria, T. Sato, and Y. Cao.
Physics matters: statistical aging prediction under trapping/detrapping.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
139-144, San Francisco, CA, June 3-7 2012.
- [4395]
- S. R. Vemuru and
N. Scheinberg.
Short-circuit power dissipation estimation for CMOS logic gates.
IEEE Transactions on Circuits and Systems - I, 41(11):762-765,
November 1994.
- [4396]
- J. D. Venables and
R. G. Lye.
A statistical model for electromigration induced failure in thin film
conductors.
In Proc. 10th Annual IEEE Reliability Physics Symposium, pages
159-164, Las Vegas, Nevada, April 5-7 1972.
- [4397]
- A. Veneris and M. S.
Abadir.
Design rewiring using ATPG.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(12):1469-1479, December 2002.
- [4398]
- A. Veneris and I. N.
Hajj.
Design error diagnosis and correction via test vector generation.
IEEE Transactions on Computer-Aided Design, 18(12):1803-1816,
December 1999.
- [4399]
- A. Veneris and
S. Safarpour.
The day sherlock holmes decided to do EDA.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
631-634, San Francisco, CA, July 26-31 2009.
- [4400]
- S. Venkatachalam and S.-B. Ko.
Design of power and area efficient approximate multipliers.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(5):1782-1786, May 2017.
- [4401]
- G. Venkataraman, K. Jayakumar, J. Hu, P. Li, S. Khatri,
A. Rajaram, P. McGuinness, and C. Alpert.
Practical techniques to reduce skew and its variations in buffered clock
networks.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 592-596, San Jose, CA, November 6-10 2005.
- [4402]
- R. Venkatesan, J. A. Davis, and J. D. Meindl.
A physical model for the transient response of capactively loaded distributed
rlc interconnects.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
763-766, New Orleans, LA, June 10-14 2002.
- [4403]
- R. Venkatesan, A. Agarwal, K. Roy, and A. Raghunathan.
Implementation of pulsed-latch and pulsed-register circuits to minimize
clocking power.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 667-673, San Jose, CA, November 7-10 2011.
- [4404]
- D. Vercruyce, D. Vansteenkiste, and D. Stroobandt.
How preserving circuit design hierarchy during FPGA packing leads to better
performance.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 37(3):629-642, March 2018.
- [4405]
- N. K.
Verghese, D. J. Allstot, and M. A. Wolfe.
Fast parasitic extraction for substrate coupling in mixed-signal ics.
In IEEE Custom Integrated Circuits Conference, pages 121-124, Santa
Clara, CA, May 1-4 1995.
- [4406]
- B. Victor and
K. Keutzer.
Bus encoding to prevent crosstalk delay.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 57-63, San Jose, CA, November 4-8 2001.
- [4407]
- T. Villa, T. Kam,
R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
Explicit and implicit algorithms for binate covering problem.
IEEE Transactions on Computer-Aided Design, 16(7):677-691, July
1997.
- [4408]
- C. De
Villemagne and R. E. Skelton.
Model reductions using a projection formulation.
International Journal of Control, 46(6):2141-2169, 1987.
- [4409]
- J. F. Villena and
L. M. Silveira.
3por - parallel projection based parameterized order reduction for
multi-dimensional linear models.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 536-542, San Jose, CA, November 7-11 2010.
- [4410]
- J. F. Villena and
L. M. Silveira.
SPARE - a scalable algorithm for passive, structure preserving,
parameter-aware model order reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(6):925-938, June 2010.
- [4411]
- J. F. Villena and
L. M. Silveira.
Multi-dimensinoal automatic sampling schemes for multi-point modeling
methodologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(8):1141-1151, August 2011.
- [4412]
- J. F. Villena and
L. M. Silveira.
Exploiting parallelism for improved automation of multidimensional model order
reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(1):37-49, January 2012.
- [4413]
- J. Viraraghavan, S. J. Pandharpure, and J. Watts.
Statistical compact model extraction: a neural network approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(12):1920-1929, December 2012.
- [4414]
- C. Visweswariah, R. A. Haring, and A. R. Conn.
Noise considerations in circuit optimization.
IEEE Transactions on Computer-Aided Design, 19(6):679-690, June
2000.
- [4415]
- C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Waler, and
S. Narayan.
First-order incremental block-based statistical timing analysis.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
331-336, San Diego, CA, June 7-11 2004.
- [4416]
- C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker,
S. Narayan, D. K. Beece, J. Piaget, N. Venkateswaran, and J. G. Hemmett.
First-order incremental block-based statistical timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2170-2180, October 2006.
- [4417]
- C. Visweswariah and A. R. Conn.
Formulation of static circuit optimization with reduced size, degeneracy, and
redundancy by timing graph manipulation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
244-251, San Jose, CA, November 7-11 1999.
- [4418]
- C. Visweswariah and R. Rohrer.
Piecewise approximate circuit simulation.
In IEEE International Conference on Computer-Aided Design, pages
248-251, 1989.
- [4419]
- C. Visweswariah.
Optimization techniques for high-performance digital circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
198-205, San Jose, CA, November 9-13 1997.
- [4420]
- C. Visweswariah.
Death, taxes and failing chips.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
343-347, Anaheim, CA, June 2-6 2003.
- [4421]
- A. Vittal, L. H.
Chen, M. Marek-Sadowska, K.-P. Wang, and S. Yang.
Crosstalk in VLSI interconnections.
IEEE Transactions on Computer-Aided Design, 18(12):1817-1824,
December 1999.
- [4422]
- A. Vittal and
M. Marek-Sadowska.
Crosstalk reduction for VLSI.
IEEE Transactions on Computer-Aided Design, 16(3):290-298, March
1997.
- [4423]
- A. Vittal and
M. Marek-Sadowska.
Low-power buffered clock tree design.
IEEE Transactions on Computer-Aided Design, 16(9):965-975, September
1997.
- [4424]
- J. Vlach, J. A.
Barby, A. Vannelli, T. Talkhan, and C.-J. R. Shi.
Group delay as an estimate of delay in logic.
IEEE Transactions on Computer-Aided Design, 10(7):949-953, July
1991.
- [4425]
- A. Vladimirescu, Y. Cao, O. Thomas, H. Qin, D. Markovic,
A. Valentian, R. Ionita, J. Rabaey, and A. Amara.
Ultra-low-voltage robust design issues in deep-submicron CMOS.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 49-52, Montreal, Quebec, June 20-23 2004.
- [4426]
- D. Vo.
Automated SPICE characterization of gate array and standard cell libraries.
In IEEE Custom Integrated Circuits Conference (CICC), pages 363-366,
1987.
- [4427]
- C. Voigt.
Gene and cellular circuit design.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
115-115, San Diego, CA, June 5-9 2011.
- [4428]
- L. von Ahn.
Human computation.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
418-419, San Francisco, CA, July 26-31 2009.
- [4429]
- S. B. K.
Vrudhula, D. Blaauw, and S. Sirichotiyakul.
Estimation of the likelihood of capacitive coupling noise.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
653-658, New Orleans, LA, June 10-14 2002.
- [4430]
- S. Vrudhula,
D. T. Blaauw, and S. Sirichotiyakul.
Probabilistic analysis of interconnect coupling noise.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(9):1188-1203, September 2003.
- [4431]
- S. Vrudhula,
J.-M. Wang, and P. Ghanta.
Hermite polynomial based interconnect analysis in the presence of process
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2001-2011, October 2006.
- [4432]
- S. B. K. Vrudhula and
H-Y. Xie.
Techniques for CMOS power estimation and logic synthesis for low power.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
21-26, Napa, CA, April 24-27 1994.
- [4433]
- L. Vu-Quoc,
Y. Zhai, and K.-D.-T. Ngo.
Efficient simulation of coupled circuit-field problems: generalized falk
method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1209-1219, August 2004.
- [4434]
- P. Vuillod,
L. Benini, A. Bogliolo, and G. De Micheli.
Clock-skew optimization for peak current reduction.
In International Symposium on Low Power Electronics and Design, pages
265-270, Monterey, CA, August 12-14 1996.
- [4435]
- P. Vuillod,
L. Benini, and G. De Micheli.
Re-mapping for low power under tight timing constraints.
In 1997 International Symposium on Low Power Electronics and Design,
pages 287-292, Monterey, CA, August 18-20 1997.
- [4436]
- M. Vujkovic,
D. Wadkins, B. Swartz, and C. Sechen.
Efficient timing closure without timing driven placement and routing.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
268-273, San Diego, CA, June 7-11 2004.
- [4437]
- M. Vujkovic and
C. Sechen.
Optimized power-delay curve generation for standard cell ics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 387-394, San Jose, CA, November 10-14 2002.
- [4438]
- J. Vygen.
Slack in static timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1876-1885, September 2006.
- [4439]
- I. Vytyaz, P. K.
Hanumolu, U.-K. Moon, and K. Mayaram.
Design-oriented analysis of circuits with equality constraints.
IEEE Transactions on Circuits and Systems, 58(5):1089-1098, May
2011.
- [4440]
- S. A. Wadekar and
A. C. Parker.
Interconnect-based system-level energy and power prediction to guide
architecture exploration.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):373-380, April 2004.
- [4441]
- R. L. Wadsack.
Fault coverage in digital integrated circuits.
The Bell System Technical Journal, 57(5):1475-1488, May-June 1978.
- [4442]
- R. L. Wadsack.
Fault modeling and logic simulation of CMOS and MOS integrated circuits.
The Bell System Technical Journal, 57(5):1449-1474, May-June 1978.
- [4443]
- I. Wagner,
V. Bertacco, and T. Austin.
Shielding against design flaws with field repairable control logic.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
344-347, San Francisco, CA, July 24-28 2006.
- [4444]
- I. Wagner,
V. Bertacco, and T. Austin.
Using field-programmable control logic to correct design errors in
microprocessors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):380-393, February 2008.
- [4445]
- K. D. Wagner.
Clock system design.
IEEE Design & Test of Computers, 5(5):9-27, October 1988.
- [4446]
- M. Wainberg and
V. Betz.
Robust optimization of multiple timing constraints.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(12):1942-1953, December 2015.
- [4447]
- K. Wakabayashi and T. Okamoto.
C-based SOC design flow and EDA tools: An ASIC and system vendor
perspective.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1507-1522, December 2000.
- [4448]
- M. J. Walker,
S. Diestelhorst, A. Hansson, A. K. Das, S. Yang, B. M. Al-Hashimi, and G. V.
Merrett.
Accurate and stable run-time power modeling for mobile and embedded cpus.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(1):106-119, January 2017.
- [4449]
- D. E. Wallace
and M. S. Chandrasekhar.
High-level delay estimation for technology-independent logic equations.
In IEEE International Conference on Computer-Aided Design, pages
188-191, Santa Clara, CA, November 11-15 1990.
- [4450]
- D. E. Wallace and
C. H. Sequin.
Plug-in timing models for an abstract timing verifier.
In 23rd ACM/IEEE Design Automation Conference, pages 683-689, Las
Vegas, NV, June 29 - July 2 1986.
- [4451]
- R. E. Walpole,
R. H. Myers, and S. L. Myers.
Probability and Statistics for Engineers and Scientists.
Prentice Hall International, Inc., Upper Saddle River, NJ, 6th edition,
1998.
- [4452]
- L. Wan and D. Chen.
Analysis of circuit dynamic behavior with timed ternary decision diagram.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 516-523, San Jose, CA, November 7-11 2010.
- [4453]
- L. Wan and D. Chen.
Analysis of digital circuit dynamic behavior with timed ternary decision
diagrams for better-than-worst-case design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(5):662-675, May 2012.
- [4454]
- S. Wane and A.-Y. Kuo.
Chip-package co-design methodology for global co-simulation of re-distribution
layers (RDL).
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 59-62, San Jose, CA, October 27-29 2008.
- [4455]
- H. Wang, H. De, and
R. Lahri.
Improving hot-electron reliability through circuit analysis and design.
In IEEE 29th Annual International Reliability Physics Symposium, pages
107-111, Las Vegas, NV, April 9-11 1991.
- [4456]
- C-Y. Wang, K. Roy,
and T-L. Chou.
Maximum power estimation for sequential circuits using a test generation based
technique.
In IEEE 1996 Custom Integrated Circuits Conference, pages 229-232,
San Diego, CA, May 5-8 1996.
- [4457]
- Q. Wang, S. B. K.
Vrudhula, and S. Ganguly.
An investigation of power delay trade-offs on powerpc circuits.
In 34th Design Automation Conference, pages 425-428, Anaheim, CA,
June 9-13 1997.
- [4458]
- J. M. Wang, E. S.
Kuh, and Q. Yu.
The chebyshev expansion based passive model for distributed interconnect
networks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
370-375, San Jose, CA, November 7-11 1999.
- [4459]
- M. Wang, X. Yang,
and M. Sarrafzadeh.
Dragon2000: Standard-cell placement tool for large industry circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 260-263, San Jose, CA, November 5-9 2000.
- [4460]
- W. Wang,
A. Raghunathan, G. Lakshminarayana, and N. K. Jha.
Input space adaptive design: A high-level methodology for energy and
performance optimization.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
738-743, Las Vegas, NV, June 18-22 2001.
- [4461]
- C.-Y. Wang, S.-W.
Tung, and J.-Y. Jou.
An automorphic approach to verification pattern generation for soc design
verification using port-order fault model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(10):1225-1232, October 2002.
- [4462]
- J. M. Wang,
C. Chu, Q. Yu, and E. S. Kuh.
On projection-based algorithms for model-order reduction of interconnects.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(11):1563-1585, November 2002.
- [4463]
- C.-C. Wang, Y.-H.
Hsueh, and Y.-P. Chen.
An area-saving decoder structure for roms.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):581-589, August 2003.
- [4464]
- J. Wang,
P. Ghanta, and S. Vrudhula.
Stochastic analysis of interconnect performance in the presence of process
variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 880-886, San Jose, CA, November 7-11 2004.
- [4465]
- J. Wang, K. K.
Muchheria, and J. G. Kumar.
A clustering based area I/O planning for flip-chip technology.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 196-204, San Jose, CA, March 22-24 2004.
- [4466]
- J.-M. Wang, O. A.
Hafiz, and J. Li.
A linear fractional transform (LFT) based model for interconnect parametric
uncertainty.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
375-380, San Diego, CA, June 7-11 2004.
- [4467]
- P. Wang, G. Pei,
and E. C.-C. Kan.
Pulsed wave interconnect.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):453-463, May 2004.
- [4468]
- W. Wang,
A. Raghunathan, G. Lakshminarayana, and N. K. Jha.
Input space adaptive design: a high-level methodology for optimizing energy and
performance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(6):590-602, June 2004.
- [4469]
- C.-C. Wang, Y.-L.
Tseng, and C.-C. Chiu.
A temperature-insensitive self-recharging circuitry used in drams.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):405-409, March 2005.
- [4470]
- H. Wang,
M. Miranda, A. Papanikolaou, F. Catthoor, and W. Dehaene.
Variable tapered pareto buffer design and implementation allowing run-time
configuration for low-power embedded srams.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(10):1127-1135, October 2005.
- [4471]
- J.-M. Wang,
B. Srinivas, D. Ma, C. C.-P. Chen, and J. Li.
System-level power and thermal modeling and analysis by orthogonal polynomial
based response surface approach (OPRS).
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 728-735, San Jose, CA, November 6-10 2005.
- [4472]
- X. Wang,
M. Ottavi, F. J. Meyer, and F. Lombardi.
Estimating the manufacturing yield of compiler-based embedded srams.
IEEE Transactions on Semiconductor Manufacturing, 18(3):412-421,
August 2005.
- [4473]
- Z. Wang, R. Murgai,
and J. Roychowdhury.
ADAMIN: automated, accurate macromodeing of digital aggressors for power and
ground supply noise prediction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):56-64, January 2005.
- [4474]
- G. Wang, W. Gong,
and R. Kastner.
On the use of bloom filters for defect maps in nanocomputing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 743-746, San Jose, CA, November 5-9 2006.
- [4475]
- G. Wang,
S. Sivaswamy, C. Ababei, K. Bazargan, R. Kastner, and E. Bozorgzadeh.
Statistical analysis and design of HARP fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2088-2102, October 2006.
- [4476]
- H.-G. Wang, C.-H.
Chan, L. Tsang, and V. Jandhyala.
On sampling algorithms in multilevel QR factorization method for
magnetoquasistatic analysis of integrated circuits over multilayered lossy
substrates.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1777-1792, September 2006.
- [4477]
- J.-M. Wang, J. Li,
S. Yanamanamanda, L. K. Vakati, and K. K. Muchherla.
Modeling the driver load in the presence of process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2264-2275, October 2006.
- [4478]
- W.-S. Wang,
V. Kreinovich, and M. Orshansky.
Statistical timing based on incomplete probabilistic descriptions of parameter
uncertainty.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
161-166, San Francisco, CA, July 24-28 2006.
- [4479]
- X. Wang,
J. Kanapka, W. Ye, N. R. Aluru, and J. White.
Algorithms in faststokes and its application to micromachined device
simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(2):248-257, February 2006.
- [4480]
- F. Wang, Y. Xie,
and H. Yu.
A novel criticality computation method in statistical timing analysis.
Design, Automation and Test in Europe (DATE-07), pages 1611-1616,
April 16-20 2007.
- [4481]
- J. Wang, D. Das,
and H. Zhou.
Gate sizing by lagrangian relaxation revisited.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 111-118, San Jose, CA, November 5-8 2007.
- [4482]
- L.-C. Wang,
P. Bastani, and M. S. Abadir.
Design-silicon timing correlation - a data mining perspective.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
384-389, San Diego, CA, June 4-8 2007.
- [4483]
- W. Wang, Z. Wei,
S. Yang, and Y. Cao.
An efficient method to identify critical gates under circuit aging.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 735-740, San Jose, CA, November 5-8 2007.
- [4484]
- W. Wang, S. Yang,
S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, and Y. Cao.
The impact of NBTI on the performance of combinational and sequential
circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
364-369, San Diego, CA, June 4-8 2007.
- [4485]
- Y. Wang, H. Luo,
K. He, R. Luo, H. Yang, and Y. Xie.
Temperature-aware NBTI modeling and the impact of input vector control on
performance degradation.
Design, Automation and Test in Europe (DATE-07), pages 546-551, April
16-20 2007.
- [4486]
- X. Wang,
M. Tehranipoor, and R. Datta.
Path-RO: a novel on-chip critical path delay measurement under process.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 640-646, San Jose, CA, November 10-13 2008.
- [4487]
- Y. Wang, W.-S.
Luk, X. Zeng, J. Tao, C. Yan, J. Tong, W. Cai, and J. Ni.
Timing yield driven clock skew scheduling considering non-gaussian
distributions of critical path delays.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
223-226, Anaheim, CA, June 8-13 2008.
- [4488]
- J. Wang, D. Das,
and H. Zhou.
Gate sizing by lagrangian relaxation revisited.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(7):1071-1084, July 2009.
- [4489]
- J. Wang,
S. Yaldiz, X. Li, and L. T. Pileggi.
SRAM parametric failure analysis.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
496-501, San Francisco, CA, July 26-31 2009.
- [4490]
- X. Wang, Y. Cai,
Q. Zhou, S. X.-D. Tan, and T. Eguia.
Decoupling capacitance efficient placement for reducing transient power supply
noise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 745-751, San Jose, CA, November 2-5 2009.
- [4491]
- W. Wang, S. Yang,
S. Bhardwaj, S. Vrudhula, F. Liu, and Y. Cao.
The impact of NBTI effect on combinational circuit: modeling, simulation, and
analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):173-183, February 2010.
- [4492]
- Y. Wang, Z. Zhang,
C.-K. Koh, G.-K.-H. Pang, and N. Wong.
PEDS: passivity enforcement for descriptor systems via hamiltonian-symplectic
matrix pencil perturbation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 800-807, San Jose, CA, November 7-11 2010.
- [4493]
- H. Wang, S.-X.-D.
Tan, G. Liao, R. Quintanilla, and A. Gupta.
Full-chip runtime error-tolerant thermal estimation and prediction for
practical thermal management.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 716-723, San Jose, CA, November 7-10 2011.
- [4494]
- J. Wang, X. Chen,
C. Liao, and S. Hu.
The approximation scheme for peak power driven voltage partitioning.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 736-741, San Jose, CA, November 7-10 2011.
- [4495]
- L. Wang,
M. Olbrich, E. Barke, T. Buchner, M. Buhler, and P. Panitz.
A theoretical probabilistic simulation framework for dynamic power estimation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 708-715, San Jose, CA, November 7-10 2011.
- [4496]
- J. Wang, X. Chen,
L. Liu, and S. Hu.
Fast approximation for peak power driven voltage partitioning in almost linear
time.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 698-704, San Jose, CA, November 5-8 2012.
- [4497]
- S. Wang, J. Chen,
and M. Tehranipoor.
Representative critical reliability paths for low-cost and accurate on-chip
aging evaluation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 736-741, San Jose, CA, November 5-8 2012.
- [4498]
- Y. Wang, X. Hu,
C.-K. Cheng, G.-K.-H. Pang, and N. Wong.
Corrigendum to "A realistic early-stage power grid verification algorithm
based on hierarchical constraints".
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(3):452-452, March 2012.
- [4499]
- Y. Wang, X. Hu,
C.-K. Cheng, G.-K.-H. Pang, and N. Wong.
A realistic early-stage power grid verification algorithm based on hierarchical
constraints.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(1):109-120, January 2012.
- [4500]
- Y. Wang, Z. Zhang,
C.-K. Koh, G. Shi, G.-K.-H. Pang, and N. Wong.
Passivity enforcement for descriptor systems via matrix pencil perturbation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):532-545, April 2012.
- [4501]
- X. Wang, W. Yueh,
D. B. Roy, S. Narasimhan, Y. Zheng, S. Mukhopadhyay, D. Mukhopadhyay, and
S. Bhunia.
Role of power grid in side channel attack and power-grid-aware secure design.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [4502]
- K. Wang, B. H.
Meyer, R. Zhang, M. Stan, and K. Skadron.
Walking pads: managing c4 placement for transient voltage noise minimization.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [4503]
- S. Wang,
F. Firouzi, F. Oboril, and M. B. Tahoori.
Stress-aware P/G TSV planning in 3d-ics.
In 20th Asia and South Pacific Design Automation Conference, pages
94-99, Chiba/Tokyo, Japan, January 19-22 2015.
- [4504]
- T. Wang, J. Liu,
C. Zhuo, and Y. Shi.
1-bit compressed sensing based framework for built-in resonance frequency
prediction using on-chip noise sensors.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 721-728, Austin, TX, November 2-6 2015.
- [4505]
- X. Wang, T. Wang,
T. Mak, M. Yang, Y. Jiang, and M. Daneshtalab.
Fine-grained runtime power budgeting for networks-on-chip.
In 20th Asia and South Pacific Design Automation Conference, pages
160-165, Chiba/Tokyo, Japan, January 19-22 2015.
- [4506]
- X. Wang, J. Xu,
Z. Wang, K. J. Chen, X. Wu, Z. Wang, P. Yang, and L. H. K. Duong.
An analytical study of power delivery systems for many-core processors using
on-chip and off-chip voltage regulators.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(9):1401-1414, September 2015.
- [4507]
- Y. Wang, M. Li,
X. Yi, Z. Song, M. Orshansky, and C. Caramanis.
Novel power grid reduction method based on l1 regularization.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4508]
- Y. Wang, S. Yao,
S. Tao, X. Chen, Y. Ma, Y. Shi, and H. Yang.
Hs3-DPG: hierarchical simulation for 3-D P/G network.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(10):2307-2311, October 2015.
- [4509]
- Y.-C. Wang,
S. Yin, M. Jun, X. Li, L. T. Pileggi, T. Mukherjee, and R. Negi.
Accurate passivity-enforced macromodeling for RF circuits via iterative
zero/pole update based on measurement data.
In 20th Asia and South Pacific Design Automation Conference, pages
441-446, Chiba/Tokyo, Japan, January 19-22 2015.
- [4510]
- J. Wang, N. Gong,
and E. G. Friedman.
PNS-FCR: flexible charge recycling dymanic circuit technique for low-power
microprocessors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(2):613-624, February 2016.
- [4511]
- J. Wang, J. Lu,
Y. Liu, X. Chu, and Y. Li.
Effective radii of on-chip decoupling capacitors under noise constraint.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(12):3415-3423, December 2016.
- [4512]
- X. Wang, H. Gu,
Y. Yang, K. Wang, and Q. Hao.
A highly scalable optical network-on-chip with small network diameter and
deadlock freedom.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(12):3424-3436, December 2016.
- [4513]
- Z. Wang, X. Wang,
J. Xu, H. Li, R. K. V. Maeda, Z. Wang, P. Yang, L.-H.-K. Duong, and Z. Wang.
An adaptive process-variation-aware technique for power-gating-induced
power/ground noise mitigation in mpsoc.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(12):3373-3386, December 2016.
- [4514]
- Z. Wang, J. Xu,
P. Yang, L.-H.-K Duong, Z. Wang, X. Wang, Z. Wang, H. Li, and R. K. V. Maeda.
A holistic modeling and analysis of optical-electrical interfaces for
inter/intra-chip interconnects.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(7):2462-2474, July 2016.
- [4515]
- J.-P. Wang, S. S.
Sapatnekar, C.-H. Kim, P. Crowell, S. Koester, S. Datta, K. Roy,
A. Raghunathan, X.-S. Hu, M. Niemier, A. Naeemi, C.-L. Chien, C. Ross, and
R. Kawakami.
A pathway to enable exponential scaling for the beyond-CMOS era.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [4516]
- M. Wang, F. Yang,
C. Yan, X. Zeng, and X. Hu.
Efficient bayesian yield optimization approach for analog and SRAM circuits.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [4517]
- S. Wang, Z. Sun,
Y. Cheng, S.-X.-D. Tan, and M. B. Tahoori.
Leveraging recovery effect to reduce electromigration degradation in
power/ground TSV.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 811-818, Irvine CA, November 13-16 2017.
- [4518]
- X. Wang, B. Xu,
and L. Chen.
Efficient memristor model implementation for simulation and application.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(7):1226-1230, July 2017.
- [4519]
- X. Wang, Y. Yan,
J. He, S.-X.-D. Tan, C. Cook, and S. Yang.
Fast physics-based electromigration analysis for multi-branch interconnect
trees.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 169-176, Irvine CA, November 13-16 2017.
- [4520]
- X. Wang,
H. Zhuang, and C.-K. Cheng.
Exploring the exponential integrators with krylov subspace algorithms for
nonlinear circuit simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 163-168, Irvine CA, November 13-16 2017.
- [4521]
- A. Wang, P. Rigge,
A. Izraelevitz, C. Markley, J. Bachrach, and B. Nikolic.
ACED: a hardware library for generating DSP systems.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [4522]
- X. Wang, S. Li,
H. Liu, and Z. Zeng.
A compact scheme of reading and writing for memristor-based multivalued memory.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 37(7):1505-1509, July 2018.
- [4523]
- X. Wang, Q. Wu,
Q. Chen, and Z. Zeng.
A novel design for memristor-based multiplexer via NOT-material implication
(NIMP).
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 37(7):1436-1444, July 2018.
- [4524]
- L.-C. Wang and M. S.
Abadir.
Data mining in EDA - basic principles, promises, and constraints.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [4525]
- T.-Y. Wang and C. C.-P.
Chen.
3-D thermal-ADI: A linear time chip level transient thermal simulator.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(12):1434-1445, December 2002.
- [4526]
- T.-Y. Wang and C. C.-P.
Chen.
Optimization of the power/ground network wire-sizing and spacing based on
sequential network simplex algorithm.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 157-162, San Jose, CA, March 18-21 2002.
- [4527]
- S. Wang and S. K. Gupta.
An automatic test pattern generator for minimizing switching activity during
scan testing activity.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(8):954-968, August 2002.
- [4528]
- J. Wang and O. Hafiz.
Predicting interconnect uncertainty with a new robust model order reduction
method.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 363-370, San Jose, CA, March 22-24 2004.
- [4529]
- Z. Wang and
A. Herkersdorf.
An efficient approach for system-level timing simulation of compiler-optimized
embedded software.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
220-225, San Francisco, CA, July 26-31 2009.
- [4530]
- R. Wang and C.-K. Koh.
A frequency-domain technique for statistical timing analysis of clock meshes.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 334-339, San Jose, CA, November 5-8 2007.
- [4531]
- F. Wang and X. Li.
Correlated bayesian model fusion: efficient performance modeling of large-scale
tunable analog/RF integrated circuits.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [4532]
- K. Wang and
M. Marek-Sadowska.
On-chip power supply network optimization using multigrid-based technique.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
113-118, Anaheim, CA, June 2-6 2003.
- [4533]
- K. Wang and
M. Marek-Sadowska.
Buffer sizing for clock power minimization subject to general skew constraints.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
159-164, San Diego, CA, June 7-11 2004.
- [4534]
- K. Wang and
M. Marek-Sadowska.
On-chip power-supply network optimization using multigrid-based technique.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):407-417, March 2005.
- [4535]
- V. Wang and D. Markovic.
Linear analysis of random process variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 292-296, San Jose, CA, November 10-13 2008.
- [4536]
- B. Wang and P. Mazumder.
Accelerated chip-level thermal analysis using multilayer green's function.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(2):325-344, February 2007.
- [4537]
- Y. Wang and C. McCrosky.
Negation trees: a unified approach to boolean function complementation.
IEEE Transactions on Computers, 45(5):626-630, May 1996.
- [4538]
- J. M. Wang and T. V.
Nguyen.
Extended krylov subspace method for reduced order analysis of linear circuits
with multiple sources.
In Design Automation Conference, pages 247-252, Los Angeles, CA, June
5-9 2000.
- [4539]
- W.-S. Wang and
M. Orshansky.
Path-based statistical timing analysis handling arbitrary delay correlations:
theory and implementation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2976-2988, December 2006.
- [4540]
- W.-S. Wang and
M. Orshansky.
Robust estimation of parametric yield under limited descriptions of
uncertainty.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 884-890, San Jose, CA, November 5-9 2006.
- [4541]
- L. Wang and N. Patel.
Improving error tolerance for multithreaded register files.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(8):1009-1020, August 2008.
- [4542]
- C-Y. Wang and K. Roy.
Control unit synthesis targeting low-power processors.
In International Conference on Computer Design, pages 454-459,
1995.
- [4543]
- C-Y Wang and K. Roy.
COSMOS: A continuous optimization approach for maximum power estimation of
CMOS circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
52-55, San Jose, CA, November 9-13 1997.
- [4544]
- C.-Y. Wang and K. Roy.
Maximum power estimation for CMOS circuits using deterministic and
statistical approaches.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(1):134-140, March 1998.
- [4545]
- C-Y Wang and K. Roy.
Maximization of power dissipation in large CMOS circuits considering spurious
transitions.
IEEE Transactions on Circuits and Systems, 47(4):483-490, April
2000.
- [4546]
- T. Wang and
J. Roychowdhury.
Design tools for oscillator-based computing systems.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4547]
- H. Wang and E. Salman.
Closed-form expressions for I/O simultaneous switching noise revisited.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(2):769-773, February 2017.
- [4548]
- L. Wang and N. R.
Shanbhag.
Low-power AEC-based MIMO signal processing for gigabit ethernet
1000base-T transceivers.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 334-339, Huntington Beach, California, August 6-7
2001.
- [4549]
- L. Wang and N. R.
Shanbhag.
Low-power MIMO signal processing.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):434-445, June 2003.
- [4550]
- S. Wang and M. B.
Tahoori.
Electromigration-aware local-via allocation in power/ground tsvs of 3-D ics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(10):2881-2892, October 2017.
- [4551]
- S. Wang and
M. Tehranipoor.
Light-weight on-chip structure for measuring timing uncertainty induced by
noise in integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1030-1041, May 2014.
- [4552]
- Q. Wang and S. B. K.
Vrudhula.
Static power optimization of deep submicron CMOS circuits for dual VT
technology.
In IEEE/ACM International Conference on Computer-Aided Design, pages
490-496, San Jose, CA, November 8-12 1998.
- [4553]
- Q. Wang and S. B. K.
Vrudhula.
A new short circuit power model for complex CMOS gates.
In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages
98-106, Como, Italy, March 4-5 1999.
- [4554]
- Q. Wang and S. B. K.
Vrudhula.
Algorithms for minimizing standby power in deep submicrometer, dual-vt CMOS
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(3):306-318, March 2002.
- [4555]
- J. Wang and X. Xiong.
Scalable power grid transient analysis via MOR-assisted time-domain
simulations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 548-552, San Jose, CA, November 18-21 2013.
- [4556]
- S. Wang.
General constructive representations for continuous piecewise-linear functions.
IEEE Transactions on Circuits and Systems, 51(9):1889-1896, September
2004.
- [4557]
- J. Wang.
Deterministic random walk preconditioning for power grid analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 392-398, San Jose, CA, November 5-8 2012.
- [4558]
- F.-Z. Wang.
A triangular periodic table of elementary circuit elements.
IEEE Transactions on Circuits and Systems, 60(3):616-623, March
2013.
- [4559]
- L.-C. Wang.
Experience of data analytics in EDA and test - principles, promises, and
challenges.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(6):885-898, June 2017.
- [4560]
- J. Warnock.
Circuit design challenges at the 14nm technology node.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
464-467, San Diego, CA, June 5-9 2011.
- [4561]
- V. Wason and
K. Banerjee.
A probabilistic framework for power-optimal repeater insertion in global
interconnects under parameter variations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 131-136, San Diego, CA, August 8-10 2005.
- [4562]
- S. Weber,
T. Ressurricao, and C. Duarte.
Yield prediction with a new generalized process capability index applicable to
non-normal data.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(6):931-942, June 2016.
- [4563]
- H. Weber and W. Mathis.
Analysis and design of nonlinear circuits with a self-consistent carleman
linearization.
IEEE Transactions on Circuits and Systems, Part I: Regular Papers,
65(12):4272-4284, December 2018.
- [4564]
- L. Wei, Z. Chen, and
K. Roy.
Mixed-vth (MVT) CMOS circuit design methodology.
In Design Automation Conference, pages 430-435, New Orleans, LA, June
21-25 1999.
- [4565]
- L. Wei, Z. Chen,
K. Roy, M. C. Johnson, Y. Ye, and V. K. De.
Design and optimization of dual-threshold circuits for low-voltage low-power
applications.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
7(1):16-24, March 1999.
- [4566]
- S. Wei,
S. Meguerdichian, and M. Potkonjak.
Gate-level characterization: foundations and hardware security applications.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
222-227, Anaheim, CA, June 13-18 2010.
- [4567]
- H. Wei, J. Zhang,
L. Wei, N. Patil, A. Lin, M. M. Shulaker, H.-Y. Chen, H.-S.-P. Wong, and
S. Mitra.
Carbon nanotube imperfection-immune digital VLSI: frequently asked questions
updated.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 227-230, San Jose, CA, November 7-10 2011.
- [4568]
- C.-J. Wei, H. Chen,
and S.-J. Chen.
Design and implementation of block-based partitioning for parallel flip-chip
power-grid analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(3):370-379, March 2012.
- [4569]
- X. Wei, C.-H. Yu,
P. Zhang, Y. Chen, Y. Wang, H. Hu, Y. Liang, and J. Cong.
Automatic systolic array architecture synthesis for high throughput CNN
inference on fpgas.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [4570]
- J. Wei and C. Rowen.
Implementing low-power configurable processors - practical options and
tradeoffs.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
706-711, Anaheim, CA, June 13-17 2005.
- [4571]
- E. Wein.
Core integration: overview and challenges.
In IEEE/ACM International Conference on Computer-Aided Design, pages
450-452, San Jose, CA, November 8-12 1998.
- [4572]
- R. Weiss.
Synthetic biology: from bacteria to stem cells.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
634-635, San Diego, CA, June 4-8 2007.
- [4573]
- J. Welser.
The semiconductor industrys nanoelectronics research initiative: motivation and
challenges.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
298-300, San Francisco, CA, July 26-31 2009.
- [4574]
- C.-H.-P. Wen, L.-C.
Wang, and J. Bhadra.
An incremental learning framework for estimating signal controllability in
unit-level verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 250-257, San Jose, CA, November 5-8 2007.
- [4575]
- W. Wen, Y. Zhang,
Y. Chen, Y. Wang, and Y. Xie.
Ps3-RAM: a fast portable and scalable statistical STT-RAM reliability
analysis method.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1187-1192, San Francisco, CA, June 3-7 2012.
- [4576]
- W. Wen, C.-R. Wu,
X. Hu, B. Liu, T.-Y. Ho, X. Li, and Y. Chen.
An EDA framework for large scale hybrid neuromorphic computing systems.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4577]
- H. Wen and L. B. Kish.
Noise based logic: why noise?
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 152-155, San Jose, CA, November 5-8 2012.
- [4578]
- C. Wen and X. Ma.
A basis-function canonical piecewise-linear approximation.
IEEE Transactions on Circuits and Systems, 55(5):1328-1334, June
2008.
- [4579]
- S.-H. Weng,
Q. Chen, and C.-K. Cheng.
Time-domain analysis of large-scale circuits by matrix exponential method with
adaptive control.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(8):1180-1193, August 2012.
- [4580]
- S.-H. Weng,
Q. Chen, N. Wong, and C.-K. Cheng.
Circuit simulation via matrix exponential method for stiffness handling and
parallel processing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 407-414, San Jose, CA, November 5-8 2012.
- [4581]
- I.-C. Wey, Y.-G. Chen,
C.-H. Yu, A.-Y. A. Wu, and J. Chen.
Design and implementation of cost-effective probabilistic-based noise-tolerant
VLSI circuits.
IEEE Transactions on Circuits and Systems, 56(11):2411-2424, November
2009.
- [4582]
- J. White.
CAD challenges in biomems design.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
629-632, San Diego, CA, June 7-11 2004.
- [4583]
- R. Wille, B. Li,
U. Schlichtmann, and R. Drechsler.
From biochips to quantum circuits: computer-aided design for emerging
technologies.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [4584]
- R. Wille,
A. Fowler, and Y. Naveh.
Computer-aided design for quantum computation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [4585]
- S. Williams,
L. Oliker, R. Vuduc, J. Shalf, K. Yelick, and J. Demmel.
Optimization of sparse matrix-vector multiplication on emerging multicore
platforms.
In ACM/IEEE International Conference for High Performance Computing,
Networking, Storage, and Analysis (SC-07), Reno, NV, November 10-16
2007.
- [4586]
- J. Williamson, Q. Liu, F. Lu, W. Mohrman, K. Li, R. Dick, and
L. Shang.
Data sensing and analysis: challenges for wearables.
In 20th Asia and South Pacific Design Automation Conference, pages
136-141, Chiba/Tokyo, Japan, January 19-22 2015.
- [4587]
- C. J. Willits,
D. C. Dietz, and A. H. Moore.
Series-system reliability estimation using very small binomial samples.
IEEE Transactions on Reliability, 46(2):296-302, June 1997.
- [4588]
- S. Wimer and L. Koren.
The optimal fan-out of clock network for power minimization by adaptive gating.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(10):1772-1780, October 2012.
- [4589]
- E. Winfree and S.-W.
Shin.
Compiling and verifying DNA-based chemical reaction network implementations.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
115-115, San Diego, CA, June 5-9 2011.
- [4590]
- A. Witvrouw.
CMOS-MEMS integration: why, how and what.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 826-827, San Jose, CA, November 5-9 2006.
- [4591]
- J. M. Wojciechowski, L. J. Opalski, and K. Zamlynski.
Design centering using an approximation to the constraint region.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(3):598-607, March 2004.
- [4592]
- M. Wolf and E. Feron.
What don't we know about CPS architectures?
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4593]
- A. Wolfe.
Opportunities and obstacles in low-power system-level CAD.
In 33rd Design Automation Conference, pages 15-20, Las Vegas, NV,
June 3-7 1996.
- [4594]
- H.-S. Won, K.-S. Kim,
K.-O. Jeong, K.-T. Park, K.-M. Choi, and J.-T. Kong.
An MTCMOS design methodology and its application to mobile computing.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 110-115, Seoul, Korea, August 25-27 2003.
- [4595]
- J. L. Wong,
F. Koushanfar, S. Meguerdichian, and M. Potkonjak.
A probabilistic constructive approach to optimization problems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 453-456, San Jose, CA, November 4-8 2001.
- [4596]
- J.-L. Wong,
F. Koushanfar, S. Megerian, and M. Potkonjak.
Probabilistic constructive optimization techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):859-868, June 2004.
- [4597]
- N. Wong,
V. Balakrishnan, and C.-K. Koh.
Passivity-preserving model reduction via a computationally efficient
project-and-balance scheme.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
369-374, San Diego, CA, June 7-11 2004.
- [4598]
- H.-Y. Wong,
L. Cheng, Y. Lin, and L. He.
FPGA device and architecture evaluation considering process variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 19-24, San Jose, CA, November 6-10 2005.
- [4599]
- J.-L. Wong,
F. Kourshanfar, and M. Potkonjak.
Flexible ASIC: shared masking for multiple media processors.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
909-914, Anaheim, CA, June 13-17 2005.
- [4600]
- E. Wong, J. Minz,
and S.-K. Lim.
Decoupling capacitor planning and sizing for noise and leakage reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 395-400, San Jose, CA, November 5-9 2006.
- [4601]
- H.-S.-P. Wong,
J. Deng, A. Hazeghi, T. Krishnamohan, and G.-C. Wan.
Carbon nanotube transistor circuits - models and tools for design and
performance optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 651-654, San Jose, CA, November 5-9 2006.
- [4602]
- J.-L. Wong,
A. Davoodi, V. Khandelwal, A. Srivastava, and M. Potkonjak.
A statistical methodology for wire-length prediction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1327-1336, July 2006.
- [4603]
- N. Wong,
V. Balakrishnan, C.-K. Koh, and T.-S. Ng.
Two algorithms for fast and accurate passivity-preserving model order
reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2062-2075, October 2006.
- [4604]
- E. Wong, J. R.
Minz, and S. K. Lim.
Decoupling-capacitor planning and sizing for noise and leakage reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(11):2023-2034, November 2007.
- [4605]
- H. Wong, V. Betz,
and J. Rose.
Quantifying the gap between FPGA and custom CMOS to aid microarchitectural
design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(10):2067-2080, October 2014.
- [4606]
- H.-S.-P. Wong,
H. Yi, M. Tung, and K. Okabe.
Physical layout design of directed self-assembly guiding alphabet for IC
contact hole/via patterning.
In ACM International Symposium on Physical Design 2015, pages 65-66,
Monterey, California, March 29 - April 1 2015.
- [4607]
- N. Wong and
V. Balakrishnan.
Fast balanced stochastic truncation via a quadratic extension of the
alternating direction implicit iteration.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 801-805, San Jose, CA, November 6-10 2005.
- [4608]
- N. Wong and
V. Balakrishnan.
Multi-shift quadratic alternating direction implicit iteration for high-speed
positive-real balanced truncation.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
257-260, San Francisco, CA, July 24-28 2006.
- [4609]
- N. Wong and
V. Balakrishnan.
Fast positive-real balanced truncation via quadratic alternating direction
implicit iteration.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(9):1725-1731, September 2007.
- [4610]
- J. S. J. Wong and P. Y. K.
Cheung.
Timing measurement platform for arbitrary black-box circuits based on
transition probability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(12):2307-2320, December 2013.
- [4611]
- N. Wong.
Fast positive-real balanced truncation of symmetric systems using cross riccati
equations.
Design, Automation and Test in Europe (DATE-07), pages 1496-1501,
April 16-20 2007.
- [4612]
- N. Wong.
Efficient positive-real balanced truncation of symmetric systems via
cross-riccati equations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(3):470-480, March 2008.
- [4613]
- N. Wong.
An efficient passivity test for descriptor systems via canonical projector
techniques.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
957-962, San Francisco, CA, July 26-31 2009.
- [4614]
- S. Woods and
G. Casinovi.
Efficient solution of systems of boolean equations.
In IEEE/ACM International Conference on Computer-Aided Design, pages
542-546, San Jose, CA, November 10-14 1996.
- [4615]
- M. H. Woods.
MOS VLSI reliability and yield trends.
In Proceedings of the IEEE, pages 1715-1729, December 1986.
- [4616]
- W. Wu, M. Pedram, and
X. Wu.
Clock-gating and its application to low power design of sequential circuits.
In IEEE 1997 Custom Integrated Circuits Conference, pages 479-482,
Santa Clara, CA, May 5-8 1997.
- [4617]
- Q. Wu, Q. Qiu,
M. Pedram, and C.-S. Ding.
Cycle-accurate macro-models for RT-level power analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(4):520-528, December 1998.
- [4618]
- L. Wu, J. Fang,
H. Yonezawa, Y. Kawakami, N. Iwanishi, H. Yan, P. Chen, A. I-H Chen,
N. Koike, Y. Okamoto, C-S Yeh, and Z. Liu.
GLACIER: A hot carrier gate level circuit characterization and simulation
system for VLSI design.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 73-79, San Jose, CA, March 20-22 2000.
- [4619]
- Q. Wu, M. Pedram, and
X. Wu.
Clock-gating and its application to low power design of sequential circuits.
IEEE Transactions on Circuits and Systems, 47(3):415-420, March
2000.
- [4620]
- W.-L. Wu, C.-N. Sze,
C.-C. Cheung, and H. Fan.
On improved graph-based alternative wiring scheme for multi-level logic
optimization.
In 7th IEEE International Conference on Electronics, Circuits and
Systems, pages 654-657, Beirut, Lebanon, December 17-19 2000.
- [4621]
- Q. Wu, Q. Qiu, and
M. Pedram.
Estimation of peak power dissipation in VLSI circuits using the limiting
distributions of extreme order statistics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(8):942-956, August 2001.
- [4622]
- X. Wu, X. Hong, Y. Cai,
C. K. Cheng, J. Gu, and W. Dai.
Area minimization of power distribution network using efficient nonlinear
programming techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 153-157, San Jose, CA, November 4-8 2001.
- [4623]
- B. Wu, J. Zhu, and
F. N. Najm.
An analytical approach for dynamic range estimation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
472-477, San Diego, CA, June 7-11 2004.
- [4624]
- B. Wu, J. Zhu, and
F. N. Najm.
Dynamic range estimation for nonlinear systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 660-667, San Jose, CA, November 7-11 2004.
- [4625]
- X. Wu, X. Hong,
Y. Cai, Z. Luo, C.-K. Cheng, J. Gu, and W. Dai.
Area minimization of power distribution network using efficient nonlinear
programming techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(7):1086-1094, July 2004.
- [4626]
- B. Wu, J. Zhu, and
F. N. Najm.
A non-parametric approach for dynamic range estimation of nonlinear systems.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
841-844, Anaheim, CA, June 13-17 2005.
- [4627]
- D. Wu,
G. Venkataraman, J. Hu, Q. Li, and R. Mahapatra.
Dicer: distributed and cost-effective redundancy for variation tolerance.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 393-397, San Jose, CA, November 6-10 2005.
- [4628]
- Y.-W. Wu, C.-L. Yang,
P.-H. Yuh, and Y.-W. Chang.
Joint exploration of architectural and physical design spaces with thermal
consideration.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 123-126, San Diego, CA, August 8-10 2005.
- [4629]
- B. Wu, J. Zhu, and
F. N. Najm.
Dynamic-range estimation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1618-1636, September 2006.
- [4630]
- H. Wu, M. D.-F. Wong,
and I-M. Liu.
Timing-constrained and voltage-island-aware voltage assignment.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
429-432, San Francisco, CA, July 24-28 2006.
- [4631]
- W. Wu, L. Jin,
J. Yang, P. Liu, and S. X.-D. Tan.
A systematic method for functional unit power estimation in microprocessors.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
554-557, San Francisco, CA, July 24-28 2006.
- [4632]
- G. Wu, T. Lin, H.-H.
Huang, C. Chu, and P. A. Beerel.
Asynchronous circuit placement by lagrangian relaxation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 641-646, San Jose, CA, November 2-6 2014.
- [4633]
- J. Wu, J. Xiong,
P. Shil, and Y. Shi.
Real time anomaly detection in wide area monitoring of smart grids.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 197-204, San Jose, CA, November 2-6 2014.
- [4634]
- K. C. Wu, I.-C. Lin,
Y.-T. Wang, and S.-S. Yang.
BTI-aware sleep transistor sizing algorithm for reliable power gating
designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(10):1591-1595, October 2014.
- [4635]
- W. Wu, W. Xu,
R. Krishnan, Y.-L. Chen, and L. He.
Rescope: high-dimensional statistical circuit simulation towards full failure
region coverage.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [4636]
- R. Wu, C.-H. Chen,
C. Li, T.-C. Huang, F. Lan, C. Zhang, Y. Pan, J. E. Bowers, R. G. Beausoleil,
and K.-T. Cheng.
Variation-aware adaptive tuning for nanophotonic interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 487-493, Austin, TX, November 2-6 2015.
- [4637]
- Y. Wu, S. Thomson,
H. Sun, D. Krause, S. Yu, and G. Kurio.
Free razor: a novel voltage scaling low-power technique for large soc designs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(11):2431-2437, November 2015.
- [4638]
- S.-L. Wu and M. Al-Khaleel.
Parameter optimization in waveform relaxation for fractiional-order RC
circuits.
IEEE Transactions on Circuits and Systems I: Regular Papers,
64(7):1781-1790, July 2017.
- [4639]
- S.-W. Wu and Y.-W. Chang.
Efficient power/ground network analysis for power integrity-driven design
methodology.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
177-180, San Diego, CA, June 7-11 2004.
- [4640]
- Q. Wu and M.-S. Hsiao.
State variable extraction and partitioning to reduce problem complexity for
ATPG and design validation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2275-2282, October 2006.
- [4641]
- B.-H. Wu and C.-Y. (Ric) Huang.
A robust general constrained random pattern generator for constraints with
variable ordering.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 109-114, San Jose, CA, November 5-8 2012.
- [4642]
- K.-C. Wu and D. Marculescu.
A low-cost, systematic methodology for soft error robustness of logic circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(2):367-379, February 2013.
- [4643]
- X. Wu and M. Pedram.
Low power sequential circuit design by using priority encoding and clock
gating.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 143-148, Italy, July 26-27 2000.
- [4644]
- H-J. Wunderlich.
Protest: a tool for probabilistic testability analysis.
In ACM/IEEE 22nd Design Automation Conference, pages 204-211,
1985.
- [4645]
- J. L. Wyatt, Jr.
Monotone sensitivity of nonlinear nonuniform RC transmission lines, with
application to timing analysis of digital MOS integrated circuits.
IEEE Transactions on Circuits and Systems, CAS-32(1):28-33, January
1985.
- [4646]
- J. L. Wyatt, Jr.
Signal delay in RC mesh networks.
IEEE Transactions on Circuits and Systems, CAS-32(5):507-510, May
1985.
- [4647]
- M. Xakellis and
F. Najm.
Statistical estimation of the switching activity in digital circuits.
In 31st ACM/IEEE Design Automation Conference, pages 728-733, San
Diego, CA, June 6-10 1994.
- [4648]
- H. Xiang, H. Qian,
C. Zhou, Y.-S. Lin, F. Yee, A. Sullivan, and P.-F. Lu.
Row based dual-VDD island generation and placement.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [4649]
- X-M. Xiao and R. Spence.
A fast constrained optimization algorithm for IC design.
In IEEE International Symposium on Circuits and Systems (ISCAS), pages
2252-2255, 1990.
- [4650]
- L. Xie, A. Davoodi,
J. Zhang, and T.-H. Wu.
Adjustment-based modeling for statistical static timing analysis with high
dimension of variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 181-184, San Jose, CA, November 10-13 2008.
- [4651]
- S. Xie, Z. Yang, and
Y. Fu.
Nonnegative matrix factorization applied to nonlinear speech and image
cryptosystems.
IEEE Transactions on Circuits and Systems, 55(8):2356-2367, September
2008.
- [4652]
- L. Xie, Z. Davoodi,
J. Zhang, and T.-H. Wu.
Adjustment-based modeling for timing analysis under variability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(7):1085-1095, July 2009.
- [4653]
- L. Xie, A. Davoodi,
and K. K. Saluja.
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing
variations.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
274-279, Anaheim, CA, June 13-18 2010.
- [4654]
- Y. Xie, M. Nikdast,
J. Xu, W. Zhang, Q. Li, X. Wu, Y. Ye, X. Wang, and W. Liu.
Crosstalk noise and bit error rate analysis for optical network-on-chip.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
657-660, Anaheim, CA, June 13-18 2010.
- [4655]
- Y. Xie, M. Nikdast,
J. Xu, X. Wu, W. Zhang, Y. Ye, X. Wang, Z. Wang, and W. Liu.
Formal worst-case analysis of crosstalk noise in mesh-based optical
networks-on-chip.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1823-1836, October 2013.
- [4656]
- L. Xie and A. Davoodi.
Robust estimation of timing yield with partial statistical information on
process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(12):2264-2276, December 2008.
- [4657]
- L. Xie and A. Davoodi.
Representative path selection for post-silicon timing prediction under
variability.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
386-391, Anaheim, CA, June 13-18 2010.
- [4658]
- L. Xie and A. Davoodi.
Bound-based statistically-critical path extraction under process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(1):59-71, January 2011.
- [4659]
- L. Xie and A. Davoodi.
Post-silicon failing-path isolation incorporating the effects of process
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(7):1008-1018, July 2012.
- [4660]
- J. Xie and
M. Swaminathan.
3d transient thermal solver using non-conformal domain decomposition approach.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 333-340, San Jose, CA, November 5-8 2012.
- [4661]
- J. Xiong, J. Chen,
J. Ma, and L. He.
Post global routing RLC crosstalk budgeting.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 504-509, San Jose, CA, November 10-14 2002.
- [4662]
- J. Xiong,
V. Zolotov, and L. He.
Robust extraction of spatial correlation.
In ACM/IEEE International Symposium on Physical Design, pages 2-9,
San Jose, CA, April 9-12 2006.
- [4663]
- J. Xiong,
V. Zolotov, N. Venkateswaran, and C. Visweswariah.
Criticality computation in parameterized statistical timing.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 63-68,
San Francisco, CA, July 24-28 2006.
- [4664]
- J. Xiong,
V. Zolotov, and L. He.
Robust extraction of spatial correlation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):619-631, April 2007.
- [4665]
- J. Xiong,
C. Visweswariah, and V. Zolotov.
Statistical ordering of correlated timing quantities and its application for
path ranking.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
122-125, San Francisco, CA, July 26-31 2009.
- [4666]
- X. Xiong and J. Wang.
An efficient dual algorithm for vectorless power grid verification under linear
current constraints.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
837-842, Anaheim, CA, June 13-18 2010.
- [4667]
- X. Xiong and J. Wang.
A hierarchical matrix inversion algorithm for vectorless power grid
verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 543-550, San Jose, CA, November 7-11 2010.
- [4668]
- X. Xiong and J. Wang.
Dual algorithms for vectorless power grid verification under linear current
constraints.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(10):1469-1482, October 2011.
- [4669]
- X. Xiong and J. Wang.
Vectorless verification of RLC power grids with transient current
constraints.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 548-554, San Jose, CA, November 7-10 2011.
- [4670]
- X. Xiong and J. Wang.
Parallel forward and back substitution for efficient power grid simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 660-663, San Jose, CA, November 5-8 2012.
- [4671]
- X. Xiong and J. Wang.
Constraint abstraction for vectorless power grid verification.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [4672]
- X. Xiong and J. Wang.
Verifying RLC power grids with transient current constraints.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(7):1059-1071, July 2013.
- [4673]
- X. Xiong and J. Wang.
Vectorless transient power grid verification: A case study with IBM
benchmarks.
In IEEE Symposium on Electromagnetic Compatibility and Signal
Integrity, pages 271-276, Santa Clara, CA, March 15-21 2015.
- [4674]
- Z. Xiu and R. A. Rutenbar.
Timing-driven placement by grid-warping.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
585-590, Anaheim, CA, June 13-17 2005.
- [4675]
- L. Xiu.
Clock technology: the next frontier.
IEEE Circuits and Systems Magazine, 17(2):27-46, Second Quarter
2017.
- [4676]
- C. Xu, T. S. Fiez, and
K. Mayaram.
An error control method for application of the discrete cosine transform to
extraction of substrate parasitics in ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):932-938, May 2006.
- [4677]
- H. Xu, W.-B. Jone, and
R. Vemuri.
Accurate energy breakeven time estimation for run-time power gating.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 161-168, San Jose, CA, November 10-13 2008.
- [4678]
- T. Xu, K. Chakrabarty,
and V. K. Pamula.
Design and optimization of a digital microfluidic biochip for protein
crystallization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 297-301, San Jose, CA, November 10-13 2008.
- [4679]
- W. Xu, Y. Chen, X. Wang,
and T. Zhang.
Improving STT MRAM storage density through smaller-than-worst-case
transistor sizing.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 87-90,
San Francisco, CA, July 26-31 2009.
- [4680]
- T. Xu, P. Li, and
B. Yan.
Decoupling for power gating: sources of power noise and design strategies.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
1002-1007, San Diego, CA, June 5-9 2011.
- [4681]
- C. Xu, S. K. Kolluri,
K. Endo, and K. Banerjee.
Analytical thermal model for self-heating in advanced finfet devices with
implications for design and reliability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(7):1045-1058, July 2013.
- [4682]
- H. Xu, V. F. Pavlidis,
X. Tang, W. Burleson, and G. DeMicheli.
Timing uncertainty in 3-D clock trees due to process variations and power
supply noise.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(12):2226-2239, December 2013.
- [4683]
- X. Xu, N. Shah,
A. Evans, S. Sinha, B. Cline, and G. Yeric.
Standard cell library design and optimization methodology for asap7 PDK.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 985-990, Irvine CA, November 13-16 2017.
- [4684]
- T. Xu and B. Brim.
A resonance-free power delivery system design methodology applying 3d optimized
extended adaptive voltage positioning.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 107-110, San Jose, CA, October 27-29 2008.
- [4685]
- M. Xu and F. J. Kurdahi.
Accurate prediction of quality metrics for logic level designs targeted toward
lookup-table-based FPGA's.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(4):411-418, December 1999.
- [4686]
- Q. Xu and P. Mazumder.
Equivalent-circuit interconnect modeling based on fifth-order differential
quadrature methods.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(6):1068-1079, December 2003.
- [4687]
- Q. Xu and N. Nicolici.
Wrapper design for multifrequency IP cores.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):678-685, June 2005.
- [4688]
- S. Xu and B. C. Schafer.
Exposing approximate computing optimizations at different levels: from
behavioral to gate-level.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(11):3077-3088, November 2017.
- [4689]
- X. Xuan, A. D.
Singh, and A. Chatterjee.
Reliability evaluation for integrated circuit with defective interconnect under
electromigration.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 29-34, San Jose, CA, March 24-26 2003.
- [4690]
- G. Y. Yacoub and W. H. Ku.
An accurate simulation technique for short-circuit power dissipation based on
current component isolation.
In IEEE International Conference on Circuits and Systems, pages
1157-1161, 1989.
- [4691]
- G. Yahalom,
O. Vikinski, and G. Sizikov.
Architecture constraints over dynamic current consumption.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 3-6, San Jose, CA, October 27-29 2008.
- [4692]
- C. Yakopcic,
T. M. Taha, G. Subramanyan, and R. E. Pino.
Generalized memristive device SPICE model and its application in circuit
design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(8):1201-1214, August 2013.
- [4693]
- H. Yalcin, J. P.
Hayes, and K. A. Sakallah.
An approximate timing analysis method for datapath circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
114-118, San Jose, CA, November 10-14 1996.
- [4694]
- H. Yalcin,
M. Mortazavi, R. Palermo, C. Bamji, and K. Sakallah.
Functional timing analysis for IP characterization.
In Design Automation Conference, pages 731-736, New Orleans, LA, June
21-25 1999.
- [4695]
- H. Yalcin,
M. Mortazavi, R. Palermo, C. Bamji, K. A. Sakallah, and J. P. Hayes.
Fast and accurate timing characterization using functional information.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(2):315-331, February 2001.
- [4696]
- H. Yalcin,
R. Palermo, M. Mortazavi, C. Bamji, K. Sakallah, and J. Hayes.
An advanced timing characterization method using mode dependency.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
657-660, Las Vegas, NV, June 18-22 2001.
- [4697]
- M. E. Yalcin,
J. A. K. Suykens, and J. Vandewalle.
True random bit generation from a double-scroll attractor.
IEEE Transactions on Circuits and Systems, 51(7):1395-1404, July
2004.
- [4698]
- H. Yalcin and J. P.
Hayes.
Hierarchical timing analysis using conditional delays.
In IEEE/ACM International Conference on Computer-Aided Design, pages
371-377, San Jose, CA, November 5-9 1995.
- [4699]
- T. J.
Yamaguchi, M. Soma, J. P. Nissen, D. E. Halter, R. Raina, and M. Ishida.
Skew measurements in clock distribution circuits using an analytic signal
method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(7):997-1009, July 2004.
- [4700]
- H. Yamamoto and
J. A. Davis.
Decreased effectiveness of on-chip dcoupling capacitance in high-frequency
operation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(6):649-659, June 2007.
- [4701]
- K. Yamamura and
K. Horiuchi.
A globally and quadratically convergent algorithm for solving nonlinear
resistive networks.
IEEE Transactions on Computer-Aided Design, 9(5):487-499, May
1990.
- [4702]
- K. Yamamura.
An algorithm for representing functions of many variables by superpositions of
functions of one variable and addition.
IEEE Transactions on Circuits and Systems, Part I, 43(4):338-340,
April 1996.
- [4703]
- T. Yamashita, T. Fujimoto, and K. Ishibashi.
A dynamic clock skew compensation circuit technique for low power clock
distribution.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 7-10, Austin, TX, May 9 - 11 2005.
- [4704]
- L. Yan, J. Luo, and
N. K. Jha.
Combined dynamic voltage scaling and adaptive body biasing for heterogeneous
distributed real-time embedded systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 30-37, San Jose, CA, November 9-13 2003.
- [4705]
- L. Yan, J. Luo, and
N. K. Jha.
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous
distributed real-time embedded systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):1030-1041, July 2005.
- [4706]
- B. Yan, S. X.-D. Tan,
P. Liu, and B. McGaughy.
SBPOR: second-order balanced truncation for passive order reduction of RLC
circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
158-161, San Diego, CA, June 4-8 2007.
- [4707]
- B. Yan, S. X.-D.Tan,
G. Chen, and L. Wu.
Modeling and simulation for on-chip power grid networks by locally dominant
krylov subspace method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 744-749, San Jose, CA, November 10-13 2008.
- [4708]
- B. Yan, L. Zhou,
S. X.-D. Tan, J. Chen, and B. McGaughy.
Demor: decentralized model order reduction of linear networks with massive
ports.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
409-414, Anaheim, CA, June 8-13 2008.
- [4709]
- C. Yan, S.-G. Wang,
and X. Zeng.
A new method for multiparameter robust stability distribution analysis of
linear analog circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 420-427, San Jose, CA, November 7-10 2011.
- [4710]
- B. Yan, S.-X.-D. Tan,
L. Zhou, J. Chen, and R. Shen.
Decentralized and passive model order reduction of linear networks with massive
ports.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(5):865-877, May 2012.
- [4711]
- B. Yan, X. Cao, and
H.-H. Li.
A neuromorphic design using chaotic mott memristor with relaxation oscillation.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [4712]
- L. Yan and J. R. English.
Economic cost modeling of environmental-stress-screening and burn-in.
IEEE Transactions on Reliability, 46(2):275-282, June 1997.
- [4713]
- C. Yan and E. Salman.
Mono3d: Open source cell library for monolithic 3-D integrated circuits.
IEEE Transactions on Circuits and Systems, Part I: Regular Papers,
65(3):1075-1085, March 2018.
- [4714]
- L. Yan.
A PCA-based PCM data anlayzing method for diagnosing process failures.
IEEE Transactions on Semiconductor Manufacturing, 19(4):404-410,
November 2006.
- [4715]
- J.-T. Yan.
On-chip optical channel routing for signal loss minimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 37(8):1654-1666, August 2018.
- [4716]
- X. Yang, B. Krauter,
and L. T. Pileggi.
Combined ac and transient power distribution analysis.
In IEEE 1996 Custom Integrated Circuits Conference, pages 233-236,
San Diego, CA, May 5-8 1996.
- [4717]
- X. Yang, W. H. Ku,
and C.-K. Cheng.
RLS interconnect delay estimation via moments of amplitude and phase
response.
In IEEE/ACM International Conference on Computer-Aided Design, pages
208-213, San Jose, CA, November 7-11 1999.
- [4718]
- J.-S. Yang, J.-Y.
Kim, J.-H. Choi, M.-H. Yoo, and J.-T. Kong.
Elimination of false aggressors using the functional relationship for full-chip
crosstalk analysis.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 344-347, San Jose, CA, March 24-26 2003.
- [4719]
- G. Yang, Z. Wang,
and S.-M. Kang.
Low power and high performance circuit techniques for high fan-in dynamic
gates.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 421-424, San Jose, CA, March 22-24 2004.
- [4720]
- J. Yang,
L. Capodieci, and D. Sylvester.
Advanced timing analysis based on post-OPC extraction of critical dimensions.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
359-364, Anaheim, CA, June 13-17 2005.
- [4721]
- C. Yang,
S. Chakraborty, D. Gope, and V. Jandhyala.
A parallel low-rank multilevel matrix compression algorithm for parasitic
extraction of electrically large structures.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
1053-1056, San Francisco, CA, July 24-28 2006.
- [4722]
- J. Yang, E. Cohen,
C. Tabery, N. Rodriguez, and M. Craig.
An up-stream design auto-fix flow for manufacturability enhancement.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 73-76,
San Francisco, CA, July 24-28 2006.
- [4723]
- Y. Yang, C. Zhu,
Z.-P. Gu, L. Shang, and R. P. Dick.
Adaptive multi-domain thermal modeling and analysis for integrated circuit
synthesis and design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 575-582, San Jose, CA, November 5-9 2006.
- [4724]
- S. Yang, W. Wang,
T. Lu, W. Wolf, N. Vijaykrishnan, and Y. Xie.
Case study of reliability-aware and lower-power design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(7):861-873, July 2008.
- [4725]
- J. Yang, Y. Cai,
Q. Zhou, and J. Shi.
Fast poisson solver preconditioned method for robust power grid analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 531-536, San Jose, CA, November 7-10 2011.
- [4726]
- J. Yang, Z. Li,
Y. Cai, and Q. Zhou.
Powerrush: a linear simulator for power grid.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 482-487, San Jose, CA, November 7-10 2011.
- [4727]
- Y.-S. Yang,
S. Sinha, A. Veneris, and R. K. Brayton.
Automating logic transformations with approximate spfds.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(5):651-664, May 2011.
- [4728]
- F. Yang, X. Zeng,
and Y.-F. Su.
AMOR: an efficient aggregating based model order reduction method for
many-terminal interconnect circuits.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
295-300, San Francisco, CA, June 3-7 2012.
- [4729]
- J. Yang, Z. Li,
Y. Cai, and Q. Zhou.
Powerrush: efficient transient simulation for power grid analysisy.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 653-659, San Jose, CA, November 5-8 2012.
- [4730]
- W. Yang, L. Wang,
and A. Mishchenko.
Lazy man's logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 597-604, San Jose, CA, November 5-8 2012.
- [4731]
- Y.-S. Yang,
A. Veneris, and N. Nicolici.
Automating data analysis and acquisition setup in a silicon debug environment.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(6):1118-1131, June 2012.
- [4732]
- J. Yang, Y. Cai,
Q. Zhou, and J. Shi.
Friendly fast poisson solver preconditioning technique for power grid analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(4):899-912, April 2014.
- [4733]
- J. Yang, Z. Li,
Y. Cai, and Q. Zhou.
Powerrush: an efficient simulator for static power grid analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(10):2103-2116, October 2014.
- [4734]
- Y.-M. Yang, Y.-W.
Chang, and I.-H.-R. Jiang.
itimerc: common path pessimism removal using effective reduction methods.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 600-605, San Jose, CA, November 2-6 2014.
- [4735]
- Y.-M. Yang,
I.-H.-R. Jiang, and S.-T. Ho.
Pushpull: short-path padding for timing error resilient circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(4):558-570, April 2014.
- [4736]
- J. Yang, L. Ma,
K. Zhao, Y. Cai, and T.-F. Ngai.
Early stage real-time soc power estimation using RTL instrumentation.
In 20th Asia and South Pacific Design Automation Conference, pages
779-784, Chiba/Tokyo, Japan, January 19-22 2015.
- [4737]
- M. Yang, J. P.
Hayes, D. Fan, and W. Qian.
Design of accurate stochastic number generators with noisy emerging devices for
stochastic computing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 638-644, Irvine CA, November 13-16 2017.
- [4738]
- Z. Yang,
C. Serafy, T. Lu, and A. Srivastava.
Phase-driven learning-based dynamic reliability management for multi-core
processors.
In ACM/IEEE 54th Design Automation Conference (DAC-2017), Austin,
Texas, June 18-22 2017.
- [4739]
- K. Yang and K.-T. Cheng.
Silicon debug for timing errors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(11):2084-2088, November 2007.
- [4740]
- C. Yang and
M. Ciesielski.
BDS: A BDD-based logic optimization system.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(7):866-876, July 2002.
- [4741]
- S. Yang and
M. Greenstreet.
Noise margin analysis for dynamic logic circuits.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 406-412, San Jose, CA, November 6-10 2005.
- [4742]
- S. Yang and M. R.
Greenstreet.
Simulating improbable events.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
154-157, San Diego, CA, June 4-8 2007.
- [4743]
- J. Yang and R. Gupta.
FV encoding for low-power data I/O.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 84-87, Huntington Beach, California, August 6-7 2001.
- [4744]
- B.-D. Yang and L.-S. Kim.
A low-power charge-recycling ROM architcture.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):590-600, August 2003.
- [4745]
- W. Yao, S. Pan,
B. Achkir, J. Fan, and L. He.
Modeling and application of multi-port TSV networks in 3-D IC.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(4):487-496, April 2013.
- [4746]
- J. Yao, Z. Ye, and
Y. Wang.
Scalable compact modeling for on-chip passive elements with correlated
parameter extraction and adaptive boundary compression.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(9):1424-1428, September 2014.
- [4747]
- E. Yao and A. Basu.
VLSI extreme learning machine: a design space exploration.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
25(1):60-74, January 2017.
- [4748]
- A.-A. Yassine and F. N.
Najm.
A fast layer elimination approach for power grid reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [4749]
- S. S. Yau and Y-S. Tang.
An efficient algorithm for generating complete test sets for combinational
logic circuits.
IEEE Transactions on Computers, C-20(11):1245-1251, November 1971.
- [4750]
- S. Yazdanshenas, B. Khaleghi, P. Ienne, and H. Asadi.
Designing low power and durable digital blocks using shadow
nanoelectronmechanical relays.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(12):3489-3498, December 2016.
- [4751]
- W. Ye, N. Vijaykrishnan,
M. Kandemir, and M. J. Irwin.
The design and use of simplepower: A cycle-accurate energy estimation tool.
In Design Automation Conference, pages 340-345, Los Angeles, CA, June
5-9 2000.
- [4752]
- X. Ye, P. Li, and
F. Liu.
Practical variation-aware interconnect delay and slew analysis for statistical
timing verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 54-59, San Jose, CA, November 5-9 2006.
- [4753]
- X. Ye, P. Li, M. Zhao,
R. Panda, and J. Hu.
Analysis of large clock meshes via harmonic-weighted model order reduction and
port sliding.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 627-631, San Jose, CA, November 5-8 2007.
- [4754]
- X. Ye, F. Y. Liu, and
P. Li.
Fast variational interconnect delay and slew computation using quadratic
models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(8):913-926, August 2007.
- [4755]
- X. Ye, Y. Zhan, and
P. Li.
Statistical leakage power minimization using fast equi-slack shell based
optimization.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 37-42, Austin, Texas,
February 26-27 2007.
- [4756]
- X. Ye, Y. Zhan, and
P. Li.
Statistical leakage power minimization using fast equi-slack shell based
optimization.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
853-858, San Diego, CA, June 4-8 2007.
- [4757]
- X. Ye, W. Dong, P. Li,
and S. Nassif.
MAPS: multi-algorithm parallel circuit simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 73-78, San Jose, CA, November 10-13 2008.
- [4758]
- X. Ye, D. Wei, and
P. Li.
A multi-algorithm approach to parallel circuit simulation.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 110-115, Monterey, CA,
February 25-26 2008.
- [4759]
- Y. Ye, F. Liu,
S. Nassif, and Y. Cao.
Statistical modeling and simulation of threshold variation under dopant
fluctuations and line-edge roughness.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
900-905, Anaheim, CA, June 8-13 2008.
- [4760]
- Z. Ye, D. Vasilyev,
Z. Zhu, and J. R. Phillips.
Sparse implicit projection (SIP) for reduction of general many-terminal
networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 746-743, San Jose, CA, November 10-13 2008.
- [4761]
- Z. Ye, Z. Zhu, and
J. R. Phillips.
Generalized krylov recycling methods for solution of multiple related linear
equation systems in electromagnetic analysis.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
682-687, Anaheim, CA, June 8-13 2008.
- [4762]
- Y. Ye, F. Liu, M. Chen,
and Y. Cao.
Variability analysis under layout pattern-dependent rapid-thermal annealing
process.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
551-556, San Francisco, CA, July 26-31 2009.
- [4763]
- X. Ye, P. Li, M. Zhao,
R. Panda, and J. Hu.
Scalable analysis of mesh-based clock distribution networks using
application-specific reduced order modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(9):1342-1353, September 2010.
- [4764]
- R. Ye, F. Yuan, and
Q. Xu.
Online clock skew tuning for timing speculation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 442-447, San Jose, CA, November 7-10 2011.
- [4765]
- X. Ye, W. Dong, P. Li,
and S. Nassif.
Hierarchical multialgorithm parallel circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(1):45-58, January 2011.
- [4766]
- Y. Ye, F. Liu,
M. Chen, S. Nassif, and Y. Cao.
Statistical modeling and simulation of threshold variation under random dopant
fluctuations and line-edge roughness.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(6):987-996, June 2011.
- [4767]
- Z. Ye, Y. Li, M. Gao,
and Z. Yu.
A novel framework for passive macro-modeling.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
546-551, San Diego, CA, June 5-9 2011.
- [4768]
- R. Ye, T. Wang,
F. Yuan, R. Kumar, and Q. Xu.
On reconfiguration-oriented approximate adder design and its application.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 48-54, San Jose, CA, November 18-21 2013.
- [4769]
- R. Ye, F. Yuan,
Z. Sun, W.-B. Jone, and Q. Xu.
Post-placement voltage island generation for timing-speculative circuits.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [4770]
- Y. Ye, J. Xu, B. Huang,
X. Wu, W. Zhang, Y. Wang, M. Nikdast, Z. Wang, W. Liu, and Z. Wang.
3-D mesh-based optical network-on-chip for multiprocessor system-on-chip.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(4):584-596, April 2013.
- [4771]
- F. Ye, F. Firouzi,
Y. Yang, K. Chakrabarty, and M. B. Tahoori.
On-chip droop-induced circuit delay prediction based on support-vector
machines.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(4):665-678, April 2016.
- [4772]
- F. Ye and K. Chakrabarty.
TSV open defects in 3-D integrated circuits: characterization, test, and
optimal spare allocation.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1024-1030, San Francisco, CA, June 3-7 2012.
- [4773]
- X. Ye and P. Li.
On-the-fly runtime adaptation for efficient execution of parallel
multi-algorithm circuit simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 298-304, San Jose, CA, November 7-11 2010.
- [4774]
- X. Ye and P. Li.
Parallel program performance modeling for runtime optimization of
multi-algorithm circuit simulation.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
561-566, Anaheim, CA, June 13-18 2010.
- [4775]
- A. Ye and J. Rose.
Using bus-based connections to improve field-programmable gate-array density
for implementing datapath circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(5):462-473, May 2006.
- [4776]
- Y. Ye and K. Roy.
Energy recovery circuits using reversible and partially reversible logic.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 43(9):769-778, September 1996.
- [4777]
- Y. Ye and K. Roy.
A graph-based synthesis algorithm for AND/XOR networks.
In 34th Design Automation Conference, pages 107-112, Anaheim, CA,
June 9-13 1997.
- [4778]
- Z. Ye and Z. Yu.
An efficient algorithm for modeling spatially-correlated process variation in
statistical full-chip leakage analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 239-244, San Jose, CA, November 2-5 2009.
- [4779]
- H. R. Yeager and R. W.
Dutton.
Improvement in norm-reducing newton methods for circuit simulation.
IEEE Transactions on Computer-Aided Design, 8(5):538-546, May
1989.
- [4780]
- G. Yeap.
CPU controller optimization in HDL logic synthesis.
In IEEE 1997 Custom Integrated Circuits Conference, pages 127-130,
Santa Clara, CA, May 5-8 1997.
- [4781]
- G. S. Yee,
R. Christopherson, T. Thorp, B. P. Wong, and C. Sechen.
An automated shielding algorithm and tool for dynamic circuits.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 369-374, San Jose, CA, March 20-22 2000.
- [4782]
- G. Yee and C. Sechen.
Clock-delayed domino for dynamic circuit design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(4):425-430, August 2000.
- [4783]
- Y.-J. Yeh, S.-Y. Kuo,
and J.-Y. Jou.
Converter-free multiple-voltage scaling techniques for low-power CMOS digital
design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(1):172-178, January 2001.
- [4784]
- H.-H. Yeh, C.-Y. Wu,
and C.-Y. Huang.
MACACO: modeling and analysis of circuits for approximate computing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 674-678, San Jose, CA, November 7-10 2011.
- [4785]
- C. Yeh and Y.-S. Kang.
Cell-based layout techniques supporting gate-level voltage scaling for low
power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(5):629-633, October 2000.
- [4786]
- C.-Y. Yeh and
M. Marek-Sadowska.
Sequential delay budgeting with interconnect prediction.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1028-1037, October 2004.
- [4787]
- C.-Y. Yeh and
M. Marek-Sadowska.
Timing-aware power noise reduction in layout.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 627-634, San Jose, CA, November 6-10 2005.
- [4788]
- T.-H. Yeh and S-J. Wang.
Power-aware high-level synthesis with clock skew management.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(1):167-171, January 2012.
- [4789]
- J.-T. Yen and Q. R. Yin.
Multiprocessor design verification methodology for motorola mpc74xx powerpc
microprocessor.
In Design Automation Conference, pages 718-723, Los Angeles, CA, June
5-9 2000.
- [4790]
- S. Yesil, M. M.
Ozdal, T. Kim, A. Ayupov, S. Burns, and O. Ozturk.
Hardware accelerator design for data centers.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 770-775, Austin, TX, November 2-6 2015.
- [4791]
- H. Yi, T. Yoneda,
M. Inoue, Y. Sato, S. Kajihara, and H. Fujiwara.
A failure prediction strategy for transistor aging.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(11):1951-1959, November 2012.
- [4792]
- J.-S. Yim, S.-O. Bae,
and C.-M. Kyung.
A floorplan based planning methodology for power and clock distribution in
asics.
In Design Automation Conference, pages 766-771, New Orleans, LA, June
21-25 1999.
- [4793]
- L. Yin, Y. Deng, and
P. Li.
Simulation-assisted formal verification of nonlinear mixed-signal circuits with
bayesian inference guidance.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(7):977-990, July 2013.
- [4794]
- X. Yin, Z. Toroczkai,
and X.-S. Hu.
An analog SAT solver based on a deterministic dynamical system.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 794-799, Irvine CA, November 13-16 2017.
- [4795]
- X. Yin, B. Sedighi,
M. Varga, M. Ercsey-Ravasz, Z. Toroczkai, and X. S. Hu.
Efficient analog circuits for boolean satisfiability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
26(1):155-167, January 2018.
- [4796]
- T. Yioultsis, A. Woo, and A. C. Cangellaris.
Passive synthesis of compact frequency-dependent interconnect models via
quadrature spectral rules.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 827-834, San Jose, CA, November 9-13 2003.
- [4797]
- M. Yoeli and S. Rinon.
Application of ternary algebra to the study of static hazards.
Journal of the Association for Computing Machinery, 11(1):84-97,
January 1964.
- [4798]
- G. Yoh and F. N. Najm.
A statistical model for electromigration failures.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 45-50, San Jose, CA, March 20-22 2000.
- [4799]
- M. Yoon.
Sequence-switch coding for low-power data transmission.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1381-1385, December 2004.
- [4800]
- H. Yoshida,
K. De, and V. Boppana.
Accurate pre-layout estimation of standard cell characteristics.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
208-211, San Diego, CA, June 7-11 2004.
- [4801]
- S. Youn and J. Kim.
Preventing global convergence failure in mixed-signal systems via indeterminate
state ("X") elimination.
IEEE Transactions on Circuits and Systems, 60(10):2561-2571, October
2013.
- [4802]
- D. Young and
A. Christou.
Failure-mechanism models for electromigration.
IEEE Transactions on Reliability, 43(2):186-192, June 1994.
- [4803]
- D. H. Younger.
Minimum feedback arc sets for a directed graph.
IEEE Transactions on Circuit Theory, CT-10(2):238-245, June 1963.
- [4804]
- A. Youssef,
M. Anis, and M. Elmasry.
POMR: a power-aware interconnect optimization methodology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):297-307, March 2005.
- [4805]
- A. Youssef,
Z. Yang, M. Anis, S. Areibi, A. Vannelli, and M. Elmasry.
A power-efficient multipin ILP-based routing technique.
IEEE Transactions on Circuits and Systems, 57(1):225-235, January
2010.
- [4806]
- Q. Yu, J. M. Wang, and
E. S. Kuh.
Multipoint moment matching model for multiport distributed interconnect
networks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
85-91, San Jose, CA, November 8-12 1998.
- [4807]
- Z. Yu, D. Yergeau, and
R. W. Dutton.
Full chip thermal simulation.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 145-149, San Jose, CA, March 20-22 2000.
- [4808]
- S. Yu, D. M. Petranovic,
S. Krishnan, K. Lee, and C. Y. Yang.
Resistance matrix in crosstalk modeling for multiconductor systems.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 122-125, San Jose, CA, March 22-24 2004.
- [4809]
- H. Yu, L. He, and
S. X.-D. Tan.
Block structure preserving model order reduction.
In IEEE Behavioral Modeling and Simulation Workshop, pages 1-6,
September 22-23 2005.
- [4810]
- H. Yu, Y. Shi, and
L. He.
Fast analysis of structured power grid by triangularization based structure
preserving model order reduction.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
205-210, San Francisco, CA, July 24-28 2006.
- [4811]
- H. Yu, Y. Shi, L. He,
and D. Smart.
A fast block structure preserving model order reduction for inverse inductance
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 7-12, San Jose, CA, November 5-9 2006.
- [4812]
- G. Yu, W. Dong,
Z. Feng, and P. Li.
A framework for accounting for process model uncertainty in statistical static
timing analysis.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
829-834, San Diego, CA, June 4-8 2007.
- [4813]
- H. Yu, C. Chu, and
L. He.
Off-chip decoupling capacitor allocation for chip package co-design.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
618-621, San Diego, CA, June 4-8 2007.
- [4814]
- G. Yu, W. Dong,
Z. Feng, and P. Li.
Statistical static timing analysis considering process variation model
uncertainty.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1880-1890, October 2008.
- [4815]
- X. Yu, , and
R. D. (Shawn) Blanton.
Multiple defect diagnosis using no assumptions on failing pattern
characteristics.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
361-366, Anaheim, CA, June 8-13 2008.
- [4816]
- H. Yu, C. Chu, Y. Shi,
D. Smart, L. He, and S. X.-D. Tan.
Fast analysis of a large-scale inductive interconnect by
block-structure-preserved macromodeling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(10):1399-1411, October 2010.
- [4817]
- B. Yu, J.-R. Gao,
D. Ding, Y. Ban, J.-S. Yang, K. Yuan, M. Cho, and D. Z. Pan.
Dealing with IC manufacturability in extreme scaling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 240-242, San Jose, CA, November 5-8 2012.
- [4818]
- C.-C. Yu, A. Alaghi,
and J. P. Hayes.
Scalable sampling methodology for logic simulation: reduced-ordered monte
carlo.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 195-201, San Jose, CA, November 5-8 2012.
- [4819]
- T. Yu, Z. Xiao, and
M. D. F. Wong.
Efficient parallel power grid analysis via additive schwarz method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 399-406, San Jose, CA, November 5-8 2012.
- [4820]
- W. Yu, T. Zhang,
X. Yuan, and H. Qian.
Fast 3-D thermal simulation for integrated circuits with domain decomposition
method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(12):2014-2018, December 2013.
- [4821]
- B. Yu, D.-Z. Pan,
T. Matsunawa, and X. Zeng.
Machine learning and pattern matching in physical design.
In 20th Asia and South Pacific Design Automation Conference, pages
286-293, Chiba/Tokyo, Japan, January 19-22 2015.
- [4822]
- H. Yu, C. Yan, X. Zeng,
and X. Li.
Impact of circuit-level non-idealities on vision-based autonomous driving
systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 962-969, Irvine CA, November 13-16 2017.
- [4823]
- C. Yu, H. Xiao, and
G. De Micheli.
Developing synthesis flows without human knowledge.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [4824]
- X. Yu and M. Abramovici.
Sequential circuit ATPG using combinational algorithms.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(8):1294-1310, August 2005.
- [4825]
- B. Yu and M. L. Bushnell.
A novel dynamic power cutoff technique (DPCT) for active leakage reduction in
deep submicron CMOS circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 214-219, Tegernsee, Germany, October 4-6 2006.
- [4826]
- H. Yu and L. He.
A provably passive and cost-efficient model for inductive interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(8):1283-1294, August 2005.
- [4827]
- Q. Yu and E. S. Kuh.
New efficient and accurate moment matching based model for crosstalk estimation
in coupled RC trees.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 151-157, San Jose, CA, March 26-28 2001.
- [4828]
- G. Yu and P. Li.
Yield-aware hierarchical optimization of large analog integrated circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 79-84, San Jose, CA, November 10-13 2008.
- [4829]
- G. Yu and P. Li.
Hierarchical analog/mixed-signal circuit optimization under process variations
and tuning.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(2):313-317, February 2011.
- [4830]
- Z. Yu and X. Liu.
Design of rotary clock based circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 43-48,
San Diego, CA, June 4-8 2007.
- [4831]
- T. Yu and M. D. F. Wong.
PGT SOLVER: an efficient solver for power grid transient analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 647-652, San Jose, CA, November 5-8 2012.
- [4832]
- L-P. Yuan, C-C.
Teng, and S-M. Kang.
Nonparametric estimation of average power dissipation in CMOS VLSI
circuits.
In IEEE 1996 Custom Integrated Circuits Conference, pages 225-228,
San Diego, CA, May 5-8 1996.
- [4833]
- L-P Yuan, C-C
Teng, and S-M Kang.
Statistical estimation of average power dissipation in CMOS VLSI circuits
using nonparametric techniques.
In International Symposium on Low Power Electronics and Design, pages
73-78, Monterey, CA, August 12-14 1996.
- [4834]
- L-P Yuan, C-C Teng,
and S-M Kang.
Statistical estimation of average power dissipation in sequential circuits.
In 34th Design Automation Conference, pages 377-382, Anaheim, CA,
June 9-13 1997.
- [4835]
- L.-P. Yuan, C.-C.
Teng, and S.-M. Kang.
Statistical estimation of average power dissipation using nonparametric
techniques.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(1):65-73, March 1998.
- [4836]
- J. Yuan, K. Albin,
A. Aziz, and C. Pixley.
Simplifying boolean constraint solving for random simulation-vector generation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 123-127, San Jose, CA, November 10-14 2002.
- [4837]
- J. Yuan, A. Aziz,
C. Pixley, and K. Albin.
Simplifying boolean constraint solving for random simulation-vector generation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(3):412-420, March 2004.
- [4838]
- L. Yuan,
S. Leventhal, and G. Qu.
Temperature-aware leakage minimization technique for real-time systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 761-764, San Jose, CA, November 5-9 2006.
- [4839]
- Y. Yuan and T. Chen.
The dynamic testing of combinational logic networks.
In IEEE 12th International Symposium on Fault Tolerant Computing,
pages 173-180, June 1982.
- [4840]
- L.-P. Yuan and S.-M. Kang.
A sequential procedure for average power analysis of sequential circuits.
In 1997 International Symposium on Low Power Electronics and Design,
pages 231-234, Monterey, CA, August 18-20 1997.
- [4841]
- F. Yuan and A. Opal.
An efficient transient analysis algorithm for mildly nonlinear circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(6):662-673, June 2002.
- [4842]
- L. Yuan and G. Qu.
Analysis of energy reduction on dynamic voltage scaling-enabled systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(12):1827-1837, December 2005.
- [4843]
- L. Yuan and G. Qu.
Enhanced leakage reduction technique by gate replacement.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 47-50,
Anaheim, CA, June 13-17 2005.
- [4844]
- L. Yuan and G. Qu.
A combined gate replacement and input vector control approach for leakage
current reduction.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(2):173-182, February 2006.
- [4845]
- L. Yuan and G. Qu.
Simultaneous input vector selection and dual threshold voltage assignment for
static leakage minimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 548-551, San Jose, CA, November 5-8 2007.
- [4846]
- F. Yuan and Q. Xu.
On timing-independent false path identification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 532-535, San Jose, CA, November 7-11 2010.
- [4847]
- R. Zafalon,
C. Guardiani, M. C. Rossi, and R. Rambaldi.
Forward power annotation on physical layout floor-plan.
In IEEE 1996 Custom Integrated Circuits Conference, pages 389-392,
San Diego, CA, May 5-8 1996.
- [4848]
- R. Zafalon,
M. Rossello, E. Macii, and M. Poncino.
Power macromodeling for a high quality RT-level power estimation.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 59-63, San Jose, CA, March 20-22 2000.
- [4849]
- M. Zaheer,
X. Li, and C. Gu.
MPME-DP: multi-population moment estimation via dirichlet process for
efficient validation of analog/mixed-signal circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 316-323, San Jose, CA, November 2-6 2014.
- [4850]
- V. Zakian.
Simplification of linear time-invariant systems by moment approximants.
International Journal of Control, 18(3):455-460, 1973.
- [4851]
- S. Zanella,
A. Nardi, A. Neviani, M. Quarantelli, S. Saxena, and C. Guardiani.
Analysis of the impact of process variations on clock skew.
IEEE Transactions on Semiconductor Manufacturing, 13(4):401-407,
November 2000.
- [4852]
- G. Zardalidis and I. G. Karafyllidis.
SECA: a new single-electron-circuit simulator.
IEEE Transactions on Circuits and Systems, 55(9):2774-2784, October
2008.
- [4853]
- P. Zarkesh-Ha, J. A. Davis, W. Loh, and J. D. Meindl.
On a pin versus gate relationship for heterogeneous systems: heterogeneous
rent's rule.
In IEEE Custom Integrated Circuits Conference, pages 93-96, Santa
Clara, CA, May 11-14 1998.
- [4854]
- P. Zarkesh-Ha, J. A. Davis, W. Loh, and J. D. Meindl.
Prediction of interconnect fan-out distribution using rent's rule.
In International Workshop on System-Level Interconnect Prediction,
pages 107-112, San Diego, CA, April 8-9 2000.
- [4855]
- E. Zeheb.
On solving the equation ax=b with more variables than unknowns.
IEEE Transactions on Circuits and Systems, 39(10):833-834, October
1992.
- [4856]
- J. Zeida and P. Frain.
General framework for removal of clock network pessimism.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 632-639, San Jose, CA, November 10-14 2002.
- [4857]
- A. Zemanian.
Delay-time bounds for on-chip and off-chip interconnection networks.
In IEEE International Symposium on Circuits and Systems (ISCAS), pages
2634-2637, 1990.
- [4858]
- J. Zeng, M. Abadir,
and J. Abraham.
False timing path identification using ATPG techniques and delay-based
estimation.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
562-565, New Orleans, LA, June 10-14 2002.
- [4859]
- Z. Zeng, X. Ye,
Z. Feng, and P. Li.
Tradeoff analysis and optimization of power delivery networks with on-chip
voltage regulation.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
831-836, Anaheim, CA, June 13-18 2010.
- [4860]
- Z. Zeng, T. Xu,
Z. Feng, and P. Li.
Fast static analysis of power grids: algorithms and implementations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 488-493, San Jose, CA, November 7-10 2011.
- [4861]
- Z. Zeng and P. Li.
Locality-driven parallel power grid optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(8):1190-1200, August 2009.
- [4862]
- J. Zeng.
Modeling and simulation of electrified droplets and its application to
computer-aided design of digital microfluidics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(2):224-233, February 2006.
- [4863]
- N.-E.
Zergainoh, L. Tambour, and A. Jerraya.
Automatic delay correction method for IP block-based design of VLSI
dedicated digital signal processing systems: theoretical foundations and
implementation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(4):349-360, April 2006.
- [4864]
- B. Zhai, D. Blaauw,
D. Sylvester, and K. Flautner.
Theoretical and practical limits of dynamic voltage scaling.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
868-873, San Diego, CA, June 7-11 2004.
- [4865]
- B. Zhai,
D. Blaauw, D. Sylvester, and K. Flautner.
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1239-1252, November 2005.
- [4866]
- B. Zhai, S. Hanson,
D. Blaauw, and D. Sylvester.
Analysis and mitigation of variability in subthreshold design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 20-25, San Diego, CA, August 8-10 2005.
- [4867]
- B. Zhai, R. G.
Dreslinski, D. Blaauw, T. Mudge, and D. Sylvester.
Energy efficient near-threshold chip multi-processing.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 32-37, Portland, Oregon, August 27-29 2007.
- [4868]
- R. Y. Zhan, H. G.
Feng, Q. Wu, G. Chen, X. K. Guan, and A. Z. Wang.
A technology-independent CAD tool for ESD protection device extraction -
esdextractor.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 510-513, San Jose, CA, November 10-14 2002.
- [4869]
- R. Zhan, H. Feng,
Q. Wu, H. Xie, X. Guan, G. Chen, and A. Z. H. Wang.
Esdextractor: a new technology-independent CAD tool for arbitrary ESD
protection device extraction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(10):1362-1370, October 2003.
- [4870]
- Y. Zhan, A. J.
Strojwas, X. Li, L. T. Pileggi, D. Newmark, and M. Sharma.
Correlation-aware statistical timing analysis with non-gaussian delay
distributions.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 77-82,
Anaheim, CA, June 13-17 2005.
- [4871]
- Y. Zhan, A. J.
Strojwas, M. Sharma, and D. Newmark.
Statistical critical path analysis considering correlations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 699-704, San Jose, CA, November 6-10 2005.
- [4872]
- Y. Zhan, T. Zhang,
and S. S. Sapatnekar.
Module assignment for pin-limited designs under the stacked-vdd paradigm.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 656-659, San Jose, CA, November 5-8 2007.
- [4873]
- X. Zhan, P. Li, and
E. Sanchez-Sinencio.
Distributed on-chip regulation: theoretical stability foundation, over-design
reduction and performance optimization.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [4874]
- Y. Zhan and S. S.
Sapatnekar.
A high efficiency full-chip thermal simulation algorithm.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 635-638, San Jose, CA, November 6-10 2005.
- [4875]
- Y. Zhan and S. S.
Sapatnekar.
High-efficiency green function-based thermal simulation algorithms.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(9):1661-1675, September 2007.
- [4876]
- H. Zhang,
V. George, and J. M. Rabaey.
Low-swing on-chip signaling techniques: effectiveness and robustness.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):264-272, June 2000.
- [4877]
- R. Zhang,
K. Roy, C.-K. Koh, and D. B. Janes.
Stochastic wire-length and delay distributions of 3-dimensional circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 208-213, San Jose, CA, November 5-9 2000.
- [4878]
- X. Zhang,
W. Shan, and K. Roy.
Low-power weighted random pattern testing.
IEEE Transactions on Computer-Aided Design, 19(11):1389-1398,
November 2000.
- [4879]
- Y. Zhang, J. Lach,
K. Skadron, and M. R. Stan.
Odd/even bus invert with two-phase transfer for buses with coupling.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 80-83, Monterey, California, August 12-14 2002.
- [4880]
- L. Zhang, Y. Hu,
and C.-C. Chen.
Statistical timing analysis in sequential circuit for on-chip global
interconnect pipelining.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
904-907, San Diego, CA, June 7-11 2004.
- [4881]
- S. Zhang,
V. Wason, and K. Banerjee.
A probabilistic framework to estimate full-chip subthreshold leakage power
distribution considering within-die and die-to-die P-T-V variations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 156-161, Newport Beach, CA, August 9-11 2004.
- [4882]
- L. Zhang,
W. Chen, Y. Hu, J. A. Gubner, and C. C.-P. Chen.
Correction-preserved non-gaussian statistical timing analysis with quadratic
timing model.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 83-88,
Anaheim, CA, June 13-17 2005.
- [4883]
- L. Zhang,
J. Wilson, R. Bashirullah, L. Luo, J. Xu, and P. Franzon.
Driver pre-emphasis techniques for on-chip global buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 186-191, San Diego, CA, August 8-10 2005.
- [4884]
- R. Zhang,
P. Gupta, L. Zhong, and N. K. Jha.
Threshold network synthesis and optimization and its application to
nanotechnologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):107-118, January 2005.
- [4885]
- B. Zhang,
A. Arapostathis, S. Nassif, and M. Orshansky.
Analytical modeling of SRAM dynamic stability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 315-322, San Jose, CA, November 5-9 2006.
- [4886]
- L. Zhang,
W. Chen, Y. Hu, and C. C.-P. Chen.
Statistical static timing analysis with conditional linear MAX/MIN
approximation and extended canonical timing model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(6):1183-1191, June 2006.
- [4887]
- L. Zhang,
W. Chen, Y. Hu, J. A. Gubner, and C.-C.-P. Chen.
Correlation-preserved statistical timing with a quadratic form of gaussian
variables.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2437-2449, November 2006.
- [4888]
- M. Zhang,
S. Mitra, T.-M. Mak, N. Seifert, N.-J. Wang, Q. Shi, K.-S. Kim, N. R.
Shanbhag, and R. J. Patel.
Sequential element design with built-in soft error resilience.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(12):1368-1378, December 2006.
- [4889]
- W. Zhang, N. K.
Jha, and L. Shang.
Nature: a hybrid nanotube/CMOS dynamically reconfigurable architecture.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
711-716, San Francisco, CA, July 24-28 2006.
- [4890]
- W. Zhang,
L. Shang, and N. K. Jha.
Nanomap: an integrated design optimization flow for a hybrid nanotube/CMOS
dynamically reconfigurable architecture.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
300-305, San Diego, CA, June 4-8 2007.
- [4891]
- L. Zhang,
A. Carpenter, B. Ciftcioglu, A. Garg, M. Huang, and H. Wu.
Injection-locked clocking: a low power clock distribution scheme for
high-performance microprocessors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(9):1251-1256, September 2008.
- [4892]
- H. Zhang, T.-H.
Chen, M.-Y. Ting, and X. Li.
Efficient design-specific worst-case corner extraction for integrated circuits.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
386-389, San Francisco, CA, July 26-31 2009.
- [4893]
- J. Zhang,
N. Patil, A. Hazeghi, and S. Mitra.
Carbon nanotube circuits in the presence of carbon nanotube density variations.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 71-76,
San Francisco, CA, July 26-31 2009.
- [4894]
- J. Zhang, N. P.
Patil, and S. Mitra.
Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital
logic circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(9):1307-1320, September 2009.
- [4895]
- W. Zhang, W. Yu,
X. Hu, L. Zhang, R. Shi, H. Peng, Z. Zhu, C.-E. Lew, R. Murgai, T. Shibuya,
N. Ito, and C.-K. Cheng.
Efficient power network analysis considering multidomain clock gating.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(9):1348-1358, September 2009.
- [4896]
- W. Zhang, T.-H.
Chen, M.-Y. Ting, and X. Li.
Toward efficient large-scale performance modeling of integrated circuits via
multi-mode/multi-corner sparse regression.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
897-902, Anaheim, CA, June 13-18 2010.
- [4897]
- W. Zhang, X. Li,
and R. A. Rutenbar.
Bayesian virtual probe: minimizing variation characterization cost for
nanoscale IC technologies via bayesian inference.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
262-267, Anaheim, CA, June 13-18 2010.
- [4898]
- Y. Zhang, P. Li,
and G. M. Huang.
Separatrices in high-dimensional state space: system-theoretical tangent
computation and application to SRAM dynamic stability analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
567-572, Anaheim, CA, June 13-18 2010.
- [4899]
- J. Zhang, N. P.
Patil, A. Hazeghi, H.-S.-P. Wong, and S. Mitra.
Characterization and design of logic circuits in the presence of carbon
nanotube density variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(8):1103-1113, August 2011.
- [4900]
- W. Zhang,
K. Balakrishnan, X. Li, D. Boning, and R. Rutenbar.
Toward efficient spatial variation decomposition via sparse regression.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 162-169, San Jose, CA, November 7-10 2011.
- [4901]
- W. Zhang, X. Li,
F. Liu, E. Acar, R. A. Rutenbar, and R. D. Blanton.
Virtual probe: a statistical framework for low-cost silicon characterization of
nanoscale integrated circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(12):1814-1827, December 2011.
- [4902]
- Y. Zhang,
X. Wang, and Y. Chen.
STT-RAM cell design optimization for persistent and non-persistent error
rate reduction: a statistical design view.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 471-477, San Jose, CA, November 7-10 2011.
- [4903]
- Z. Zhang, I. M.
Elfadel, and L. Daniel.
Model order reduction of fully parameterized systems by recursive least square
optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 523-530, San Jose, CA, November 7-10 2011.
- [4904]
- J. Zhang, A. Lin,
N. Patil, H. Wei, L. Wei, H.-S.-P. Wong, and S. Mitra.
Robust digital VLSI using carbon nanotubes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):453-471, April 2012.
- [4905]
- W. Zhang,
A. Singhee, J. Xiong, P. Habitz, A. Joshi, C. Visweswariah, and J. Sundquist.
A dynamic method for efficient random mismatch characterization of standard
cells.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 180-186, San Jose, CA, November 5-8 2012.
- [4906]
- J. Zhang,
F. Yuan, R. Ye, and Q. Xu.
Forter: a forward error correction scheme for timing error resilience.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 55-60, San Jose, CA, November 18-21 2013.
- [4907]
- W. Zhang,
K. Balakrishnan, X. Li, D. S. Boning, S. Saxena, A. Strojwas, and R. A.
Rutenbar.
Efficient spatial pattern analysis for variation decomposition via robust
sparse regression.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(7):1072-1085, July 2013.
- [4908]
- W. Zhang, X. Li,
S. Saxena, A. Strojwas, and R. Rutenbar.
Automatic clustering of wafer spatial signatures.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [4909]
- Y. Zhang,
I. Bayram, Y. Wang, H. Li, and Y. Chen.
ADAMS: asymmetric differential STT-RAM cell structure for reliable and
high-performance applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 9-16, San Jose, CA, November 18-21 2013.
- [4910]
- Z. Zhang, T. A.
El-Moselhy, I. M. Elkfadel, and L. Daniel.
Stochastic testing method for transistor-level uncertainty quantification based
on generalized polynomial chaos.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1533-1545, October 2013.
- [4911]
- Z. Zhang, I. M.
Elfadel, and L. Daniel.
Uncertainty quantification for integrated circuits: stochastic spectral
methods.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 803-810, San Jose, CA, November 18-21 2013.
- [4912]
- Z. Zhang, T. A.
El-Moselhy, I. M. Elfadel, and L. Daniel.
Calculation of generalized polynomial-chaos basis functions and gauss
quadrature rules in hierarchical uncertainty quantification.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(5):728-740, May 2014.
- [4913]
- Q. Zhang,
Y. Tian, T. Wang, F. Yuan, and Q. Xu.
Approxeigen: an approximate computing technique for large-scale
eigen-decomposition.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 824-830, Austin, TX, November 2-6 2015.
- [4914]
- R. Zhang,
K. Mazumdar, B. H. Meyer, K. Wang, K. Skadron, and M. R. Stan.
Transient voltage noise in charge-recycled power delivery networks for
many-layer 3d-IC.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 152-158, Rome, Italy, July 22-24 2015.
- [4915]
- G.-L. Zhang,
B. Li, and U. Schlichtmann.
Piecetimer: a holistic timing analysis framework considering setup/hold time
interdependency using a piecewise model.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin, TX, November 7-10 2016.
- [4916]
- X. Zhang,
A. Ramachandran, and C. Zhuge.
Machine learning on fpgas to face the iot revolution.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 894-901, Irvine CA, November 13-16 2017.
- [4917]
- Z. Zhang,
K. Batselier, H. Liu, L. Daniel, and N. Wong.
Tensor computation: a new framework for high-dimensional problems in EDA.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(4):521-536, April 2017.
- [4918]
- G.-L. Zhang,
B. Li, M. Hashimoto, and U. Schlichtmann.
Virtualsync: timing optimization by synchronizing logic waves with sequential
and combinational components as delay units.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [4919]
- W. Zhang,
H. Huang, J. Zhang, M. Jiang, and G. Luo.
Adaptive-precision framework for SGD using deep Q-learning.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [4920]
- Y. Zhang and C. Chu.
Fast and effective placement refinement for routability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(9):1751-1756, September 2013.
- [4921]
- X. Zhang and A. Louri.
A multilayer nanophotonic interconnection network for on-chip many-core
communications.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
156-161, Anaheim, CA, June 13-18 2010.
- [4922]
- H. Zhang and J. Rabaey.
Low-swing interconnect interface circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 161-166, Monterey, CA, August 10-12 1998.
- [4923]
- M. Zhang and N. R.
Shanbhag.
A soft error rate analysis (SERA) methodology.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 111-118, San Jose, CA, November 7-11 2004.
- [4924]
- M. Zhang and N. R.
Shanbhag.
Soft-error-rate-analysis (SERA) methodology.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2140-2155, October 2006.
- [4925]
- Z-Y Zhao, Q-M Zhang,
G-L Tan, and J. M. Xu.
A new preconditioner for CGS iteration in solving large sparse nonsymmetric
linear equations in semiconductor device simulation.
IEEE Transactions on Computer-Aided Design, 10(11):1432-1440,
November 1991.
- [4926]
- M. Zhao, R. V.
Panda, S. S. Sapatnekar, T. Edwards, R. Chaudhry, and D. Blaauw.
Hierarchical analysis of power distribution networks.
In Design Automation Conference, pages 150-155, Los Angeles, CA, June
5-9 2000.
- [4927]
- S. Zhao, K. Roy,
and C.-K. Koh.
Frequency domain analysis of switching noise on power supply network.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 487-492, San Jose, CA, November 5-9 2000.
- [4928]
- M. Zhao, R. V.
Panda, S. S. Sapatnekar, and D. Blaauw.
Hierarchical analysis of power distribution networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(2):159-168, February 2002.
- [4929]
- S. Zhao, K. Roy,
and C.-K. Koh.
Decoupling capacitance allocation and its application to power-supply
noise-aware floorplanning.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(1):81-92, January 2002.
- [4930]
- M. Zhao, Y. Fu,
V. Zolotov, S. Sundarewsaran, and R. Panda.
Optimal placement of power supply pads and pins.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
165-170, San Diego, CA, June 7-11 2004.
- [4931]
- P. Zhao, T. K.
Darwish, and M. A. Bayoumi.
High-performance and low-power conditional discharge flip-flop.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):477-484, May 2004.
- [4932]
- S. Zhao, B. Yao,
H. Chen, Y. Zhu, C.-K. Cheng, M. Hutton, T. Collins, S. Srinivasan, N. Chou,
and P. Suaris.
Improving the efficiency of static timing analysis with false paths.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 527-531, San Jose, CA, November 6-10 2005.
- [4933]
- D. Zhao,
S. Upadhyaya, and M. Margala.
Design of a wireless test control network with radio-on-chip technology for
nanometer system-on-a-chip.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1411-1418, July 2006.
- [4934]
- M. Zhao, Y. Fu,
V. Zolotov, S. Sundareswaran, and R. Panda.
Optimal placement of power-supply pads and pins.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):144-154, January 2006.
- [4935]
- M. Zhao, R. Panda,
S. Sundareswaran, S. Yan, and Y. Fu.
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling
and linear programming.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
217-222, San Francisco, CA, July 24-28 2006.
- [4936]
- M. Zhao, R. Panda,
B. Reschke, Y. Fu, T. Mewett, S. Chandrasekaran, S. Sundareswaran, and
S. Yan.
On-chip decoupling capacitance and PIG wire co-optimization for dynamic
noise.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
162-167, San Diego, CA, June 4-8 2007.
- [4937]
- C. Zhao, Y. Zhao,
and S. Dey.
Intelligent robustness insertion for optimal transient error tolerance
improvement in VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(6):714-724, June 2008.
- [4938]
- J. Zhao,
S. Madduri, R. Vadlamani, W. Burleson, and R. Tessier.
A dedicated monitoring infrastructure for multicore processors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(6):1011-1022, June 2011.
- [4939]
- X. Zhao, J. Wang,
Z. Feng, and S. Hu.
Power grid analysis with hierarchical support graphs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 543-547, San Jose, CA, November 7-10 2011.
- [4940]
- X. Zhao, J. R.
Tolbert, S. Mukhopadhyay, and S.-K. Lim.
Variation-aware clock network design methodology for ultralow voltage (ULV)
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(8):1222-1234, August 2012.
- [4941]
- X. Zhao, Y. Wan,
M. Scheuermann, and S.-K. Lim.
Transient modeling of TSV-wire electromigration and lifetime analysis of
power distribution network for 3d ics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 363-370, San Jose, CA, November 18-21 2013.
- [4942]
- X. Zhao, Z. Feng,
and C. Zhuo.
An efficient spectral graph sparsification approach to scalable reduction of
large flip-chip power grids.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 218-223, San Jose, CA, November 2-6 2014.
- [4943]
- X. Zhao, L. Han, and
Z. Feng.
A performance-guided graph sparsification approach to scalable and robust
SPICE-accurate integrated circuit simulations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(10):1639-1651, October 2015.
- [4944]
- Z. Zhao, Y. Wang,
and Z. Feng.
SAMG: sparsified graph-theoretic algebraic multigrid for solving large
symmetric diagonally dominant (SDD) matrices.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 601-606, Irvine CA, November 13-16 2017.
- [4945]
- Y. Zhao and S. Dey.
Fault-coverage analysis techniques of crosstalk in chip interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(6):770-782, June 2003.
- [4946]
- X. Zhao and Z. Feng.
GPSCP: A general-purpose support-circuit preconditioning approach to
large-scale SPICE-accurate nonlinear circuit simulations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 429-435, San Jose, CA, November 5-8 2012.
- [4947]
- X. Zhao and Z. Feng.
Towards efficient SPICE-accurate nonlinear circuit simulation with on-the-fly
support-circuit preconditioners.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1119-1124, San Francisco, CA, June 3-7 2012.
- [4948]
- M. Zhao and S. S.
Sapatnekar.
Technology mapping for domino logic.
In IEEE/ACM International Conference on Computer-Aided Design, pages
248-251, San Jose, CA, November 8-12 1998.
- [4949]
- M. Zhao and S. S.
Sapatnekar.
Timing-driven partitioning and timing optimization of mixed static-domino
implementations.
IEEE Transactions on Computer-Aided Design, 19(11):1322-1336,
November 2000.
- [4950]
- H. Zhao and S. Tan.
Multi-physics-based FEM analysis for post-voiding analysis of
electromigration failure effects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [4951]
- H. Zhao and S. X.-D. Tan.
Postvoiding FEM analysis for electromigration failure characterization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
26(11):2483-2493, November 2018.
- [4952]
- H. Zheng,
B. Krauter, and L. Pileggi.
Electrical modeling of integrated-package power and ground distributions.
IEEE Design & Test of Computers, pages 24-31, May-June 2003.
- [4953]
- R. Zheng, J. Suh,
C. Xu, N. Hakim, B. Bakkaloglu, and Y. Cao.
Programmable analog device array (PANDA): a platform for transistor-level
analog reconfigurability.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
322-327, San Diego, CA, June 5-9 2011.
- [4954]
- L. Zheng, S. Shin,
and S.-M.-S. Kang.
Modular structure of compact model for memristive devices.
IEEE Transactions on Circuits and Systems, 61(5):1390-1399, May
2014.
- [4955]
- H. Zheng and L. T.
Pileggi.
Modeling and analysis of regular symmetrically structured power/ground
distribution networks.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
395-398, New Orleans, LA, June 10-14 2002.
- [4956]
- H. Zheng and L. T.
Pileggi.
Robust and passive model order reduction for circuits containing susceptance
elements.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 761-766, San Jose, CA, November 10-14 2002.
- [4957]
- G. Zhong, C.-K.
Yoh, and K. Roy.
A twisted-bundle layout structure for minimizing inductive coupling noise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 406-411, San Jose, CA, November 5-9 2000.
- [4958]
- G. Zhong, C.-K.
Koh, and K. Roy.
On-chip interconnect modeling by wire duplication.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 341-346, San Jose, CA, November 10-14 2002.
- [4959]
- G. Zhong, C.-K.
Koh, and K. Roy.
On-chip interconnect modeling by wire duplication.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(11):1521-1532, November 2003.
- [4960]
- L. Zhong, S. Ravi,
A. Raghunathan, and N. K. Jha.
Power estimation for cycle-accurate functional descriptions of hardware.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 668-675, San Jose, CA, November 7-11 2004.
- [4961]
- L. Zhong, S. Ravi,
A. Raghunathan, and N. K. Jha.
RTL-aware cycle-accurate functional power estimation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2103-2117, October 2006.
- [4962]
- L. Zhong and N. K. Jha.
Interconnect-aware high-level synthesis for low power.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 110-117, San Jose, CA, November 10-14 2002.
- [4963]
- Y. Zhong and M. D.-F. Wong.
Fast algorithms for IR drop analysis in large power grid.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 351-357, San Jose, CA, November 6-10 2005.
- [4964]
- D. Zhou, N. Chen,
and W. Cai.
A fast wavelet collocation method for high-speed VLSI circuit.
In IEEE/ACM International Conference on Computer-Aided Design, pages
115-122, San Jose, CA, November 5-9 1995.
- [4965]
- H. Zhou, N. Shenoy,
and W. Nicholls.
Timing analysis with crosstalk as fixpoints on complete lattice.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
714-719, Las Vegas, NV, June 18-22 2001.
- [4966]
- S. Zhou, Y. Zhu,
Y. Hu, R. Graham, M. Hutton, and C.-K. Cheng.
Timing model reduction for hierarchical timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 415-422, San Jose, CA, November 5-9 2006.
- [4967]
- Q. Zhou, L. Zhong,
and K. Mohanram.
Power signal processing: a new perspective for power analysis and optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 165-170, Portland, Oregon, August 27-29 2007.
- [4968]
- S. Zhou, B. Yao,
H. Chen, Y. Zhu, M. Hutton, T. Collins, S. Srinivasan, N.-C. Chou, P. Suaris,
and C.-K. Cheng.
Efficient timing analysis with known false paths using biclique covering.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(5):959-969, May 2007.
- [4969]
- Y. Zhou,
S. Thekkei, and S. Bhunia.
Low power FPGA design using hybrid CMOS-NEMS approach.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 14-19, Portland, Oregon, August 27-29 2007.
- [4970]
- T.-Y. Zhou, H. Liu,
D. Zhou, and T. Tarim.
A fast analog circuit analysis algorithm for design modification and
verification.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(2):308-313, February 2011.
- [4971]
- Y. Zhou, E. Gad,
M. S. Nakhla, and R. Achar.
Structural characterization and efficient implementation techniques for
A-stable high-order integration methods.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(1):101-108, January 2012.
- [4972]
- H. Zhou, H. Zhu,
T. Cui, D.-Z. Pan, D. Zhou, and X. Zeng.
Thermal stress and reliability analysis of TSV-based 3-D ics with a novel
adaptive strategy finite element method.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
26(7):1312-1325, July 2018.
- [4973]
- H. Zhou and C. Lin.
Retiming for wire pipelining in system-on-chip.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1338-1345, September 2004.
- [4974]
- Q. Zhou and K. Mohanram.
Cost-effective radiation hardening technique for combinational logic.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 100-106, San Jose, CA, November 7-11 2004.
- [4975]
- Q. Zhou and
K. Mohanram.
Elmore model for energy estimation in RC trees.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
965-970, San Francisco, CA, July 24-28 2006.
- [4976]
- Z. Zhou and K. Mohanram.
Gate sizing to radiation harden combinational logic.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):155-166, January 2006.
- [4977]
- T.-Y. Zhou and G. Wan.
A practical SOC simulation verification solution: robust design and automatic
modeling.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 89-92, Montreal, Quebec, June 20-23 2004.
- [4978]
- H. Zhou and D. F. Wong.
An exact gate decomposition algorithm for low-power technology mapping.
In IEEE/ACM International Conference on Computer-Aided Design, pages
575-580, San Jose, CA, November 9-13 1997.
- [4979]
- H. Zhou.
Timing analysis with crosstalk is a fixpoint on a complete lattice.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(9):1261-1269, September 2003.
- [4980]
- Z. Zhu, B. Yao, and
C.-K. Cheng.
Power network analysis using an adaptive algebraic multigrid approach.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
105-108, Anaheim, CA, June 2-6 2003.
- [4981]
- Z. Zhu, B. Song, and
J. K. White.
Algorithms in fastimp: a fast and wide band impedance extraction program for
complicated 3-D geometries.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):981-998, July 2005.
- [4982]
- X.-L. Zhu, X.-D.
Zhang, Z.-Z. Ding, and Y. Jia.
Adaptive nonlinear PCA algorithms for blind source separation without
prewhitening.
IEEE Transactions on Circuits and Systems, 53(3):745-753, March
2006.
- [4983]
- C. Zhu, Z. (Peter)
Gu, L. Shang, R. P. Dick, and R. G. Knobel.
Towards an ultra-low-power architecture using single-electron tunneling
transistors.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
312-317, San Diego, CA, June 4-8 2007.
- [4984]
- Z. Zhu, H. Peng,
C.-K. Cheng, K. Rouz, M. Borah, and E.-S. Kuh.
Two-stage newton-raphson method for transistor-level simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(5):881-895, May 2007.
- [4985]
- H. Zhu, Y. Wang,
F. Liu, X. Li, X. Zeng, and P. Feldmann.
Efficient transient analysis of power delivery network with clock/power gating
by sparse approximation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(3):409-421, March 2015.
- [4986]
- D. Zhu, S. Yu RA N.
Chang, and M. Pedram.
Toward a profitable grid-connected hybrid electrical energy storage system for
residential use.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(7):1151-1164, July 2016.
- [4987]
- W. Zhu, Z. Huang,
J. Chen, and Y.-W. Chang.
Analytical solution of poisson's equation and its application to VLSI global
placement.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
San Diego, CA, November 5-8 2018.
- [4988]
- J. Zhu and S. Calman.
Context sensitive symbolic pointer analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(4):516-531, April 2005.
- [4989]
- J. Zhu and D. D. Gajski.
An ultra-fast instruction set simulator.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):363-373, June 2002.
- [4990]
- N. Zhu and H.-Y. Koh.
Power grid modeling techniques for hierarchical power network analysis.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 313-318, San Jose, CA, March 26-28 2001.
- [4991]
- Z. Zhu and J. Phillips.
Random sampling of moment graph: a stochastic krylov-reduction algorithm.
Design, Automation and Test in Europe (DATE-07), pages 1502-1507,
April 16-20 2007.
- [4992]
- Y. Zhu and S.-X.-D. Tan.
GPU-accelerated parallel monte carlo analysis of analog circuits by
hierarchical graph-based solver.
In 20th Asia and South Pacific Design Automation Conference, pages
719-724, Chiba/Tokyo, Japan, January 19-22 2015.
- [4993]
- Z. Zhu and J. White.
Fastsies: a fast stochastic integral equation solver for modeling the rough
surface effect.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 675-682, San Jose, CA, November 6-10 2005.
- [4994]
- Y. Zhu and J. Xiong.
Modern big data analytics for old-fashioned semiconductor industry
applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 776-780, Austin, TX, November 2-6 2015.
- [4995]
- J. Zhu.
Symbolic pointer analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 150-157, San Jose, CA, November 10-14 2002.
- [4996]
- H. Zhuang, S.-H.
Weng, J.-H. Lin, and C.-K. Cheng.
MATEX: a distributed framework for transient simulation of power distribution
networks.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [4997]
- H. Zhuang,
W. Yu, I. Kang, X. Wang, and C.-K. Cheng.
An algorithmic framework for efficient large-scale circuit simulation using
exponential integrators.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4998]
- H. Zhuang,
W. Yu, S.-H. Weng, I. Kang, J.-H. Lin, X. Zhang, R. Coutts, and C.-K. Cheng.
Simulation algorithms with exponential integration for time-domain analysis of
large-scale power delivery networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(10):1681-1693, October 2016.
- [4999]
- C. Zhuo, J. Hu,
M. Zhao, and K. Chen.
Fast decap allocation based on algebraic multigrid.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 107-111, San Jose, CA, November 5-9 2006.
- [5000]
- C. Zhuo, J. Hu,
M. Zhao, and K. Chen.
Power grid analysis and optimization using algebraic multigrid.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(4):738-751, April 2008.
- [5001]
- C. Zhuo, D. Blaauw,
and D. Sylvester.
Post-fabrication measurement-driven oxide breakdown reliability prediction and
management.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 441-448, San Jose, CA, November 2-5 2009.
- [5002]
- C. Zhuo, K. Chopra,
D. Sylvester, and D. Blaauw.
Process variation and temperature-aware full chip oxide breakdown reliability
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(9):1321-1334, September 2011.
- [5003]
- C. Zhuo, G. Wilke,
R. Chakraborty, A. Aydiner, S. Chakravarty, and W.-K. Shih.
A silicon-validated methodology for power delivery modeling and simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 255-262, San Jose, CA, November 5-8 2012.
- [5004]
- C. Zhuo,
D. Sylvester, and D. Blaauw.
A statistical framework for post-fabrication oxide breakdown reliability
prediction and management.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(4):630-643, April 2013.
- [5005]
- C. Zhuo, H. Gan, and
W.-K. Shih.
Early-stage power grid design: extraction, modeling and optimization.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [5006]
- C. Zhuo, G. Wilke,
R. Chatraborty, A. A. Aydiner, S. Chakravarty, and W.-K. Shih.
Silicon-validated power delivery modeling and analysis on a 32-nm DDR I/O
interface.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(9):1760-1771, September 2015.
- [5007]
- C. Zhuo, K. Unda,
Y. Shi, and W.-K. Shih.
A novel cross-layer framework for early-stage power delivery and architecture
co-exploration.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [5008]
- A. Ziabari,
J.-H. Park, E. K. Ardestani, J. Renau, S.-M. Kang, and A. Shakouri.
Power blurring: fast static and transient thermal analysis method for packaged
integrated circuits and power devices.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(11):2366-2379, November 2014.
- [5009]
- C. H. Ziesler,
J. Kim, V. S. Sathe, and M. C. Papaefthymiou.
A 225 mhz resonant clocked ASIC chip.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 48-53, Seoul, Korea, August 25-27 2003.
- [5010]
- A. Zjajo, Q. Tang,
M. Berkelaar, J. P. de Gyvez, A. Di Bucchianico, and N. van der Meijs.
Stochastic analysis of deep-submicrometer CMOS process for reliable circuits
designs.
IEEE Transactions on Circuits and Systems, 58(1):164-175, January
2011.
- [5011]
- J. G. Zola.
Simple model of metal oxide varistor for pspice simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(10):1491-1494, October 2004.
- [5012]
- V. Zolotov,
D. Blaauw, R. Panda, and C. Oh.
Noise injection and propagation in high performance designs.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 425-430, San Jose, CA, March 18-21 2002.
- [5013]
- V. Zolotov,
D. Blaauw, S. Sirichotiyakul, M. Becer, C. Oh, R. Panda, A. Grinshpon, and
R. Levy.
Noise propagation and failure criteria for VLSI designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 587-594, San Jose, CA, November 10-14 2002.
- [5014]
- V. Zolotov,
J. Xiong, S. Abbaspour, D. J. Hathaway, and C. Visweswariah.
Compact modeling of variational waveforms.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 705-712, San Jose, CA, November 5-8 2007.
- [5015]
- V. Zolotov,
J. Xiong, H. Fatemi, and C. Visweswariah.
Statistical path selection for at-speed test.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 624-631, San Jose, CA, November 10-13 2008.
- [5016]
- V. Zolotov,
C. Visweswariah, and J. Xiong.
Voltage binning under process variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 425-432, San Jose, CA, November 2-5 2009.
- [5017]
- V. Zolotov,
J. Xiong, H. Fatemi, and C. Visweswariah.
Statistical path selection for at-speed test.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(5):749-759, May 2010.
- [5018]
- V. Zolotov,
D. Sinha, J. Hemmett, E. Foreman, C. Visweswariah, J. Xiong, J. Leitzen, and
N. Venkateswaran.
Timing analysis with nonseparable statistical and deterministic variations.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1061-1066, San Francisco, CA, June 3-7 2012.
- [5019]
- V. Zolotov and
P. Feldmann.
Variation aware cross-talk aggressor alignment by mixed integer linear
programming.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [5020]
- V. Zolotov and
J. Xiong.
Optimal statistical chip disposition.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 95-102, San Jose, CA, November 7-10 2011.
- [5021]
- Y. Zorian,
S. Dey, and M. J. Rodgers.
Test of future system-on-chips.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 392-398, San Jose, CA, November 5-9 2000.
- [5022]
- A. Zou, J. Leng,
X. He, Y. Zu, V. J. Reddi, and X. Zhang.
Efficient and reliable power delivery in voltage-stacked manycore system with
hybrid charge-recycling regulators.
In ACM/IEEE 54th Design Automation Conference (DAC-2018), San
Francisco, California, June 24-28 2018.
- [5023]
- P. Zuber,
P. Dobrovolny, and M. Miranda.
A holistic approach for statistical SRAM analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
717-722, Anaheim, CA, June 13-18 2010.
- [5024]
- P. S.
Zuchowski, C. B. Reynolds, R. J. Grupp, S. G. Davis, B. Cremen, and
B. Troxel.
A hybrid ASIC and FPGA architecture.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 187-194, San Jose, CA, November 10-14 2002.
- [5025]
- P. S.
Zuchowski, P. A. Habitz, J. D. Hayes, and J. H. Oppold.
Process and environmental variation impacts on ASIC timing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 336-342, San Jose, CA, November 7-11 2004.
- [5026]
- C. A. Zukowski.
Relaxing bounds for linear RC mesh circuits.
IEEE Transactions on Computer-Aided Design, CAD-5(2):305-312, April
1986.
- [5027]
- V. Zyuban and P. Kogge.
The energy complexity of register files.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 305-310, Monterey, CA, August 10-12 1998.
- [5028]
- V. Zyuban and P. Kogge.
Application of STD to latch-power estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
7(1):111-115, March 1999.
- [5029]
- V. Zyuban and P. Kogge.
Optimization of high-performance superscalar architectures for energy
efficiency.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 84-89, Italy, July 26-27 2000.
- [5030]
- V. Zyuban and
D. Meltzer.
Clocking strategies and scannable latches for low power applications.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 346-351, Huntington Beach, California, August 6-7
2001.
- [5031]
- V. Zyuban and
P. Strenski.
Unified methodology for resolving power-performance tradeoffs at the
microarchitectural and circuit levels.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 166-171, Monterey, California, August 12-14 2002.
- [5032]
- V. Zyuban.
Optimization of scannable latches for low energy.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(5):778-788, October 2003.
- [1]
- K. V.
Aadithya, A. Demir, S. Venugopalan, and J. Roychowdhury.
Accurate prediction of random telegraph noise effects in srams and drams.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):73-86, January 2013.
- [2]
- K. Aadithya
and J. Roychowdhury.
Dae2fsm: automatic generation of accurate discrete-time logical abstractions
for continuous-time circuit dynamics.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
311-316, San Francisco, CA, June 3-7 2012.
- [3]
- J. Aarestad,
C. Lamech, J. Plusquellic, D. Acharyya, and K. Agarwal.
Characterizing within-die and die-to-die delay variations introduced by process
variations and SOI history effect.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
534-539, San Diego, CA, June 5-9 2011.
- [4]
- C. Ababei and
K. Bazargan.
Placement method targeting predictability robustness and performance.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 81-85, San Jose, CA, November 9-13 2003.
- [5]
- W. Abadeer and
W. Ellis.
Behavior of NBTI under AC dynamic circuit conditions.
In International Reliability Physics Symposium (IRPS), pages 17-22,
Dallas, TX, March 30-April 4 2003.
- [6]
- A. Abbasinasab and M. Marek-Sadowska.
Blech effect in interconnects: applications and design guidelines.
In ACM International Symposium on Physical Design 2015, pages
111-118, Monterey, California, March 29 - April 1 2015.
- [7]
- S. Abbaspour, M. Pedram, A. Ajami, and C. Kashyap.
Fast interconnect and gate timing analysis for performance optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(12):1383-1388, December 2006.
- [8]
- S. Abbaspour, R. Banerji, P. Feldmann, and D. D. Ling.
Efficient variational interconnect modeling for statistical timing analysis by
combined sensitivity analysis and model-order reduction.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 86-91, Austin, Texas,
February 26-27 2007.
- [9]
- S. Abbaspour, H. Fatemi, and M. Pedram.
Parametrized non-gaussian variational gate timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(8):1495-1508, August 2007.
- [10]
- R. A. Abdallah
and N. R. Shanbhag.
Reducing energy at the minimum energy operating point via statistical error
compensation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(6):1328-1337, June 2014.
- [11]
- S. Abdel-Hafeez and A. Gordon-Ross.
A digital CMOS parallel counter architecture based on state look-ahead logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(6):1023-1033, June 2011.
- [12]
- R. Abdel-Khalek and V. Bertacco.
Functional post-silicon diagnosis and debug for networks-on-chip.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 557-563, San Jose, CA, November 5-8 2012.
- [13]
- A. Abdollahi, F. Fallah, and M. Pedram.
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 213-218, Monterey, California, August 12-14 2002.
- [14]
- A. Abdollahi, F. Fallah, and M. Pedram.
Leakage current reduction in sequential circuits by modifying the scan chains.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 49-54, San Jose, CA, March 24-26 2003.
- [15]
- A. Abdollahi, F. Fallah, and M. Pedram.
Leakage current reduction in CMOS VLSI circuits by input vector control.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(2):140-154, February 2004.
- [16]
- A. Abdollahi, F. Fallah, and M. Pedram.
An effective power mode transition technique in MTCMOS circuits.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 37-42,
Anaheim, CA, June 13-17 2005.
- [17]
- A. Abdollahi and
M. Pedram.
A new canonical form for fast boolean matching in logic synthesis and
verification.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
379-384, Anaheim, CA, June 13-17 2005.
- [18]
- A. Abdollahi.
Probabilistic decision diagrams for exact probabilistic analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 266-272, San Jose, CA, November 5-8 2007.
- [19]
- A. Abel and J. Reineke.
MEMIN: SAT-based exact minimization of incompletely specified mealy
machines.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 94-101, Austin TX, November 2-6 2015.
- [20]
- Abhishek and F. N.
Najm.
Incremental power grid verification.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
151-156, San Francisco, CA, June 3-7 2012.
- [21]
- A. I.
Abou-Seido, B. Nowak, and C. Chu.
Fitted elmore delay: a simple and accurate interconnect delay model.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(7):691-696, July 2004.
- [22]
- J. A. Abraham and
W. K. Fuchs.
Fault and error models for VLSI.
In Proceedings of the IEEE, pages 639-654, May 1986.
Published as Proceedings of the IEEE, volume 74, number 5.
- [23]
- J. A. Abraham and H-C.
Shih.
Testing of MOS VLSI circuits.
In International Symposium on Circuits and Systems, Kyoto, Japan, June
5-7 1985.
- [24]
- J. Abraham.
Power calculation and modeling in deep submicron.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 124-126, Monterey, CA, August 10-12 1998.
- [25]
- M. Abramovici, M. A. Breuer, and A. D. Friedman.
Digital Systems Testing and Testable Design.
Computer Science Press, New York, NY, 1990.
- [26]
- H. Abrishami, S. Hatami, and M. Pedram.
Design and multicorner optimization of the energy-delay product of CMOS
flip-flops under the negative bias temperature instability effect.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):869-881, June 2013.
- [27]
- M. H.
Abu-Rahma, K. Chowdhury, J. Wang, Z. Chen, S.-S. Yoon, and M. Anis.
A methodology for statistical estimation of read access yield in srams.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
205-210, Anaheim, CA, June 8-13 2008.
- [28]
- M. H.
Abu-Rahma, M. Anis, and S.-S. Yoon.
Reducing SRAM power using fine-grained wordline pulsewidth control.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(3):356-364, March 2010.
- [29]
- M. H. Abu-Rahma and
M. Anis.
A statistical design-oriented delay variation model accounting for within-die
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(11):1983-1995, November 2008.
- [30]
- Y. Abulafia and
A. Kornfeld.
Estimation of FMAX and ISB in microprocessors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(10):1205-1209, October 2005.
- [31]
- M. Abusultan and
S. P. Khatri.
A flash-based digital circuit design flow.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [32]
- E. Acar, S. Nassif,
Y. Liu, and L. T. Pileggi.
Assessment of true worst case circuit performance under interconnect parameter
variations.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 431-436, San Jose, CA, March 26-28 2001.
- [33]
- E. Acar, F. Dartu,
and L. Pileggi.
TETA: Transistor-level waveform evaluation for timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(5):605-616, May 2002.
- [34]
- E. Acar,
S. Nassif, Y. Liu, and L. T. Pileggi.
Time-domain simulation of variational interconnect models.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 419-424, San Jose, CA, March 18-21 2002.
- [35]
- E. Acar, A. Devgan,
R. Rao, F. Liu, H. Su, S. Nassif, and J. Burns.
Leakage and leakage sensitivity computation for combinational circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 96-99, Seoul, Korea, August 25-27 2003.
- [36]
- V. Acary,
O. Bonnefon, and B. Brogliato.
Time-stepping numerical simulation of switched circuits within the nonsmooth
dynamical systems approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(7):1042-1055, July 2010.
- [37]
- G. Acciani,
D. Congedo, and B. Dilecce.
Improving the computational efficiency of the tree relaxation method for an
iterative solution of linear circuit equations.
IEEE Transactions on Computer-Aided Design, 10(5):668-670, May
1991.
- [38]
- R. Achar, M. S.
Nakhla, H. S. Dhindsa, A. R. Sridhar, D. Paul, and N. M. Nakhla.
Parallel and scalable transient simulator for power grids via waveform
relaxation (PTS-PWR).
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(2):319-332, February 2011.
- [39]
- B. D. Ackland and
R. A. Clark.
Event-EMU : an event driven timing simulator for MOS VLSI circuits.
In IEEE International Conference on Computer-Aided Design, pages
80-83, 1989.
- [40]
- B. Ackland and
C. Nicol.
High performance dsps - what's hot and what's not?
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 1-6, Monterey, CA, August 10-12 1998.
- [41]
- T. Addabbo,
A. Fort, L. Kocarev, S. Rocchi, and V. Vignoli.
Pseudo-chaotic lossy compressors for true random number generation.
IEEE Transactions on Circuits and Systems, 58(8):1897-1909, August
2011.
- [42]
- A. Adir, A. Nahir,
G. Shurek, A. Ziv, C. Meissner, and J. Schumann.
Leveraging pre-silicon verification resources for the post-silicon validation
of the IBM power7 processor.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
569-574, San Diego, CA, June 5-9 2011.
- [43]
- D. Adler.
SIMMOS: a multiple-delay switch-level simulator.
In 23rd ACM/IEEE Design Automation Conference, pages 159-163, Las
Vegas, NV, June 29 - July 2 1986.
- [44]
- D. Adler.
A dynamically-directed switch model for MOS logic simulation.
In 25th ACM/IEEE Design Automation Conference, pages 506-511,
Anaheim, CA, June 12-15 1988.
- [45]
- D. Adler.
Switch-level simulation using dynamic graph algorithms.
IEEE Transactions on Computer-Aided Design, 10(3):346-355, March
1991.
- [46]
- A. Agarwal,
D. Blaauw, and V. Zolotov.
Statistical clock skew analysis considering intra-die process variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 914-921, San Jose, CA, November 9-13 2003.
- [47]
- A. Agarwal,
D. Blaauw, and V. Zolotov.
Statistical timing analysis for intra-die process variations with spatial
correlations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 900-907, San Jose, CA, November 9-13 2003.
- [48]
- A. Agarwal,
D. Blaauw, V. Zolotov, and S. Vrudhula.
Computation and refinement of statistical bounds on circuit delay.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
348-353, Anaheim, CA, June 2-6 2003.
- [49]
- A. Agarwal,
V. Zolotov, and D. T. Blaauw.
Statistical timing analysis using bounds and selective enumeration.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(9):1243-1260, September 2003.
- [50]
- K. Agarwal,
D. Sylvester, and D. Blaauw.
An effective capacitance based driver output model for on-chip RLC
interconnects.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
376-381, Anaheim, CA, June 2-6 2003.
- [51]
- K. Agarwal,
D. Sylvester, and D. Blaauw.
Simple metrics for slew rate of RC circuits based on two circuit moments.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
950-953, Anaheim, CA, June 2-6 2003.
- [52]
- A. Agarwal,
F. Dartu, and D. Blaauw.
Statistical gate delay model considering multiple input switching.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
658-663, San Diego, CA, June 7-11 2004.
- [53]
- A. Agarwal,
C.-H. Kim, S. Mukhopadhyay, and K. Roy.
Leakage in nano-scale technologies: mechanisms, impact and design
considerations.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 6-11,
San Diego, CA, June 7-11 2004.
- [54]
- A. Agarwal,
V. Zolotov, and D. T. Blaauw.
Statistical clock skew analysis considering intradie-process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1231-1242, August 2004.
- [55]
- K. Agarwal,
D. Sylvester, and D. Blaauw.
A library compatible driver output model for on-chip RLC transmission lines.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):128-136, January 2004.
- [56]
- K. Agarwal,
D. Sylvester, and D. Blaauw.
A simple metric for slew rate of RC circuits based on two circuit moments.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1346-1354, September 2004.
- [57]
- K. Agarwal,
D. Sylvester, D. Blaauw, F. Liu, S. Nassif, and S. Vrudhula.
Variational delay metrics for interconnect timing analysis.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
381-384, San Diego, CA, June 7-11 2004.
- [58]
- A. Agarwal,
K. Chopra, D. Blaauw, and V. Zolotov.
Circuit optimization using statistical static timing analysis.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
321-324, Anaheim, CA, June 13-17 2005.
- [59]
- A. Agarwal,
K. Kang, S. K. Bhunia, J. D. Gallagher, and K. Roy.
Effectiveness of low power dual-vt designs in nano-scale technologies under
process parameter variations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 14-19, San Diego, CA, August 8-10 2005.
- [60]
- A. Agarwal,
K. Kang, and K. Roy.
Accurate estimation and modeling of total chip leakage considering inter- &
intra-die process variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 736-741, San Jose, CA, November 6-10 2005.
- [61]
- K. Agarwal,
M. Agarwal, D. Sylvester, and D. Blaauw.
Statistical interconnect metrics for physical-design optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1273-1288, July 2006.
- [62]
- K. Agarwal,
D. Sylvester, and D. Blaauw.
Modeling and analysis of crosstalk noise in coupled RLC interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):892-901, May 2006.
- [63]
- K. Agarwal,
R. Rao, D. Sylvester, and R. Brown.
Parametric yield analysis and optimization in leakage dominated technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(6):613-623, June 2007.
- [64]
- M. Agarwal,
B. C. Paul, M. Zhang, and S. Mitra.
Circuit failure prediction and its application to transistor aging.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 98-105, Austin, Texas,
February 26-27 2007.
- [65]
- M. Agarwal,
V. Balakrishnan, A. Bhuyan, K. Kim, M. Mizuno, B. C. Paul, W. Wang, Y. Cao,
and S. Mitra.
Optimized circuit failure prediction for aging: practicality and promise.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 116-119, Monterey, CA,
February 25-26 2008.
- [66]
- K. Agarwal,
D. Acharyya, and J. Plusquellic.
Characterizing within-die variation from multiple supply port IDDQ
measurements.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 418-424, San Jose, CA, November 2-5 2009.
- [67]
- A. Agarwal and
M. Levy.
The KILL rule for multicore.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
750-753, San Diego, CA, June 4-8 2007.
- [68]
- K. Agarwal and F. Liu.
Efficient computation of current flow in signal wires for reliability analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 741-746, San Jose, CA, November 5-8 2007.
- [69]
- K. Agarwal and
S. Nassif.
Statistical analysis of SRAM cell stability.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 57-62,
San Francisco, CA, July 24-28 2006.
- [70]
- K. Agarwal and
S. Nassif.
Characterizing process variation in nanometer CMOS.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
396-399, San Diego, CA, June 4-8 2007.
- [71]
- K. Agarwal and
S. Nassif.
The impact of random device variation on SRAM cell stability in sub-90nm
CMOS technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(1):86-97, January 2008.
- [72]
- A. Agarwal and K. Roy.
A noise tolerant cache design to reduce gate and sub-threshold leakage in the
nanometer regime.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 18-21, Seoul, Korea, August 25-27 2003.
- [73]
- A. Agarwal and
R. Vermuri.
Hierarchical performance macromodels of feasible regions for synthesis of
analog and RF circuits.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 430-436, San Jose, CA, November 6-10 2005.
- [74]
- B. N.
Agarwala, M. J. Attardo, and P. Ingraham.
Dependence of electromigration-induced failure time on length and width of
aluminum thin-film conductors.
Journal of Applied Physics, 41(10):3954-3960, September 1970.
- [75]
- R. Aggrawal,
R. Murgai, and M. Fujita.
Speeding up technology-independent timing optimization by network partitioning.
In IEEE/ACM International Conference on Computer-Aided Design, pages
83-90, San Jose, CA, November 9-13 1997.
- [76]
- Y. Aghaghiri, F. Fallah, and M. Pedram.
Irredundant address bus encoding for low power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 182-187, Huntington Beach, California, August 6-7
2001.
- [77]
- Y. Aghaghiri, F. Fallah, and M. Pedram.
ALBORZ: address level bus power optimization.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 470-475, San Jose, CA, March 18-21 2002.
- [78]
- Y. Aghaghiri, F. Fallah, and M. Pedram.
Reducing transitions on memory buses using sector-based encoding technique.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 190-195, Monterey, California, August 12-14 2002.
- [79]
- Y. Aghaghiri, F. Fallah, and M. Pedram.
Transition reduction in memory buses using sector-based encoding techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1164-1174, August 2004.
- [80]
- A. Agnihotri, M. C. Yildiz, A. Khatkhate, A. Mathur, S. Ono, and
P. H. Madden.
Fractional cut: improved recursive bisection placement.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 307-310, San Jose, CA, November 9-13 2003.
- [81]
- M. Agostinelli, M. Alioto, D. Esseni, and L. Selmi.
Leakage-delay tradeoff in finfet logic circuits: a comparative analysis with
bulk technology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):232-245, February 2010.
- [82]
- V. D. Agrawal,
K-T Cheng, and P. Agrawal.
CONTEST: a concurrent test generator for sequential circuits.
In 25th ACM/IEEE Design Automation Conference, pages 84-89, Anaheim,
CA, June 12-15 1988.
- [83]
- V. D. Agrawal,
K-T. Cheng, and P. Agrawal.
A directed search method for test generation using a concurrent simulator.
IEEE Transactions on Computer-Aided Design, 8(2):131-138, February
1989.
- [84]
- A. Agrawal,
H. Li, and K. Roy.
DRG-cache: A data retention gated-ground cache for low power.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
473-478, New Orleans, LA, June 10-14 2002.
- [85]
- P. Agrawal and S. M.
Reddy.
Test generation at MOS level.
In IEEE International Conference on Computers, Systems, and Signal
Processing, pages 1116-1119, Bangalore, India, Dec. 10-12 1984.
- [86]
- V. D. Agrawal and S. C.
Seth.
Probabilistic testability.
In IEEE International Conference on Computer Design: VLSI in
Computers, pages 562-565, Port Chester, NY, Oct. 7-10 1985.
- [87]
- V. D. Agrawal.
Information theory in digital testing - a new approach to functional test
pattern generation.
In IEEE International Conference on Circuits and Computers, pages
928-931, Port Chester, NY, Oct. 1-3 1980.
- [88]
- V. D. Agrawal.
An information theoretic approach to digital fault testing.
IEEE Transactions on Computers, C-30(8):582-587, August 1981.
- [89]
- P. Agrawal.
Test generation at switch-level.
In IEEE International Conference on Computer-Aided Design, pages
128-130, Santa Clara, CA, Nov. 12-15 1984.
- [90]
- M. Ahadi and S. Roy.
Sparse linear regression (SPLINER) approach for efficient multidimensional
uncertainty quantification of high-speed circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(10):1640-1652, October 2016.
- [91]
- Lars Valerian Ahlfors.
Complex Analysis.
McGraw-Hill, New York, NY, 1979.
- [92]
- R. Ahmadi and F. N. Najm.
Timing analysis in presence of power supply and ground voltage variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 176-183, San Jose, CA, November 9-13 2003.
- [93]
- F. Ahmed and L. Milor.
Analysis and on-chip monitoring of gate oxide breakdown in SRAM cells.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(5):855-864, May 2012.
- [94]
- E. Ahmed and J. Rose.
The effect of LUT and cluster size on deep-submicron FPGA performance and
density.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(3):288-298, March 2004.
- [95]
- Alfred V. Aho, John E.
Hopcroft, and Jeffrey D. Ullman.
The Design and Analysis of Computer Algorithms.
Addison-Wesley Publishing Company, 1974.
- [96]
- A. V. Aho, B. W.
Kernighan, and P. J. Weinberger.
The Awk Programming Language.
Addison-Wesley, Reading, MA, 1988.
- [97]
- M. Ahrens,
M. Gester, N. Klewinghaus, D. Muller, S. Payer, C. Schulte, and G. Tellez.
Detailed routing algorithms for advanced technology nodes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(4):563-576, April 2015.
- [98]
- R. Aitken and
S. Becker.
Cell library techniques using advanced transistor structures.
In International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 199-204, Austin, TX, May 17-20 2004.
- [99]
- A. A. Ajami,
K. Banerjee, and M. Pedram.
Analysis of substrate thermal gradient effects on optimal buffer insertion.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 44-48, San Jose, CA, November 4-8 2001.
- [100]
- A. H. Ajami,
K. Banerjee, M. Pedram, and L. P.P.P. van Ginneken.
Analysis of non-uniform temperature-dependent interconnect performance in high
performance ics.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
567-572, Las Vegas, NV, June 18-22 2001.
- [101]
- A. H. Ajami,
K. Banerjee, and M. Pedram.
Modeling and analysis of nonuniform substrate temperature effects on global
ULSI interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(6):849-861, June 2005.
- [102]
- S. B. Akers, Jr.
On a theory of boolean functions.
SIAM Journal, 7(4):487-498, December 1959.
- [103]
- S. B. Akers.
Functional testing with binary decision diagrams.
In IEEE 8th International Conference on Fault-Tolerant Computing,
pages 75-82, Tolouse, France, June 21-23 1978.
- [104]
- C. J. Akl and M. A.
Bayoumi.
Reducing interconnect delay uncertainty via hybrid polarity repeater insertion.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(9):1230-1239, September 2008.
- [105]
- C. J. Akl and M. A.
Bayoumi.
Transition skew coding for global on-chip interconnect.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(8):1091-1096, August 2008.
- [106]
- F. Akopyan,
J. Sawada, A. Cassidy, R. Alvarez-Icaza, J. Arthur, P. Merolla, N. Imam,
Y. Nakamura, P. Datta, G.-J. Nam, B. Taba, M. Beakes, B. Brezzo, J. B. Kuang,
R. Manohar, W. P. Risk, B. Jackson, and D. S. Modha.
Truenorth: design and tool flow of a 65 mw 1 million neuron programmable
neurosynaptic chip.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(10):1537-1557, October 2015.
- [107]
- S. A. Al-Arian and
D. P. Agrawal.
Physical failures and fault models of CMOS circuits.
IEEE Transactions on Circuits and Systems, CAS-34(3):269-279, March
1987.
- [108]
- A. A.
Al-Yamani, S. Ramsundar, and D. K. Pradhan.
A defect tolerance scheme for nanotechnology circuits.
IEEE Transactions on Circuits and Systems, 54(11):2402-2409, November
2007.
- [109]
- A. Alaghi,
C. Li, and J. P. Hayes.
Stochastic circuits for real-time image-processing applications.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [110]
- A. Alaghi and J. P.
Hayes.
STRAUSS: spectral transform use in stochastic circuit synthesis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(11):1770-1783, November 2015.
- [111]
- M. R. Alam,
M. E. Salehi Nasab, and S. Mehdi Fakhraie.
Power efficient high-level synthesis by centralized and fine-grained clock
gating.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(12):1954-1963, December 2015.
- [112]
- M. M.
Alaybeyi, J. Y. Lee, and R. A. Rohrer.
Numerical integration algorithms and asymptotic waveform evaluation (AWE).
In IEEE/ACM International Conference on Computer-Aided Design, pages
76-79, Santa Clara, CA, November 8-12 1992.
- [113]
- C. Albea,
F. Gordillo, and C. Canudas de Wit.
High performance control design for dynamic voltage scaling devices.
IEEE Transactions on Circuits and Systems, 58(12):2919-2930, December
2011.
- [114]
- C. Albrecht,
B. Korte, J. Schietke, and J. Vygen.
Cycle time and slack optimization for VLSI chips.
In IEEE/ACM International Conference on Computer-Aided Design, pages
232-238, San Jose, CA, November 7-11 1999.
- [115]
- E. F. M.
Albuquerque and M. M. Silva.
A comparison by simulation and by measurement of the substrate noise generated
by CMOS, CSL, and CBL digital circuits.
IEEE Transactions on Circuits and Systems, 52(4):734-741, April
2005.
- [116]
- M. F. Ali, A. Veneris,
S. Safarpour, R. Drechsler, A. Smith, and M. Abadir.
Debugging sequential circuits using boolean satisfiability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 204-209, San Jose, CA, November 7-11 2004.
- [117]
- M. Alidina,
J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou.
Precomputation-based sequential logic optimization for low power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2(4):426-436, December 1994.
- [118]
- M. Alidina,
J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou.
Precomputation-based sequential logic optimization for low power.
In IEEE/ACM International Conference on Computer-Aided Design, pages
74-81, San Jose, CA, November 6-10 1994.
- [119]
- M. Alidina,
J. Monteiro, A. Ghosh, and M. Papaefthymiou.
Precomputation-based sequential logic optimization for low power.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
57-62, Napa, CA, April 24-27 1994.
- [120]
- A. Alimohammad, S. F. Fard, B. F. Cockburn, and C. Schlegel.
A compact and accurate gaussian variate generator.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(5):517-527, May 2008.
- [121]
- M. Alioto,
G. Palumbo, and M. Poli.
Evaluation of energy consumption in RC ladder circuits driven by a ramp
input.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1094-1107, October 2004.
- [122]
- M. Alioto,
G. Palumbo, and M. Poli.
Energy consumption in RC tree circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(5):452-461, May 2006.
- [123]
- M. Alioto,
G. Palumbo, and M. Poli.
Analysis and modeling of energy consumption in RLC tree circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):278-291, February 2009.
- [124]
- M. Alioto,
E. Consoli, and G. Palumbo.
Flip-flop energy/performance versus clock slope and impact on the clock network
design.
IEEE Transactions on Circuits and Systems, 57(6):1273-1286, June
2010.
- [125]
- M. Alioto,
G. Palumbo, and M. Pennisi.
Understanding the effect of process variations on the delay of static and
domino logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(5):697-710, May 2010.
- [126]
- M. Alioto,
E. Consoli, and G. Palumbo.
Analysis and comparison in the energy-delay-area domain of nanometer CMOS
flip-flops: part I - methodology and design strategies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(5):725-736, May 2011.
- [127]
- M. Alioto,
E. Consoli, and G. Palumbo.
Analysis and comparison in the energy-delay-area domain of nanometer CMOS
flip-flops: part II - results and figures of merit.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(5):737-750, May 2011.
- [128]
- M. Alioto and
G. Palumbo.
Power estimation in adiabatic circuits: a simple and accurate model.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(5):608-615, October 2001.
- [129]
- M. Alioto and
G. Palumbo.
NAND/NOR adiabatic gates: power consumption evaluation and comparion versus
the fan-in.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(9):1253-1262, September 2002.
- [130]
- M. Alioto and
G. Palumbo.
Design strategies for source coupled logic gates.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(5):640-654, May 2003.
- [131]
- M. Alioto and
G. Palumbo.
Impact of supply voltage variations on full adder delay: analysis and
comparison.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(12):1322-1335, December 2006.
- [132]
- M. Alioto.
CAD models of the input admittance of RC wires: comparison and selection
strategies.
In IEEE 20th International Conference on Microelectronics (ICM), pages
154-157, Sharjah, UAE, December 14-17 2008.
- [133]
- M. Alioto.
Ultra-low power VLSI circuit design demystified and explained: a tutorial.
IEEE Transactions on Circuits and Systems, 59(1):3-29, January
2012.
- [134]
- Y. Alkabani1, T. Massey, F. Koushanfar, and M. Potkonjak.
Input vector control for post-silicon leakage current minimization in the
presence of manufacturing variability.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
606-609, Anaheim, CA, June 8-13 2008.
- [135]
- G. A. Allan.
Yield prediction by sampling IC layout.
IEEE Transactions on Computer-Aided Design, 19(3):359-371, March
2000.
- [136]
- N. Allec,
Z. Hassan, L. Shang, R. P. Dick, and R. Yang.
Thermalscope: multi-scale thermal analysis for nanometer-scale integrated
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 603-610, San Jose, CA, November 10-13 2008.
- [137]
- D. Allen,
D. Behrends, and B. Stanisic.
Converting a 64b powerpc processor from CMOS bulk to SOI technology.
In Design Automation Conference, pages 892-897, New Orleans, LA, June
21-25 1999.
- [138]
- J. M. Allred,
S. Roy, and K. Chakraborty.
Dark silicon aware multicore systems: Employing design automation with
architectural insight.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1192-1196, May 2014.
- [139]
- F. A. Aloul,
A. Ramani, I. L. Markov, and K. A. Sakallah.
Generic ILP versus specialized 0-1 ILP: An update.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 450-457, San Jose, CA, November 10-14 2002.
- [140]
- F. A. Aloul, B. D.
Sierawski, and K. A. Sakallah.
Satometer: how much have we searched.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(8):995-1004, August 2003.
- [141]
- E. Alpaslan,
B. Kruseman, A. K. Majhi, W. M. Heuvalman, and J. Dworak.
NIM-X: a noise index model-based X-filling technique to overcome the
power supply switching noise effects on path delay test.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(5):809-813, May 2012.
- [142]
- C. J. Alpert,
A. Devgan, and S. T. Quay.
Buffer insertion for noise and delay optimization.
In IEEE/ACM 35th Design Automation Conference, pages 362-367, San
Francisco, CA, June 15-19 1998.
- [143]
- C. J. Alpert,
A. Devgan, and S. T. Quay.
Is wire tapering worthwhile?
In IEEE/ACM International Conference on Computer-Aided Design, pages
430-435, San Jose, CA, November 7-11 1999.
- [144]
- C. J. Alpert,
A. Devgan, and C. Kashyap.
A two moment RC delay metric for performance optimization.
In International Symposium on Physical Design, pages 69-74, San
Diego, CA, April 9-12 2000.
- [145]
- C. J. Alpert,
A. Devgan, and C. V. Kashyap.
RC delay metrics for performance optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(5):571-582, May 2001.
- [146]
- C. J. Alpert,
F. Liu, C. Kashyap, and A. Devgan.
Delay and slew metrics using the lognormal distribution.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
382-385, Anaheim, CA, June 2-6 2003.
- [147]
- C. J. Alpert,
F.-Y. Liu, C. V. Kashyap, and A. Devgan.
Closed-form delay and slew metrics made easy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(12):1661-1669, December 2004.
- [148]
- C. Alpert,
Z. Li, G.-J. Nam, C.-N. Sze, N. Viswanathan, and S. I. Ward.
Placement: hot or not?
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 283-290, San Jose, CA, November 5-8 2012.
- [149]
- C. J. Alpert.
The ispd98 circuit benchmark suite.
In ACM/IEEE International Symposium on Physical Design, pages 80-85,
Monterey, CA, April 6-8 1998.
- [150]
- M. D. Altman,
J. P. Bardhan, B. Tidor, and J. K. White.
FFTSVD: a fast multiscale boundary-element method solver suitable for
bio-MEMS and biomolecule simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(2):274-284, February 2006.
- [151]
- M. Altun, M. D.
Riedel, and C. Neuhauser.
Nanoscale digital computation through percolation.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
615-616, San Francisco, CA, July 26-31 2009.
- [152]
- M. Altun and M. D.
Riedel.
Lattice-based computation of boolean functions.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
609-612, Anaheim, CA, June 13-18 2010.
- [153]
- A. Alvandpour, P. Larsson-Edefors, and C. Svensson.
Separation and extraction of short-circuit power consumption in digital CMOS
VLSI circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 245-249, Monterey, CA, August 10-12 1998.
- [154]
- H. Amanthan,
C.-H. Kim, and K. Roy.
Larger-than-vdd forward body bias in sub-0.5v nanoscale CMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 8-13, Newport Beach, CA, August 9-11 2004.
- [155]
- S. V. Amari and R. B.
Misra.
Closed-form expressions for distribution of sum of exponential random
variables.
IEEE Transactions on Reliability, 46(4):519-522, December 1997.
- [156]
- L. Amaru, P.-E.
Gaillardon, and G. De Micheli.
Majority-inverter graph: a new paradigm for logic optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(5):806-819, May 2016.
- [157]
- B. Amelifard, F. Fallah, and M. Pedram.
Low-power fanout optimization using multiple threshold voltage inverters.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 95-98, San Diego, CA, August 8-10 2005.
- [158]
- B. Amelifard, F. Fallah, and M. Pedarm.
Low-power fanout optimization using MTCMOS and multi-vt techniques.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 334-337, Tegernsee, Germany, October 4-6 2006.
- [159]
- B. Amelifard, F. Fallah, and M. Pedram.
Leakage minimization of SRAM cells in a dual-vt and dual-tox technology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(7):851-860, July 2008.
- [160]
- B. Amelifard, F. Fallah, and M. Pedram.
Low-power fanout optimization using multi-threshold voltages and multi-channel
lengths.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(4):478-489, April 2009.
- [161]
- B. Amelifard
and M. Pedram.
Design of an efficient power delivery network in an soc to enable dynamic power
management.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 328-333, Portland, Oregon, August 27-29 2007.
- [162]
- B. Amelifard and
M. Pedram.
Optimal selection of voltage regulator modules in a power delivery network.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
168-173, San Diego, CA, June 4-8 2007.
- [163]
- B. Amelifard and
M. Pedram.
Optimal design of the power delivery network for multiple voltage-island
system-on-chipst.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(6):888-900, June 2009.
- [164]
- E. A.
Amerasekera and F. N. Najm.
Failure Mechanisms in Semiconductor Devices.
John Wiley & Sons, Inc., Chichester, England, 2nd edition, 1997.
- [165]
- B. W. Amick, C. R.
Gauthier, and D. Liu.
Macro-modeling concepts for the chip electrical interface.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
391-394, New Orleans, LA, June 10-14 2002.
- [166]
- C. S. Amin, M. H.
Chowdhury, and Y. I. Ismail.
Realizable RLCK circuit crunching.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
226-231, Anaheim, CA, June 2-6 2003.
- [167]
- C. S. Amin,
F. Dartu, and Y. I. Ismail.
Weibull based analytical waveform model.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 161-168, San Jose, CA, November 9-13 2003.
- [168]
- C. S. Amin,
F. Dartu, and Y. I. Ismail.
Modeling unbuffered latches for timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 254-260, San Jose, CA, November 7-11 2004.
- [169]
- C. S. Amin, M. H.
Chowdhury, and Y. I. Ismail.
Realizable reduction of interconnect circuits including self and mutual
inductances.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(2):271-277, February 2005.
- [170]
- C. S. Amin,
F. Dartu, and Y. I. Ismail.
Weibull-based analytical waveform model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(8):1156-1168, August 2005.
- [171]
- C. S. Amin, Y. I.
Ismail, and F. Dartu.
Piece-wise approximations of RLCK circuit responses using moment matching.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
927-932, Anaheim, CA, June 13-17 2005.
- [172]
- C. S. Amin,
N. Menezes, K. Killpack, F. Dartu, U. Choudhury, N. Hakim, and Y. I. Ismail.
Statistical static timing analysis: how simple can we get?
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
652-657, Anaheim, CA, June 13-17 2005.
- [173]
- C. Amin, C. Kashyap,
N. Menezes, K. Killpack, and E. Chiprout.
A multi-port current source model for multiple-input switching effects in
CMOS library cells.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
247-252, San Francisco, CA, July 24-28 2006.
- [174]
- A. Amirabadi, A. Afzali-Kusha, Y. Mortazavi, and M. Nourani.
Clock delayed domino logic with efficient variable threshold voltage keeper.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(2):125-134, February 2007.
- [175]
- B. S. Amrutur and
M. A. Horowitz.
Speed and power scaling of SRAM's.
IEEE Transactions on Solid-State Circuits, 35(2):175-185, February
2000.
- [176]
- D. Amsallem
and J. Roychowdhury.
Modspec: an open, flexible specification framework for multi-domain device
modelling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 367-374, San Jose, CA, November 7-10 2011.
- [177]
- M. E. Amyeen,
W. K. Fuchs, I. Pomeranz, and V. Boppana.
Fault equivalence identification in combinational circuits using implication
and evaluation techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(7):922-936, July 2003.
- [178]
- H. Ananthan and
K. Roy.
Technology-circuit co-design in width-quantized quasi-planar double-gate
SRAM.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 155-160, Austin, TX, May 9 - 11 2005.
- [179]
- H. Ananthan and
K. Roy.
A fully physical model for leakage distribution under process variations in
nanoscale double-gate CMOS.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
413-418, San Francisco, CA, July 24-28 2006.
- [180]
- D. F.
Anastasakis, N. Gopal, and L. T. Pillage.
On the stability of moment-matching approximations in asumptotic waveform
evaluation.
SRC Technical Report C91905, Journal Preprint, December 1991.
- [181]
- D. F.
Anastasakis, N. Gopal, S. Y. Kim, and L. T. Pillage.
On the stability of moment-matching approximations in assymptotic waveform
evaluation.
In 29th ACM/IEEE Design Automation Conference, pages 207-212,
Anaheim, CA, June 8-12 1992.
- [182]
- J. H.
Anderson, F. N. Najm, and T. Tuan.
Active leakage power optimization for fpgas.
In ACM/SIGDA International Symposium on Field Programmable Gate
Arrays, pages 33-41, Monterey, CA, February 22-24 2004.
- [183]
- J. H. Anderson and
F. N. Najm.
Power-aware technology mapping for LUT-based fpgas.
In IEEE International Conference on Field-Programmable Technology,
pages 211-218, Hong Kong, December 16-18 2002.
- [184]
- J. H. Anderson and
F. N. Najm.
Switching activity analysis and pre-layout activity prediction for fpgas.
In ACM/IEEE International Workshop on System-Level Interconnect
Prediction, pages 15-21, Monterey, CA, April 5-6 2003.
- [185]
- J. H. Anderson and
F. N. Najm.
Interconnect capacitance estimation for fpgas.
In IEEE/ACM Asia and South Pacific Design Automation Conference
(ASP-DAC), pages 713-718, Yokohama, Japan, January 27-30 2004.
- [186]
- J. H. Anderson and
F. N. Najm.
Low-power programmable routing circuitry for fpgas.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 602-609, San Jose, CA, November 7-11 2004.
- [187]
- J. H. Anderson and
F. N. Najm.
A novel low-power FPGA routing switch.
In IEEE Custom Integrated Circuits Conference (CICC), pages 719-722,
Orlando, FL, October 3-6 2004.
- [188]
- J. H. Anderson and
F. N. Najm.
Power estimation techniques for fpgas.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1015-1027, October 2004.
- [189]
- J. H. Anderson and
F. N. Najm.
Active leakage power optimization for fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(3):423-437, March 2006.
- [190]
- J. H. Anderson and
F. N. Najm.
Low-power programmable FPGA routing circuitry.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(8):1048-1060, August 2009.
- [191]
- James A.
Anderson and Edward Rosenfeld, editors.
Neurocomputing : Foundations of Research.
MIT Press, 1988.
- [192]
- J. H. Anderson.
Geometrical approach to reduction of dynamical systems.
In Proceedings of the IEE, pages 1014-1018, July 1967.
Published as Proceedings of the IEE, volume 114, number 7.
- [193]
- C. J. Anderson.
Beyond innovation: dealing with the risks and complexity of processor design in
22nm.
In ACM/IEEE 46th Design Automation Conference (DAC-09), page 103, San
Francisco, CA, July 26-31 2009.
- [194]
- N. Andrikos,
L. Lavagno, D. Pandini, and C. P. Sotiriou.
A fully-automated desynchronization flow for synchronous circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
982-985, San Diego, CA, June 4-8 2007.
- [195]
- C. Angione,
J. Costanza, G. Carapezza, P. Lio, and G. Nicosia.
Pareto epsilon-dominance and identifiable solutions for biocad modeling.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [196]
- M. Anis,
S. Areibi, M. Mahmoud, and M. Elmasry.
Dynamic and leakage power reduction in MTCMOS circuits using an automated
efficient gate clustering technique.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
480-485, New Orleans, LA, June 10-14 2002.
- [197]
- M. H. Anis, M. W.
Allam, and M. I. Elmasry.
Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and
MTCMOS technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(2):71-78, April 2002.
- [198]
- M. Anis, S. Areibi,
and M. Elmasry.
Design and optimization of multithreshold CMOS (MTCMOS) circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(10):1324-1342, October 2003.
- [199]
- M. Anton,
I. Colonescu, E. Macii, and M. Poncino.
Fast characterization of RTL power macromodels.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 1591-1594, St. Julian, Malta, September 2-5 2001.
- [200]
- D. A.
Antonelli, D.-Z. Chen, T. J. Dysart, and X.-S. Hu.
Quantum-dot cellular automata (QCA) circuit partitioning: problem modeling
and solutions.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
363-368, San Diego, CA, June 7-11 2004.
- [201]
- D. A. Antoniadis.
SOI CMOS as a mainstream low-power technology: a critical assessment.
In 1997 International Symposium on Low Power Electronics and Design,
pages 295-300, Monterey, CA, August 18-20 1997.
- [202]
- I. Apostolopoulou, K. Daloukas, N. Evmorfopoulos, and
G. Stamoulis.
Selective inversion of inductance matrix for large-scale sparse RLC
simulation.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [203]
- K. Arabi,
K. Samadi, and Y. Du.
3d VLSI: a schalable integration beyond 2d.
In ACM International Symposium on Physical Design 2015, pages 1-7,
Monterey, California, March 29 - April 1 2015.
- [204]
- N. Arai.
When and how will an AI be smart enough to design?
In 20th Asia and South Pacific Design Automation Conference, page 562,
Chiba/Tokyo, Japan, January 19-22 2015.
- [205]
- E. Arbel,
C. Eisner, and O. Rokhlenko.
Resurrecting infeasible clock-gating functions.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
160-165, San Francisco, CA, July 26-31 2009.
- [206]
- S. Ardalan,
F. Yuan, and K. Raahemifar.
Low power technique for delay reduction in static CMOS circuits.
In The First Annual Northeast Workshop on Circuits and Systems
(NEWCAS-03), pages 165-168, Montreal, Quebec, June 17-20 2003.
- [207]
- L. A. Arledge and
W. T. Lynch.
Scaling and performance implications for power supply and other signal routing
constraints imposed by I/O pad limitations.
In IEEE Symposium on IC/Package Design Integration, 1998.
- [208]
- D. B. Armstrong.
On finding a nearly minimal set of fault detection tests for combinational
logic nets.
IEEE Transactions on Electronic Computers, EC-15(1):66-73, February
1966.
- [209]
- J. V. Arthur and K. A.
Boahen.
Silicon-neuron design: a dynamical systems approach.
IEEE Transactions on Circuits and Systems, 58(5):1034-1043, May
2011.
- [210]
- H. Arts,
M. Berkelaar, and C. A. J. van Eijk.
Polarized observability don't cares.
In IEEE/ACM International Conference on Computer-Aided Design, pages
626-631, San Jose, CA, November 10-14 1996.
- [211]
- H. Arts,
M. Berkelaar, and K. van Eijk.
Computing observability don't cares efficiently through polarization.
IEEE Transactions on Computer-Aided Design, 17(7):573-581, July
1998.
- [212]
- D. Arumi,
R. Rodriguez-Montanes, J. Figueras, S. Eichenberger, C. Hora, and
B. Kruseman.
Gate leakage impact on full open defects in interconnect lines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(12):2209-2220, December 2011.
- [213]
- D. Arumi,
R. Rodriguez-Montanes, J. Figueras, S. Eichenberger, C. Hora, and
B. Kruseman.
Diagnosis of interconnect full open defects in the presence of gate leakage
currents.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(2):301-312, February 2013.
- [214]
- K. S. Arun and V. B. Rao.
New heuristics and lower bounds for graph partitioning.
In IEEE International Symposium on Circuits and Systems, pages
1172-1175, June 1991.
- [215]
- R. Arunachalam, K. Rajagopal, and L. T. Pileggi.
TACO: Timing analysis with coupling.
In Design Automation Conference, pages 266-269, Los Angeles, CA, June
5-9 2000.
- [216]
- R. Arunachalam, R. D. Blanton, and L. T. Pileggi.
False coupling interactions in static timing analysis.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
726-731, Las Vegas, NV, June 18-22 2001.
- [217]
- Arvind, R. S.
Nikhil, D. L. Rosenband, and N. Dave.
High-level synthesis: an essential ingredient for designing complex asics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 775-782, San Jose, CA, November 7-11 2004.
- [218]
- H. Asadi and M. B.
Tahoori.
Soft error derating computation in sequential circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 497-501, San Jose, CA, November 5-9 2006.
- [219]
- F. H. A. Asgari and
M. Sachdev.
A low-power reduced swing global clocking methodology.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):538-545, May 2004.
- [220]
- P. Ashar and S. Malik.
Functional timing analysis using ATPG.
IEEE Transactions on Computer-Aided Design, 14(8):1025-1030, August
1995.
- [221]
- T. Askham and
L. Greengard.
Norm-preserving discretization of integral equations for elliptic pdes with
internal layers I: the one-dimensional case.
SIAM Review, 56(4):625-641, December 2014.
- [222]
- F. Assaderaghi.
Circuit styles and strategies for CMOS VLSI design on SOI.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 282-287, San Diego, CA, August 16-17 1999.
- [223]
- G. Astfalk,
I. Lustig, R. Marsten, and D. Shanno.
The interior-point method for linear programming.
IEEE Software, 9(4):61-68, July 1992.
- [224]
- E. M. Atakov,
T. S. Sriram, D. Dunnell, and S. Pizzanello.
Effect of VLSI interconnect layout on electromigration performance.
In IEEE International Reliability Physics Symposium, pages 348-355,
Reno, NV, 1998.
- [225]
- W. Athas,
L. Youngs, and A. Reinhart.
Compact models for estimating microprocessor frequency and power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 313-318, Monterey, California, August 12-14 2002.
- [226]
- W. Athas.
Practical considerations of clock-powered logic.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 173-178, Italy, July 26-27 2000.
- [227]
- K. Athikulwongse, J.-S. Yang, D.-Z. Pan, and S.-K. Lim.
Impact of mechanical stress on the full chip timing for
through-silicon-via-based 3-C ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):905-917, June 2013.
- [228]
- M. J. Attardo,
R. Rutledge, and R. C. Jack.
Statistical metallurgical model for electromigration failure in aluminum
thin-film conductors.
Journal of Applied Physics, 42(11):4343-4349, October 1971.
- [229]
- M. J. Attardo and
R. Rosenberg.
Electromigration damage in aluminum film conductors.
Journal of Applied Physics, 41(6):2381-2386, May 1970.
- [230]
- L. M. Augustin.
An algebra of waveforms.
In L. J. M. Claesen, editor, Formal VLSI Specification and Synthesis: VLSI
Design Methods, I, pages 309-318. Elsevier Science Publishers B. V.
(North-Holland), New York, NY, 1990.
- [231]
- S. Aur, C. Duvvury,
and W. Hunter.
Setting the trap for hot carriers.
IEEE Circuits and Devices Magazine, 11(4):18-24, July 1995.
- [232]
- T. M. Austin.
Designing robust microarchitectures.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 78-78,
San Diego, CA, June 7-11 2004.
- [233]
- M. Avci and F. N. Najm.
Early P/G grid voltage integrity verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 816-823, San Jose, CA, November 7-11 2010.
- [234]
- M. Avci and F. N. Najm.
Verification of the power and ground grids under general and hierarchical
constraints.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(2):729-742, February 2016.
- [235]
- R. L. Aveyard.
A boolean model for a class of discrete event systems.
IEEE Transactions on Systems, Man, and Cybernetics, SMC-4(3):249-258,
May 1974.
- [236]
- H. Awano and T. Sato.
Efficient transistor-level timing yield estimation via line sampling.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [237]
- M. Aydonat and F. N.
Najm.
Power grid correction using sensitivity analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 808-815, San Jose, CA, November 7-11 2010.
- [238]
- N. Azizi,
A. Moshovos, and F. N. Najm.
Low-leakage asymmetric-cell SRAM.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 48-51, Monterey, California, August 12-14 2002.
- [239]
- N. Azizi, F. N.
Najm, and A. Moshovos.
Low-leakage asymmetric-cell SRAM.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):701-715, August 2003.
- [240]
- N. Azizi, M. M.
Khellah, V. De, and F. N. Najm.
Variations-aware low-power design with voltage scaling.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
529-534, Anaheim, CA, June 13-17 2005.
- [241]
- N. Azizi, M. M.
Khellah, V. K. De, and F. N. Najm.
Variations-aware low-power design and block clustering with voltage scaling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(7):746-757, July 2007.
- [242]
- N. Azizi and F. N. Najm.
An asymmetric SRAM cell to lower gate leakage.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 534-539, San Jose, CA, March 22-24 2004.
- [243]
- N. Azizi and F. N. Najm.
Compensation for within-die variations in dynamic logic by using body-bias.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 167-170, Quebec City, Quebec, June 19-22 2005.
- [244]
- N. Azizi and F. N. Najm.
Look-up table leakage reductions for fpgas.
In IEEE Custom Integrated Circuits Conference (CICC), pages 187-190,
San Jose, CA, September 18-21 2005.
- [245]
- N. Azizi and F. N. Najm.
A family of cells to reduce the soft-error-rate in ternary-CAM.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
779-784, San Francisco, CA, July 24-28 2006.
- [246]
- N. Azizi and F. N. Najm.
Using keeper control and body bias for fine grained threshold voltage
compensation in dynamic logic.
In 20th Canadian Conference on Electrical and Computer Engineering
(CCECE), pages 1639-1644, Vancouver, BC, April 22-26 2007.
- [247]
- P. Babighian, L. Benini, and E. Macii.
A scalable algorithm for RTL insertion of gated clocks based on odcs
computation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):29-42, January 2005.
- [248]
- P. Babighina, L. Benini, A. Macii, and E. Macii.
Post-layout leakage power minimization based on distributed sleep transistor
insertion.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 138-143, Newport Beach, CA, August 9-11 2004.
- [249]
- W. W. Bachmann and
S. A. Huss.
Efficient algorithms for multilevel power estimation of VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(2):238-254, February 2005.
- [250]
- M. Badaroglu, K. Tiri, S. Donnay, P. Wambacq, I. Verbauwhede,
G. Gielen, and H. De Man.
Clock tree optimization in synchronous CMOS digital circuits for substrate
noise reduction using folding of supply current transients.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
399-404, New Orleans, LA, June 10-14 2002.
- [251]
- M. Badaroglu, P. Wambacq, G. Van der Plas, S. Donnay, G. G. E.
Gielen, and H. J. De Man.
Digital ground bounce reduction by supply current shaping and clock frequency
modulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):65-76, January 2005.
- [252]
- A. Baghbanbehrouzian and N. Masoumi.
Analytical solutions for distributed interconnect models - part II: arbitrary
input response and multicoupled lines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(9):1879-1888, September 2015.
- [253]
- R. I. Bahar, E. A.
Frohm, C. M. Gaona, G. D. Hachtel, E. Macii, A. Pardo, and F. Somenzi.
Algebraic decision diagrams and their applications.
In IEEE/ACM International Conference on Computer-Aided Design, pages
188-191, Santa Clara, CA, November 7-11 1993.
- [254]
- R. I. Bahar,
H. Cho, G. D. Hachtel, and F. Somenzi.
An application of ADD-based timing analysis to combinational low power
re-synthesis.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
39-44, Napa, CA, April 24-27 1994.
- [255]
- R. I. Bahar,
G. D. Hachtel, E. Macii, and F. Somenzi.
A symbolic method to reduce power consumption of circuits containing false
paths.
In IEEE/ACM International Conference on Computer-Aided Design, pages
368-371, San Jose, CA, November 6-10 1994.
- [256]
- R. I. Bahar,
M. Burns, G. D. Hachtel, E. Macii, H. Shin, and F. Somenzi.
Symbolic computation of logic implications for technology-dependent low-power
synthesis.
In International Symposium on Low Power Electronics and Design, pages
163-168, Monterey, CA, August 12-14 1996.
- [257]
- R. Iris Bahar,
H. Cho, G. D. Hachtel, E. Macii, and F. Somenzi.
Symbolic timing analysis and resynthesis for low power of combinational
circuits containing false paths.
IEEE Transactions on Computer-Aided Design of Circuits and Systems,
16(10):1101-1115, October 1997.
- [258]
- R. I. Bahar and
F. Somenzi.
Boolean techniques for low power driven re-synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
428-432, San Jose, CA, November 5-9 1995.
- [259]
- Z. Bai, P. Feldmann,
and R. W. Freund.
How to make theoretically passive reduced-order models passive in practice.
In IEEE Custom Integrated Circuits Conference, pages 207-210, Santa
Clara, CA, May 11-14 1998.
- [260]
- Z. Bai, R. D. Slone,
W. T. Smith, and Q. Ye.
Error bound for reduced system model by pade approximation via the lanczos
process.
IEEE Transactions on Computer-Aided Design, 18(2):133-141, February
1999.
- [261]
- G. Bai, S. Bobba, and
I. N. Hajj.
Power bus maximum voltage drop in digital VLSI circuits.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 263-268, San Jose, CA, March 20-22 2000.
- [262]
- G. Bai, S. Bobba,
and I. N. Hajj.
Simulation and optimization of the power distribution network in VLSI
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 481-486, San Jose, CA, November 5-9 2000.
- [263]
- G. Bai, S. Bobba, and
I. N. Hajj.
RC power bus maximum voltage drop in digital VLSI circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 205-210, San Jose, CA, March 26-28 2001.
- [264]
- G. Bai, S. Bobba,
and I. N. Hajj.
RC power bus maximum voltage drop in digital VLSI circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 257-258, San Jose, CA, March 26-28 2001.
- [265]
- G. Bai, S. Bobba,
and I. N. Hajj.
Static timing analysis including power supply noise effect on propagation delay
in VLSI circuits.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
295-300, Las Vegas, NV, June 18-22 2001.
- [266]
- X. Bai, R. Chandra,
S. Dey, and P. V. Srinivas.
Interconnect coupling-aware driver modeling in static noise analysis for
nanometer circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1256-1263, August 2004.
- [267]
- X. Bai and S. Dey.
High-level crosstalk defect simulation methodology for system-on-chip
interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1355-1361, September 2004.
- [268]
- G. Bai and I. N. Hajj.
Simultaneouos switching noise and resonance analysis of on-chip power
distributon network.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 163-168, San Jose, CA, March 18-21 2002.
- [269]
- D. H. Bailey.
Misleading performance claims in parallel computations.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
528-533, San Francisco, CA, July 26-31 2009.
- [270]
- B. S. Bajwa,
N. Schumann, and H. Kojima.
Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit
DSP.
In 1997 International Symposium on Low Power Electronics and Design,
pages 137-142, Monterey, CA, August 18-20 1997.
- [271]
- H. B. Bakoglu.
Circuits, Interconnections, and Packaging for VLSI.
Addison-Wesley Pub. Co., Inc., Reading, MA, 1990.
- [272]
- N. Balabanian
and T. A. Bickart.
Electrical Network Theory.
John Wiley & Sons, Inc., New York, NY, 1969.
- [273]
- S. Balachandran and D. Bhatia.
A priori wirelength and interconnect estimation based on circuit
characteristics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):1054-1065, July 2005.
- [274]
- B. Balaji,
M. A. Al Faruque, N. Dutt, R. Gupta, and Y. Agarwal.
Models, abstractions, and architectures: the missing links in cyber-physical
systems.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [275]
- K. J.
Balakrishnan and N. A. Touba.
Relationship between entropy and test data compression.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(2):386-395, February 2007.
- [276]
- F. Balarin.
Worst-case analysis of discrete systems.
In IEEE/ACM International Conference on Computer-Aided Design, pages
347-352, San Jose, CA, November 7-11 1999.
- [277]
- R. Baldick,
A. B. Kahng, A. Kennings, and I. L. Markov.
Efficient optimization by modifying the objective function: application to
timing-driven VLSI layout.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(8):947-956, August 2001.
- [278]
- H. A. Balef,
M. Kamal, A. Afzali-Kusha, and M. Pedram.
All-region statistical model for delay variation based on log-skew-normal
distribution.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(9):1503-1508, September 2016.
- [279]
- A. Balivada,
D. R. Holberg, and L. T. Pillage.
Calculation and application of time-domain waveform sensitivities in asymptotic
waveform evaluation.
In IEEE Custom Integrated Circuits Conference, pages 8.4.1-8.4.4,
1991.
- [280]
- M. O. Ball and J. S.
Provan.
Disjoint products and efficient computation of reliability.
Operations Research, 36(5):703-715, Sept.-Oct. 1988.
- [281]
- B. Bandali,
E. Gad, and M. Bolic.
Accelerated harmonic-balance analysis using a graphical processing unit
platform.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(7):1017-1030, July 2014.
- [282]
- D. Baneres,
J. Cortadella, and M. Kishinevsky.
A recursive paradigm to solve boolean relations.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
416-421, San Diego, CA, June 7-11 2004.
- [283]
- K. Banerjee,
A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu.
On thermal effects in deep sub-micron VLSI interconnects.
In Design Automation Conference, pages 885-891, New Orleans, LA, June
21-25 1999.
- [284]
- P. Banerjee,
M. Haldar, A. Nayak, V. Kim, V. Saxena, S. Parkes, D. Bagchi, S. Pal,
N. Tripathi, D. Zaretsky, R. Anderson, and J. R. Uribe.
Overview of a compiler for synthesizing MATLAB programs onto fpgas.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(3):312-324, March 2004.
- [285]
- P. Banerjee and
J. A. Abraham.
Generating tests for physical failures in MOS logic circuits.
In IEEE International Test Conference, pages 554-559, Philadelphia,
PA, October 1983.
- [286]
- K. Banerjee and
A. Mehrotra.
Coupled analysis of electromigration reliability and performance in ULSI
signal nets.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 158-164, San Jose, CA, November 4-8 2001.
- [287]
- K. Banerjee and
A. Mehrotra.
Analysis of on-chip inductance effects for distributed RLC interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(8):904-915, August 2002.
- [288]
- K. Banerjee and
N. Srivastava.
Are carbon nanotubes the future of VLSI interconnections.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
809-814, San Francisco, CA, July 24-28 2006.
- [289]
- A. Baniasadi
and A. Moshovos.
SEPAS: a highly accurate energy-efficient branch predictor.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 38-43, Newport Beach, CA, August 9-11 2004.
- [290]
- S. R. Banna,
P. C. H. Chan, M. Chan, and S. K. H. Fung.
Fully depleted CMOS/SOI device design guidelines for low power
applications.
In 1997 International Symposium on Low Power Electronics and Design,
pages 301-306, Monterey, CA, August 18-20 1997.
- [291]
- B. R.
Bannister, D. R. Melton, and G. E. Taylor.
Testability of digital circuits via the spectral domain.
In IEEE International Conference on Computer Design, pages 340-343,
1989.
- [292]
- A. Bansal, R. N.
Singh, R. N. Kanj, S. Mukhopadhyay, J.-F. Lee, E. Acar, A. Singhee, K. Kim,
C.-T. Chuang, S. Nassif, F.-L. Heng, and K. K. Das.
Yield estimation of SRAM circuits using "virtual SRAM fab".
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 631-636, San Jose, CA, November 2-5 2009.
- [293]
- J. P. Bardhan
and A. Hildebrandt.
A fast solver for nonlocal electrostatic theory in biomolecular science and
engineering.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
801-805, San Diego, CA, June 5-9 2011.
- [294]
- T. S. Barnett,
A. D. Singh, and V. P. Nelson.
Extending integrated-circuit yield-models to estimate early-life reliability.
IEEE Transactions on Reliability, 52(3):296-300, September 2003.
- [295]
- M. Barocci,
L. Benini, A. Bogliolo, B. Ricco, and G. De Micheli.
Lookup table power macro-models for behavioral library components.
In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages
173-181, Como, Italy, March 4-5 1999.
- [296]
- Z. Barzilai,
J. L. Carter, V. S. Iyengar, I. Nair, B. K. Rosen, J. Rutledge, and G. M.
Silberman.
Efficient fault simulation of CMOS circuits with accurate models.
In IEEE International Test Conference, pages 520-529, Sept. 8-11
1986.
- [297]
- D. Baschiera
and B. Courtois.
Testing CMOS: a challenge.
VLSI Design, pages 58-62, October 1984.
- [298]
- R. Bashirullah, W. Liu, and R. K. Cavin.
Low-power design methodology for an on-chip bus with adaptive bandwidth
capability.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
628-633, Anaheim, CA, June 2-6 2003.
- [299]
- R. Bashirullah, W. Liu, and R. K. Cavin, III.
Current-model signaling in deep submicrometer global interconnects.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):406-417, June 2003.
- [300]
- R. Bashirullah, W. Liu, R. Cavin, and D. Edwards.
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth
capability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(8):876-880, August 2004.
- [301]
- P. Bastani,
N. Callegari, L.-C. Wang, and M. S. Abadir.
Ranking of unmodeled systematic timing effects.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 104-109, Monterey, CA,
February 25-26 2008.
- [302]
- P. Bastani,
N. Callegari, L.-C. Wang, and M. S. Abadir.
Statistical diagnosis of unmodeled systematic timing effects.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
355-360, Anaheim, CA, June 8-13 2008.
- [303]
- P. Bastani,
K. Killpack, L.-C. Wang, and E. Chiprout.
Speedpath prediction based on learning from a small set of examples.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 98-103, Monterey, CA,
February 25-26 2008.
- [304]
- P. Bastani,
K. Killpack, L.-C. Wang, and E. Chiprout.
Speedpath prediction based on learning from a small set of examples.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
217-222, Anaheim, CA, June 8-13 2008.
- [305]
- A. Basu, S.-C. Lin,
V. Wason, A. Mehrotra, and K. Banerjee.
Simultaneous optimization of supply and threshold voltages for low-power and
high-performance circuits in the leakage dominant era.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
884-887, San Diego, CA, June 7-11 2004.
- [306]
- M. J. Batek.
Test-set preserving logic transformations.
In 29th ACM/IEEE Design Automation Conference, pages 454-458,
Anaheim, CA, June 8-12 1992.
- [307]
- J. Bautista.
Tera-scale computing and interconnect challenges.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
665-667, Anaheim, CA, June 8-13 2008.
- [308]
- M. A. Bawiec and
M. Nikodem.
Boolean logic function synthesis for generalised threshold gate circuits.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 83-86,
San Francisco, CA, July 26-31 2009.
- [309]
- A. A.
Bayrakci, A. Demir, and S. Tasiran.
Fast monte carlo estimation of timing yield with importance sampling and
transistor-level circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(9):1328-1341, September 2010.
- [310]
- A. A. Bayrakci.
Accelerated accurate timing yield estimation based on control variates and
importance sampling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(8):2787-2798, August 2016.
- [311]
- K. Bazargan,
S. Kim, and M. Sarrafzadeh.
NOSTRADAMUS: A floorplanner of uncertain designs.
In ACM/IEEE International Symposium on Physical Design, pages 18-23,
Monterey, CA, April 6-8 1998.
- [312]
- K. Bazargan,
S. Kim, and M. Sarrafzadeh.
Nostradamus: A floorplanner of uncertain designs.
IEEE Transactions on Computer-Aided Design, 18(4):389-397, April
1999.
- [313]
- M. Beattie,
S. Gupta, and L. Pileggi.
Hierarchical interconnect circuit models.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 215-221, San Jose, CA, November 5-9 2000.
- [314]
- M. Beattie,
B. Krauter, L. Alatan, and L. Pileggi.
Equipotential shells for efficient inductance extraction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(1):70-79, January 2001.
- [315]
- M. W. Beattie and
L. T. Pileggi.
Error bounds for capacitance extraction via window techniques.
IEEE Transactions on Computer-Aided Design, 18(3):311-321, March
1999.
- [316]
- M. W. Beattie and
L. T. Pileggi.
Inductance 101: Modeling and extraction.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
323-328, Las Vegas, NV, June 18-22 2001.
- [317]
- M. W. Beattie and
L. T. Pileggi.
On-chip induction modeling: basics and advanced methods.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):712-729, December 2002.
- [318]
- M. W. Beattie and
L. T. Pileggi.
Parasitics extraction with multipole refinement.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(2):288-292, February 2004.
- [319]
- D. L. Beatty and R. E.
Bryant.
Fast incremental circuit analysis using extracted hierarchy.
In 25th ACM/IEEE Design Automation Conference, pages 495-500,
Anaheim, CA, June 12-15 1988.
- [320]
- M. R. Becer,
D. Blaauw, R. Panda, and I. N. Hajj.
Pre-route noise estimation in deep submicron integrated circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 413-418, San Jose, CA, March 18-21 2002.
- [321]
- M. R. Becer,
D. Blaauw, I. Algor, R. Panda, C. Oh, V. Zolotov, and I. N. Hajj.
Post-route gate sizing for crosstalk noise reduction.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 171-176, San Jose, CA, March 24-26 2003.
- [322]
- M. R. Becer,
D. Blaauw, R. Panda, and I. N. Hajj.
Early probabilistic noise estimation for capacitively coupled interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(3):337-345, March 2003.
- [323]
- M. R. Becer,
D. Blaauw, H. Algor, R. Panda, C. Oh, V. Zolotov, and I. N. Hajj.
Postroute gate sizing for crossing noise reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(12):1670-1677, December 2004.
- [324]
- M. Becer,
V. Zolotov, R. Panda, A. Grinshpon, I. Algor, R. Levy, and C. Oh.
Pessimism reduction in crosstalk noise aware STA.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 954-961, San Jose, CA, November 6-10 2005.
- [325]
- M. Becer and I. N. Hajj.
An analytical model for delay and crosstalk estimation in interconnects.
In 7th IEEE International Conference on Electronics, Circuits and
Systems, pages 831-835, Beirut, Lebanon, December 17-19 2000.
- [326]
- M. Becer and I. N. Hajj.
An analytical model for delay and crosstalk estimation with application to
decoupling.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 51-57, San Jose, CA, March 20-22 2000.
- [327]
- M. Becker,
A. Masrur, and S. Chakraborty.
Composing real-time applications from communicating black-box components.
In 20th Asia and South Pacific Design Automation Conference, pages
624-629, Chiba/Tokyo, Japan, January 19-22 2015.
- [328]
- P. Beckett.
A low-power reconfigurable logic array based on double-gate transistors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(2):115-123, February 2008.
- [329]
- D. K. Beece,
J. Xiong, C. Visweswariah, V. Zolotov, and Y. Li.
Transistor sizing of custom high-performance digital circuits with parametric
yield considerations.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
781-786, Anaheim, CA, June 13-18 2010.
- [330]
- F. Beeftink,
P. Kudva, D. Kung, and L. Stok.
Gate-size selection for standard cell libraries.
In IEEE/ACM International Conference on Computer-Aided Design, pages
545-550, San Jose, CA, November 8-12 1998.
- [331]
- S. De Beer,
M. du Plessis, and E. Seevinck.
An SRAM array based on a four-transistor CMOS SRAM cell.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(9):1203-1208, September 2003.
- [332]
- P. A. Beerel,
K. Y. Yun, S. M. Nowick, and P-C. Yeh.
Estimation and bounding of energy consumption in burst-mode control circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
26-33, San Jose, CA, November 5-9 1995.
- [333]
- R. Beers.
Pre-RTL formal verification: an intel experience.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
806-811, Anaheim, CA, June 8-13 2008.
- [334]
- C. C. Beh, K. H. Arya,
C. E. Radke, and K. E. Torku.
Do stuck fault models reflect manufacturing defects.
In IEEE International Test Conference, pages 35-42, 1982.
- [335]
- A. R. B. Behrouzian.
Analytical solutions for distributed interconnect models - part I: step input
response of finite and semi-infinite lines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(12):2596-2606, December 2014.
- [336]
- F. Beichelt and
P. Tittmann.
A generalized reduction method for the connectedness probability of stochastic
networks.
IEEE Transactions on Reliability, 40(2):198-203, June 1991.
- [337]
- B. A. Beitman and
A. Ito.
Generation of electromigration ground rules utilizing monte carlo simulation
methods.
IEEE Transactions on Semiconductor Manufacturing, 4(1):63-66,
February 1991.
- [338]
- V. Beiu, S. Aunet,
J. Nyathi, R. R. Rydberg, III, and W. Ibrahim.
Serial addition: locally connected architectures.
IEEE Transactions on Circuits and Systems, 54(11):2564-2579, November
2007.
- [339]
- N. Bellas,
I. N. Hajj, C. D. Polychronopoulos, and G. Stamoulis.
Architectural and compiler techniques for energy reduction in high-performance
microprocessors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):317-326, June 2000.
- [340]
- N. E. Bellas,
I. N. Hajj, and C. D. Polychronopoulos.
Using dynamic cache management techniques to reduce energy in general purpose
processors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(6):693-708, December 2000.
- [341]
- G. Beltrame,
C. Brandolese, W. Fornaciari, F. Salice, D. Sciuto, and V. Trianni.
An assembly-level execution-time model for pipelined architectures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 195-200, San Jose, CA, November 4-8 2001.
- [342]
- G. Beltrame,
L. Fossati, and D. Sciuto.
Decision-theoretic design space exploration of multiporcessor platforms.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(7):1083-1095, July 2010.
- [343]
- L. Bening.
A two-state methodology for RTL logic simulation.
In Design Automation Conference, pages 672-677, New Orleans, LA, June
21-25 1999.
- [344]
- L. Benini,
M. Favalli, P. Olivo, and B. Ricco.
A novel approach to cost-effective estimate of power dissipation in CMOS ics.
In European Design Automation Conference (EDAC), pages 354-360,
1993.
- [345]
- L. Benini,
M. Favalli, and B. Ricco.
Analysis of hazard contributions to power dissipation in CMOS ics.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
27-32, Napa, CA, April 24-27 1994.
- [346]
- L. Benini,
P. Siegel, and G. De Micheli.
Saving power by synthesizing gate clocks for sequential circuits.
IEEE Design and Test of Computers, 11(4):32-40, December 1994.
- [347]
- L. Benini,
G. De Micheli, E. Macii, M. Poncino, and S. Quer.
System-level power optimization of special purpose applications: The beach
solution.
In 1997 International Symposium on Low Power Electronics and Design,
pages 24-29, Monterey, CA, August 18-20 1997.
- [348]
- L. Benini,
G. De Micheli, E. Macii, M. Poncino, and R. Scarsi.
Fast power estimation for deterministic input streams.
In IEEE/ACM International Conference on Computer-Aided Design, pages
494-501, San Jose, CA, November 9-13 1997.
- [349]
- L. Benini,
A. Bogliolo, S. Cavallucci, and B. Ricco.
Monitoring system activity for OS-directed dynamic power management.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 185-190, Monterey, CA, August 10-12 1998.
- [350]
- L. Benini,
A. Bogliolo, and G. De Micheli.
Dynamic power management of electronic systems.
In IEEE/ACM International Conference on Computer-Aided Design, pages
696-702, San Jose, CA, November 8-12 1998.
- [351]
- L. Benini,
R. Hodgson, and P. Siegel.
System-level power estimation and optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 173-178, Monterey, CA, August 10-12 1998.
- [352]
- L. Benini,
G. De Micheli, E. Macii, M. Poncino, and S. Quer.
Power optimization of core-based systems by address bus encoding.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(4):554-562, December 1998.
- [353]
- L. Benini,
A. Macii, E. Macii, M. Poncino, and R. Scarsi.
Synthesis of low-overhead interfaces for power-efficient communication over
wide buses.
In Design Automation Conference, pages 128-133, New Orleans, LA, June
21-25 1999.
- [354]
- L. Benini,
A. Bogliolo, and G. De Micheli.
A survey of design techniques for system-level dynamic power management.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):299-316, June 2000.
- [355]
- L. Benini,
A. Macii, E. Macii, M. Poncino, and R. Scarsi.
Architectures and synthesis algorithms for power efficient bus-interfaces.
IEEE Transactions on Computer-Aided Design, 19(9):969-980, September
2000.
- [356]
- L. Benini,
A. Macii, and M. Poncino.
A recursive algorithm for low-power memory partitioning.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 78-83, Italy, July 26-27 2000.
- [357]
- L. Benini,
G. De Micheli, A. Macii, E. Macii, M. Poncino, and R. Scarsi.
Glitch power minimization by selective gate freezing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):287-298, June 2000.
- [358]
- L. Benini,
G. De Micheli, E. Macii, M. Poncino, and R. Scarsi.
A multilevel engine for fast power simulation of realistic input streams.
IEEE Transactions on Computer-Aided Design, 19(4):459-472, April
2000.
- [359]
- L. Benini,
G. De Micheli, A. Lioy, E. Macii, G. Odasso, and M. Poncino.
Synthesis of power-managed sequential components based on computational kernel
extraction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(9):1118-1131, September 2001.
- [360]
- L. Benini,
G. De Micheli, and E. Macii.
Designing low-power circuits: practical recipes.
IEEE Circuits and Systems Magazine, 1(1):6-25, Q1 2001.
- [361]
- L. Benini,
A. Macii, E. Macii, and M. Poncino.
Minimizing memory acess energy in embedded systems by selective instruction
compression.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):521-531, October 2002.
- [362]
- L. Benini,
A. Galati, and A. Macii.
Energy-efficient data scrambling on memory-processor interfaces.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 26-29, Seoul, Korea, August 25-27 2003.
- [363]
- L. Benini,
D. Bruni, A. Macii, and E. Macii.
Memory energy minimization by data compression: algorithms, architectures and
implementation.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(3):255-268, March 2004.
- [364]
- L. Benini and G. De
Micheli.
State assignment for low power dissipation.
In IEEE 1994 Custom Integrated Circuits Conference, pages 136-139,
San Diego, CA, May 1-4 1994.
- [365]
- L. Benini and G. De
Micheli.
Automatic synthesis of low-power gated-clock finite-state machines.
IEEE Transactions on Computer-Aided Design, 15(6):630-643, June
1996.
- [366]
- L. Benini and G. De
Micheli.
System level power optimization: techniques and tools.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 288-293, San Diego, CA, August 16-17 1999.
- [367]
- J. Benkoski and
A. J. Strojwas.
A new approach to hierarchical and statistical timing simulations.
IEEE Transactions on Computer-Aided Design, CAD-6(6):1039-1052,
November 1987.
- [368]
- J. Benkoski and
A. J. Strojwas.
The role of timing verification in layout synthesis.
In 28th ACM/IEEE Design Automation Conference, pages 612-619, San
Francisco, CA, June 17-21 1991.
- [369]
- P. Benner,
S. Gugercin, and K. Willcox.
A survey or projection-based model reduction methods for parametric dynamical
systems.
SIAM Review, 57(4):483-531, December 2015.
- [370]
- T. R. Bennett,
J. M. Booker, S. Keller-McNulty, and N. D. Singpurwalla.
Testing the untestable: reliability in the 21st century.
IEEE Transactions on Reliability, 52(1):118-124, March 2003.
- [371]
- M. Benoit,
S. Taylor, D. Overhauser, and S. Rochel.
Power distribution in high-performance design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 274-278, Monterey, CA, August 10-12 1998.
- [372]
- R. A.
Bergamaschi, D. Brand, L. Stok, M. Berkelaar, and S. Prakash.
Efficient use of large don't cares in high-level and logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
272-278, San Jose, CA, November 5-9 1995.
- [373]
- R. A.
Bergamaschi and Y. W. Jiang.
State-based power analysis for systems-on-chip.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
638-641, Anaheim, CA, June 2-6 2003.
- [374]
- R. A.
Bergamaschi and W. R. Lee.
Designing systems-on-chip using cores.
In Design Automation Conference, pages 420-425, Los Angeles, CA, June
5-9 2000.
- [375]
- R. A. Bergamaschi.
Behavioral network graph unifying the domains of high-level and logic
synthesis.
In Design Automation Conference, pages 213-218, New Orleans, LA, June
21-25 1999.
- [376]
- R. Bergamaschi.
The A to Z of socs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 791-798, San Jose, CA, November 10-14 2002.
- [377]
- J. P. Bergmann
and M. A. Horowitz.
Vex - A CAD toolbox.
In Design Automation Conference, pages 523-528, New Orleans, LA, June
21-25 1999.
- [378]
- M. R.
C. M. Berkelaar, P. H. W. Buurman, and J. A. G. Jess.
Computing the entire active area/power consumption versus delay tradeoff curve
for gate sizing with a piecewise linear simulator.
IEEE Transactions on Computer-Aided Design, 15(11):1423-1434,
November 1996.
- [379]
- D. Berleant and
J. Zhang.
Bounding the times to failure of 2-component systems.
IEEE Transactions on Reliability, 53(4):542-550, December 2004.
- [380]
- A. Berman and R. J.
Plemmons.
Nonnegative Matrices in the Mathematical Sciences.
Number 9 in Classics in applied mathematics. SIAM Publishing, Philadelphia, PA,
1994.
- [381]
- C. Leonard Berman.
Circuit width, register allocation, and ordered binary decision diagrams.
IEEE Transactions on Computer-Aided Design, 10(8):1059-1066, August
1991.
- [382]
- G. Bernacchia and M. C. Papaefthymiou.
Analytical macromodeling for high-level power estimation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
280-283, San Jose, CA, November 7-11 1999.
- [383]
- R. Bernardini and G. Cortelazzo.
Tools for designing chaotic systems for secure random number generation.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(5):552-565, May 2001.
- [384]
- A. Bernasconi, V. Ciriani, F. Luccio, and L. Pagli.
Three-level logic minimization based on function regularities.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(8):1005-1016, August 2003.
- [385]
- K. Bernstein, J. E. Bertsch, W. F. Clark, J. J. Ellis-Monaghan,
L. G. Heller, and E. J. Nowak.
Practical performance/power alternatives within an existing CMOS technology
generation.
In International Symposium on Low Power Electronics and Design, pages
365-370, Monterey, CA, August 12-14 1996.
- [386]
- K. Bernstein, P. Andry, J. Cann, P. Emma, D. Greenberg,
W. Haensch, M. Ignatowski, S. Koester, J. Magerlein, R. Puri, and A. Young.
Interconnects in the third dimension: design and process challenges for 3d ics.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
562-567, San Diego, CA, June 4-8 2007.
- [387]
- G. M.
Bernstein and M. A. Lieberman.
Secure random number generation using chaotic circuits.
IEEE Transactions on Circuits and Systems, 37(9):1157-1164, September
1990.
- [388]
- V. Bertacco and
M. Damiani.
The disjunctive decomposition of logic functions.
In IEEE/ACM International Conference on Computer-Aided Design, pages
78-82, San Jose, CA, November 9-13 1997.
- [389]
- V. Bertacco.
Humans for EDA and EDA for humans.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
729-733, San Francisco, CA, June 3-7 2012.
- [390]
- D. Bertozzi,
L. Benini, and B. Ricco'.
Parametric timing and power macromodels for high level simulation of low-swing
interconnects.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 307-312, Monterey, California, August 12-14 2002.
- [391]
- D. Bertozzi,
L. Benini, and G. De Micheli.
Error control schemes for on-chip communication links: the energy-reliability
tradeoff.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(6):818-831, June 2005.
- [392]
- R. M. Bevensee.
Probabilistic potential theory applied to electrical engineering problems.
In Proceedings of the IEEE, pages 423-437, April 1973.
Published as Proceedings of the IEEE, volume 61, number 4.
- [393]
- W. T. Beyene.
Application of artifical neural networks to statistical analysis and nonlinear
modeling of high-speed interconnect systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):166-176, January 2007.
- [394]
- D. Bhaduri,
S. K. Shukla, P. S. Graham, and M. B. Gokhale.
Reliability analysis of large circuits using scalable techniques and tools.
IEEE Transactions on Circuits and Systems, 54(11):2447-2460, November
2007.
- [395]
- S. Bhanja and
N. Ranganathan.
Dependency preserving probabilistic modeling of switching activity using
bayesian networks.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
209-214, Las Vegas, NV, June 18-22 2001.
- [396]
- S. Bhanja and
N. Ranganathan.
Switching activity estimation of VLSI circuits using bayesian networks.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):558-567, August 2003.
- [397]
- S. Bhanja and
N. R. Ranganathan.
Cascaded bayesian inferencing for switching activity estimation with correlated
inputs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1360-1370, December 2004.
- [398]
- K. Bharath,
E. Engin, M. Swamminathan, K. Uriu, and T. Yamada.
Computationally efficient power integrity simulation for system-on-package
applications.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
612-617, San Diego, CA, June 4-8 2007.
- [399]
- K. Bharath,
E. Engin, and M. Swaminathan.
Automatic package and board decoupling capacitor placement using genetic
algorithms and M-FDM.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
560-565, Anaheim, CA, June 8-13 2008.
- [400]
- M. Bhardwaj,
R. Min, and A. P. Chandrakasan.
Quantifying and enhancing power awareness of VLSI systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(6):757-772, December 2001.
- [401]
- S. Bhardwaj,
S. B. K. Vrudhula, and D. Blaauw.
Estimation of signal arrival times in the presence of delay noise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 418-422, San Jose, CA, November 10-14 2002.
- [402]
- S. Bhardwaj,
S. B. K. Vrudhula, and D. Blaauw.
TAU: timing analysis under uncertainty.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 615-620, San Jose, CA, November 9-13 2003.
- [403]
- S. Bhardwaj, S. Vrudhula, and D. Blaauw.
Probability distribution of signal arrival times using bayesian networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(11):1784-1794, November 2005.
- [404]
- S. Bhardwaj, P. Ghanta, and S. Vrudhula.
A framework for statistical timing analysis using non-linear delay and slew
models.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 225-230, San Jose, CA, November 5-9 2006.
- [405]
- S. Bhardwaj, S. Vrudhula, P. Ghanta, and Y. Cao.
Modeling of intra-die process variations for accurate analysis and optimization
of nano-scale circuits.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
791-796, San Francisco, CA, July 24-28 2006.
- [406]
- S. Bhardwaj, S. Vrudhula, and A. Goel.
A unified approach for full chip statistical timing and leakage analysis of
nanoscale circuits considering intradie process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1812-1825, October 2008.
- [407]
- S. Bhardwaj and
S. Vrudhula.
Formalizing designer's preferences for multiattribute optimization with
application to leakage-delay tradeoffs.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 713-718, San Jose, CA, November 6-10 2005.
- [408]
- S. Bhardwaj and
S. B. K. Vrudhula.
Leakage minimization of nano-scale circuits in the presence of systematic and
random variations.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
541-546, Anaheim, CA, June 13-17 2005.
- [409]
- S. Bhardwaj and
S. Vrudhula.
Leakage minimization of digital circuits using gate sizing in the presence of
process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(3):445-455, March 2008.
- [410]
- S. Bhattacharjee and D. K. Pradhan.
LPRAM: a novel methodology for low-power high-performance RAM design with
testability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):637-651, May 2004.
- [411]
- M. Bhattacharya and P. Mazumder.
Augmentation of SPICE for simulation of circuits containing resonant
tunneling diodes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(1):39-50, January 2001.
- [412]
- A. J. Bhavnagarwala, B. L. Austin, K. A. Bowman, and J. D.
Meindl.
A minimum total power methodology for projecting limits on CMOS GSI.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):235-251, June 2000.
- [413]
- A. N. Bhoj and N. K. Jha.
Design of logic gates and flip-flops in high-performance finfet technology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(11):1975-1988, November 2013.
- [414]
- P. S.
Bhojwani, J. D. Lee, and R. N. Mahapatra.
SAPP: scalable and adaptable peak power management in nocs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 340-345, Portland, Oregon, August 27-29 2007.
- [415]
- S. Bhunia,
K. Roy, and J. Segura.
A novel wavelet transform based transient current analysis for fault detection
and localization.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
361-366, New Orleans, LA, June 10-14 2002.
- [416]
- S. Bhunia,
N. Banerjee, Q. Chen, H. Mahmoodi, and K. Roy.
A novel synthesis approach for active leakage power reduction using dynamic
supply gating.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
479-484, Anaheim, CA, June 13-17 2005.
- [417]
- S. Bhunia and K. Roy.
A novel wavelet transform-based transient current analysis for fault dectection
and localization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(4):503-507, April 2005.
- [418]
- Y. Bi, K. van der Kolk,
D. Ioan, and N. P. van der Meijs.
Sensitivity computation of interconnect capacitances with respect to geometric
parameters.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 209-212, San Jose, CA, October 27-29 2008.
- [419]
- X. Bi, Z. Sun, and
H. Li.
Probabilistic design methodology to improve run-time stability and performance
of STT-RAM caches.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 88-94, San Jose, CA, November 5-8 2012.
- [420]
- G. Biagetti,
S. Orcioni, L. Signoracci, C. Turchetti, P. Crippa, and M. Alessandrini.
Sisma: A statistical simulator for mismatch analysis of MOS ics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 490-496, San Jose, CA, November 10-14 2002.
- [421]
- G. Biagetti,
S. Orcioni, C. Turchetti, P. Crippa, and M. Alessandrini.
Sisma - a tool for efficient analysis of analog CMOS integrated circuits
affected by device mismatch.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(2):192-207, February 2004.
- [422]
- S. Bilavarn,
G. Gogniat, J.-L. Philppe, and L. Bossuet.
Design space pruning through early estimations of area/delay tradeoffs for
FPGA implementations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):1950-1968, October 2006.
- [423]
- O. Billoint,
H. Sarhan, I. Rayane, M. Vinet, P. Batude, C. Fenouillet-Beranger, O. Rozeau,
G. Cibrario, F. Deprat, O. Turkyilmaz, S. Thuries, and F. Clermidy.
From 2d to monolithic 3d: design possibilities, expectations and challenges.
In ACM International Symposium on Physical Design 2015, page 127,
Monterey, California, March 29 - April 1 2015.
- [424]
- D. Bindel and A. Hood.
Localization theorems for nonlinear eigenvalue problems.
SIAM Review, 57(4):585-607, December 2015.
- [425]
- G. Bischoff and
R. Razdan.
Static charge delay analysis of MOS circuits.
In IEEE Custom Integrated Circuits Conference, pages 8.5.1-8.5.4,
1991.
- [426]
- L. Bisdounis, O. Koufopavlou, and S. Nikolaidis.
Accurate evaluation of CMOS short-circuit power dissipation for short-channel
devices.
In International Symposium on Low Power Electronics and Design, pages
189-192, Monterey, CA, August 12-14 1996.
- [427]
- L. Bisdounis, S. Nikolaidis, and O. Koufopavlou.
Propagation delay and short-circuit power dissipation modeling of the CMOS
inverter.
IEEE Transactions on Circuits and Systems - I: Fundamental Theory and
Applications, 45(3):259-270, March 1998.
- [428]
- B. Bishop,
V. Lyuboslavsky, N. Vijaykrishnan, and M. J. Irwin.
Design considerations for databus charge recovery.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(1):104-106, February 2001.
- [429]
- D. T. Blaauw,
A. Dharchoudhury, R. Panda, S. Sirichotiyakul, C. Oh, and T. Edwards.
Emerging power management tools for processor design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 143-148, Monterey, CA, August 10-12 1998.
- [430]
- D. Blaauw,
V. Zolotov, S. Sundareswaran, C. Oh, and R. Panda.
Slope propagation in static timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 338-343, San Jose, CA, November 5-9 2000.
- [431]
- D. Blaauw,
V. Zolotov, and S. Sundareswaran.
Slope propagation in static timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(10):1180-1195, October 2002.
- [432]
- D. Blaauw,
S. Sirichotiyakul, and C. Oh.
Driver modeling and alignment for worst-case delay noise.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(2):157-166, April 2003.
- [433]
- D. T. Blaauw,
C. Oh, V. Zolotov, and A. Dasgupta.
Static electromigration analysis for on-chip signal interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(1):39-48, January 2003.
- [434]
- D. Blaauw,
K. Chopra, A. Srivastava, and L. Scheffer.
Statistical timing analysis: from basic principles to state of the art.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(4):589-607, April 2008.
- [435]
- D. Blaauw and
K. Chopra.
CAD tools for variation tolerance.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
766-766, Anaheim, CA, June 13-17 2005.
- [436]
- J. R. Black.
Electromigration failure modes in aluminum metallization for semiconductor
devices.
In Proceedings of the IEEE, pages 1587-1594, September 1969.
Published as Proceedings of the IEEE, volume 57, number 9.
- [437]
- R. D. Blanton,
X. Li, K. Mai, D. Marculescu, R. Marculescu, J. Paramesh, J. Schneider, and
D. E. Thomas.
Statistical learning in chip (SLIC).
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 664-669, Austin TX, November 2-6 2015.
- [438]
- S. Bobba,
T. Thorp, K. Aingaran, and D. Lin.
IC power distribution challenges.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 643-650, San Jose, CA, November 4-8 2001.
- [439]
- S. Bobba and I. N. Hajj.
Estimation of maximum current envelope for power bus analysis and design.
In ACM/IEEE International Symposium on Physical Design, pages
141-146, Monterey, CA, April 6-8 1998.
- [440]
- S. Bobba and I. N. Hajj.
Maximum leakage power estimation for CMOS circuits.
In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages
116-124, Como, Italy, March 4-5 1999.
- [441]
- S. Bobba and I. N. Hajj.
Maximum voltage variation in the power distribution network of VLSI circuits
with RLC models.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 376-381, Huntington Beach, California, August 6-7
2001.
- [442]
- S. Bodapati and F. N.
Najm.
Pre-layout estimation of individual wire lengths.
In International Workshop on System-Level Interconnect Prediction,
pages 93-98, San Diego, CA, April 8-9 2000.
- [443]
- S. Bodapati and
F. N. Najm.
Frequency-domain supply current macro-model.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 295-298, Huntington Beach, California, August 6-7
2001.
- [444]
- S. Bodapati and
F. N. Najm.
Prelayout estimation of individual wire lengths.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(6):943-958, December 2001.
- [445]
- S. Bodapati and F. N.
Najm.
High-level current macro-model for power-grid analysis.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
385-390, New Orleans, LA, June 10-14 2002.
- [446]
- S. Bodapati and F. N.
Najm.
High-level current macro model for logic blocks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):837-855, May 2006.
- [447]
- P. Bogdan and Y. Xue.
Mathematical models and control algorithms for dynamic optimization of
multicore platforms: a complex dynamics approach.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 170-175, Austin TX, November 2-6 2015.
- [448]
- A. Bogliolo, L. Benini, G. De Micheli, and B. Ricco.
Gate-level current waveform simulation of CMOS integrated circuits.
In International Symposium on Low Power Electronics and Design, pages
109-112, Monterey, CA, August 12-14 1996.
- [449]
- A. Bogliolo, L. Benini, and B. Ricco.
Power estimation of cell-based CMOS circuits.
In 33rd Design Automation Conference, pages 433-438, Las Vegas, NV,
June 3-7 1996.
- [450]
- A. Bogliolo,
L. Benini, G. De Micheli, and B. Ricco.
Gate-level power and current simulation of CMOS integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
5(4):473-488, December 1997.
- [451]
- A. Bogliolo, L. Benini, B. Ricco, and G. De Micheli.
Efficient switching activity computation during high-level synthesis of
control-dominated designs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 127-132, San Diego, CA, August 16-17 1999.
- [452]
- A. Bogliolo, R. Corgnati, E. Macii, and M. Poncino.
Parametrized RTL power models for combinational soft macros.
In IEEE/ACM International Conference on Computer-Aided Design, pages
284-287, San Jose, CA, November 7-11 1999.
- [453]
- A. Bogliolo, E. Macii, V. Mihailovici, and M. Poncino.
Combinational characterization-based power macro-models for sequential macros.
In Ninth International Workshop on Power and Timing optimization and
Simulation, pages 293-302, Kos, Greece, October 1999.
- [454]
- A. Bogliolo, R. Corgnati, E. Macii, and M. Poncino.
Parametrized RTL power models for soft macros.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(6):880-887, December 2001.
- [455]
- A. Bogliolo and
L. Benini.
Node sampling: a robust RTL power modeling approach.
In IEEE/ACM International Conference on Computer-Aided Design, pages
461-467, San Jose, CA, November 8-12 1998.
- [456]
- A. Bogliolo and
L. Benini.
Robust RTL power macromodels.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(4):578-581, December 1998.
- [457]
- A. Bogliolo.
Encodings for high-performance signaling.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 170-175, Huntington Beach, California, August 6-7
2001.
- [458]
- J. Bokor.
Prospects for emerging nanoelectronics in mainstream information processing
systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 647-648, San Jose, CA, November 5-9 2006.
- [459]
- M. Bolotski and
P. Alvelda.
Low-power miniaturized information display systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 279-281, Monterey, CA, August 10-12 1998.
- [460]
- A. Bona, M. Sami,
D. Sciuto, C. Silvano, V. Zaccaria, and R. Zafalon.
Energy estimation and optimization of embedded VLIW processors based on
instruction clustering.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
886-891, New Orleans, LA, June 10-14 2002.
- [461]
- B. N. Bond,
Z. Mahmood, Y. Li, R. Sredojevgic, A. Megretski, V. Stojanovic, Y. Avniel,
and L. Daniel.
Compact modeling of nonlinear analog circuits using system identification via
semidefinite programming and incremental stability certification.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(8):1149-1162, August 2010.
- [462]
- B. N. Bond and L. Daniel.
A piecewise-linear moment-matching approach to parametrized model-order
reduction for highly nonlinear systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(12):2116-2129, December 2007.
- [463]
- B. N. Bond and L. Daniel.
Stabilizing schemes for piecewise-linear reduced order models via projection
and weighting functions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 860-867, San Jose, CA, November 5-8 2007.
- [464]
- B. N. Bond and L. Daniel.
Guaranteed stable projection-based model reduction for indefinite and unstable
linear systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 728-735, San Jose, CA, November 10-13 2008.
- [465]
- B. N. Bond and L. Daniel.
Automated compact dynamical modeling: An enabling tool for analog designers.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
415-420, Anaheim, CA, June 13-18 2010.
- [466]
- M. Borah, R. M.
Owens, and M. J. Irwin.
Transistor sizing for low power CMOS circuits.
IEEE Transactions on Computer-Aided Design, 15(6):665-671, June
1996.
- [467]
- S. Borkar,
T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De.
Parameter variations and impact on circuits and microarchitecture.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
338-342, Anaheim, CA, June 2-6 2003.
- [468]
- S. Borkar,
T. Karnik, and V. De.
Design and reliability challenges in nanometer technologies.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 75-75,
San Diego, CA, June 7-11 2004.
- [469]
- S. Borkar.
Design challenges of technology scaling.
In IEEE/ACM International Symposium on Microarchitecture (MICRO-32),
pages 23-29, November 16-18 1999.
- [470]
- S. Borkar.
Thousand-core chips - a technology perspective.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
746-749, San Diego, CA, June 4-8 2007.
- [471]
- S. Borkar.
Design perspectives on 22nm CMOS and beyond.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 93-94,
San Francisco, CA, July 26-31 2009.
- [472]
- S. Borkar.
3d integration for energy efficient system design.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
214-219, San Diego, CA, June 5-9 2011.
- [473]
- A. K. Bose,
P. Kozak, C-Y Lo, H. N. Nham, E. Pacas-Skewes, and K. Wu.
A fault simulator for MOS LSI circuits.
In IEEE 19th Design Automation Conference, pages 400-409, June
1982.
- [474]
- G. Boselli,
G. Trucco, and V. Liberali.
Properties of digital switching currents in fully CMOS combinational logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(12):1625-1638, December 2010.
- [475]
- B. E. Boser.
From micro to nano: MEMS as an interface to the nano world.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 824-825, San Jose, CA, November 5-9 2006.
- [476]
- M. J. Bosley and F. P.
Lees.
A survey of simple transfer-function derivations from high-order state-variable
models.
Automata, 8:765-775, 1972.
- [477]
- C. S.
Bouganis, K. Pournara, and P. Y. K. Cheung.
Exploration of heterogeneous fpgas for mapping linear projection designs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(3):436-449, March 2010.
- [478]
- V. Bourenkov, K. G. McCarthy, and A. Mathewson.
MOS table models for circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):352-362, March 2005.
- [479]
- C. Bowen.
Walking a thin line: performance and quality grading vs. yield overcut.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [480]
- W. J. Bowhill and
et al.
Circuit implementation of a 300-mhz 64-bit second-generation CMOS alpha
CPU.
Digital Technical Journal, 7(1):100-118, July 1995.
- [481]
- K. A. Bowman,
B. L. Austin, J. C. Eble, X. Tang, and J. D. Meindl.
A physical alpha-power law MOSFET model.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 218-222, San Diego, CA, August 16-17 1999.
- [482]
- K. A. Bowman,
X. Tang, J. C. Eble, and J. D. Meindl.
Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit
performance.
IEEE Journal of Solid-State Circuits, 35(8):1186-1193, August
2000.
- [483]
- K. A. Bowman,
S. G. Duvall, and J. D. Meindl.
Impact of die-to-die and within-die parameter fluctuations on the maximum clock
frequency distribution.
In IEEE International Solid-State Circuits Conference (ISSCC), pages
278-279, San Francisco, CA, February 4-8 2001.
- [484]
- K. A. Bowman,
S. B. Samaan, and N. Z. Hakim.
Maximum clock frequency distribution model with practical VLSI design
considerations.
In International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 183-191, Austin, TX, May 17-20 2004.
- [485]
- K. Bowman,
J. Tschanz, M. Khellah, M. Ghoneima, Y. I. Ismail, and V. De.
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 79-84, Tegernsee, Germany, October 4-6 2006.
- [486]
- K. A. Bowman,
A. R. Alameldeen, S. T. Srinivasan, and C. B. Wilkerson.
Impact of die-to-die and within-die parameter variations on the throughput
distribution of multi-core processors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 50-55, Portland, Oregon, August 27-29 2007.
- [487]
- K. Bowman,
J. Tschanz, C. Wilkerson, S.-L. Lu, T. Karnik, V. De, and S. Borkar.
Circuit techniques for dynamic variation tolerance.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 4-7,
San Francisco, CA, July 26-31 2009.
- [488]
- K. A. Bowman,
A. R. Alameldeen, S. T. Srinivasan, and C. B. Wilkerson.
Impact of die-to-die and within-die parameter variations on the clock frequency
and throughput of multi-core processors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(12):1679-1690, December 2009.
- [489]
- K. A. Bowman and J. D.
Meindl.
Impact of within-die parameter fluctuations on future maximum clock frequency
distributions.
In IEEE Custom Integrated Circuits Conference (CICC), pages 229-232,
2001.
- [490]
- K. A. Bowman and J. W.
Tschanz.
Resilient microprocessor design for improving performance and energy
efficiency.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 85-88, San Jose, CA, November 7-11 2010.
- [491]
- S. Boyd, L. El
Ghaoui, E. Feron, and V. Balakrishnan.
Linear matrix inequalities in system and control theory.
Society for Industrial and Applied Mathematics (SIAM), Philadelphia, PA,
1994.
- [492]
- J. P. Boyd.
Finding the zeros of a univariate equation: proxy rootfinders, chebyshev
interpolation, and the companion matrix.
SIAM Review, 55(2):375-396, June 2013.
- [493]
- E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh.
Optimal integer delay budgeting on directed acyclic graphs.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
920-925, Anaheim, CA, June 2-6 2003.
- [494]
- K. Brace, R. L.
Rudell, and R. E. Bryant.
Efficient implementation of a BDD package.
In 27th ACM/IEEE Design Automation Conference, pages 40-45, Orlando,
FL, June 24-28 1990.
- [495]
- H. G. Brachtendorf, R. Melville, P. Feldmann, and S. Lampe.
Homotopy method for finding the steady states of oscillators.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(6):867-878, June 2014.
- [496]
- J. E. Bracken,
V. Raghavan, and R. A. Rohrer.
Extension of the asymptotic waveform evaluation technique with the method of
characteristics.
In IEEE/ACM International Conference on Computer-Aided Design, pages
71-75, Santa Clara, CA, November 8-12 1992.
- [497]
- A. R.
Brahmbhatt, J. Zhang, Q. Wu, and Q. Qiu.
Low-power bus encoding using an adaptive hybrid algorithm.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
987-990, San Francisco, CA, July 24-28 2006.
- [498]
- A. Brambilla, A. Premoli, and G. Storti-Gajani.
Recasting modified nodal analysis to improve reliability in numerical circuit
simulation.
IEEE Transactions on Circuits and Systems, 52(3):522-534, March
2005.
- [499]
- A. Brambilla and
D. D'Amore.
Energy-based control of numerical errors in time-domain simulation of dynamic
circuits.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(5):543-551, May 2001.
- [500]
- A. Brambilla
and P. Maffezzoni.
Statistical method for the analysis of interconnect delay in submicrometer
layouts.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(8):957-966, August 2001.
- [501]
- A. Brambilla and G. Storti-Gajani.
Frequency warping in time-domain circuit simulation.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(7):904-913, July 2003.
- [502]
- D. Brand, R. A.
Bergamaschi, and L. Stok.
Don't cares in synthesis: theoretical pitfalls and practical solutions.
IEEE Transactions on Computer-Aided Design, 17(4):285-304, April
1998.
- [503]
- D. Brand and
C. Visweswariah.
Inaccuracies in power estimation during logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
388-394, San Jose, CA, November 10-14 1996.
- [504]
- D. Brand.
Detecting sneak paths in transistor networks.
IEEE Transactions on Computers, C-35(3):274-278, March 1986.
- [505]
- D. Brand.
Exhaustive simulation need not require an exponential number of tests.
In IEEE/ACM International Conference on Computer-Aided Design, pages
98-101, Santa Clara, CA, November 8-12 1992.
- [506]
- Y. Brandman,
A. Orlitsky, and J. Hennessy.
A spectral lower bound technique for the size of decision trees and two-level
AND/OR circuits.
IEEE Transactions on Computers, 39(2):282-287, February 1990.
- [507]
- C. Brandolese, W. Fomaciani, F. Salice, and D. Suito.
An instruction-level functionality-based energy estimation model for 32-bits
microprocessors.
In Design Automation Conference, pages 346-351, Los Angeles, CA, June
5-9 2000.
- [508]
- C. Brandolese, F. Salice, W. Fornaciari, and D. Sciuto.
Static power modeling of 32-bit microprocessors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(11):1306-1316, November 2002.
- [509]
- C. Brandolese, W. Fornaciari, and F. Salice.
An area estimation methodology for FPGA based designs at systemc-level.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
129-132, San Diego, CA, June 7-11 2004.
- [510]
- F. H. Branin, Jr.
Transient analysis of lossless transmission lines.
In Proceedings of the IEEE, pages 2012-2013, November 1967.
Published as Proceedings of the IEEE, volume 55, number 11.
- [511]
- F. H. Branin, Jr.
The analysis and design of power distribution nets on LSI chips.
In IEEE International Conference on Circuits and Computers, pages
785-790, Port Chester, NY, October 1-3 1980.
- [512]
- R. B.
Brashear, D. R. Holberg, M. Ray Mercer, and L. T. Pillage.
ETA: Electrical-level timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
258-262, Santa Clara, CA, November 8-12 1992.
- [513]
- R. K. Brayton,
A. J. Hoffman, and T. R. Scott.
A theorem on inverses of convex sets of real matrices with application to the
worst case DC problem.
IEEE Transactions on Circuits and Systems, 24(8):409-415, August
1977.
- [514]
- Robert K.
Brayton, Gary D. Hachtel, Curtis T. McMullen, and Alberto L.
Sangiovanni-Vincentelli.
Logic Minimization Algorithms for VLSI Synthesis.
Kluwer Academic Publishers, Hingham, MA, 1984.
- [515]
- R. K. Brayton.
Compatible observability don't cares revisited.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 618-623, San Jose, CA, November 4-8 2001.
- [516]
- J. P. Brennan,
A. Dean, S. Kenyon, and S. Ventrone.
Low power methodology and design techniques for processor design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 268-273, Monterey, CA, August 10-12 1998.
- [517]
- U. Brenner.
Boonplace legalization: minimizing movement by iterative augmentation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(8):1215-1227, August 2013.
- [518]
- M. A. Breuer,
M. Sarrafzadeh, and F. Somenzi.
Fundamental CAD algorithms.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1449-1475, December 2000.
- [519]
- M. A. Breuer and
R. L. Harrison.
Procedures for eliminating static and dynamic hazards in test generation.
IEEE Transactions on Computers, C-23(10):1069-1974, October 1974.
- [520]
- M. Breuer.
Hardware that produces bounded rather than exact results.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
871-876, Anaheim, CA, June 13-18 2010.
- [521]
- F. Brglez,
D. Bryan, and K. Kozminski.
Combinational profiles of sequential benchmark circuits.
In IEEE International Symposium on Circuits and Systems, pages
1929-1934, 1989.
- [522]
- F. Brglez and
H. Fujiwara.
A neutral netlist of 10 combinational benchmark circuits and a target
translator in fortran.
In IEEE International Symposium on Circuits and Systems (ISCAS-85),
pages 663-698,, June 1985.
- [523]
- F. Brglez.
On testability analysis of combinational networks.
In IEEE International Symposium on Circuits and Systems, pages
221-225, 1984.
- [524]
- J. Briaire and K. S.
Krisch.
Principles of substrate crosstalk generation in CMOS circuits.
IEEE Transactions on Computer-Aided Design, 19(6):645-653, June
2000.
- [525]
- L. M. Brocco,
S. P. McCormick, and J. Allen.
Macromodeling CMOS circuits for timing simulation.
IEEE Transactions on Computer-Aided Design, 7(12):1237-1249, December
1988.
- [526]
- R. W.
Broderesen, M. A. Horowitz, D. Markovic, B. Nikolic, and V. Stojanovic.
Methods for true power minimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 35-42, San Jose, CA, November 10-14 2002.
- [527]
- R. W.
Brodersen, A. Chandrakasan, and S. Sheng.
Technologies for personal communications.
In 1991 Symposium on VLSI Circuits, pages 5-9, Tokyo, Japan, 1991.
- [528]
- S. Brokar.
Electronics beyond nano-scale CMOS.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
807-808, San Francisco, CA, July 24-28 2006.
- [529]
- R. F. Brown.
Model stability in use of moments to estimate pulse transfer functions.
Electronics Letters, 7(19):587-589, September 23 1971.
- [530]
- S. D. Brown.
An overview of technology, architecture and CAD tools for programmable logic
devices.
In IEEE Custom Integrated Circuits Conference, pages 69-76, 1994.
- [531]
- M. Brownlee,
P. K. Hanumolu, U.-K. Moon, and K. Mayaram.
The effect of power supply noise on right oscillator phase noise.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 225-228, Montreal, Quebec, June 20-23 2004.
- [532]
- D. Bruni,
G. Oliveri, A. Bogliolo, and L. Benini.
Delay-sensitive power estimation at the register-transfer level.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 1031-1034, St. Julian, Malta, September 2-5 2001.
- [533]
- L. Brusamarello, R. da Silva, G. I. Wirth, and R. A. L. Reis.
Probabilistic approach for yield analysis of dynamic logic circuits.
IEEE Transactions on Circuits and Systems, 55(8):2238-2248, September
2008.
- [534]
- K. Bryan and T. Leise.
Making do with less: an introduction to compressed sensing.
SIAM Review, 55(3):547-566, September 2013.
- [535]
- R. E. Bryant and Y-A.
Chen.
Verification of arithmetic circuits with binary moment diagrams.
In 32nd Design Automation Conference, pages 535-541, San Francisco,
CA, June 12-16 1995.
- [536]
- R. E. Bryant.
An algorithm for MOS logic simulation.
LAMDA, (Fourth Quarter):46-53, 1980.
- [537]
- R. E. Bryant.
A switch-level model and simulator for MOS digital systems.
IEEE Transactions on Computers, C-33(2):160-177, February 1984.
- [538]
- R. E. Bryant.
Graph-based algorithms for boolean function manipulation.
IEEE Transactions on Computers, C-35(8):677-691, August 1986.
- [539]
- R. E. Bryant.
Algorithmic aspects of symbolic switch network analysis.
IEEE Transactions on Computer-Aided Design, CAD-6(4):618-633, July
1987.
- [540]
- R. E. Bryant.
Boolean analysis of MOS circuits.
IEEE Transactions on Computer-Aided Design, CAD-6(4):634-649, July
1987.
- [541]
- R. E. Bryant.
A survey of switch-level algorithms.
IEEE Design & Test of Computers, 4(4):26-40, August 1987.
- [542]
- R. E. Bryant.
Binary decision diagrams and beyond: enabling technologies for formal
verification.
In IEEE/ACM International Conference on Computer-Aided Design, pages
236-243, San Jose, CA, November 5-9 1995.
- [543]
- I. Brynjolfson
and Z. Zilic.
Dynamic clock management for low power applications in fpgas.
In IEEE Custom Integrated Circuits Conference (CICC), pages
7.3.1-7.3.4, 2000.
- [544]
- M. Bucci,
L. Germani, R. Luzzi, P. Tommasino, A. Trifiletti, and M. Varanonuovo.
A high-speed IC random-number source for smartcard microcontrollers.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(11):1373-1380, November 2003.
- [545]
- M. Bucci,
L. Giancane, R. Luzzi, G. Scotti, and A. Trifiletti.
Delay-based dual-rail precharge logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(7):1147-1153, July 2011.
- [546]
- P. Buch, C. K.
Lennard, and A. R. Newton.
Engineering change for power optimization using global sensitivity and
synthesis flexibility.
In 1997 International Symposium on Low Power Electronics and Design,
pages 88-91, Monterey, CA, August 18-20 1997.
- [547]
- P. Buch,
A. Narayan, A. R. Newton, and A. Sangiovanni-Vincentelli.
Logic synthesis for large pass transistor circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
663-670, San Jose, CA, November 9-13 1997.
- [548]
- R. K.
Budhathoki, M. Pd. Sah, S. P. Adhikari, H. Kim, and L. Chua.
Composite behavior of multiple memristor circuits.
IEEE Transactions on Circuits and Systems, 60(10):2688-2700, October
2013.
- [549]
- M. Budnik,
A. Raychowdhury, A. Bansal, and K. Roy.
A high density, carbon nanotube capacitor for decoupling applications.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
935-938, San Francisco, CA, July 24-28 2006.
- [550]
- M. M. Budnik and K. Roy.
A power delivery and decoupling network minimizing ohmic loss and supply
voltage variation in silicon nanoscale technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(12):1336-1346, December 2006.
- [551]
- D. Bufistov,
J. Cortadella, M. Kishinevsky, and S. Sapatnekar.
A general model for performance optimization of sequential systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 362-369, San Jose, CA, November 5-8 2007.
- [552]
- D. E.
Bufistov, J. Cortadella, M. Galceran-Oms, J. Julvez, and M. Kishinevsky.
Retiming and recycling for elastic systems with early evaluation.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
288-291, San Francisco, CA, July 26-31 2009.
- [553]
- V. Bulovi,
I. Kymissis, I. Nausieda, K. Ryu, A. Wang, A. I. Akinwande, and C. G. Sodini.
Molecular organic electronic circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 830-831, San Jose, CA, November 5-9 2006.
- [554]
- J. Bunda, W. C.
Athas, and D. Fussell.
Evaluating power implications of CMOS microprocessor design decisions.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
147-152, Napa, CA, April 24-27 1994.
- [555]
- W. L Buntine,
L. Su, A. R. Newton, and A. Mayer.
Adaptive methods for netlist partitioning.
In IEEE/ACM International Conference on Computer-Aided Design, pages
356-363, San Jose, CA, November 9-13 1997.
- [556]
- A. Buonomo and A. L.
Schiavo.
A constructive method for finding the periodic response of nonlinear circuits.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(7):885-893, July 2003.
- [557]
- R. Burch,
J. Hall, F. Najm, D. Hocevar, P. Yang, and M. McGraw.
A CAD system for measuring voltage drop and electromigration in VLSI
metallization patterns.
Texas Instruments Technical Journal, 5(3):74-84, May-June 1988.
- [558]
- R. Burch,
F. Najm, P. Yang, and D. Hocevar.
Pattern-independent current estimation for reliability analysis of CMOS
circuits.
In 25th ACM/IEEE Design Automation Conference, pages 294-299,
Anaheim, CA, June 12-15 1988.
- [559]
- R. Burch, F. Najm,
P. Yang, and T. Trick.
Mcpower: A monte carlo approach to power estimation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
90-97, Santa Clara, CA, November 8-12 1992.
- [560]
- R. Burch, F. Najm,
P. Yang, and T. Trick.
A monte carlo approach for power estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
1(1):63-71, March 1993.
- [561]
- T. D. Burd and R. W.
Brodersen.
Design issues for dynamic voltage scaling.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 9-14, Italy, July 26-27 2000.
- [562]
- A. Burg,
C. Benkeser, C. Roth, and G. Karakonstantis.
On the exploitation of the inherent error resilience of wireless systems under
unreliable silicon.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
510-515, San Francisco, CA, June 3-7 2012.
- [563]
- D. Burke and T. Smy.
Thermal models for optical circuit simulation using a finite cloud method and
model reduction techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(8):1177-1186, August 2013.
- [564]
- T. M. Burks, K. A.
Sakallah, and T. N. Mudge.
Critical paths in circuits with level-sensitive latches.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
3(2):273-291, June 1995.
- [565]
- T. M. Burks and K. A.
Sakallah.
Min-max linear programming and the timing analysis of digital circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
152-155, Santa Clara, CA, November 7-11 1993.
- [566]
- W. P.
Burleson, M. Ciesielski, F. Klass, and W. Liu.
Wave-pipelining: A tutorial and research survey.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(3):464-474, September 1998.
- [567]
- J. R. Burnham,
C.-K. K. Yang, and H. Hindi.
A stochastic jitter model for analyzing digital timing-recovery circuits.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
116-121, San Francisco, CA, July 26-31 2009.
- [568]
- S. M. Burns,
M. Ketkar, N. Menezes, K. A. Bowman, J. W. Tschanz, and V. De.
Comparative analysis of conventional and statistical design techniques.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 31-36, Austin, Texas,
February 26-27 2007.
- [569]
- S. M. Burns,
M. Ketkar, N. Menezes, K. A. Bowman, J. W. Tschanz, and V. De.
Comparative analysis of conventional and statistical design techniques.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
238-243, San Diego, CA, June 4-8 2007.
- [570]
- J. Burns,
G. Carpenter, E. Kursun, R. Puri, J. Warnock, and M. Scheuermann.
Design, CAD and technology challenges for future processors: 3d perspectives.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
212-212, San Diego, CA, June 5-9 2011.
- [571]
- S. Bush.
Automatic generation of gate level models with accurate timing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 52-55, 1987.
- [572]
- M. Butts,
A. DeHon, and S. C. Goldstein.
Molecular electronics: Devices, systems and tools for gigagate, gigabit chips.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 433-440, San Jose, CA, November 10-14 2002.
- [573]
- K. M.
Buyuksahin, P. Patra, and F. N. Najm.
ESTIMA: an architectural-level power estimator for multi-ported pipelines
register files.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 294-297, Seoul, Korea, August 25-27 2003.
- [574]
- K. M. Buyuksahin
and F. N. Najm.
High-level power estimation with interconnect effects.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 197-202, Italy, July 26-27 2000.
- [575]
- K. M. Buyuksahin
and F. N. Najm.
High-level area estimation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 271-274, Monterey, California, August 12-14 2002.
- [576]
- K. M. Buyuksahin
and F. N. Najm.
Early power estimation for VLSI circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):1076-1088, July 2005.
- [577]
- R. H. Byrd, G. D.
Hachtel, M. R. Lightner, and M. H. Heydemann.
Switch level simulation: models, theory, and algorithms.
In A. L. Sangiovanni-Vincentelli, editor, Advances in Computer-Aided
Engineering Design, pages 93-148. JAI Press Inc., 1985.
- [578]
- E. Cai, D. Stamoulis,
and D. Marculescu.
Exploring aging deceleration in finfet-based multi-core systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [579]
- J-P. Caisso,
E. Cerny, and N. C. Rumin.
A recursive technique for computing delays in series-parallel MOS transistor
circuits.
IEEE Transactions on Computer-Aided Design, 10(5):589-595, May
1991.
- [580]
- N. Calazans,
R. Jacobi, Q. Zhang, and C. Trullemans.
Improving bdds manipulation through incremental reduction and enhanced
heuristics.
In IEEE Custom Integrated Circuits Conference, pages 11.3.1-11.3.5,
1991.
- [581]
- A. E.
Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, and A. Zelikovsky.
On wirelength estimation for row-based placement.
In ACM/IEEE International Symposium on Physical Design, pages 4-11,
Monterey, CA, April 6-8 1998.
- [582]
- A. E.
Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, and A. Zelikovsky.
On wirelength estimations for row-based placement.
IEEE Transactions on Computer-Aided Design, 18(9):1265-1278,
September 1999.
- [583]
- B. H. Calhoun,
F. A. Honore, and A. Chandrakasan.
Design methodology for fine-grained leakage control in MTCMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 104-109, Seoul, Korea, August 25-27 2003.
- [584]
- B. H. Calhoun,
A. Wang, N. Verma, and A. Chandrakasan.
Sub-threshold design: the challenges of minimizing circuit energy.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 366-368, Tegernsee, Germany, October 4-6 2006.
- [585]
- B. H. Calhoun
and A. Chandrakasan.
Characterizing and modeling minimum energy operation for subthreshold circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 90-95, Newport Beach, CA, August 9-11 2004.
- [586]
- B. H. Calhoun and
K. Craig.
Flexible on-chip power delivery for energy efficient heterogeneous systems.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [587]
- A. Calimera,
R. I. Bahar, E. Macii, and M. Poncino.
Temperature-insensitive dual-vth synthesis for nanometer CMOS technologies
under inverse temperature dependence.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(11):1608-1620, November 2010.
- [588]
- N. Callegari, P. Bastani, L.-C. Wang, and M. S. Abadir.
A statistical diagnosis approach for analyzing design - silicon timing
mismatch.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(11):1728-1741, November 2009.
- [589]
- N. Callegari, L.-C. Wang, and P. Bastani.
Speedpath analysis based on hypothesis pruning and ranking.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
346-351, San Francisco, CA, July 26-31 2009.
- [590]
- D. Van
Campenhout, T. Mudge, and K. A. Sakallah.
Timing verification of sequential dynamic circuits.
IEEE Transactions on Computer-Aided Design, 18(5):645-658, May
1999.
- [591]
- P. Camurati,
P. Prinetto, and M. Sonza Reorda.
Random testability analysis : comparing and evaluating existing approaches.
In IEEE International Conference on Computer Design, pages 70-73,
1988.
- [592]
- A. C. Cangellaris.
Confronting and exploiting operating environment uncertainty in predictive
analysis of signal integrity.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 496, San Jose, CA, November 5-8 2012.
- [593]
- F. Cannillo,
C. Toumazou, and T. S. Lande.
Nanopower subthreshold MCML in submicrometer CMOS technology.
IEEE Transactions on Circuits and Systems, 56(8):1598-1611, August
2009.
- [594]
- R. Y. Cannon and K. D.
Brown.
Equation based timing: methodology and model for cell libraries.
In IEEE Custom Integrated Circuits Conference, pages 367-370, Santa
Clara, CA, May 1-4 1995.
- [595]
- M.-A. Cantin,
Y. Savaria, D. Prodanos, and P. Lavoie.
A metric for automatic word-length determination of hardware datapaths.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2228-2231, October 2006.
- [596]
- A. Cao, A. Adalal,
J. Bauman, P. Delisle, P. Dedood, P. Donehue, M. Dell'OcaKhouja, T. Doan,
M. Doreswamy, P. Ferolito, O. Geva, D. Greenhill, S. Gopaladhine, J. Irwin,
L. Lev, J. MacDonald, M. Ma, S. Mitra, P. Patel, A. Prabhu, et al.
CAD methodology for the design of the ultrasparc-I microprocessor at SUN
microsystems inc.
In 32nd Design Automation Conference, pages 19-22, San Francisco, CA,
June 12-16 1995.
- [597]
- Y. Cao, C. Hu,
X. Huang, A. B. Kahng, S. Muddu, D. Stroobandt, and D. Sylvester.
Effects of global interconnect optimizations on performance estimation of deep
submicron design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 56-61, San Jose, CA, November 5-9 2000.
- [598]
- Y. Cao, X. Huang,
N. Chang, S. Lin, O. S. Nakagawa, W. Xie, and C. Hu.
Effective on-chip inductance modeling for muliple signal lines and application
on repeater insertion.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 185-190, San Jose, CA, March 26-28 2001.
- [599]
- Y. Cao, Y.-M. Lee,
T.-H. Chen, and C. C.-P. Chen.
Hiprime: Hierarchical and passivity reserved interconnect macromodeling engine
for RLKC power delivery.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
379-384, New Orleans, LA, June 10-14 2002.
- [600]
- Y. Cao, C. Hu,
X. Huang, A. B. Kahng, I. L. Markov, M. Oliver, D. Stroobandt, and
D. Sylvester.
Improved a priori interconnect predictions and technology extrapolation in the
GTX system.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
11(1):3-14, February 2003.
- [601]
- Y. Cao, X.-D. Yang,
X. Huang, and D. Sylvester.
Switch-factor based loop RLC modeling for efficient timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 848-853, San Jose, CA, November 9-13 2003.
- [602]
- Y. Cao, X. Yang,
X. Huang, and D. Sylvester.
Switch-factor based loop RLC modeling for efficient timing analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(9):1072-1078, September 2005.
- [603]
- K. Cao, S. Dobre, and
J. Hu.
Standard cell characterization considering lithography induced variations.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
801-804, San Francisco, CA, July 24-28 2006.
- [604]
- Y. Cao and L. T. Clark.
Mapping statistical process variations toward circuit performance variability:
an analytical modeling approach.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
658-663, Anaheim, CA, June 13-17 2005.
- [605]
- Y. Cao and L. T. Clark.
Mapping statistical process variations toward circuit performance variability:
An analytical modeling approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(10):1866-1873, October 2007.
- [606]
- A. Cao and C.-K. Koh.
Post-layout logic optimization of domino circuits.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
820-825, San Diego, CA, June 7-11 2004.
- [607]
- Y. Cao and H. Yasuura.
A system-level energy minimization approach using datapath width optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 231-236, Huntington Beach, California, August 6-7
2001.
- [608]
- L. Cao.
Circuit power estimation using pattern recognition techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 412-417, San Jose, CA, November 10-14 2002.
- [609]
- M. Capobianchi, V. Labay, F. Shi, and G. Mizushima.
Simulating the electrical behaviour of integrated circuit devices in the
presence of thermal interactions.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2231-2241, October 2006.
- [610]
- L. Capodieci, P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang.
Toward a methodology for manufacturability-driven design rule exploration.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
311-316, San Diego, CA, June 7-11 2004.
- [611]
- J.-A.
Carballo, J. L. Burns, S.-M. Yoo, I. Vo, and V. R. Norman.
A semi-custom voltage-island technique and its application to high-speed serial
links.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 60-65, Seoul, Korea, August 25-27 2003.
- [612]
- F. Carbognani, F. Buergin, N. Felber, H. Kaeslin, and
W. Fichtner.
Transmission gates combined with level-restoring CMOS gates reduce glitches
in low-power low-frequency multipliers.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(7):830-836, July 2008.
- [613]
- J. Carletta,
R. Veillette, F. Krach, and Z. Fang.
Determining appropriate precisions for signals in fixed-point IIR filters.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
656-661, Anaheim, CA, June 2-6 2003.
- [614]
- L. P. Carloni,
P. C. McGeer, A. Saldanha, and A. L. Sangiovanni-Vincentelli.
Trace driven logic synthesis - application to power minimization.
In IEEE/ACM International Conference on Computer-Aided Design, pages
581-588, San Jose, CA, November 9-13 1997.
- [615]
- J. Carmona,
J.-M. Colom, J. Cortadella, and F. Garcia-Valles.
Synthesis of asynchronous controllers using integer linear programming.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1637-1651, September 2006.
- [616]
- J. Carmona,
J. Cortadella, Y. Takada, and F. Peper.
From molecular interactions to gates: a systematic approach.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 891-898, San Jose, CA, November 5-9 2006.
- [617]
- D. De Caro.
Glitch-free NAND-based digitally controlled delay-lines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(1):55-66, January 2013.
- [618]
- J. A. Carrasco and
V. Sune.
An ROBDD-based combinatorial method for the evaluation of yield of
defect-tolerant systems-on-chip.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):207-220, February 2009.
- [619]
- B. Carre.
Graphs and networks.
Clarendon Press-Oxford, Oxford, 1979.
- [620]
- H. Caruso.
The ESS muddle: physics vs relics.
In Annual Reliability and Maintainability Symposium, pages 233-241,
Washington, DC, January 16-19 1995.
- [621]
- G. Casinovi and A. Sangiovanni-Vincentelli.
A macromodeling algorithm for analog circuits.
IEEE Transactions on Computer-Aided Design, 10(2):150-160, February
1991.
- [622]
- G. Casinovi and
C. Young.
Estimation of power dissipation in switched-capacitor circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(12):1625-1636, December 2003.
- [623]
- P. Caspi, A. Mili,
and Ch. Robach.
An information measure on nets - application to the testability of digital
systems.
In B. Dubuisson, editor, Information and Systems, pages 35-39.
Pergamon, New York, NY, 1978.
- [624]
- M. R. Casu,
M. Graziano, G. Masera, G. Piccinini, and M. Zamboni.
An electromigration and thermal model of power wires for a priori high-level
reliability prediction.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):349-358, April 2004.
- [625]
- B. Catanzaro, K. Keutzer, and B.-Y. Su.
Parallelizing CAD: a timely research agenda for EDA.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages 12-17,
Anaheim, CA, June 8-13 2008.
- [626]
- S. Cauley,
V. Balakrishnan, and C.-K. Koh.
A parallel direct solver for the simulation of large-scale power/ground
networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):636-641, April 2010.
- [627]
- E. Cerny, J. P.
Hayes, and N. C. Rumin.
Accuracy of magnitude-class calculations in switch-level modeling.
IEEE Transactions on Computer-Aided Design, 11(4):443-452, April
1992.
- [628]
- E. Cerny and J. Gecsei.
Simulation of MOS circuits by decision diagrams.
IEEE Transactions on Computer-Aided Design, CAD-4(4):685-693, October
1985.
- [629]
- E. Cerny and C. Mauras.
Tautology checking using cross-controllability and cross-observability
relations.
In IEEE International Conference on Computer-Aided Design, pages
34-37, Santa Clara, CA, November 11-15 1990.
- [630]
- N. Chabini and W. Wolf.
Reducing dynamic power consumption in synchronous sequential digital designs
using retiming and supply voltage scaling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(6):573-589, June 2004.
- [631]
- D. Chai,
A. Kondratyev, Y. Ran, K. H. Tseng, Y. Watanabe, and M. Marek-Sadowska.
Temporofunctional crosstalk noise analysis.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
860-863, Anaheim, CA, June 2-6 2003.
- [632]
- W. Chai and D. Jiao.
Direct matrix solution of linear complexity for surface integral-equation based
impedance extraction of high bandwidth interconnects.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
206-211, San Diego, CA, June 5-9 2011.
- [633]
- G. J. Chaitin.
Randomness and mathematical proof.
Scientific American, 232(5):47-52, May 1975.
- [634]
- G. R. Chaji and S. M.
Fakhraie.
A low-power high-performance digital circuit for deep submicron techniques.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 123-126, Quebec City, Quebec, June 19-22 2005.
- [635]
- C. Chakrabarti, T. Mudge, S. Mahlke, Y. Park, M. Woh,
R. Dreslinski, S. Seo, and D. Blaauw.
Process variation in near-threshold wide SIMD architectures.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
980-987, San Francisco, CA, June 3-7 2012.
- [636]
- K. Chakrabarty, R. B. Fair, and J. Zeng.
Design tools for digital microfluidic biochips: toward functional
diversification and more than moore.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(7):1001-1017, July 2010.
- [637]
- K. Chakrabarty.
Design automation and test solutions for digital microfluidic biochips.
IEEE Transactions on Circuits and Systems, 57(1):4-17, January
2010.
- [638]
- A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram,
L. Benini, A. Macii, E. Macii, and M. Poncino.
Dynamic thermal clock skew compensation using tunable delay buffers.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(6):639-649, June 2008.
- [639]
- S. Chakraborty, A. Annaswamy, L. Thiele, D. Goswami, P. Kumar,
and K. Lampka.
A hybrid approach to cyber-physical systems verification.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
688-696, San Francisco, CA, June 3-7 2012.
- [640]
- A. Chakraborty
and D.-Z. Pan.
Skew management of NBTI impacted gated clock trees.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):918-927, June 2013.
- [641]
- S. T.
Chakradhar, M. L. Bushnell, and V. D. Agrawal.
Automatic test generation using neural networks.
In IEEE International Conference on Computer-Aided Design, pages
416-419, Santa Clara, CA, Nov. 7-10 1988.
- [642]
- S. T.
Chakradhar, V. D. Agrawal, and M. L. Bushnell.
Automatic test generation using quadratic 0-1 programming.
In 27th ACM/IEEE Design Automation Conference (DAC90), pages 654-659,
Orlando, FL, June 24-28 1990.
- [643]
- S. T.
Chakradhar and A. Raghunathan.
Best-effort computing: re-thinking parallel software and hardware.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
865-870, Anaheim, CA, June 13-18 2010.
- [644]
- S. Chakravarty
and H. B. Hunt, III.
On the computation of detection probability for multiple faults.
In IEEE International test conference, pages 252-262, Sept. 8-11
1986.
- [645]
- S. Chakravarty
and H. B. Hunt, III.
A note on detecting sneak paths in transistor networks.
IEEE Transactions on Computers, 38(6):861-864, June 1989.
- [646]
- S. Chakravarty
and H. B. Hunt, III.
On computing signal probability and detection probability of stuck-at faults.
IEEE Transactions on Computers, 39(11):1369-1377, November 1990.
- [647]
- S. Chakravarty
and H. B. Hunt, III.
On computing reliability-measures of boolean circuits.
IEEE Transactions on Reliability, 40(5):582-592, December 1991.
- [648]
- S. Chakravarty
and S. S. Ravi.
Computing optimal test sequences from complete test sets for stuck-open faults
in CMOS circuits.
IEEE Transactions on Computer-Aided Design, 9(3):329-331, March
1990.
- [649]
- S. Chakravarty.
A note on random versus deterministic testing of gate-level combinational
circuits.
In IEEE International Conference on Computer-Aided Design, pages
152-155, Santa Clara, CA, Nov. 9-12 1987.
- [650]
- S. Chakravarty.
On the complexity of using bdds for the synthesis and analysis of boolean
circuits.
In Proc. 27th Annual Allerton Conference on Communications, Control, and
Computing, pages 730-739, Monticello, IL, Sept. 27-29 1989.
- [651]
- S. K. Chakravarty.
On the complexity of computing tests for CMOS gates.
IEEE Transactions on Computer-Aided Design, 8(9):973-980, September
1989.
- [652]
- V. Champac,
V. Avendano, and J. Figueras.
Built-in sensor for signal integrity faults in digital interconnect signals.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):256-269, February 2010.
- [653]
- S. C. Chan, K. L.
Shepard, and D.-J. Kim.
Static noise analysis for digital integrated circuits in partially depleted
silicon-on-insulator technology.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(8):916-927, August 2002.
- [654]
- T. F. Chan, J. Cong,
T. Kong, J. R. Shinnerl, and K. Sze.
An enhanced multilevel algorithm for circuit placement.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 299-306, San Jose, CA, November 9-13 2003.
- [655]
- P. K. Chan and
K. Karplus.
Computing signal delay in general RC networks by tree/link partitioning.
In 26th ACM/IEEE Design Automation Conference, pages 485-490, June
1989.
- [656]
- P. K. Chan and K. Karplus.
Computing signal delay in general RC networks by tree/link partitioning.
IEEE Transactions on Computer-Aided Design, 9(8):898-902, August
1990.
- [657]
- V. Chan and W. Q. Meeker.
A failure-time model for infant-mortality and wearout failure modes.
IEEE Transactions on Reliability, 48(4):377-387, December 1999.
- [658]
- P. K. Chan and M. D. F.
Schlag.
Bounds on signal delay in RC mesh networks.
IEEE Transactions on Computer-Aided Design, 8(6):581-589, June
1989.
- [659]
- S. C. Chan and K. L.
Shepard.
Practical consideration in RLCK crosstalk analysis for digital integrated
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 598-604, San Jose, CA, November 4-8 2001.
- [660]
- P. K. Chan.
An extension of elmore's delay.
IEEE Transactions on Circuits and Systems, CAS-33(11):1147-1149,
November 1986.
- [661]
- P. K. Chan.
An extension of elmore's delay and its application for timing analysis of MOS
pass transistor networks.
IEEE Transactions on Circuits and Systems, CAS-33(11):1149-1152,
November 1986.
- [662]
- P. K. Chan.
Signal delay in RC networks with floating capacitors.
In IEEE International Conference on Circuits and Systems, pages
2831-2834, 1988.
- [663]
- P. K. Chan.
Comments on "asymptotic waveform evaluation for timing analysis".
IEEE Transactions on Computer-Aided Design, 10(8):1078-1079, August
1991.
- [664]
- V. Chandra,
H. Schmit, A. Xu, and L. Pileggi.
A power aware system level interconnect design methodology for
latency-insensitive systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 275-282, San Jose, CA, November 7-11 2004.
- [665]
- S. Chandra,
K. Lahiri, A. Raghunathan, and S. Dey.
Considering process variations during system-level power analysis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 342-345, Tegernsee, Germany, October 4-6 2006.
- [666]
- S. Chandra,
K. Lahiri, A. Raghunathan, and S. Dey.
System-on-chip power management considering leakage power variations.
In ACM/IEEE 44th Design Automation Conference (DAC-07), San Diego, CA,
June 4-8 2007.
- [667]
- S. Chandra,
K. Lahiri, A. Raghunathan, and S. Dey.
Variation-aware system-level power analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(8):1173-1184, August 2010.
- [668]
- S. Chandra,
A. Raghunathan, and S. Dey.
Variation-aware voltage level selection.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(5):925-936, May 2012.
- [669]
- A. P. Chandrakasan, M. Potkonjak, J. Rabaey, and R. W.
Brodersen.
HYPER-LP: A system for power minimization using architectural
transformations.
In IEEE/ACM International Conference on Computer-Aided Design, pages
300-303, Santa Clara, CA, November 8-12 1992.
- [670]
- A. P. Chandrakasan, S. Sheng, and R. W. Brodersen.
Low-power CMOS digital design.
IEEE Journal of Solid-State Circuits, 27(4):473-484, April 1992.
- [671]
- A. P. Chandrakasan, R. Allmon, A. Stratakos, and R. W.
Brodersen.
Design of portable systems.
In IEEE 1994 Custom Integrated Circuit Conference, pages 259-266, San
Diego, CA, May 1-4 1994.
- [672]
- A. P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R. W.
Brodersen.
Optimizing power using transformations.
IEEE Transactions on Computer-Aided Design, 14(1):12-31, January
1995.
- [673]
- A. Chandrakasan, I. Yang, C. Vieri, and D. Antoniadis.
Design considerations and tools for low-voltage digital system design.
In 33rd Design Automation Conference, pages 113-118, Las Vegas, NV,
June 3-7 1996.
- [674]
- R. Chandramouli, N. Vijaykrishnan, and N. Ranganathan.
Sequential tests for integrated-circuit failures.
IEEE Transactions on Reliability, 47(4):463-471, December 1998.
- [675]
- V. Chandramouli and K. A. Sakallah.
Modeling the effects of temporal proximity of input transitions on gate
propagation delay and transition time.
In 33rd Design Automation Conference, pages 617-622, Las Vegas, NV,
June 3-7 1996.
- [676]
- R. Chandramouli and V. K. Srikantam.
Multimode power modeling and maximum-likelihood estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(11):1244-1248, November 2004.
- [677]
- K. Chandrasekar, C. Weis, B. Akesson, N. Wehn, and K. Goossens.
Towards variation-aware system-level power estimation of drams: an empirical
approach.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [678]
- A. Chandrasekharan, M. Soeken, D. Große, and R. Drechsler.
Approximation-aware rewriting of aigs for error tolerant applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [679]
- Chang, Manning,
and Metze.
Fault Diagnosis of Digital Systems.
R. E. Krieger Publishing Company, 1974.
- [680]
- F-C. Chang, C-F.
Chen, and P. Subramaniam.
An accurate and efficient gate level delay calculator for MOS circuits.
In 25th ACM/IEEE Design Automation Conference, pages 282-287,
Anaheim, CA, June 12-15 1988.
- [681]
- M-C. Chang, J-H.
Chern, and P. Yang.
An accurate grid local truncation error for device simulation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
275-282, Santa Clara, CA, November 7-11 1993.
- [682]
- S.-C. Chang,
M. Marek-Sadowska, and K.-T. Cheng.
Perturb and simplify: multilevel boolean network optimizer.
IEEE Transactions on Computer-Aided Design, 15(12):1494-1504,
December 1996.
- [683]
- S.-C. Chang,
L. P.P.P. van Ginneken, and M. Marek-Sadowska.
Fast boolean optimization by rewiring.
In IEEE/ACM International Conference on Computer-Aided Design, pages
262-269, San Jose, CA, November 10-14 1996.
- [684]
- N. Chang, K. Kim,
and J. Cho.
Bus encoding for low-power high-performance memory systems.
In Design Automation Conference, pages 800-805, Los Angeles, CA, June
5-9 2000.
- [685]
- N. Chang,
K. Kim, and H. G. Lee.
Cycle-accurate energy consumption measurement and analysis: case study of
arm7tdmi.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 185-190, Italy, July 26-27 2000.
- [686]
- C.-W. Chang,
K. Wang, and M. Marek-Sadowska.
Layout-driven hot-carrier degradation minimization using logic restructuring
techniques.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages 97-102,
Las Vegas, NV, June 18-22 2001.
- [687]
- Y.-J. Chang, C.-L.
Yang, and F. Lai.
A power-aware SWDR cell for reducing cache write power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 14-17, Seoul, Korea, August 25-27 2003.
- [688]
- C.-C. Chang,
J. Cong, M. Romesis, and M. Xie.
Optimality and scalability study of existing placement algorithms.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(4):537-549, April 2004.
- [689]
- C.-W. J. Chang,
M.-F. Hsiao, B. Hu, K. Wang, M. Marek-Sadowska, C.-K. Cheng, and S.-J. Chen.
Fast postplacement optimization using functional symmetries.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):102-118, January 2004.
- [690]
- Y.-J. Chang,
F. Lai, and C.-L. Yang.
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(8):827-836, August 2004.
- [691]
- H. Chang,
V. Zolotov, S. Narayan, and C. Visweswariah.
Parameterized block-based statistical timing analysis with non-gaussian
parameters, nonlinear delay functions.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 71-76,
Anaheim, CA, June 13-17 2005.
- [692]
- Y.-C. Chang,
K.-H. Tam, and L. He.
Power-optimal repeater insertion considering vdd and vth as design freedoms.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 137-142, San Diego, CA, August 8-10 2005.
- [693]
- A. C.-C. Chang,
R. H.-M. Huang, and C. H.-P. Wen.
CASSER: a closed-form analysis framework for statistical soft error rate.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1837-1848, October 2013.
- [694]
- J.-W. Chang,
S.-H. Yeh, T.-W. Huang, and T.-Y. Ho.
Integrated fluidic-chip co-design methodology for digital microfludic biochips.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(2):216-227, February 2013.
- [695]
- N. Chang,
D. Baek, and J. Hong.
Power consumption characterization, modeling and estimation of electric
vehicles.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 175-182, San Jose, CA, November 2-6 2014.
- [696]
- W.-H. Chang,
M.-C.-T. Chao, and S.-H. Chen.
Practical routability-driven design flow for multilayer power networks using
aluminum-pad layer.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1069-1081, May 2014.
- [697]
- H. Chang and J. A.
Abraham.
VIPER: An efficient vigorously sensitizable path extractor.
In 30th ACM/IEEE Design Automation Conference, pages 112-117, Dallas,
Texas, June 14-18 1993.
- [698]
- K.-H. Chang and C. Browy.
Improving gate-level simulation accuracy when unknowns exist.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
936-940, San Francisco, CA, June 3-7 2012.
- [699]
- M.-C. Chang and W.-H.
Chang.
Asynchoronous fine-grain power-gated logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(6):1143-1153, June 2013.
- [700]
- Y.-T. Chang and K.-T.
Cheng.
Self-referential verification for gate-level implementations of arithmetic
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(7):1102-1112, July 2004.
- [701]
- A. Chang and W. J. Dally.
Explaining the gap between ASIC and custom power: a custom perspective.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
281-284, Anaheim, CA, June 13-17 2005.
- [702]
- L. Chang and
W. Haensch.
Near-threshold operation for power-efficient computing? it depends...
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1155-1159, San Francisco, CA, June 3-7 2012.
- [703]
- Y.-S. Chang and C.-M.
Kyung.
Conforming block inversion for low power memory.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(1):15-19, February 2002.
- [704]
- S-C. Chang and
M. Marek-Sadowska.
Perturb and simplify: multi-level boolean network optimizer.
In IEEE/ACM International Conference on Computer-Aided Design, pages
2-5, San Jose, CA, November 6-10 1994.
- [705]
- J-M. Chang and M. Pedram.
Register allocation and binding for low power.
In 32nd Design Automation Conference, pages 29-35, San Francisco, CA,
June 12-16 1995.
- [706]
- J-M. Chang and M. Pedram.
Energy minimization using multiple supply voltages.
In International Symposium on Low Power Electronics and Design, pages
157-162, Monterey, CA, August 12-14 1996.
- [707]
- H. Chang and S. S.
Sapatnekar.
Statistical timing alaysis considering spatial correlations using a single
PERT-like traversal.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 621-625, San Jose, CA, November 9-13 2003.
- [708]
- H. Chang and S. S.
Sapatnekar.
Full-chip analysis of leakage power under process variations, including spatial
correlations.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
523-528, Anaheim, CA, June 13-17 2005.
- [709]
- H. Chang and S. S.
Sapatnekar.
Statistical timing analysis under spatial correlations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(9):1467-1482, September 2005.
- [710]
- M. C.-T. Chao, L.-C.
Wang, K.-T. Cheng, and S. Kundu.
Static statistical timing analysis for latch-based pipeline designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 468-472, San Jose, CA, November 7-11 2004.
- [711]
- T. Charania,
A. Opal, and M. Sachdev.
Analysis and design of on-chip decoupling capacitors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(4):648-658, April 2013.
- [712]
- A. Chatterjee, M. Nandakumar, and I-C. Chen.
An investigation of the impact of technology scaling on power wasted as
short-circuit current in low voltage static CMOS circuits.
In International Symposium on Low Power Electronics and Design, pages
145-150, Monterey, CA, August 12-14 1996.
- [713]
- B. Chatterjee, M. Sachdev, S. Hsu, R. Krishnamurthy, and
S. Borkar.
Effectiveness and scaling trends of leakage control techniques for sub-130nm
CMOS technologies.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 122-127, Seoul, Korea, August 25-27 2003.
- [714]
- B. Chatterjee, M. Sachdev, and R. Krishnamurthy.
Leakage control techniques for designing robust, low power wide-OR domino
logic for sub-130nm CMOS technologies.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 415-420, San Jose, CA, March 22-24 2004.
- [715]
- S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam.
Reducing structural bias in technology mapping.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 519-526, San Jose, CA, November 6-10 2005.
- [716]
- D. Chatterjee, A. DeOrio, and V. Bertacco.
Event-driven gate-level simulation with GP-gpus.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
557-562, San Francisco, CA, July 26-31 2009.
- [717]
- S. Chatterjee, M. Fawaz, and F. N. Najm.
Redundancy-aware electromigration checking for mesh power grids.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 540-547, San Jose, CA, November 18-21 2013.
- [718]
- S. Chatterjee, M. Fawaz, and F. N. Najm.
Redundancy-aware power grid electromigration checking under workload
uncertainties.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(9):1509-1522, September 2015.
- [719]
- S. Chatterjee, V. Sukharev, and F. N. Najm.
Fast physics-based electromigration checking for on-die power grids.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [720]
- A. Chatterjee and
R. K. Roy.
Synthesis of low power linear DSP circuits using activity metrics.
In IEEE 7th International Conference on VLSI Design, pages 265-270,
January 1994.
- [721]
- S. Chattopadhyay, S. Roy, and P. P. Chaudhuri.
KGPMIN: An efficient multilevel multioutput AND-OR-XOR minimizer.
IEEE Transactions on Computer-Aided Design, 16(3):257-265, March
1997.
- [722]
- A. Chattopadhyay and Z. Zilic.
GALDS: a complete framework for designing multiclock asics and socs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):641-654, June 2005.
- [723]
- A. Chatzigeorgiou, S. Nikolaidis, and I. Tsoukalas.
A modeling technique for CMOS gates.
IEEE Transactions on Computer-Aided Design, 18(5):557-575, May
1999.
- [724]
- A. Chaudhary, D.-Z. Chen, X.-S. Hu, K. Whitton, and M. Niemier.
Eliminating wire crossings for molecular quantum-dot cellular automata
implementation.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 565-571, San Jose, CA, November 6-10 2005.
- [725]
- K. Chaudhary and
M. Pedram.
Computing the area versus delay trade-off curves in technology mapping.
IEEE Transactions on Computer-Aided Design, 14(12):1480-1489,
December 1995.
- [726]
- R. Chaudhry,
D. Blaauw, R. Panda, and T. Edwards.
Current signature compression for IR-drop analysis.
In Design Automation Conference, pages 162-167, Los Angeles, CA, June
5-9 2000.
- [727]
- Y.-M. Chee, C. J.
Colbourn, and A.-C.-H. Ling.
Optimal memoryless encoding for low power off-chip data buses.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 369-374, San Jose, CA, November 5-9 2006.
- [728]
- H. H. Chen, R. G.
Mathews, and J. A. Newkirk.
Test generation for MOS circuits.
In IEEE 1984 International Test Conference, pages 70-79, 1984.
- [729]
- H. H. Chen, R. G.
Mathews, and J. A. Newkirk.
An algorithm to generate tests for MOS circuits at the switch level.
In IEEE 1985 International Test Conference, pages 304-312, 1985.
- [730]
- H-C Chen, D. H-C Du,
and L-R Liu.
Critical path selection for performance optimization.
IEEE Transactions on Computer-Aided Design, 12(2):185-195, February
1993.
- [731]
- X. Chen, P. Pan,
and C. L. Liu.
Desensitization for power reduction in sequential circuits.
In 33rd Design Automation Conference, pages 795-800, Las Vegas, NV,
June 3-7 1996.
- [732]
- Z. Chen, K. Roy,
and T-L Chou.
Power sensitivity - A new method to estimate power dissipation considering
uncertain specifications of primary inputs.
In IEEE/ACM International Conference on Computer-Aided Design, pages
40-44, San Jose, CA, November 9-13 1997.
- [733]
- Z. Chen, K. Roy,
and T-L Chou.
Sensitivity of power dissipation to uncertainties in primary input
specification.
In IEEE 1997 Custom Integrated Circuits Conference, pages 487-490,
Santa Clara, CA, May 5-8 1997.
- [734]
- C-P Chen, C. C. N.
Chu, and D. F. Wong.
Fast and exact simultaneous gate and wire sizing by lagrangian relaxation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
617-624, San Jose, CA, November 8-12 1998.
- [735]
- R. Y. Chen, R. M.
Owens, M. J. Irwin, and R. S. Bajwa.
Validation of an architectural level power analysis technique.
In IEEE/ACM 35th Design Automation Conference, pages 242-245, San
Francisco, CA, June 15-19 1998.
- [736]
- Z. Chen,
M. Johnson, L. Wei, and K. Roy.
Estimation of standby leakage power in CMOS circuits considering accurate
modeling of transistor stacks.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 239-244, Monterey, CA, August 10-12 1998.
- [737]
- Z. Chen, K. Roy,
and E. K. P. Chong.
Estimation of power sensitivity in sequential circuits with power macromodeling
application.
In IEEE/ACM International Conference on Computer-Aided Design, pages
468-472, San Jose, CA, November 8-12 1998.
- [738]
- Z. Chen, K. Roy,
and T.-L. Chou.
Efficient statistical approach to estimate power considering uncertain
properties of primary inputs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(3):484-492, September 1998.
- [739]
- J. Y. Chen, W. B.
Jone, J. S. Wang, H.-I. Lu, and T. F. Chen.
Segmented bus design for low-power systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
7(1):25-29, March 1999.
- [740]
- W. Chen, C.-T.
Hsieh, and M. Pedram.
Gate sizing with controlled displacement.
In 1999 International Symposium on Physical Design, pages 127-132,
Monterey, CA, April 12-14 1999.
- [741]
- C. Chen, X. Yang,
and M. Sarrafzadeh.
Potential slack: an effective metric of combinational circuit performance.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 198-201, San Jose, CA, November 5-9 2000.
- [742]
- D. Chen, E. Li,
E. Rosenbaum, and S.-M. Kang.
Interconnect thermal modeling for accurate simulation of circuit timing and
reliability.
IEEE Transactions on Computer-Aided Design, 19(2):197-205, February
2000.
- [743]
- P. Chen, D. A.
Kirkpatrick, and K. Keutzer.
Miller factor for gate-level coupling delay calculation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 68-74, San Jose, CA, November 5-9 2000.
- [744]
- P. Chen, D. A.
Kirkpatrick, and K. Keutzer.
Switching window computation for static timing analysis in the presence of
crosstalk noise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 331-337, San Jose, CA, November 5-9 2000.
- [745]
- W. Chen, C.-T.
Hsieh, and M. Pedram.
Simultaneous gate sizing and fanout optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 374-378, San Jose, CA, November 5-9 2000.
- [746]
- Z. Chen, K. Roy,
and E. K. Chong.
Estimation of power dissipation using a novel power macromodeling technique.
IEEE Transactions on Computer-Aided Design, 19(11):1363-1369,
November 2000.
- [747]
- C. Chen,
A. Srivastava, and M. Sarrafzadeh.
On gate level power optimization using dual-supply voltages.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(5):616-629, October 2001.
- [748]
- L.-C. Chen, S. K.
Gupta, and M. A. Breuer.
A new gate delay model for simultaneous switching and its applications.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
289-294, Las Vegas, NV, June 18-22 2001.
- [749]
- C. Chen, C. Kang,
and M. Sarrafzadeh.
Activity-sensitive clock tree construction for low power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 279-282, Monterey, California, August 12-14 2002.
- [750]
- C. Chen, X. Yang,
and M. Sarrafzadeh.
Predicting potential performance for digital circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(3):253-262, March 2002.
- [751]
- L. H. Chen,
M. Marek-Sadowska, and F. Brewer.
Coping with buffer delay change due to power and ground noise.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
860-865, New Orleans, LA, June 10-14 2002.
- [752]
- P. Chen,
Y. Kukimoto, and K. Keutzer.
Refining switching window by time slots for crosstalk noise calculation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 583-586, San Jose, CA, November 10-14 2002.
- [753]
- W.-Y. Chen, S. K.
Gupta, and M. A. Breuer.
Analytical models for crosstalk excitation and propagation in VLSI circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(10):1117-1131, October 2002.
- [754]
- Y. Chen, A. B.
Kahng, G. Robins, and A. Zelikovsky.
Area fill synthesis for uniform layout density.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(10):1132-1147, October 2002.
- [755]
- B. Chen, H. Yang,
R. Luo, and H. Wang.
A novel method for worst-case interconnect delay estimation.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(6):778-781, June 2003.
- [756]
- D. Chen, J. Cong,
and Y. Fan.
Low-power high-level synthesis for FPGA architctures.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 134-139, Seoul, Korea, August 25-27 2003.
- [757]
- H. Chen, C.-K.
Cheng, A. B. Kahng, I. Mandoiu, Q. Wang, and B. Yao.
The Y-architecture for on-chip interconnect: analysis and methodology.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 13-19, San Jose, CA, November 9-13 2003.
- [758]
- L.-H. Chen,
M. Marek-Sadowska, and F. Brewer.
Buffer delay change in the presence of power and ground noise.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):461-473, June 2003.
- [759]
- O. T.-C. Chen,
S. Wang, and Y.-W. Wu.
Minimization of switching activities of partial products for designing
low-power multipliers.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):418-433, June 2003.
- [760]
- T.-H. Chen,
C. Luk, and C. C.-P. Chen.
INDUCTWISE: inductance-wise interconnect simulator and extractor.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(7):884-894, July 2003.
- [761]
- T.-H. Chen,
C. Luk, and C. C.-P. Chen.
Supreme: substrate and power-delivery reluctance-enhanced macromodel
evaluation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 786-792, San Jose, CA, November 9-13 2003.
- [762]
- T.-C. Chen, S.-R.
Pan, and Y.-W. Chang.
Timing modeling and optimization under the transmission line model.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(1):28-41, January 2004.
- [763]
- T.-H. Chen, J.-L.
Tsai, C. C.-P. Chen, and T. Karnik.
Hisim: hierarchical interconnect-centric circuit simulator.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 489-496, San Jose, CA, November 7-11 2004.
- [764]
- H. Chen, C.-K.
Cheng, A. B. Kahng, I. I. Mandoiu, Q. Wang, and B. Yao.
The Y architecture for on-chip interconnect: analysis and methodology.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(4):588-599, April 2005.
- [765]
- H. Chen, C. Yeh,
G. Wilke, S. Reddy, H. Nguyen, W. Walker, and R. Murgai.
A sliding window scheme for accurate clock mesh analysis.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 939-946, San Jose, CA, November 6-10 2005.
- [766]
- H.-M. Chen, L.-D.
Huang, I.-M. Liu, and M.-D.-F. Wong.
Simultaneous power supply planning and noise avoidance in floorplan design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(4):578-587, April 2005.
- [767]
- X. Chen,
A. Davare, H. Hsieh, A. Sangiovanni-Vincentelli, and Y. Watanabe.
Simulation based deadlock analysis for system level designs.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
260-265, Anaheim, CA, June 13-17 2005.
- [768]
- Y. Chen, H. Li,
K. Roy, and C.-K. Koh.
Cascaded carry-select adder (c2sa): a new structure for low-power CSA design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 115-118, San Diego, CA, August 8-10 2005.
- [769]
- G.-K. Chen,
D. Blaauw, T. Mudge, D. Sylvester, and N.-S. Kim.
Yield-driven near-threshold SRAM design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 660-666, San Jose, CA, November 5-8 2007.
- [770]
- P.-Y. Chen, K.-H.
Ho, and T.-T. Hwang.
Skew aware polarity assignment in clock tree.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 376-379, San Jose, CA, November 5-8 2007.
- [771]
- R. Chen, E. A.
Foreman, P. A. Habitz, J. G. Hemmett, K. Kalafala, J. S. Piaget, P. Qi,
N. Venkateswaran, C. Visweswariah, J. Xiong, and V. Zolotov.
Static timing: back to our roots.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 130-136, Austin,
Texas, February 26-27 2007.
- [772]
- Y. Chen, H. Li,
J. LI, and C.-K. Koh.
Variable-latency adder (VL-adder): new arithmetic circuit design practice to
overcome NBTI.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 195-200, Portland, Oregon, August 27-29 2007.
- [773]
- P.-Y. Chen, C.-Y.
Liu, and T.-T. Hwang.
Transition-aware decoupling-capacitor allocation in power noise reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 426-429, San Jose, CA, November 10-13 2008.
- [774]
- T.-W. Chen, K. Kim,
Y. Kim, and S. Mitra.
Delay shifts predict gate-oxide early life failures.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 120-127, Monterey, CA,
February 25-26 2008.
- [775]
- M. Chen, W. Zhao,
F. Liu, and Y. Cao.
Finite-point-based transistor model: a new approach to fast circuit simulation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(10):1470-1480, October 2009.
- [776]
- G. Chen,
D. Sylvester, D. Blaauw, and T. Mudge.
Yield-driven near-threshold SRAM design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(11):1590-1598, November 2010.
- [777]
- Y. Chen, H. Li,
C.-K. Koh, G. Sun, J. Li, Y. Xie, and K. Roy.
Variable-latency adder (VL-adder) designs for low power and NBTI tolerance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(11):1621-1624, November 2010.
- [778]
- Y. Chen, D. Niu,
Y. Xie, and K. Chakrabarty.
Cost-effective integration of three-dimensional (3d) ics emphasizing testing
cost analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 471-476, San Jose, CA, November 7-11 2010.
- [779]
- Y. Chen,
S. Safarpour, J. Marques-Silva, and A. Veneris.
Automated design debugging with maximum satisfiability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1804-1817, November 2010.
- [780]
- F.-W. Chen, S.-L.
Chen, Y.-S. Lin, and T.-T. Hwang.
A physical-location-aware X-bit redistribution for maximum IR-drop
reduction.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(12):2255-2264, December 2012.
- [781]
- H. Chen, C. c. Lu,
Y.-D. Wu, and T.-J. Chiu.
Learning from biological neurons to compute with electronic noise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 168-171, San Jose, CA, November 5-8 2012.
- [782]
- Q. Chen, S.-H.
Weng, and C.-K. Cheng.
A practical regularization technique for modified nodal analysis in large-scale
time-domain circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(7):1031-1040, July 2012.
- [783]
- X. Chen, Y. Wang,
and H. Yang.
NICSLU: an adaptive sparse matrix solver for parallel circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(2):261-274, February 2013.
- [784]
- Y.-C. Chen, C.-Y.
Wang, and C.-Y. Huang.
Verification of reconfigurable binary decision diagram-based single-electron
transistor arrays.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1473-1483, October 2013.
- [785]
- Y.-H. Chen, C.-L.
Hsu, L.-C. Tsai, T.-W. Huang, and T.-Y. Ho.
A reliability-oriented placement algorithm for reconfigurable digital
microfluidic biochips using 3-d deferred decision making technique.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(8):1151-1162, August 2013.
- [786]
- Y.-G. Chen, H. Geng,
K.-Y. Lai, Y. Shi, and S.-C. Chang.
Multibit retention registers for power gated designs: concept, design and
deployment.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(4):507-518, April 2014.
- [787]
- H.-B. Chen,
S.-X.-D. Tan, X. Huang, and V. Sukharev.
New electromigration modeling and analysis considering time-varying temperature
and current densities.
In 20th Asia and South Pacific Design Automation Conference, pages
352-357, Chiba/Tokyo, Japan, January 19-22 2015.
- [788]
- H.-B. Chen,
S.-X.-D. Tan, V. Sukharev, X. Huang, and T. Kim.
Interconnect reliability modeling and analysis for multi-branch interconnect
trees.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [789]
- X. Chen, X. Li,
and S.-X.-D. Tan.
From robust chip to smart building: CAD algorithms and methodologies for
uncertainty analysis of building performance.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 457-464, Austin TX, November 2-6 2015.
- [790]
- C.-C. Chen, T. Liu,
and L. Milor.
System-level modeling of microprocessor reliability degradation due to bias
temperature instability and hot carrier injection.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(8):2712-2725, August 2016.
- [791]
- H.-B. Chen,
S.-X.-D. Tan, X. Huang, T. Kim, and V. Sukharev.
Analytical modeling and characterization of electromigration effects for
multibranch interconnect trees.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(11):1811-1824, November 2016.
- [792]
- X. Chen, L. Wang,
B. Li, Y. Wang, X. Li, Y. Liu, and H. Yang.
Modeling random telegraph noise as a randomness source and its application in
true random number generation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(9):1435-1448, September 2016.
- [793]
- T.-H. Chen and C.-P. Chen.
Efficient large-scale power grid analysis based on preconditioned
krylov-subspace iterative methods.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
559-562, Las Vegas, NV, June 18-22 2001.
- [794]
- D. Chen and J. Cong.
Delay optimal low-power circuit clustering for fpgas with dual supply voltages.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 70-73, Newport Beach, CA, August 9-11 2004.
- [795]
- H-C. Chen and D. H. C. Du.
Path sensitization in critical path problem.
In IEEE International Conference on Computer-Aided Design, pages
208-211, Santa Clara, CA, November 11-14 1991.
- [796]
- H-C Chen and D. H-C Du.
Path sensitization in critical path problems.
IEEE Transactions on Computer-Aided Design, 12(2):196-207, February
1993.
- [797]
- H-Y. Chen and S. Dutta.
A timing model for static CMOS gates.
In IEEE International Conference on Computer-Aided Design, pages
72-75, 1989.
- [798]
- T. Chen and M. K. H. Fan.
On convex formulation of the floorplan area minimization problem.
In ACM/IEEE International Symposium on Physical Design, pages
124-128, Monterey, CA, April 6-8 1998.
- [799]
- G. Chen and E. G.
Friedman.
An RLC interconnect model based on fourier analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(2):170-183, February 2005.
- [800]
- G. Chen and E. G.
Friedman.
Low-power repeaters driving RC and RLC interconnects with interconnects
with delay and bandwidth constraints.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(2):161-172, February 2006.
- [801]
- T. Chen and A. Hajjar.
Analysing statistical timing behaviour of coupled interconnects using quadratic
delay change characteristics.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 183-188, San Jose, CA, March 24-26 2003.
- [802]
- T. Chen and A. Hajjar.
Statistical timing analysis of coupled interconnects using quadratic
delay-change characteristics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(12):1677-1683, December 2004.
- [803]
- T.-H. Chen and J. P. Hayes.
Equivalence among stochastic logic circuits and its application.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [804]
- J. Chen and L. He.
Piecewise linear model for transmission line with capacitive loading and ramp
input.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(6):928-937, June 2005.
- [805]
- J. Chen and L. He.
Worst case crosstalk noise for nonswitching victims in high-speed buses.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(8):1275-1283, August 2005.
- [806]
- J. Chen and L. He.
Modeling and synthesis of multiport transmission line for multichannel
communication.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1664-1676, September 2006.
- [807]
- J. Chen and L. He.
Efficient in-package decoupling capacitor optimization for I/O power
integrity.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):734-738, April 2007.
- [808]
- M.-J. Chen and J.-S. Ho.
A three-parameters-only MOSFET subthreshold current CAD model considering
back-gate bias and process variations.
IEEE Transactions on Computer-Aided Design, 16(4):343-352, April
1997.
- [809]
- P. Chen and K. Keutzer.
Towards true crosstalk noise analysis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
132-137, San Jose, CA, November 7-11 1999.
- [810]
- H. H. Chen and D. D. Ling.
Power supply noise analysis methodology for deep-submicron VLSI chip design.
In 34th Design Automation Conference, pages 638-643, Anaheim, CA,
June 9-13 1997.
- [811]
- Y.-Y. Chen and J.-J. Liou.
Extraction of statistical timing profiles using test data.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
509-514, San Diego, CA, June 4-8 2007.
- [812]
- L. H. Chen and
M. Marek-Sadowska.
Efficient closed-form crosstalk delay metrics.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 431-436, San Jose, CA, March 18-21 2002.
- [813]
- H. Chen and
J. Marques-Silva.
A two-variable model for SAT-based ATPG.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(12):1943-1956, December 2013.
- [814]
- T. Chen and
S. Naffziger.
Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV)
for improving delay and leakage under the presence of process variation.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(5):888-889, October 2003.
- [815]
- B. Chen and
I. Nedelchev.
Power compiler: A gate-level power optimization and synthesis system.
In IEEE Conference on Computer Design (ICCD), pages 74-79, Austin,
TX, October 1997.
- [816]
- Z. Chen and K. Roy.
A power macromodeling technique based on power sensitivity.
In IEEE/ACM 35th Design Automation Conference, pages 678-683, San
Francisco, CA, June 15-19 1998.
- [817]
- D-S. Chen and
M. Sarrafzadeh.
An exact algorithm for low power library specific gate re-sizing.
In 33rd Design Automation Conference, pages 783-788, Las Vegas, NV,
June 3-7 1996.
- [818]
- C. Chen and
M. Sarrafzadeh.
Provably good algorithm for low power consumption with dual supply voltages.
In IEEE/ACM International Conference on Computer-Aided Design, pages
76-79, San Jose, CA, November 7-11 1999.
- [819]
- C-H Chen and C-Y Tsui.
Towards the capability of providing power-area-delay trade-off at the register
transfer level.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 24-29, Monterey, CA, August 10-12 1998.
- [820]
- R. Chen and H. Zhou.
Clock schedule verification under process variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 619-625, San Jose, CA, November 7-11 2004.
- [821]
- R. Chen and H. Zhou.
Timing macro-modeling of IP blocks with crosstalk.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 155-159, San Jose, CA, November 7-11 2004.
- [822]
- R. Chen and H. Zhou.
An efficient data structure for maxplus merge in dynamic programming.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):3004-3009, December 2006.
- [823]
- R. Chen and H. Zhou.
Statistical timing verification for transparently latched circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1847-1855, September 2006.
- [824]
- R. Chen and H. Zhou.
Timing budgeting under arbitrary process variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 344-349, San Jose, CA, November 5-8 2007.
- [825]
- R. Chen and H. Zhou.
Fast estimation of timing yield bounds for process variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(3):241-248, March 2008.
- [826]
- Y. Chen and H. Zhou.
Synthesis of resilient circuits from guarded atomic actions.
In 20th Asia and South Pacific Design Automation Conference, pages
550-555, Chiba/Tokyo, Japan, January 19-22 2015.
- [827]
- T. Chen.
Impact of on-chip inductance when transitioning from al to cu based technology.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 173-178, San Jose, CA, March 26-28 2001.
- [828]
- T. Chen.
On the impact of on-chip inductance on signal nets under the influence of power
grid noise.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):339-348, March 2005.
- [829]
- J. Chen.
Carbon nanotubes for potential electronic and optoelectronic applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 649-650, San Jose, CA, November 5-9 2006.
- [830]
- D. I. Cheng,
K-T. Cheng, D. C. Wang, and M. Marek-Sadowska.
A new hybrid methodology for power estimation.
In 33rd Design Automation Conference, pages 439-444, Las Vegas, NV,
June 3-7 1996.
- [831]
- Y-K. Cheng, C-C.
Teng, A. Dharchoudhury, E. Rosenbaum, and S-M. Kang.
icet: A complete chip-level thermal reliability diagnosis tool for CMOS
VLSI chips.
In 33rd Design Automation Conference, pages 548-551, Las Vegas, NV,
June 3-7 1996.
- [832]
- D. I. Cheng,
K. T. Cheng, D. C. Wang, and M. Marek-Sadowska.
A hybrid methodology for switching activities estimation.
IEEE Transactions on Computer-Aided Design, 17(4):357-366, April
1998.
- [833]
- Y.-K. Cheng,
P. Raha, C.-C. Teng, E. Rosenbaum, and S.-M. Kang.
ILLIADS-T: An electrothermal timing simulator for temperature-sensitive
reliability diagnosis of CMOS VLSI chips.
IEEE Transactions on Computer-Aided Design, 17(8):668-681, August
1998.
- [834]
- L. Cheng, L. Deng,
D. Chen, and M. D.-F. Wong.
A fast simultaneous input vector generation and gate replacement algorithm for
leakage power reduction.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
117-120, San Francisco, CA, July 24-28 2006.
- [835]
- L. Cheng, F. Li,
P. Wong, and L. He.
Device and architecture cooptimization for FPGA power reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(7):1211-1221, July 2007.
- [836]
- L. Cheng,
J. Xiong, and L. He.
Non-linear statistical static timing analysis for non-gaussian variation
sources.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 80-85, Austin, Texas,
February 26-27 2007.
- [837]
- L. Cheng,
J. Xiong, and L. He.
Non-linear statistical static timing analysis for non-gaussian variation
sources.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
250-255, San Diego, CA, June 4-8 2007.
- [838]
- L. Cheng,
P. Gupta, and L. He.
Efficient additive statistical leakage estimation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(11):1777-1781, November 2009.
- [839]
- L. Cheng,
P. Gupta, C. Spanos, K. Qian, and L. He.
Physically justifiable die-level modeling of spatial variation in view of
systematic across wafer variability.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
104-109, San Francisco, CA, July 26-31 2009.
- [840]
- L. Cheng,
J. Xiong, and L. He.
Non-gaussian statistical timing anaylsis using second-order polynomial fitting.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(1):130-140, January 2009.
- [841]
- L. Cheng,
P. Gupta, C. J. Spanos, K. Qian, and L. He.
Physically justifiable die-level modeling of spatial variation in view of
systematic across wafer variability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(3):388-401, March 2011.
- [842]
- L. Cheng, F. Gong,
W. Xu, J. Xiong, L. He, and M. Sarrafzadeh.
Fourier series approximation for max operation in non-gaussian and quadratic
statistical static timing analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(8):1383-1391, August 2012.
- [843]
- Y. Cheng,
L. Zhang, Y. Han, and X. Li.
Thermal-constrained task allocation for interconnect energy reduction in 3-D
homogeneous mpsocs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(2):239-249, February 2013.
- [844]
- Y. Cheng,
A. Todri-Sanial, J. Yang, and W. Zhao.
Alleviating through-silicon-via electromigration for 3-D integrated circuits
taking advantage of self-healing effect.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(11):3310-3322, November 2016.
- [845]
- K-T Cheng and
V. Agrawal.
An entropy measure for the complexity of multi-output boolean functions.
In 27th ACM/IEEE Design Automation Conference (DAC90), pages 302-305,
Orlando, FL, June 24-28 1990.
- [846]
- Y-K. Cheng and S-M. Kang.
Fast thermal analysis for CMOS VLSIC reliability.
In IEEE 1996 Custom Integrated Circuits Conference, pages 479-482,
San Diego, CA, May 5-8 1996.
- [847]
- Y.-K. Cheng and S.-M. Kang.
An efficient method for hot-spot identification in ULSI circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
124-127, San Jose, CA, November 7-11 1999.
- [848]
- Y.-K. Cheng and S.-M. Kang.
A temperature-aware simulation environment for reliable ULSI chip design.
IEEE Transactions on Computer-Aided Design, 19(9):1211-1220,
September 2000.
- [849]
- K.-T. Cheng and
A. S. Krishnakumar.
Automatic generation of functional vectors using the extended finite state
machine model.
ACM Transactions on Design Automation of Electronic Systems,
1(1):57-79, January 1996.
- [850]
- W.-C. Cheng and
M. Pedram.
Power-optimal encoding for DRAM address bus.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 250-252, Italy, July 26-27 2000.
- [851]
- W.-C. Cheng and
M. Pedram.
Memory bus encoding for low power: A tutorial.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 199-204, San Jose, CA, March 26-28 2001.
- [852]
- W.-C. Cheng and
M. Pedram.
Power-optimal encoding for a DRAM address bus.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(2):109-118, April 2002.
- [853]
- Y. Cheon, P.-H.
Ho, A. B. Kahng, S. Reda, and Q. Wang.
Power-aware placement.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
795-800, Anaheim, CA, June 13-17 2005.
- [854]
- B. S. Cherkauer
and E. G. Friedman.
Channel width tapering of serially connected mosfets with emphasis on power
dissipation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2(1):100-114, March 1994.
- [855]
- J.-H. Chern,
J. Huang, L. Arledge, P.-C. Li, and P. Yang.
Multilevel metal capacitance models for CAD design synthesis systems.
IEEE Electron Device Letters, 13(1):32-34, January 1992.
- [856]
- G. A. Cherry and S. J.
Qin.
Multiblock principal component analysis based on a combined index for
semiconductor fault detection and diagnosis.
IEEE Transactions on Semiconductor Manufacturing, 19(2):159-172, May
2006.
- [857]
- E. M. Cherry.
Loop gain, input impedance and output impedance of feedback amplifiers.
IEEE Circuits and Systems Magazine, 8(1):55-71, Q1 2008.
- [858]
- H. Cherupalli
and J. Sartori.
Graph-based dynamic analysis: efficient characterization of dynamic timing and
activity distributions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 729-735, Austin TX, November 2-6 2015.
- [859]
- W.-T. Cheung and N. Wong.
Power optimization in a repeater-inserted interconnect via geometric
programming.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 226-231, Tegernsee, Germany, October 4-6 2006.
- [860]
- M. Chew, A. Aslyan,
J.-H. Choy, and X. Huang.
Accurate full-chip estimation of power map, current densities and temperature
for EM assessment.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 440-445, San Jose, CA, November 2-6 2014.
- [861]
- M. Chew and A. J.
Strojwas.
Re-evaluation mode timing simulation.
In IEEE International Symposium on Circuits and Systems, pages
2395-2398, June 1991.
- [862]
- A. Chhabra,
H. Rawat, M. Jain, P. Tessier, D. Pierredon, L. Bergher, and P. Kumar.
FALPEM: framework for architectural-level power estimation and optimization
for large memory sub-systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(7):1138-1142, July 2015.
- [863]
- J. C. Chi, H. H. Lee,
S. H. Tsai, and M. C. Chi.
Gate level multiple supply voltage assignment algorithm for power optimization
under timing constraint.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(6):637-648, June 2007.
- [864]
- A. C. L. Chiang,
I. S. Reed, and A. V. Banes.
Path sensitization, partial boolean difference, and automated fault diagnosis.
IEEE Transactions on Computers, pages 189-195, February 1972.
- [865]
- T.-Y. Chiang,
K. Banerjee, and K. C. Saraswat.
Compact modeling and SPICE-based simulation for electrothermal analysis of
multilevel ULSI interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 165-172, San Jose, CA, November 4-8 2001.
- [866]
- K-W. Chiang and Z. G.
Vranesic.
Test generation for MOS complex gate networks.
In IEEE 12th International Symposium on Fault Tolerant Computing,
pages 149-157, June 1982.
- [867]
- K-W. Chiang and Z. G.
Vranesic.
On fault detection in CMOS logic circuits.
In IEEE 20th Design Automation Conference, pages 50-56, Miami Beach,
FL, June 27-29 1983.
- [868]
- H.-C. Chang Chien,
H.-C. Ou, T.-C. Chen, T.-Y. Kuan, and Y.-W. Chang.
Double patterning lithography-aware analog placement.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [869]
- A. Chinea,
P. Triverio, and S. Grivet-Talocia.
Campact macromodeling of electrically long interconnects.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 199-202, San Jose, CA, October 27-29 2008.
- [870]
- R.-L.-S. Ching,
E.-F.-Y. Young, K.-C.-K. Leung, and C. Chu.
Post-placement voltage island generation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 641-646, San Jose, CA, November 5-9 2006.
- [871]
- D. G.
Chinnery, B. Nikolic, and K. Keutzer.
Achieving 550 mhz in an ASIC methodology.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
420-425, Las Vegas, NV, June 18-22 2001.
- [872]
- D. G. Chinnery
and K. Keutzer.
Closing the power gap between ASIC and custom: an ASIC perspective.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
275-280, Anaheim, CA, June 13-17 2005.
- [873]
- D. G. Chinnery
and K. Keutzer.
Linear programming for sizing, vth and vdd assignment.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 149-154, San Diego, CA, August 8-10 2005.
- [874]
- M. Chinosi,
R. Zafalon, and C. Guardiani.
Automatic characterization and modeling of power consumption in static rams.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 112-114, Monterey, CA, August 10-12 1998.
- [875]
- M. Chinosi,
R. Zafalon, and C. Guardiani.
Parallel mixed-level power simulation based on spatio-temporal circuit
partitioning.
In Design Automation Conference, pages 562-567, New Orleans, LA, June
21-25 1999.
- [876]
- D.-S. Chiou, S.-H.
Chen, S.-C. Chang, and C. Yeh.
Timing driven power gating.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
121-124, San Francisco, CA, July 24-28 2006.
- [877]
- D.-S. Chiou, D.-C.
Juan, Y.-T. Chen, and S.-C. Chang.
Fine-grainted sleep transistor sizing algorithm for leakage power minimization.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 81-86,
San Diego, CA, June 4-8 2007.
- [878]
- V. K. Chippa,
D. Mohapatra, K. Roy, S. T. Chakradhar, and A. Raghunathan.
Scalable effort hardward design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(9):2004-2016, September 2014.
- [879]
- E. Chiprout and
M. Nakhla.
Generalized moment-matching methods for transient analysis of interconnect
networks.
In 29th ACM/IEEE Design Automation Conference, pages 201-206,
Anaheim, CA, June 8-12 1992.
- [880]
- E. Chiprout.
Fast flip-chip power grid analysis via locality and grid shells.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 485-488, San Jose, CA, November 7-11 2004.
- [881]
- E. Chiprout.
On-die power grids - the missing link.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
940-945, Anaheim, CA, June 13-18 2010.
- [882]
- E. Chiprout.
Power grid effects and their impact on-die.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 667-669, San Jose, CA, November 5-8 2012.
- [883]
- G.-R. Chiu, D. P.
Singh, V. Manohararajah, and S. D. Brown.
Mapping arbitrary logic functions into synchronous embedded memories for area
reduction on fpgas.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 135-142, San Jose, CA, November 5-9 2006.
- [884]
- C.-T. Chiu, W.-C.
Huang, C.-H. LIn, W.-C. Lai, and Y.-F. Tsao.
Embedded transition inversion coding with low switching activity for serial
links.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1797-1810, October 2013.
- [885]
- S-B. Cho, Y-C. Shin,
and I-C. Lim.
A test generation algorithm for CMOS circuits.
In IEEE International Symposium on Circuits and Systems, pages
1551-1554, Kyoto, Japan, 1985.
- [886]
- H. Cho, G. D. Hachtel,
B. Plessier, and F. Somenzi.
Algorithms for approximate FSM traversal.
In 30th ACM/IEEE Design Automation Conference, pages 25-30, Dallas,
Texas, June 14-18 1993.
- [887]
- M. Cho, S. Ahmed, and
D. Z. Pan.
TACO: temperature aware clock-tree optimization.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 582-587, San Jose, CA, November 6-10 2005.
- [888]
- C. Cho, D. Kim,
J. Kim, J.-O. Plouchart, and R. Trzcinski.
Statistical framework for technology-model-product co-design and convergence.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
503-508, San Diego, CA, June 4-8 2007.
- [889]
- M. Cho, K. Lu,
K. Yuan, and D.-Z. Pan.
Boxrouter 2.0: architecture and implementation of a hybrid and robust global
router.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 503-508, San Jose, CA, November 5-8 2007.
- [890]
- Y. Cho, Y. Kim,
S. Park, and N. Chang.
System-level power estimation using an on-chip bus performance monitoring unit.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 149-154, San Jose, CA, November 10-13 2008.
- [891]
- H. Cho, L. Leem, and
S. Mitra.
ERSA: error resilient system architecture for probabilistic applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):546-558, April 2012.
- [892]
- J. Choi, J. Jeon,
and K. Choi.
Power minimization of functional units by partially guarded computation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 131-136, Italy, July 26-27 2000.
- [893]
- S. H. Choi,
F. Dartu, and K. Roy.
Timed pattern generation for noise-on-delay calculation.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
870-873, New Orleans, LA, June 10-14 2002.
- [894]
- S. H. Choi, B. C.
Paul, and K. Roy.
Novel sizing algorithm for yield improvement under process variation in
nanometer technology.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
454-459, San Diego, CA, June 7-11 2004.
- [895]
- K Choi, R. Soma, and
M. Pedram.
Fine-grained dynamic voltage and frequency scaling for precise energy and
performance tradeoff based on the ratio of off-chip access to on-chip
computation times.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):18-28, January 2005.
- [896]
- J.-H. Choi,
A. Bansal, M. Meterelliyoz, J. Murthy, and K. Roy.
Leakage power dependent temperature estimation to predict thermal runaway in
finfet circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 583-586, San Jose, CA, November 5-9 2006.
- [897]
- J.-H. Choi,
J. Murthy, and K. Roy.
The effect of process variation on device temperature in finfet circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 747-751, San Jose, CA, November 5-8 2007.
- [898]
- K.-W. Choi and
A. Chatterjee.
Ha2tsd: Hierarchical time slack distribution for ultra-low power CMOS VLSI.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 207-212, Monterey, California, August 12-14 2002.
- [899]
- K.-W. Choi and
A. Chatterjee.
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra
low-power CMOS VLSI.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 72-77, Seoul, Korea, August 25-27 2003.
- [900]
- M. Choi and L. Milor.
Impact on circuit performance of deterministic within-die variation in
nanoscale semiconductor manufacturing.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1350-1367, July 2006.
- [901]
- Y. Choi and E. E.
Swartzlander.
Speculative carry generation with prefix adder.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(3):321-326, March 2008.
- [902]
- A. Chojnacki and
L. Jozwiak.
High-quality FPGA designs through functional decomposition with sub-function
input support selection based on information relationship measures.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 409-414, San Jose, CA, March 26-28 2001.
- [903]
- K. Chopra,
S. Shah, A. Srivastava, D. Blaauw, and D. Sylvester.
Parametric yield maximization using gate sizing based on efficient statistical
power and delay gradient computation.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 1023-1028, San Jose, CA, November 6-10 2005.
- [904]
- K. Chopra,
B. Zhai, D. Blaauw, and D. Sylvester.
A new statistical max operation for propagating skewness in statistical timing
analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 237-243, San Jose, CA, November 5-9 2006.
- [905]
- K. Chopra,
N. Shenoy, and D. Blaauw.
Variogram based robust extraction of process variation.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 112-117, Austin,
Texas, February 26-27 2007.
- [906]
- K. Chopra,
C. Zhuo, D. Blaauw, and D. Sylvester.
A statistical approach for full-chip gate-oxide reliability analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 698-705, San Jose, CA, November 10-13 2008.
- [907]
- K. Chopra and
S. B. K. Vrudhula.
Implicit pseudo boolean enumeration algorithms for input vector control.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
767-772, San Diego, CA, June 7-11 2004.
- [908]
- K. Chopra and
S. Vrudhula.
Efficient symbolic algorithms for computing the minimum and bounded leakage
states.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2820-2832, December 2006.
- [909]
- T-L. Chou, K. Roy,
and S. Prasad.
Estimation of circuit activity considering signal correlations and simultaneous
switching.
In IEEE/ACM International Conference on Computer-Aided Design, pages
300-303, San Jose, CA, November 6-10 1994.
- [910]
- P. H. Chou, C. Park,
J. Park, K. Pham, and J. Liu.
B#: a battery emulator and power profiling instrument.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 288-293, Seoul, Korea, August 25-27 2003.
- [911]
- C.-H. Chou, N.-Y.
Tsai, H. Yu, C.-R. Lee, Y. Shi, and S.-C. Chang.
On the preconditioner of conjugate gradient method - a power grid simulation
perspective.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 494-497, San Jose, CA, November 7-10 2011.
- [912]
- T-L. Chou and K. Roy.
Statistical estimation of sequential circuit activity.
In IEEE/ACM International Conference on Computer-Aided Design, pages
34-37, San Jose, CA, November 5-9 1995.
- [913]
- T-L. Chou and K. Roy.
Accurate power estimation of CMOS sequential circuits.
IEEE Transactions on Very Large Integration (VLSI) Systems,
4(3):369-380, September 1996.
- [914]
- T.-L. Chou and K. Roy.
Estimation of activity for static and domino CMOS circuits considering signal
correlations and simultaneous switching.
IEEE Transactions on Computer-Aided Design, 15(10):1257-1265, October
1996.
- [915]
- M. R.
Choudhury, Q. Zhou, and K. Mohanram.
Design optimization for single-event upset robustness using simultaneous
dual-vdd and sizing techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 204-209, San Jose, CA, November 5-9 2006.
- [916]
- M. Choudhury, Y. Yoon, J. Guo, and K. Mohanram.
Technology exploration for graphene nanoribbon fets.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
272-277, Anaheim, CA, June 8-13 2008.
- [917]
- M. R. Choudhury
and K. Mohanram.
Reliability analysis of logic circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(3):392-405, March 2009.
- [918]
- M. R. Choudhury
and K. Mohanram.
Low cost concurrent error masking using approximate logic circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(8):1163-1176, August 2013.
- [919]
- P. Chow, S. O. Seo,
J. Rose, K. Chung, G. Paez-Monzon, and I. Rahardja.
The design of an SRAM-based field-programmable gate array - part I:
Architecture.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(2):191-197, June 1999.
- [920]
- P. Chow, S. O.
Seo, J. Rose, K. Chung, G. Paez-Monzon, and I. Rahardja.
The design of an SRAM-based field-programmable gate array - part II:
Circuit design and layout.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(3):321-330, September 1999.
- [921]
- Chee K. Chow.
Projection of circuit performance distributions by multivariate statistics.
IEEE Transactions on Semiconductor Manufacturing, 2(2):60-65, May
1989.
- [922]
- A. Chowdhary, K. Rajagopal, S. Venkatesan, T. Cao, V. Tiourin,
Y. Parasuram, and B. Halpin.
How accurately can we model timing in a placement engine?
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
801-806, Anaheim, CA, June 13-17 2005.
- [923]
- S. Chowdhury and J. S. Barkatullah.
Current estimation in MOS IC logic circuits.
In IEEE International Conference on Computer-Aided Design, Santa
Clara, CA, November 7-10 1988.
- [924]
- S. Chowdhury and J. S. Barkatullah.
Current estimation in MOS IC logic circuits.
In IEEE International Conference on Computer-Aided Design, pages
212-215, Santa Clara, CA, Nov. 7-10 1988.
- [925]
- S. Chowdhury
and J. S. Barkatullah.
Estimation of maximum currents in MOS IC logic circuits.
IEEE Transactions on Computer-Aided Design, 9(6):642-654, June
1990.
- [926]
- S. Chowdhury and
M. A. Breuer.
The construction of minimal area power and ground nets for VLSI circuits.
In IEEE 22nd Design Automation Conference, pages 794-797, 1985.
- [927]
- S. U. Chowdhury
and M. A. Breuer.
Minimal area design of power/ground nets having graph topologies.
IEEE Transactions on Circuits and Systems, CAS-34(12):1441-1451,
December 1987.
- [928]
- S. Chowdhury.
An automated design of minimum-area IC power/ground nets.
In 24th ACM/IEEE Design Automation Conference, pages 223-229,
1987.
- [929]
- S. U. Chowdhury.
Optimum design of reliable IC power networks having general graph topologies.
In 26th ACM/IEEE Design Automation Conference, pages 787-790, June
25-29 1989.
- [930]
- J.-H. Choy,
A. Kteyan, V. Sukharev, S. Chatterjee, F. N. Najm, and S. Moreau.
Finite-difference methodology for full chip electromigration analysis applied
to a 3d IC test structure.
In IEEE International Conference on Simulation of Semiconductor Processes
and Devices (SISPAD-17), pages 41-44, Kamakura, Japan, September 7-9
2017.
- [931]
- W. A. Chren, Jr.
Low delay-power product CMOS design using one-hot residue coding.
In ACM/IEEE International Symposium on Low Power Design, pages
145-150, Dana Point, CA, April 23-26 1995.
- [932]
- P. Christie and
D. Stroobandt.
The interpretation and application of rent's rule.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(6):639-648, December 2000.
- [933]
- P. Christie.
Rent exponent prediction methods.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(6):679-688, December 2000.
- [934]
- C. Chu, E. F. Y.
Young, D. K. Y. Tong, and S. Dechu.
Retiming with interconnect and gate delay.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 221-226, San Jose, CA, November 9-13 2003.
- [935]
- C.-T. Chu, X. Zhang,
L. He, and T.-T. Jing.
Temperature aware microprocessor floorplanning considering application
dependent power load.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 586-589, San Jose, CA, November 5-8 2007.
- [936]
- C-Y Chu and M. A. Horowitz.
Charge sharing models for MOS circuits.
In IEEE International Conference on Computer-Aided Design, pages
274-277, Santa Clara, CA, Nov. 11-13 1986.
- [937]
- C-Y. Chu and M. A.
Horowitz.
Charge-sharing models for switch-level simulation.
IEEE Transactions on Computer-Aided Design, CAD-6(6):1053-1061,
November 1987.
- [938]
- C. C. N. Chu and D. F. Wong.
An efficient and optimal algorithm for simultaneous buffer and wire sizing.
IEEE Transactions on Computer-Aided Design, 18(9):1297-1304,
September 1999.
- [939]
- C. C. N. Chu and M. D. F.
Wong.
Greedy wire-sizing is linear time.
IEEE Transactions on Computer-Aided Design, 18(4):398-405, April
1999.
- [940]
- C. Chu.
FLUTE: fast lookup table based wirelength estimation technique.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 696-701, San Jose, CA, November 7-11 2004.
- [941]
- L. O. Chua and A-C. Deng.
Canonical piecewise-linear modeling.
IEEE Transactions on Circuits and Systems, CAS-33(5):511-525, May
1986.
- [942]
- L. O. Chua.
Global optimization : a naive approach.
IEEE Transactions on Circuits and Systems, 37(7):966-969, July
1990.
- [943]
- Y.-L. Chuang,
P.-W. Lee, and Y.-W. Chang.
Voltage-drop aware analytical placement by global power spreading for
mixed-size circuit designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 666-673, San Jose, CA, November 2-5 2009.
- [944]
- P. Chuang,
D. Li, and M. Sachdev.
Constant delay logic style.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(3):554-565, March 2013.
- [945]
- C. T. Chuang and R. Puri.
SOI digital CMOS VLSI - a design perspective.
In Design Automation Conference, pages 709-714, New Orleans, LA, June
21-25 1999.
- [946]
- E.-Y. Chung,
L. Benini, and G. De Micheli.
Dynamic power management using adaptive learning tree.
In IEEE/ACM International Conference on Computer-Aided Design, pages
274-279, San Jose, CA, November 7-11 1999.
- [947]
- E-Y. Chung,
L. Benini, and G. De Micheli.
Automatic source code specialization for energy reduction.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 80-83, Huntington Beach, California, August 6-7 2001.
- [948]
- J. Chung,
J. Xiong, V. Zolotov, and J. A. Abraham.
Path criticality computation in parameterized statistical timing analysis using
a novel operator.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):497-508, April 2012.
- [949]
- J. Chung,
J. Xiong, V. Zolotov, and J. A. Abraham.
Testability-driven statistical path selection.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(8):1275-1287, August 2012.
- [950]
- C.-C. Chung,
D. Sheng, and S.-E. Shen.
High-resolution all-digital duty-cycle corrector in 65-nm CMOS technology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1096-1105, May 2014.
- [951]
- J. Chung and J. A.
Abraham.
A hierarchy of subgraphs underlying a timing graph and its use in capturing
topological correlation in SSTA.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 321-327, San Jose, CA, November 2-5 2009.
- [952]
- J. Chung and J. A.
Abraham.
On computing criticality in refactored timing graphs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(12):1935-1939, December 2012.
- [953]
- J. Chung and J. A.
Abraham.
Refactoring of timing graphs and its use in capturing topological correction in
SSTA.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):485-496, April 2012.
- [954]
- J. Chung and J. A.
Abraham.
Concurrent path selection algorithm in statistical timing analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(9):1715-1726, September 2013.
- [955]
- Y.-T. Chung and J.-H. R.
Jiang.
Functional timing analysis made fast and general.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(9):1421-1434, September 2013.
- [956]
- K-S Chung and C. L. Liu.
Local transformation techniques for multi-level logic circuits utilizing
circuit symmetries for power reduction.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 215-220, Monterey, CA, August 10-12 1998.
- [957]
- J. Ciric and C. Sechen.
Efficient canonical form for boolean marching of complex functions in large
libraries.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 610-617, San Jose, CA, November 4-8 2001.
- [958]
- J. Ciric and C. Seehen.
Efficient canonical form for boolean matching of complex functions in large
libraries.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(5):535-544, May 2003.
- [959]
- M. A. Cirit.
Estimating dynamic power consumption of CMOS circuits.
In IEEE International Conference on Computer-Aided Design, pages
534-537, Nov. 9-12 1987.
- [960]
- M. A. Cirit.
RC trees revisited.
In IEEE 1988 Custom Integrated Circuits Conference, pages
6.7.1-6.7.4, Rochester, NY, May 16-19 1988.
- [961]
- M. A. Cirit.
Switch level random pattern testability analysis.
In 25th ACM/IEEE Design Automation Conference, pages 587-590,
Anaheim, CA, June 12-15 1988.
- [962]
- M. A. Cirit.
Characterizing a VLSI standard cell library.
In IEEE Custom Integrated Circuits Conference (CICC), pages
25.7.1-25.7.4, 1991.
- [963]
- J. Clabes,
J. Friedrich, M. Sweet, J. DiLullo, S. Chu, D. Plass, J. Dawson, P. Muench,
L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz,
S. Runyon, G. Gorman, P. Restle, R. Kalla, J. McGill, and S. Dodson.
Design and implementation of the power5 microprocessor.
In International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 143-145, Austin, TX, May 17-20 2004.
- [964]
- J. Clabes,
J. Friedrich, M. Sweet, J. DiLullo, S. Chu, D. Plass, J. Dawson, P. Muench,
L. Powell, M. Floyd, B. Sinharoy, M. Lee, M. Goulet, J. Wagoner, N. Schwartz,
S. Runyon, G. Gorman, P. Restle, R. Kalla, J. McGill, and S. Dodson.
Design and implementation of the power5 microprocessor.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
670-672, San Diego, CA, June 7-11 2004.
- [965]
- L. T. Clark,
B. Choi, and M. Wilkerson.
Reducing translation lookaside buffer active power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 10-13, Seoul, Korea, August 25-27 2003.
- [966]
- L. T. Clark,
M. Morrow, and W. Brown.
Reverse-body bias and supply collapse for low effective standby power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(9):947-956, September 2004.
- [967]
- L. T. Clark,
R. Patel, and T. S. Beatty.
Managing standby and active model leakage power in deep sub-micron design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 274-279, Newport Beach, CA, August 9-11 2004.
- [968]
- E. M. Clarke,
K. L. McMillan, X. Zhao, M. Fujita, and J. Yang.
Spectral transforms for large boolean functions with applications to technology
mapping.
In 30th ACM/IEEE Design Automation Conference, pages 54-60, Dallas,
Texas, June 14-18 1993.
- [969]
- J. J. Clement,
S. P. Riege, R. Cvijetic, and C. V. Thompson.
Methodology for electromigration critical threshold design rule evaluation.
IEEE Transactions on Computer-Aided Design, 18(5):576-581, May
1999.
- [970]
- J. Clement.
Electromigration modeling for integrated circuit interconnect reliability
analysis.
IEEE Transactions on Device and Materials Reliability, 1(1):33-42,
March 2001.
- [971]
- B. Cline,
K. Chopra, D. Blaauw, and Y. Cao.
Analysis and modeling of CD variation for statistical static timing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 60-66, San Jose, CA, November 5-9 2006.
- [972]
- B. T. Cline,
V. Joshi, D. Sylvester, and D. Blaauw.
STEEL: a technique for stress-enhanced standard cell library design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 691-697, San Jose, CA, November 10-13 2008.
- [973]
- J. Coburn,
S. Ravi, and A. Raghunathan.
Power emulation: a new paradigm for power estimation.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
700-705, Anaheim, CA, June 13-17 2005.
- [974]
- P. Cocchini,
M. Pedram, G. Piccinini, and M. Zamboni.
Fanout optimization under a submicron transistor-level delay model.
In IEEE/ACM International Conference on Computer-Aided Design, pages
551-556, San Jose, CA, November 8-12 1998.
- [975]
- P. Cocchini and
M. Pedram.
Fanout optimization using bipolar LT-trees.
IEEE Transactions on Computer-Aided Design, 19(3):339-349, March
2000.
- [976]
- L. Codecasa.
Noval feedbak theory of electric circuits - part I: cut-based decomposition.
IEEE Transactions on Circuits and Systems, 59(7):1491-1504, July
2012.
- [977]
- L. Codecasa.
Novel feedback theory of electric circuits - part II: loop invariants.
IEEE Transactions on Circuits and Systems, 59(7):1505-1518, July
2012.
- [978]
- C. P. Coelho,
J. R. Phillips, and L. Miguel Silveira.
A convex programming approach to positive real rational approximation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 245-251, San Jose, CA, November 4-8 2001.
- [979]
- C. P. Coelho,
J. Philips, and L. M. Silveira.
A convex programming approach for generating guaranteed passive approximations
to tabulated frequency-data.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(2):293-301, February 2004.
- [980]
- J. Cong, C-K. Koh,
and K-S. Leung.
Simultaneous buffer and wire sizing for performance and power optimization.
In International Symposium on Low Power Electronics and Design, pages
271-276, Monterey, CA, August 12-14 1996.
- [981]
- J. Cong, Z. Pan,
L. He, C-K Koh, and K-Y Khoo.
Interconnect design for deep submicron ics.
In IEEE/ACM International Conference on Computer-Aided Design, pages
478-485, San Jose, CA, November 9-13 1997.
- [982]
- J. Cong, T. Kong,
J. R. Shinnerl, M. Xie, and X. Yuan.
Large-scale circuit placement: gap and promise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 883-890, San Jose, CA, November 9-13 2003.
- [983]
- J. Cong, M. Romesis,
and J. R. Shinnerl.
Fast floorplanning by look-ahead enabled recursive bipartitioning.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1719-1732, September 2006.
- [984]
- J. Cong, P. Gupta,
and J. Lee.
Evaluating statistical power optmization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1750-1762, November 2010.
- [985]
- J. Cong and L. He.
Theory and algorithm of local-refinement-based optimization with application to
device and interconnect sizing.
IEEE Transactions on Computer-Aided Design, 18(4):406-420, April
1999.
- [986]
- J. Cong and
M. Sarrafzadeh.
Incremental physical design.
In International Symposium on Physical Design, pages 84-92, San
Diego, CA, April 9-12 2000.
- [987]
- A. R. Conn, P. K.
Coulman, R. A. Haring, G. L. Morrill, and C. Viswewariah.
Optimization of custom MOS circuits by transistor sizing.
In IEEE/ACM International Conference on Computer-Aided Design, pages
174-180, San Jose, CA, November 10-14 1996.
- [988]
- A. R. Conn, P. K.
Coulman, R. A. Haring, G. L. Morrill, C. Visweswariah, and C. W. Wu.
Jiffytune: circuit optimization using time-domain sensitivities.
IEEE Transactions on Computer-Aided Design, 17(12):1291-1309,
December 1998.
- [989]
- A. R. Conn, R. A.
Haring, and C. Visweswariah.
Noise considerations in circuit optimization.
In IEEE/ACM International Conference on Computer-Aided Design, pages
220-227, San Jose, CA, November 8-12 1998.
- [990]
- A. R. Conn, I. M.
Elfadel, W. W. Molzen, P. R. O'Brien, P. N. Strenski, C. Visweswariah, and
C. B. Whan.
Gradient-based optimization of custom circuits using a static-timing
formulation.
In Design Automation Conference, pages 452-459, New Orleans, LA, June
21-25 1999.
- [991]
- E. Consoli,
G. Palumbo, and M. Pennisi.
Reconsidering high-speed design criteria for transmission-gate-based
master-slave flip-flop.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):284-295, February 2012.
- [992]
- G. A. Constantinides, P. Y. K. Cheung, and W. Luk.
Wordlength optimization for linear digital signal processing.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(10):1432-1449, October 2003.
- [993]
- T. M. Conte, K. N.
Menezes, S. W. Sathaye, and M. C. Toburen.
System-level power consumption modeling and tradeoff analysis techniques for
superscalar processor design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(2):129-137, April 2000.
- [994]
- M. Conti,
P. Crippa, S. Orcioni, and C. Turchetti.
Layout-based statistical modeling for the prediction of the matching properties
of MOS transistors.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(5):680-685, May 2002.
- [995]
- C. Cook, Z. Sun,
T. Kim, and S. X.-D. Tan.
Finite difference method for electromigration analysis of multi-branch
interconnects.
In IEEE International Conference on Synthesis, Modeling, Analysis and
Simulation Methods and Applications to Circuit Design (SMACD), pages
1-4, Lisbon, Portugal, June 27-30 2016.
- [996]
- R. W. Cook and M. J. Flynn.
Logical network cost and entropy.
IEEE Transactions on Computers, C-22(9):823-826, September 1973.
- [997]
- S. A. Cook.
The complexity of theorem-proving procedures.
In The 3rd Annual ACM Symposium on Theory of Computing, pages
151-158, Shaker Heights, OH, May 3-5 1971.
- [998]
- M. Cooke,
H. Mahmoodi-Meimand, and K. Roy.
Energy recovery clocking scheme and flip-flops for ultra low-energy
applications.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 54-59, Seoul, Korea, August 25-27 2003.
- [999]
- M. M.
Corbalan, A. Keval, T. Toms, D. Lisk, R. Radojcic, and M. Nowak.
Power and signal integrity challenges in 3d systems.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1000]
- V. H. Cordero and
S. P. Khatri.
Clock distribution scheme using coplanar transmission lines.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 56-61, Monterey, CA,
February 25-26 2008.
- [1001]
- R. Cordone,
F. Ferrandi, D. Sciuto, and R. W. Calvo.
An efficient heuristic approach to solve the unate covering problem.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(12):1377-1388, December 2001.
- [1002]
- J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev.
Synthesizing petri nets from state-based models.
In IEEE/ACM International Conference on Computer-Aided Design, pages
164-171, San Jose, CA, November 5-9 1995.
- [1003]
- J. Cortadella and M. Kishinevsky.
Synchronous elastic circuits with early evaluation and token counterflow.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
416-419, San Diego, CA, June 4-8 2007.
- [1004]
- J. C. Costa, J. C.
Monteiro, and S. Devadas.
Switching activity estimation using limited depth reconvergent path analysis.
In 1997 International Symposium on Low Power Electronics and Design,
pages 184-189, Monterey, CA, August 18-20 1997.
- [1005]
- M. Costagliola, D. de Caro, A. Girardi, R. Izzi, N. Rinaldi,
M. Spirito, and P. Spirito.
An experimental power-lines model for digital asics based on transmission
lines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(1):162-166, January 2012.
- [1006]
- O. Coudert,
R. Haddad, and K. Keutzer.
What is the state of the art in commercial EDA tools for low power?
In International Symposium on Low Power Electronics and Design, pages
181-187, Monterey, CA, August 12-14 1996.
- [1007]
- O. Coudert and
R. Haddad.
Integrated resynthesis for low power.
In International Symposium on Low Power Electronics and Design, pages
169-174, Monterey, CA, August 12-14 1996.
- [1008]
- O. Coudert and J. C.
Madre.
Implicit and incremental computation of primes and essential primes of boolean
functions.
In 29th ACM/IEEE Design Automation Conference, pages 36-39, Anaheim,
CA, June 8-12 1992.
- [1009]
- O. Coudert and J. C.
Madre.
New ideas for solving covering problems.
In 32nd Design Automation Conference, pages 641-646, San Francisco,
CA, June 12-16 1995.
- [1010]
- O. Coudert.
Gate sizing for constrained delay/power/area optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
5(4):465-472, December 1997.
- [1011]
- O. Coudert.
Timing and design closure in physical design flows.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 511-516, San Jose, CA, March 18-21 2002.
- [1012]
- O. Coudert.
An efficient algorithm to verify generalized false paths.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
188-193, Anaheim, CA, June 13-18 2010.
- [1013]
- S. L. Coumeri and
D. E. Thomas.
Memory modeling for system synthesis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 179-184, Monterey, CA, August 10-12 1998.
- [1014]
- S. L. Coumeri and
D. E. Thomas, Jr.
Memory modeling for system synthesis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):327-334, June 2000.
- [1015]
- P. F. Cox, R. G.
Burch, P. Yang, and D. E. Hocevar.
New implicit integration method for efficient latency exploitation in circuit
simulation.
IEEE Transactions on Computer-Aided Design, 8(10):1051-1064, October
1989.
- [1016]
- Y. L. Le Coz,
D. Krishna, D. M. Petranovic, W. M. Loh, and P. Bendix.
A sum-over-paths impulse-response moment extraction algorithm for
IC-interconnect networks: verification, coupled RC lines.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 665-670, San Jose, CA, November 9-13 2003.
- [1017]
- J. F. Croix and D. F. Wong.
A fast and accurate technique to optimize characterization tables for logic
synthesis.
In 34th Design Automation Conference, pages 337-340, Anaheim, CA,
June 9-13 1997.
- [1018]
- J. F. Croix and D. F. Wong.
Blade and razor: cell and interconnect delay analysis using current-based
models.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
386-389, Anaheim, CA, June 2-6 2003.
- [1019]
- J. Crossley,
A. Puggelli, H.-P. Le, B. Yang, R. Nancollas, K. Jung, L. Kong, N. Narevsky,
Y. Lu, N. Sutardja, E. J. An, A. L. Sangiovanni-Vincentelli, and E. Alon.
BAG: a designer-oriented integrated framework for the development of AMS
circuit generators.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 74-81, San Jose, CA, November 18-21 2013.
- [1020]
- A. L. Crouch and J. C.
Potter.
A box of dots: using scan-based path delay test for timing verification.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [1021]
- J. Cui and D. L. Maskell.
A fast high-level event-driven thermal estimator for dynamic thermal aware
scheduling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(6):904-917, June 2012.
- [1022]
- T. S. Czajkowski
and S. D. Brown.
Using negative edge triggered ffs to reduce glitching oower in FPGA circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
324-329, San Diego, CA, June 4-8 2007.
- [1023]
- T. S. Czajkowski
and S. D. Brown.
Functionally linear decomposition and synthesis of logic circuits for fpgas.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages 18-23,
Anaheim, CA, June 8-13 2008.
- [1024]
- T. S. Czajkowski
and S. D. Brown.
Decomposition-based vectorless toggle rate computation for FPGA circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1723-1735, November 2010.
- [1025]
- J. L. da Silva,
Jr., F. Catthoor, D. Verkest, and H. De Man.
Power exploration for dynamic data types through virtual memory management
refinement.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 311-316, Monterey, CA, August 10-12 1998.
- [1026]
- F. Dabiri,
A. Nahapetian, T. Massey, M. Potkonjak, and M. Sarrafzadeh.
General methodology for soft-error-aware power optimization using gate sizing.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1788-1797, October 2008.
- [1027]
- H. F. Dadgour,
R. V. Joshi, and K. Banerjee.
A novel variation-aware low-power keeper architecture for wide fan-in dynamic
gates.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
977-982, San Francisco, CA, July 24-28 2006.
- [1028]
- H. Dadgour,
V. De, and K. Banerjee.
Statistical modeling of metal-gate work-function variability in emerging device
technologies and implications for circuit design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 270-277, San Jose, CA, November 10-13 2008.
- [1029]
- H. F. Dadgour and
K. Banerjee.
Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power
applications.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
306-311, San Diego, CA, June 4-8 2007.
- [1030]
- H. F. Dadgour and
K. Banerjee.
A novel variation-tolerant keeper architecture for high-performance low-power
wide fan-in dynamic or gates.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(11):1567-1577, November 2010.
- [1031]
- W. Daems,
G. Gielen, and W. Sansen.
Simulation-based automatic generation of signomial and posynomial performance
models for analog integrated circuit sizing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 70-74, San Jose, CA, November 4-8 2001.
- [1032]
- A. J. Daga, L. Mize,
S. Sripada, C. Wolff, and Q. Wu.
Automated timing model generation.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
146-151, New Orleans, LA, June 10-14 2002.
- [1033]
- M. Dagenais.
Efficient algorithmic decomposition of transistor groups into series, parallel,
and bridge combinations.
IEEE Transactions on Circuits and Systems, 38(6):569-581, June
1991.
- [1034]
- J. Dai, L. Wang, and
F. Jain.
Analysis of defect tolerance in molecular crossbar electronics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(4):529-540, April 2009.
- [1035]
- W. W-M Dai.
Chip parasitic extraction and signal integrity verification.
In 34th Design Automation Conference, pages 717-719, Anaheim, CA,
June 9-13 1997.
- [1036]
- K. Daloukas,
N. Evmorfopoulos, G. Drasidis, M. Tsiampas, P. Tsompanopoulou, and G. I.
Stamoulis.
Fast transform-based preconditioners for large-scale power grid analysis on
massively parallel architectures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 384-391, San Jose, CA, November 5-8 2012.
- [1037]
- K. Daloukas,
N. Evmorfopoulos, P. Tsompanopoulou, and G. Stamoulis.
Parallel fast transform-based preconditioners for large-scale power grid
analysis on graphics processing units (gpus).
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(10):1653-1666, October 2016.
- [1038]
- J. Dambre,
D. Stroobandt, and J. Van Campenhout.
Toward the accurate prediction of placement wire length distributions in VLSI
circuits.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):339-348, April 2004.
- [1039]
- M. Damiani and G. De
Micheli.
Don't care set specifications in combinational and sequential logic circuits.
IEEE Transactions on Computer-Aided Design, 12(3):365-388, March
1993.
- [1040]
- R. I. Damper and
N. Burgess.
MOS test pattern generation using path algebras.
IEEE Transactions on Computers, C-36(9):1123-1128, September 1987.
- [1041]
- A. P. Dancy,
R. Amirtharajah, and A. P. Chandrakasan.
High-efficiency multiple output DC-DC conversion for low-voltage systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):252-263, June 2000.
- [1042]
- T. N. Dang,
A. Roychoudhury, T. Mitra, and P. Mishra.
Generating test programs to cover pipeline interactions.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
142-147, San Francisco, CA, July 26-31 2009.
- [1043]
- L. Daniel, A. L.
Sangiovanni-Vincentelli, and J. White.
Techniques for including dielectrics when extracting passive low-order models
of high speed interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 240-244, San Jose, CA, November 4-8 2001.
- [1044]
- L. Daniel, O.-C.
Siong, L.-S. Chay, K.-H. Lee, and J. White.
A multiparameter moment-matching model-reduction approach for generating
geometrically parameterized interconnect performance models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):678-693, May 2004.
- [1045]
- L. Daniel and
J. Phillips.
Model order reduction for strictly passive and causal distributed systems.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages 46-51,
New Orleans, LA, June 10-14 2002.
- [1046]
- H. Q. Dao, K. Nowka,
and V. G. Oklobdzija.
Analysis of clocked timing elements for dynamic voltage scaling effects over
process parameter variation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 56-59, Huntington Beach, California, August 6-7 2001.
- [1047]
- H.-Q. Dao, B. R.
Zeydel, and V. G. Oklobdzija.
Energy optimization of pipelined digital systems using circuit sizing and
supply scaling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(2):122-134, February 2006.
- [1048]
- J. Darringer, E. Davidson, D. Hathaway, B. Koenemann, M. Lavin,
J. K. Morrell, K. Rahmat, W. Roesner, E. Schanzenbach, G. Tellez, and
L. Trevillyan.
EDA in IBM: Past, present, and future.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1476-1497, December 2000.
- [1049]
- J. A. Darringer.
Multi-core design automation challenges.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
760-764, San Diego, CA, June 4-8 2007.
- [1050]
- F. Dartu,
N. Menezes, and L. T. Pileggi.
Performance computation for precharacterized CMOS gates with RC loads.
IEEE Transactions on Computer-Aided Design, 15(5):544-553, May
1996.
- [1051]
- F. Dartu and L. T.
Pileggi.
Calculating worst-case gate delays due to dominant capacitance coupling.
In 34th Design Automation Conference, pages 46-51, Anaheim, CA, June
9-13 1997.
- [1052]
- F. Dartu and L. T.
Pileggi.
TETA: Transistor-level engine for timing analysis.
In IEEE/ACM 35th Design Automation Conference, pages 595-598, San
Francisco, CA, June 15-19 1998.
- [1053]
- K. K. Das, R. V.
Joshi, C.-T. Chuang, P. W. Cook, and R. B. Brown.
New optimal design strategies and analysis of ultra-low leakage circuits for
nano-scale SOI technology.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 168-171, Seoul, Korea, August 25-27 2003.
- [1054]
- S. Das, A. P.
Chandrakasan, and R. Reif.
Calibration of rent's rule models for three-dimensional integrated circuits.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):359-366, April 2004.
- [1055]
- S. Das, D. Blaauw,
D. Bull, K. Flautner, and R. Aitken.
Addressing design margins through error-tolerant circuits.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 11-12,
San Francisco, CA, July 26-31 2009.
- [1056]
- D. Das, K. Killpack,
C. Kashyap, A. Jas, and H. Zhou.
Pessimism reduction in coupling-aware static timing analysis using timing and
logic filtering.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(3):466-478, March 2010.
- [1057]
- D. Das, A. Shebaita,
H. Zhou, Y. Ismail, and K. Killpack.
FA-STAC: an algorithmic framework for fast and accurate coupling aware
static timing analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(3):443-456, March 2011.
- [1058]
- S. Das, P. Whatmough,
and D. Bull.
Modeling and characterization of the system-level power delivery network for a
dual-core ARM cortex-a57 cluster in 28nm CMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 146-151, Rome, Italy, July 22-24 2015.
- [1059]
- A. Dasgupta and
R. Karri.
Electromigration reliability enhancement via bus activity distributions.
In 33rd Design Automation Conference, pages 353-356, Las Vegas, NV,
June 3-7 1996.
- [1060]
- A. Dasgupta and
R. Karri.
High-reliability, low-energy microarchitecture synthesis.
IEEE Transactions on Computer-Aided Design, 17(12):1273-1280,
December 1998.
- [1061]
- A. Datta,
S. Bhunia, S. Mukhopadhyay, and K. Roy.
Delay modeling and statistical design of pipelined circuit under process
variation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2427-2436, November 2006.
- [1062]
- A. Datta,
S. Bhunia, J.-H. Choi, S. Mukhopadhyay, and K. Roy.
Profit aware circuit design under process variations considering speed binning.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(7):806-815, July 2008.
- [1063]
- A. Davare,
K. Lwin, A. Kondratyev, and A. Sangiovanni-Vincentelli.
The best of both worlds: the efficient asynchronous implementation of
synchronous specifications.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
588-591, San Diego, CA, June 7-11 2004.
- [1064]
- M. Dave, M. Jain,
M. S. Baghini, and D. Sharma.
A variation tolerant current-mode signaling scheme for on-chip interconnects.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(2):342-353, February 2013.
- [1065]
- H. A. David and H. N.
Nagaraja.
Order Statistics.
John Wiley & Sons, Inc., Hoboken, NJ, 3rd edition, 2003.
- [1066]
- R. David and K. Wagner.
Analysis of detection probability and some applications.
IEEE Transactions on Computers, 39(10):1284-1291, October 1990.
- [1067]
- M. Davio,
A. Thayse, and G. Bioul.
Symbolic computation of fourier transforms of boolean functions.
Philips Research Reports, 27:386-403, August 1972.
- [1068]
- J. A. Davis, V. K.
De, and J. D. Meindl.
A stochastic wire length distribution for gigascale integration (GSI).
In IEEE 1997 Custom Integrated Circuits Conference, pages 145-150,
Santa Clara, CA, May 5-8 1997.
- [1069]
- E. J. Davison.
A method for simplifying linear dynamic systems.
IEEE Transactions on Automatic Control, AC-11(1):93-101, January
1966.
- [1070]
- A. Davoodi,
V. Khandelwal, and A. Srivastava.
Empirical models for net-length probability distribution and applications.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1066-1075, October 2004.
- [1071]
- A. Davoodi,
V. Khandelwal, and A. Srivastaya.
Variability inspired implementation selection problem.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 423-427, San Jose, CA, November 7-11 2004.
- [1072]
- A. Davoodi,
V. Khandelval, and A. Srivastava.
Probabilistic evaluation solutions in variability-driven optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):3010-3016, December 2006.
- [1073]
- A. Davoodi and
A. Srivastava.
Voltage scheduling under unpredictabilities: a risk management paradigm.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 302-305, Seoul, Korea, August 25-27 2003.
- [1074]
- A. Davoodi and
A. Srivastava.
Probabilistic dual-vth leakage optimization under variability.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 143-148, San Diego, CA, August 8-10 2005.
- [1075]
- A. Davoodi and
A. Srivastava.
Variability driven gate sizing for binning yield optimization.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
959-964, San Francisco, CA, July 24-28 2006.
- [1076]
- A. Davoodi and
A. Srivastava.
Variability driven gate sizing for binning yield optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(6):683-692, June 2008.
- [1077]
- S. K. De and N. R. Aluru.
Physical and reduced-order dynamic analysis of MEMS.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 270-273, San Jose, CA, November 9-13 2003.
- [1078]
- V. De and S. Borkar.
Technology and design challenges for low power and high performance.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 163-168, San Diego, CA, August 16-17 1999.
- [1079]
- E. de Angel and
E. E. Swartzlander, Jr.
Survey of low power techniques for roms.
In 1997 International Symposium on Low Power Electronics and Design,
pages 7-11, Monterey, CA, August 18-20 1997.
- [1080]
- D. K. de Vries.
Methods to quantify the detection probability of killing defects.
IEEE Transactions on Semiconductor Manufacturing, 18(3):406-411,
August 2005.
- [1081]
- V. De.
Fine-grain power management in manycore processor and system-on-chip (soc)
designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 159-164, Austin TX, November 2-6 2015.
- [1082]
- D. Debnath and
Z. G. Vranesic.
A fast algorithm for OR-AND-OR synthesis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(9):1166-1176, September 2003.
- [1083]
- V. Degalahal, R. Ramanarayanan, N. Vijaykrishnan, Y. Xie, and
M. J. Irwin.
The effect of threshold voltages on the soft error rate.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 503-510, San Jose, CA, March 22-24 2004.
- [1084]
- V. Degalahal, L. Li, V. Narayanan, M. Kandemir, and M. J. Irwin.
Soft errors issues in low-power caches.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(10):1157-1166, October 2005.
- [1085]
- M. M. Dehnavi,
D. M. Fernandez, J.-L. Gaudiot, and D. D. Giannacopoulos.
Parallel sparse approximate inverse preconditioning on graphic processing
units.
IEEE Transactions on Parallel and Distributed Systems,
24(9):1852-1862, September 2013.
- [1086]
- A. DeHon and K. L.
Likharev.
Hybrid CMOS/nanoelectronic digital circuits: devices, archiectures, and
design automation.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 375-382, San Jose, CA, November 6-10 2005.
- [1087]
- D. L.
Deleganes, M. Barany, G. Geannopoulos, K. Kreitzer, A. P. Singh, and
S. Wijeratne.
Low voltage swing logic circuits for a pentiumr 4 processor integer core.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
678-680, San Diego, CA, June 7-11 2004.
- [1088]
- A. Demir,
A. Mehrotra, and J. Roychowdhury.
Phase noise in oscillators: a unifying theory and numerical methods for
characterization.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 47(5):655-675, May 2000.
- [1089]
- A. Demir and B. Erman.
Simulation of temporal stochastic phenomena in electronic and biological
systems: a comparative review, examples and synergies.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 811-818, San Jose, CA, November 18-21 2013.
- [1090]
- S. Demko, W. F.
Moss, and P. W. Smith.
Decay rates for inverses of band matrices.
Mathematics of computation, 43(168):491-499, October 1984.
- [1091]
- A-C. Deng, Y-C.
Shiau, and K-H. Loh.
Time domain current waveform simulation of CMOS circuits.
In IEEE International Conference on Computer-Aided Design, pages
208-211, Santa Clara, CA, Nov. 7-10 1988.
- [1092]
- J. Deng,
K. Batselier, Y. Zhang, and N. Wong.
An efficient two-level DC operating points finder for transistor circuits.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [1093]
- Y. Deng and W. P. Maly.
2.5-dimensional VLSI system integration.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):668-677, June 2005.
- [1094]
- A-C. Deng and Y-C. Shiau.
Generic linear RC delay modeling for digital CMOS circuits.
IEEE Transactions on Computer-Aided Design, 9(4):367-376, April
1990.
- [1095]
- B. Dennington.
Low power design from technology challenge to great products.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 213-213, Tegernsee, Germany, October 4-6 2006.
- [1096]
- V. V. Deodhar and
J. A. Davis.
Optimization of throughput performance for low-power VLSI interconnects.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):308-318, March 2005.
- [1097]
- H. S. Deogun,
R. R. Rao, D. Sylvester, and D. Blaauw.
Leakage- and crosstalk-aware bus encoding for total power reduction.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
779-782, San Diego, CA, June 7-11 2004.
- [1098]
- H. S. Deogun,
R. Senger, D. Sylvester, R. Brown, and K. Nowka.
A dual-vdd boosted pulsed bus technique for low power and low leakage
operation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 73-78, Tegernsee, Germany, October 4-6 2006.
- [1099]
- U. Desai, S. Tam,
R. Kim, J. Zhang, and S. Rusu.
Itanium processor clock design.
In International Symposium on Physical Design, pages 94-98, San
Diego, CA, April 9-12 2000.
- [1100]
- D. Deschacht.
DSM interconnects: importance of inductance effects and corresponding range
of length.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(7):777-779, July 2006.
- [1101]
- Charles A. Desoer and
Ernest S. Kuh.
Basic Circuit Theory.
McGraw-Hill Book Company, 1969.
- [1102]
- P. F.
Desrumaux, Y. Dupret, J. Tingleff, S. Minehaney, M. Redfordy, L. Latorrez,
and P. Nou.
An efficient control variates method for yield estimation of analog circuits
based on a local model.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 415-421, San Jose, CA, November 5-8 2012.
- [1103]
- A. Deutsch,
P. W. Coteus, G. V. Kopcsay, H. H. Smith, C. W. Surovic, B. L. Krauter, D. C.
Edelstein, and P. J. Restle.
On-chip wiring design challenges for gigahertz operation.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
529-555, Las Vegas, NV, June 18-22 2001.
- [1104]
- S. Devadas,
K. Keutzer, and J. White.
Estimation of power dissipation in CMOS combinational circuits.
In IEEE Custom Integrated Circuits Conference, pages 19.7.1-19.7.6,
1990.
- [1105]
- S. Devadas,
K. Keutzer, S. Malik, and A. Wang.
Certified timing verification and the transition delay of a logic circuit.
In 29th ACM/IEEE Design Automation Conference, pages 549-555,
Anaheim, CA, June 8-12 1992.
- [1106]
- S. Devadas,
K. Keutzer, and J. White.
Estimation of power dissipation in CMOS combinational circuits using boolean
function manipulation.
IEEE Transactions on Computer-Aided Design, 11(3):373-383, March
1992.
- [1107]
- S. Devadas,
K. Keutzer, and S. Malik.
Computation of floating mode delay in combinational circuits: theory and
algorithms.
IEEE Transactions on Computer-Aided Design, 12(12):1913-1923,
December 1993.
- [1108]
- S. Devadas,
K. Keutzer, S. Malik, and A. Wang.
Computation of floating mode delay in combinational circuits: practice and
implementation.
IEEE Transactions on Computer-Aided Design, 12(12):1924-1936,
December 1993.
- [1109]
- S. Devadas,
K. Keutzer, S. Malik, and A. Wang.
Certified timing verification and the transition delay of a logic circuit.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2(3):333-342, September 1994.
- [1110]
- S. Devadas and
S. Malik.
A survey of optimization techniques targeting low power VLSI circuits.
In 32nd Design Automation Conference, pages 242-247, San Francisco,
CA, June 12-16 1995.
- [1111]
- S. Devadas.
Comparing two-level and ordered binary decision diagram representations of
logic functions.
IEEE Transactions on Computer-Aided Design, 12(5):722-723, May
1993.
- [1112]
- A. Devgan,
H. Ji, and W. Dai.
How to efficiently capture on-chip inductance effects: introducing a new
circuit element K.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 150-155, San Jose, CA, November 5-9 2000.
- [1113]
- A. Devgan and
C. Kashyap.
Block-based static timing analysis with uncertainty.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 607-614, San Jose, CA, November 9-13 2003.
- [1114]
- A. Devgan and P. R.
O'Brien.
Realizable reduction for RC interconnect circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
204-207, San Jose, CA, November 7-11 1999.
- [1115]
- A. Devgan and R. A.
Rohrer.
Event driven adaptively controlled explicit simulation of integrated circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
136-140, Santa Clara, CA, November 7-11 1993.
- [1116]
- A. Devgan.
Efficient and accurate transient simulation in charge-voltage plane.
In IEEE/ACM International Conference on Computer-Aided Design, pages
110-114, San Jose, CA, November 5-9 1995.
- [1117]
- A. Devgan.
Efficient coupled noise estimation for on-chip interconnects.
In IEEE/ACM International Conference on Computer-Aided Design, pages
147-151, San Jose, CA, November 9-13 1997.
- [1118]
- S. Dey, F. Brglez, and
G. Kedem.
Corolla based circuit partitioning and resynthesis.
In 27th ACM/IEEE Design Automation Conference (DAC90), pages 607-612,
Orlando, FL, June 24-28 1990.
- [1119]
- S. Dey,
A. Raghunathan, N. K. Jha, and K. Wakabayashi.
Controller-based power management for control-flow intensive designs.
IEEE Transactions on Computer-Aided Design, 18(10):1496-1508, October
1999.
- [1120]
- T. Dhaene and D. De
Zutter.
Selection of lumped element models for coupled lossy transmission lines.
IEEE Transactions on Computer-Aided Design, 11(7):805-815, July
1992.
- [1121]
- N. V. T. D'Halleweyn, J. Benson, W. Redman-White, K. Mistry, and
M. Swanenberg.
MOOSE: a physically based compact DC model of SOI ldmosfets for analogue
circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(10):1399-1410, October 2004.
- [1122]
- N. Dhanwada,
D. Hathaway, V. Zyuban, P. Peng, K. Moody, W. Dungan, A. Joseph, R. Rao, and
C. Gonzalez.
Efficient PVT independent abstraction of large IP blocks for hierarchical
power analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 458-465, San Jose, CA, November 18-21 2013.
- [1123]
- N. Dhanwada,
R. Davis, and J. Frenkil.
Towards a standard flow for system level power modeling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 73, San Jose, CA, November 2-6 2014.
- [1124]
- I. B. Dhaou,
M. Ismail, and H. Tenhunen.
Current mode, low-power, on-chip signaling in deep-submicron CMOS technology.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(3):397-406, March 2003.
- [1125]
- I. B. Dhaou and
H. Tenhunen.
Efficient library characterization for high-level power estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(6):657-661, June 2004.
- [1126]
- A. Dharchoudhury, R. Panda, D. Blaauw, R. Vaidyanathan,
B. Tutuianu, and D. Bearden.
Design and analysis of power distribution networks in powerpc microprocessors.
In IEEE/ACM 35th Design Automation Conference, pages 738-743, San
Francisco, CA, June 15-19 1998.
- [1127]
- A. Dharchoudhury and S. M. Kang.
Performance-constrained worst-case variability minimization of VLSI circuits.
In 30th ACM/IEEE Design Automation Conference, pages 154-158, Dallas,
TX, June 14-18 1993.
- [1128]
- A. Dharchoudhury and S. M. Kang.
Worst-case analysis and optimization of VLSI circuit performances.
IEEE Transactions on Computer-Aided Design, 14(4):481-492, April
1995.
- [1129]
- F. M. D'Heurle.
Electromigration and failure in electronics : an introduction.
In Proceedings of the IEEE, page 1409, October 1971.
Published as Proceedings of the IEEE, volume 59, number 10.
- [1130]
- Y. S. Dhillon,
A. U. Diril, A. Chatterjee, and H.-H. S. Lee.
Algorithm for achieving minimum energy consumption in CMOS circuits using
multiple supply and threshold voltages at the module level.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 693-700, San Jose, CA, November 9-13 2003.
- [1131]
- Y. S. Dhillon,
A. U. Diril, A. Chatterjee, and A. D. Singh.
Analysis and optimization of nanometer CMOS circuits for soft-error
tolerance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(5):514-524, May 2006.
- [1132]
- G. Dhiman and T. S.
Rosing.
Dynamic power management using machine learning.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 747-754, San Jose, CA, November 5-9 2006.
- [1133]
- R. P. Dick,
G. Lakshminarayana, A. Raghunathan, and N. K. Jha.
Analysis of power dissipation in embedded systems using real-time operating
systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(5):615-627, May 2003.
- [1134]
- R. P. Dick.
Reliability, thermal, and power modeling and optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 181-184, San Jose, CA, November 7-11 2010.
- [1135]
- Donald L. Dietmeyer.
Logic Design of Digital Systems, 3rd Ed..
Allyn and Bacon, Inc., Boston, MA, 1988.
- [1136]
- G. Dimitrakopoulos and V. Paliouras.
A novel architecture and a systematic graph-based optimization methodology for
modulo multiplication.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(2):354-370, February 2004.
- [1137]
- C.-S. Ding, C.-T.
Hsieh, Q. Wu, and M. Pedram.
Stratified random sampling for power estimation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
576-582, San Jose, CA, November 10-14 1996.
- [1138]
- C-S Ding, Q. Wu, C-T
Hsieh, and M. Pedram.
Statistical estimation of the cumulative distribution function for power
dissipation in VLSI circuits.
In 34th Design Automation Conference, pages 371-376, Anaheim, CA,
June 9-13 1997.
- [1139]
- C-S Ding, C-T
Hsieh, and M. Pedram.
Improving sampling efficiency for system level power estimation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 115-117, Monterey, CA, August 10-12 1998.
- [1140]
- C.-S. Ding, C.-Y.
Tsui, and M. Pedram.
Gate-level power estimation using tagged probabilistic simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 17(11):1099-1107, November 1998.
- [1141]
- C.-S. Ding, Q. Wu,
C.-T. Hsieh, and M. Pedram.
Stratified random sampling for power estimation.
IEEE Transactions on Computer-Aided Design, 17(6):465-471, June
1998.
- [1142]
- C.-S. Ding, C.-T.
Hsieh, and M. Pedram.
Improving the efficiency of monte carlo power estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(5):584-593, October 2000.
- [1143]
- L. Ding, D. Blaauw,
and P. Mazumder.
Efficient crosstalk noise modeling using aggressor and tree reductions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 595-600, San Jose, CA, November 10-14 2002.
- [1144]
- L. Ding, D. Blaauw,
and P. Mazumder.
Accurate crosstalk noise modeling for early signal integrity analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(5):627-634, May 2003.
- [1145]
- Y. Ding, Y. Wu, and
W. Qian.
Generating multiple correlated probabilities for MUX-based stochastic
computing architecture.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 519-526, San Jose, CA, November 2-6 2014.
- [1146]
- L. Ding and P. Mazumder.
A novel technique to improve noise immunity of CMOS dynamic logic circuits.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
900-903, San Diego, CA, June 7-11 2004.
- [1147]
- L. Ding and
P. Mazumder.
On circuit techniques to improve noise immunity of CMOS dynamic logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(9):910-925, September 2004.
- [1148]
- Q. Dinh, D. Chen,
and M.-D.-F. Wong.
A routing approach to reduce glitches in low power fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(2):235-245, February 2010.
- [1149]
- S. W.
Director, P. K. Khosla, R. A. Rohrer, and R. A. Rutenbar.
Reengineering the curriculum: Design and analysis of a new undergraduate
electrical and computer engineering degree at carnegie mellon university.
In Proceedings of the IEEE, pages 1246-1269, September 1995.
Published as Proceedings of the IEEE, volume 83, number 9.
- [1150]
- A. U. Diril, Y. S.
Dhillon, A. Chatterjee, and A. D. Singh.
Level-shifter free design of low power dual supply voltage CMOS circuits
using dual threshold voltages.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(9):1103-1107, September 2005.
- [1151]
- T. Djurhuus and
V. Krozer.
Theory of injection-locked oscillator phase noise.
IEEE Transactions on Circuits and Systems, 58(2):312-325, February
2011.
- [1152]
- V. B.
Dmitriev-Zdorov.
Multicycle generalization - a new way to improve the convergence of waveform
relaxation for circuit simulation.
IEEE Transactions on Computer-Aided Design, 17(5):435-443, May
1998.
- [1153]
- L. Dolecek,
M. Qazi, D. Shah, and A. Chandrakasan.
Breaking the simulation barrier: SRAM evaluation through norm minimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 322-329, San Jose, CA, November 10-13 2008.
- [1154]
- J. Donald and
M. Martonosi.
Power efficiency for variation-tolerant multicore processors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 304-309, Tegernsee, Germany, October 4-6 2006.
- [1155]
- W. E. Donath.
Equivalence of memory to "random logic".
IBM Journal of Research and Development, pages 401-407, September
1974.
- [1156]
- C. Dong, D. Chen,
S. Tanachutiwat, and W. Wang.
Performance and power evaluation of a 3d CMOS/nanomaterial reconfigurable
architecture.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 758-764, San Jose, CA, November 5-8 2007.
- [1157]
- W. Dong, P. Li,
and G.-M. Huang.
SRAM dynamic stability: theory, variability and analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 378-385, San Jose, CA, November 10-13 2008.
- [1158]
- W. Dong, P. Li,
and X. Ye.
Wavepipe: parallel transient simulation of analog and digital circuits on
multi-core shared-memory machines.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
238-243, Anaheim, CA, June 8-13 2008.
- [1159]
- X. Dong, J. Zhao,
and Y. Xie.
Fabrication cost analysis and cost-aware design space exploration for 3-D
ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(12):1959-1972, December 2010.
- [1160]
- W. Dong and P. Li.
Final-value odes: stable numerical integration and its application to parallel
circuit analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 403-409, San Jose, CA, November 2-5 2009.
- [1161]
- W. Dong and P. Li.
Parallelizable stable explicit numerical integration for efficient circuit
simulation.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
382-385, San Francisco, CA, July 26-31 2009.
- [1162]
- C. Dong and X. Li.
Efficient SRAM failure rate prediction via gibbs sampling.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
200-205, San Diego, CA, June 5-9 2011.
- [1163]
- N. Dong and
J. Roychowdhury.
General-purpose nonlinear model-order reduction using piecewise-polynomial
representations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):249-264, February 2008.
- [1164]
- M. Donno,
A. Ivaldi, L. Benini, and E. Macii.
Clock-tree power optimization based on RTL clock-gating.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
622-627, Anaheim, CA, June 2-6 2003.
- [1165]
- F. Dorfler and
F. Bullo.
Kron reduction of graphs with applications to electrical networks.
IEEE Transactions on Circuits and Systems, 60(1):150-163, January
2013.
- [1166]
- A. Doumar and H. Ito.
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable
gate arrays: a survey.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):386-405, June 2003.
- [1167]
- B. Doyle,
P. Mahoney, E. Fetzer, and S. Naffziger.
Clock distribution on a dual-core, multi-threaded itanium family
microprocessor.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 1-6, Austin, TX, May 9 - 11 2005.
- [1168]
- N. Dragone,
R. Zafalon, C. Guardiani, and C. Silvano.
Power invariant vector compaction based on bit clustering and temporal
partitioning.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 118-120, Monterey, CA, August 10-12 1998.
- [1169]
- R. Drechsler, M. Sauerhoff, and D. Sieling.
The complexity of the inclusion operation on ofdds.
IEEE Transactions on Computer-Aided Design, 17(5):457-459, May
1998.
- [1170]
- R. Drechsler, N. Drechsler, and W. Gunther.
Fast exact minimization of BDD's.
IEEE Transactions on Computer-Aided Design, 19(3):384-389, March
2000.
- [1171]
- F. Dresig, Ph.
Lanches, O. Rettig, and U. G. Baitinger.
Simulation and reduction of CMOS power dissipation at logic level.
In European Design Automation Conference (EDAC), pages 341-346,
1993.
- [1172]
- M. Drinic,
D. Kirovski, S. Megerian, and M. Potkonjak.
Latency-guided on-chip bus-network design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2663-2673, December 2006.
- [1173]
- D. G. Drmanac,
F. Liu, and L.-C. Wang.
Predicting variability in nanoscale lithography processes.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
545-550, San Francisco, CA, July 26-31 2009.
- [1174]
- N. Dronavalli
and V. Malik.
A design method for estimating power in CMOS gates using logical lffort.
In The First Annual Northeast Workshop on Circuits and Systems
(NEWCAS-03), pages 113-116, Montreal, Quebec, June 17-20 2003.
- [1175]
- Y. Du, D. Guo, M.-D.-F.
Wong, H. Yi, H.-S.-P. Wong, H. Zhang, and Q. Ma.
Block copolymer directed self-assembly (DSA) aware contact layer optimization
for 10 nm 1d standard cell library.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 186-193, San Jose, CA, November 18-21 2013.
- [1176]
- X. Duan, Y. Hu, and
K. Mayaram.
Simulation of ring oscillators using the harmonic balance method.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 137-140, Montreal, Quebec, June 20-23 2004.
- [1177]
- C. Duan, C. Zhu, and
S. P. Khatri.
Forbidden transition free crosstalk avoidance CODEC design.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 44-49, Monterey, CA,
February 25-26 2008.
- [1178]
- X. Duan and K. Mayaram.
An efficient and robust method for ring-oscillator simulation using the
harmonic-balance method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(8):1225-1233, August 2005.
- [1179]
- X. Duan and K. Mayaram.
Frequency-domain simulation of ring oscillators with a multiple-probe method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2833-2842, December 2006.
- [1180]
- F. Dubeau and
C. Gnang.
Fixed point and newton's methods for solving a nonlinear equation: from linear
to high-order convergence.
SIAM Review, 56(4):691-708, December 2014.
- [1181]
- F. Dubeau and C. Gnang.
Fixed point and newton's methods for solving a nonlinear equation: From linear
to higher-order convergence.
SIAM Review, 56(4):691-708, 2014.
- [1182]
- E. Dubrova,
M. Teslenko, and A. Martinelli.
Kauffman networks: analysis and applications.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 479-484, San Jose, CA, November 6-10 2005.
- [1183]
- R. J. Duffin.
Topology of series-parallel networks.
Journal of Mathematical Analysis and Applications, pages 303-318,
1965.
- [1184]
- L. Dupont,
S. Roy, and J.-Y. Chouinard.
A hardware architecture for the generation of wnaf random integers.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 99-102, Quebec City, Quebec, June 19-22 2005.
- [1185]
- J. A. Dussault.
A testability measure.
In IEEE Digital Semiconductor Test Symposium, pages 113-116, Cherry
Hill, NJ, Oct-Nov. 1978.
- [1186]
- S. Dutt and W. Deng.
Probability-based approaches to VLSI circuit partitioning.
IEEE Transactions on Computer-Aided Design, 19(5):534-549, May
2000.
- [1187]
- R. Dutta and
M. Marek-Sadowska.
Automatic sizing of power/ground (p/g) networks in VLSI.
In 26th ACM/IEEE Design Automation Conference, pages 783-786, Las
Vegas, NV, June 25-29 1989.
- [1188]
- R. W. Dutton and
A. J. Strojwas.
Perspectives on technology and technology-driven CAD.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1544-1560, December 2000.
- [1189]
- S. G. Duvall.
Practical statistical design of complex integrated circuit products.
In ACM/IEEE Design Automation Conference, pages 561-565, Dallas, TX,
June 14-18 1993.
- [1190]
- S. G. Duvall.
Toward a practical methodology for the statistical design of complex integrated
circuits.
In 1993 International Symposium on VLSI Technology, Systems, and
Applications, pages 112-116, Taipei, Taiwan, May 12-14 1993.
- [1191]
- S. G. Duvall.
Statistical circuit modeling and optimization.
In IEEE International Workshop on Statistical Metrology, pages 56-63,
Honolulu, HI, June 11 2000.
- [1192]
- C. Duvvury.
ESD: Design for IC chip quality and reliability.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 251-259, San Jose, CA, March 20-22 2000.
- [1193]
- C. Dwyer.
Computer-aided design for DNA self-assembly: process and applications.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 662-667, San Jose, CA, November 6-10 2005.
- [1194]
- E. Dyer,
M. Majzoobi, and F. Koushanfar.
Hybrid modeling of non-stationary process variations.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
194-199, San Diego, CA, June 5-9 2011.
- [1195]
- L. G. e Silva,
L. M. Silveira, and J. R. Phillips.
Efficient computation of the worst-delay corner.
Design, Automation and Test in Europe (DATE-07), pages 1617-1622,
April 16-20 2007.
- [1196]
- L. G. e Silva,
J. Phillips, and L. M. Silveira.
Effective corner-based techniques for variation-aware IC timing verification.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(1):157-162, January 2010.
- [1197]
- L. G. e Silva,
J. R. Phillips, and L. M. Silveira.
Speedpath analysis under parametric timing models.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
268-273, Anaheim, CA, June 13-18 2010.
- [1198]
- R. Ebendt,
W. Gunther, and R. Drechsler.
An improved branch and bound algorithm for exact BDD minimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(12):1657-1663, December 2003.
- [1199]
- M. Ebrahimi,
F. Oboril, S. Kiamehr, and M. B. Tahoori.
Aging-aware logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 61-68, San Jose, CA, November 18-21 2013.
- [1200]
- D. Eckerbert and P. Larsson-Edefors.
Cycle-true leakage current modeling for CMOS gates.
In IEEE International Symposium on Circuits and Systems (ISCAS), pages
V.507-V.510, 2001.
- [1201]
- A. Edman and
C. Svensson.
Timing closure through a globally synchronous, timing partitioned design
methodology.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 71-74,
San Diego, CA, June 7-11 2004.
- [1202]
- N. Een and N. Sorensson.
Translating pseudo-boolean constraints into SAT.
Journal on Satisfiability, Boolean Modeling and Computation, 2:1-25,
February 2006.
- [1203]
- S. Eggersglub, R. Wille, and R. Drechsler.
Improved SAT-based ATPG: more constraints, better compaction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 85-90, San Jose, CA, November 18-21 2013.
- [1204]
- T. J. Eguia,
S.-X.-D. Tan, R. Shen, D. Li, E. H. Pacheco, M. Tirumala, and L. Wang.
General parameterized thermal modeling for high-performance microprocessor
design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):211-224, February 2012.
- [1205]
- E. B. Eichelberger.
Hazard detection in combinational and sequential switching circuits.
IBM Journal, pages 90-99, March 1965.
- [1206]
- M. Eiermann and
W. Stechele.
Novel modeling techniques for RTL power estimation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 323-328, Monterey, California, August 12-14 2002.
- [1207]
- M. Eisele,
J. Berthold, D. Schmitt-Landsiedel, and R. Mahnkopf.
The impact of intra-die device parameter variation on path delays and on the
design for yield of low voltage digital circuits.
In International Symposium on Low Power Electronics and Design, pages
237-242, Monterey, CA, August 12-14 1996.
- [1208]
- M. Eisele,
J. Berthold, D. Schmitt-Landsiedel, and R. Mahnkopf.
The impact of intra-die device parameter variations on path delays and on the
design for yield of low voltage digital circuits.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
5(4):360-368, December 1997.
- [1209]
- W. T. Eisenmann
and H. E. Graeb.
Fast transient power and noise estimation for VLSI circiuts.
In IEEE/ACM International Conference on Computer-Aided Design, pages
252-257, San Jose, CA, November 6-10 1994.
- [1210]
- D. A. El-Dib and M. I.
Elmasry.
Modified register-exchange viterbi decoder for low-power wireless
communications.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(2):371-378, February 2004.
- [1211]
- W. El-Essawy, D. H. Albonesi, and B. Sinharoy.
A microarchitectural-level step-power analysis tool.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 263-266, Monterey, California, August 12-14 2002.
- [1212]
- A. M.
El-Husseini and M. Morrise.
Clocking design automation in intel's core i7 and future designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 276-278, San Jose, CA, November 7-10 2011.
- [1213]
- T. El-Moselhy, I. M. Elfadel, and D. Widiger.
Efficient algorithm for the computation of on-chip capacitance sensitivities
with respect to a large set of parameters.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
906-911, Anaheim, CA, June 8-13 2008.
- [1214]
- T. A.
El-Moselhy, I. M. Elfadel, and L. Daniel.
A capacitance solver for incremental variation-aware extraction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 662-669, San Jose, CA, November 10-13 2008.
- [1215]
- T. El-Moselhy
and L. Daniel.
Stochastic integral equation solver for efficient variation-aware interconnect
extraction.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
415-420, Anaheim, CA, June 8-13 2008.
- [1216]
- T. El-Moselhy
and L. Daniel.
Stochastic dominant singular vectors method for variation-aware extraction.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
667-672, Anaheim, CA, June 13-18 2010.
- [1217]
- M. A. El-Moursy
and E. G. Friedman.
Power characteristics of inductive interconnect.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1295-1306, December 2004.
- [1218]
- M. A. El-Moursy
and E. G. Friedman.
Shielding effect of on-chip interconnect inductance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):396-400, March 2005.
- [1219]
- K. M.
El-Shennawy, G. P. Fiani, and M. B. Tayel.
Closed-form solutions for voltage pulse response of open, shorted, and loaded
distributed RC thin film structures.
IEEE Transactions on Circuits and Systems, 38(12):1567-1571, December
1991.
- [1220]
- Y. M. El-Ziq and S. Y. H.
Su.
Fault diagnosis of MOS combinational networks.
IEEE Transactions on Computers, C-31(2):129-139, February 1982.
- [1221]
- Y. M. El-Ziq.
Failure analysis and test generation for VLSI physical defects.
In IEEE Custom Integrated Circuits Conference, pages 300-303,
Rochester, NY, May 1983.
- [1222]
- R. D. Eldred.
Test routines based on symbolic logical statements.
Journal of the Association for Computing Machinery, 6(1):33-36,
January 1959.
- [1223]
- I. M. Elfadel and
D. D. Ling.
A block rational arnoldi algorithm for multipoint passive model-order reduction
of multiport RLC networks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
66-71, San Jose, CA, November 9-13 1997.
- [1224]
- I. M. Elfadel and
D. D. Ling.
Zeros and passivity of arnoldi-reduced-order models for interconnect networks.
In 34th Design Automation Conference, pages 28-33, Anaheim, CA, June
9-13 1997.
- [1225]
- M. Elgebaly and
M. Sachdev.
Efficient adaptive voltage scaling system through on-chip critical path
emulation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 375-380, Newport Beach, CA, August 9-11 2004.
- [1226]
- P. J. H. Elias and
N. P. van der Meijs.
Extracting circuit models for large RC interconnetions that are accurate up
to a predefined signal frequency.
In 33rd Design Automation Conference, pages 764-769, Las Vegas, NV,
June 3-7 1996.
- [1227]
- W. C. Elmore.
The transient response of damped linear networks with particular regard to
wideband amplifiers.
Journal of Applied Physics, 19(1):55-63, January 1948.
- [1228]
- Y. M. Elziq.
Automatic test generation for stuck-open faults in CMOS VLSI.
In IEEE 18th Design Automation Conference, pages 347-354, Nashville,
TN, June 1981.
- [1229]
- Y. M. Elziq.
Functional-level test generation for stuck-open faults in CMOS VLSI.
In IEEE International Test Conference, pages 536-546, Philadelphia,
PA, Oct. 27-29 1981.
- [1230]
- S. H. K. Embabi and
R. Damodaran.
Delay models for CMOS, bicmos and binmos circuits and their applications for
timing simulations.
IEEE Transactions on Computer-Aided Design, 13(9):1132-1142,
September 1994.
- [1231]
- T. Enami,
S. Ninomiya, and M. Hashimoto.
Statistical timing analysis considering spatially and temporally correlated
dynamic power supply noise.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(4):541-553, April 2009.
- [1232]
- Y. Eo, S. Shin, W. R.
Eisenstadt, and J. Shim.
A decoupling technique for efficient timing analysis of VLSI interconnects
with dynamic circuit switching.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1321-1337, September 2004.
- [1233]
- S. Ercolani,
M. Favalli, M. Damiani, P. Olivo, and B. Ricco.
Estimate of signal probability in combinational logic networks.
In IEEE European Test Conference, pages 132-138, 1989.
- [1234]
- S. Ercolani,
M. Favalli, M. Damiani, P. Olivo, and B. Ricco.
Testability measures in pseudorandom testing.
IEEE Transactions on Computer-Aided Design, 11(6):794-800, June
1992.
- [1235]
- R. Erwe and N. Tanabe.
Efficient simulation of MOS circuits.
IEEE Transactions on Computer-Aided Design, 10(4):541-544, April
1991.
- [1236]
- B. Eschermann.
State assignment for hardwired VLSI control units.
ACM Computing Surveys, 25(4):415-436, December 1993.
- [1237]
- R. Escovar,
S. Ortiz, and R. Suaya.
An improved long distance treatment for mutual inductance.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(5):783-793, May 2005.
- [1238]
- R. Escovar and
R. Suaya.
Transmission line design of clock trees.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 334-340, San Jose, CA, November 10-14 2002.
- [1239]
- R. Escovar and
R. Suaya.
Optimal design of clock trees for multigigahertz applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(3):329-345, March 2004.
- [1240]
- K. S. Eshbaugh.
Generation of correlated parameters for statistical circuit simulation.
IEEE Transactions on Computer-Aided Design, 11(10):1198-1206, October
1992.
- [1241]
- S. E. Esmaeili
and A. J. Al-Khalili.
Integrated power and clock distribution network.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1941-1945, October 2013.
- [1242]
- J. Evans, P. Lall,
and R. Bauernschub.
A framework fo reliability modeling of electronics.
In Annual Reliability and Maintainability Symposium, pages 144-151,
Washington, DC, January 16-19 1995.
- [1243]
- N. E. Evmorfopoulos, G. I. Stamoulis, and J. N. Avaritsiotis.
A monte carlo approach for maximum power estimation based on extreme value
theory.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(4):415-432, April 2002.
- [1244]
- N. E. Evmorfopoulos, D. P. Karampatzakis, and G. I. Stamoulis.
Voltage-drop-constrained optimization of power distribution network based on
reliable maximum current estimates.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 479-484, San Jose, CA, November 7-11 2004.
- [1245]
- N. Evmorfopoulos, D. Karampatzakis, and G. Stamoulis.
Precise identification of the worst-case voltage drop conditions in power grid
verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 112-118, San Jose, CA, November 5-9 2006.
- [1246]
- N. Evmorfopoulos, M.-A. Rammou, G. Stamoulis, and J. Moondanos.
Characterization of the worst-case current waveform excitations in general
RLC-model power grid analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 824-830, San Jose, CA, November 7-11 2010.
- [1247]
- A. Exposito,
B. Soler, and J. A. Rosendo Macias.
Application of generalized phasors to eigenvector and natural response
computation of LTI circuits.
IEEE Transactions on Circuits and Systems, 53(7):1533-1543, July
2006.
- [1248]
- S. A. Fahmy and A. R.
Moham.
Architecture for real-time nonparametric probability density function
estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(5):910-920, May 2013.
- [1249]
- B. J.
Falkowski, I. Schafer, and M. A. Perkowski.
Effective computer methods for the calculation of rademacher-walsh spectrum for
completely and incompletely specified boolean functions.
IEEE Transactions on Computer-Aided Design, 11(10):1207-1226, October
1992.
- [1250]
- F. Fallah,
S. Liao, and S. Devadas.
Solving covering problems using LPR-based lower bounds.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(1):9-17, February 2000.
- [1251]
- J. Fan, N. Mi, and
X.-D. Sheldon.
Statistical model order reduction for interconnect circuits considering spatial
correlations.
Design, Automation and Test in Europe (DATE-07), pages 1508-1513,
April 16-20 2007.
- [1252]
- S.-C. Fang, J.-M.
Wang, and W.-S. Feng.
A new direct design for three-input XOR function on the transistor level.
IEEE Transactions on Circuits and Systems, Part I, 43(4):343-348,
April 1996.
- [1253]
- P. Fang, J. Tao,
J. F. Chen, and C. Hu.
Design-in hot-carrier reliability for high performance logic applications.
In IEEE Custom Integrated Circuits Conference, pages 525-531, Santa
Clara, CA, May 11-14 1998.
- [1254]
- C. F. Fang, R. A.
Rutenbar, and T. Chen.
Fast, accurate static analysis for fixed-point finite-precision effects in
DSP designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 275-282, San Jose, CA, November 9-13 2003.
- [1255]
- C. F. Fang, R. A.
Rutenbar, M. Puschel, and T. Chen.
Toward efficient static analysis of finite-precision effects in DSP
applications via affine arithmetic modeling.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
496-501, Anaheim, CA, June 2-6 2003.
- [1256]
- H. Fang,
K. Chakrabarty, Z. Wang, and X. Gu.
Diagnosis of board-level functional failures under uncertainty using
dempster-shafer theory.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(10):1586-1599, October 2012.
- [1257]
- J. Fang, S. Gupta,
S. V. Kumar, S. K. Marella, V. Mishra, P. Zhou, and S. S. Sapatnekar.
Circuit reliability: from physics to architectures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 243-246, San Jose, CA, November 5-8 2012.
- [1258]
- E.-J.-W. Fang,
T.-C.-J. Shih, and D.-S.-Y. Huang.
IR to routing challenge and solution for interposer-based design.
In 20th Asia and South Pacific Design Automation Conference, pages
226-230, Chiba/Tokyo, Japan, January 19-22 2015.
- [1259]
- C. Fang, Q. Huang,
F. Yang, X. Zeng, D. Zhou, and X. Li.
Efficient performance modeling of analog integrated circuits via kernel density
based sparse regression.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [1260]
- J.-W. Fang and Y.-W. Chang.
Area-I/O flip-chip routing for chip-package co-design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 518-522, San Jose, CA, November 10-13 2008.
- [1261]
- J. Fang and S. S.
Sapatnekar.
Scalable methods for analyzing the circuit failure probability due to gate
oxide breakdown.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(11):1960-1973, November 2012.
- [1262]
- I. Fang and S. S.
Sapatnekar.
Incorporating hot-carrier injection effects into timing analysis for large
circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(12):2738-2751, December 2014.
- [1263]
- G.-P. Fang.
A new time-stepping method for circuit simulation.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1264]
- N. R. Farnum and
P. Booth.
Uniqueness of maximum likelihood estimators of the 2-parameter weibull
distribution.
IEEE Transactions on Reliability, 46(4):523-525, December 1997.
- [1265]
- A. H. Farrahi,
D. J. Hathaway, M. Wang, and M. Sarrafzadeh.
Quality of EDA CAD tools: definitions, metrics, and directions.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 395-405, San Jose, CA, March 20-22 2000.
- [1266]
- A. H. Farrahi,
C. Chen, A. Srivastava, G. Tellez, and M. Sarrafzadeh.
Activity-driven clock design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(6):705-714, June 2001.
- [1267]
- K. Farzan and D. A.
Johns.
Coding schemes for chip-to-chip interconnect applications.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(4):393-406, April 2006.
- [1268]
- H. Fatemi,
S. Nazarian, and M. Pedram.
Statistical logic cell delay analysis using a current-based model.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
253-256, San Francisco, CA, July 24-28 2006.
- [1269]
- M. Favalli and
L. Benini.
Analysis of glitch power dissipation in CMOS ics.
In ACM/IEEE International Symposium on Low Power Design, pages
123-128, Dana Point, CA, April 23-26 1995.
- [1270]
- M. Fawaz,
S. Chatterjee, and F. N. Najm.
A vectorless framework for power grid electromigration checking.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 553-560, San Jose, CA, November 18-21 2013.
- [1271]
- M. Fawaz and F. N. Najm.
Accurate verification of RC power grids.
IEEE Design Automation and Test in Europe (DATE), pages 814-817,
March 14-18 2016.
- [1272]
- M. Fawaz and F. N. Najm.
Fast simulation-based verification of RC power grids.
In IEEE Canadian Conference on Electrical and Computer Engineering
(CCECE), pages 1182-1187, Vancouver, BC, May 15-18 2016.
- [1273]
- M. Fawaz and F. N. Najm.
Fast vectorless RLC grid verification.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 36(3):489-502, March 2017.
- [1274]
- M. Fawaz and F. N. Najm.
Parallel simulation-based verification of RC power grids.
In IEEE Computer Society Annual Symposium on VLSI (ISVLSI-17), pages
445-452, Bochum, Germany, July 3-5 2017.
- [1275]
- M. Fayyazi and
L. Kirsch.
Efficient simulation of oscillatory combinational loops.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
777-780, Anaheim, CA, June 13-18 2010.
- [1276]
- Y. Fei, S. Ravi,
A. Raghunathan, and N. K. Jha.
A hybrid energy-estimation technique for extensible processors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):652-664, May 2004.
- [1277]
- W. Fei, H. Yu,
W. Zhang, and K.-S. Yeo.
Design exploration of hybrid CMOS and memristor circuit by new modified nodal
analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(6):1012-1025, June 2012.
- [1278]
- A. Feinberg and
A. Widom.
Connecting parametric aging to catastrophic failure through thermodynamics.
IEEE Transactions on Reliability, 45(1):28-33, March 1996.
- [1279]
- P. Feldmann, S. Abbaspour, D. Sinha, G. Schaeffer, R. Banerji,
and H. Gupta.
Driver waveform computation for timing analysis with multiple voltage threshold
driver models.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 74-79, Monterey, CA,
February 25-26 2008.
- [1280]
- P. Feldmann, S. Abbaspour, D. Sinha, G. Schaeffer, R. Banerji,
and H. Gupta.
Driver waveform computation for timing analysis with multiple voltage threshold
driver models.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
425-428, Anaheim, CA, June 8-13 2008.
- [1281]
- P. Feldmann and
S. Abbaspour.
Towards a more physical approach to gate modeling for timing, noise, and power.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
453-455, Anaheim, CA, June 8-13 2008.
- [1282]
- P. Feldmann and
R. W. Freund.
Efficient linear circuit analysis by pade approximation via the lanczos
process.
IEEE Transactions on Computer-Aided Design, 14(5):639-649, May
1995.
- [1283]
- P. Feldmann and
R. W. Freund.
Reduced-order modeling of large linear subcircuits via a block lanczos
algorithm.
In 32nd Design Automation Conference, pages 474-479, San Francisco,
CA, June 12-16 1995.
- [1284]
- P. Feldmann and
F. Liu.
Sparse and efficient reduced order modeling of linear subcircuits with large
number of terminals.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 88-92, San Jose, CA, November 7-11 2004.
- [1285]
- P. Feldmann and
R. A. Rohrer.
Proof of the number of independent kirchhoff equations in an electrical
circuit.
IEEE Transactions on Circuits and Systems, 38(7):681-684, July
1991.
- [1286]
- Z. Feng, P. Li, and
Y. Zhan.
Fast second-order statistical static timing analysis using parameter dimension
reduction.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
244-249, San Diego, CA, June 4-8 2007.
- [1287]
- Z. Feng, P. Li, and
Y. Zhan.
An on-the-fly parameter dimension reduction approach to fast second-order
statistical static timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(1):141-153, January 2009.
- [1288]
- C. Feng, H. Zhou,
C. Yan, J. Tao, and X. Zeng.
Efficient approximation algorithms for chemical mechanical polishing dummy
fill.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(3):402-415, March 2011.
- [1289]
- Z. Feng, Z. Zeng,
and P. Li.
Parallel on-chip power distribution network analysis on multi-core-GPU
platforms.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(10):1823-1836, October 2011.
- [1290]
- Z. Feng, X. Zhao,
and Z. Zeng.
Robust parallel preconditioned power grid simulation on GPU with adaptive
runtime performance modeling and optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(4):562-573, April 2011.
- [1291]
- Z. Feng and P. Li.
Performance-oriented statistical parameter reduction of parameterized systems
via reduced rank regression.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 868-875, San Jose, CA, November 5-9 2006.
- [1292]
- Z. Feng and P. Li.
A methodology for timing model characterization for statistical static timing
analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 725-729, San Jose, CA, November 5-8 2007.
- [1293]
- Z. Feng and P. Li.
Parameterized waveform-independent gate models for timing and noise analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 61-66, Austin, Texas,
February 26-27 2007.
- [1294]
- Z. Feng and P. Li.
Multigrid on GPU: tackling power grid analysis on parallel SIMT platforms.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 647-654, San Jose, CA, November 10-13 2008.
- [1295]
- Z. Feng and P. Li.
Performance-oriented parameter dimension reduction of VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(1):137-150, January 2009.
- [1296]
- Z. Feng and Z. Zeng.
Parallel multigrid preconditioning on graphics processing units (gpus) for
robust power grid analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
661-666, Anaheim, CA, June 13-18 2010.
- [1297]
- Z. Feng.
Scalable multilevel vectorless power grid voltage integrity verification.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(8):1388-1397, August 2013.
- [1298]
- Z. Feng.
Scalable vectorless power grid current integrity verification.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1299]
- Z. Feng.
Fast RC reduction of flip-chip power grids using geometric templates.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(11):2357-2365, November 2014.
- [1300]
- Z. Feng.
Spectral graph sparsification in nearly-linear time leveraging efficient
spectral perturbation analysis.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [1301]
- F. J. Ferguson and
J. P. Shen.
Multiple-fault test sets for MOS complex gates.
In IEEE International Conference on Computer-Aided Design, pages
36-38, Santa Clara, CA, Nov. 18-21 1985.
- [1302]
- V. Ferragina, N. Ghittori, G. Torelli, G. Boselli, G. Trucco,
and V. Liberali.
A time-domain current model for fully CMOS logic gates.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 29-32, Montreal, Quebec, June 20-23 2004.
- [1303]
- A. Ferre and
J. Figueras.
Leakage power bounds in CMOS digital technologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(6):731-738, June 2002.
- [1304]
- R. Ferreira,
A-M Trullemans, J. Costa, and J. Monteiro.
Probabilistic bottom-up RTL power estimation.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 439-446, San Jose, CA, March 20-22 2000.
- [1305]
- I. A. Ferzli,
F. N. Najm, and L. Kruse.
Early power grid verification under circuit current uncertainties.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 116-121, Portland, Oregon, August 27-29 2007.
- [1306]
- I. A. Ferzli,
F. N. Najm, and L. Kruse.
A geometric approach for early power grid verification using current
constraints.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 40-47, San Jose, CA, November 5-8 2007.
- [1307]
- I. A. Ferzli,
E. Chiprout, and F. N. Najm.
Verification and co-design of the package and die power delivery system using
wavelets.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 7-10, San Jose, CA, October 27-29 2008.
- [1308]
- I. A. Ferzli,
E. Chiprout, and F. N. Najm.
Verification and codesign of the package and die power delivery system using
wavelets.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(1):92-102, January 2010.
- [1309]
- I. A. Ferzli and F. N.
Najm.
Statistical estimation of leakage-induced power grid voltage drop considering
within-die process variations.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
856-859, Anaheim, CA, June 2-6 2003.
- [1310]
- I. A. Ferzli and F. N.
Najm.
Statistical verification of power grids considering process-induced leakage
current variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 770-777, San Jose, CA, November 9-13 2003.
- [1311]
- I. Ferzli and F. N. Najm.
Statistical estimation of circuit timing vulnerability due to leakage-induced
power grid voltage drop.
In International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 17-24, Austin, TX, May 17-20 2004.
- [1312]
- I. A. Ferzli and F. N.
Najm.
Analysis and verification of power grids considering process-induced
leakage-current variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):126-143, January 2006.
- [1313]
- G. Fey, A. Sulflow,
and R. Drechsler.
Computing bounds for fault tolerance using formal techniques.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
190-195, San Francisco, CA, July 26-31 2009.
- [1314]
- G. Fey and R. Drechsler.
Minimizing the number of paths in bdds: theory and algorithm.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):4-11, January 2006.
- [1315]
- M. Fiedler.
Algebraic connectivity of graphs.
Czechoslovak Mathematical Journal, 23(98):298-305, 1973.
- [1316]
- M. Fiedler.
A property of eigenvectors of nonnegative symmetric matrices and its
application to graph theory.
Czechoslovak Mathematical Journal, 25(100):619-633, 1975.
- [1317]
- H. Filiol,
I. O'Connor, and D. Morche.
Analog IC variability bound estimation using the cornish-fisher expansion.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(9):1457-1461, September 2012.
- [1318]
- F. Filippetti
and M. Artioli.
Ime: 4-term formula method for the symbolic analysis of linear circuits.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(3):526-538, March 2004.
- [1319]
- S. Fine, S. Ur, and
A. Ziv.
Probabilistic regression suites for functional verification.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 49-54,
San Diego, CA, June 7-11 2004.
- [1320]
- M. S. Finkelstein.
On the exponential formula for reliability.
IEEE Transactions on Reliability, 53(2):265-268, July 2004.
- [1321]
- J. Finn, P. Nuzzo,
and A. Sangiovanni-Vincentelli.
A mixed discrete-continuous optimization scheme for cyber-physical system
architecture exploration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 216-223, Austin TX, November 2-6 2015.
- [1322]
- F. Firouzi,
S. Kiamehr, and M. B. Tahoori.
Power-aware minimum NBTI vector selection using a linear programming
approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):100-110, January 2013.
- [1323]
- A. H. Fischer,
A. Abel, M. Lepper, A. E. Zitzelsberger, and A. von Glasgow.
Experimental data and statistical models for bimodal EM failures.
In Annual International Reliability Physics Symposium, pages 359-363,
San Jose, CA, April 10-13 2000.
- [1324]
- M. Fischer and H. K.
Dirks.
Multigranular parallel algorithms for solving linear equations in VLSI
circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):728-736, May 2004.
- [1325]
- J. P. Fishburn and
C. A. Schevon.
Shaping a distributed-RC line to minimize elmore delay.
IEEE Transactions on Circuits and Systems I, 42(12):1020-1022,
December 1995.
- [1326]
- C. Fisher,
R. Blankenship, J. Jensen, T. Rossman, and K. Svilich.
Optimization of standard cell libraries for low power, high speed, or minimal
area designs.
In IEEE 1996 Custom Integrated Circuits Conference, pages 493-496,
San Diego, CA, May 5-8 1996.
- [1327]
- M. P. Flynn and J.-J. Kang.
Global signaling over lossy transmission lines.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 985-992, San Jose, CA, November 6-10 2005.
- [1328]
- M. Foltin,
B. Foutz, and S. Tyler.
Efficient stimulus-independent timing abstraction model based on a new concept
of circuit block transparency.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
158-163, New Orleans, LA, June 10-14 2002.
- [1329]
- N. Fong, N. Wong,
Q. Wang, H. Liu, and Y. Zhang.
Fast nonlinear model order reduction via associated transforms of high-order
volterra transfer functions.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
289-294, San Francisco, CA, June 3-7 2012.
- [1330]
- R. A. Fonseca,
L. Dilillo, A. Bosio1, P. Girard, S. Pravossoudovitch, A. Virazel, and
N. Badereddine.
A statistical simulation method for reliability analysis of SRAM core-cells.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
853-856, Anaheim, CA, June 13-18 2010.
- [1331]
- E. A. Foreman,
P. A. Habitz, M.-C. Cheng, and C. Tamon.
Inclusion of chemical-mechanical polishing variation in statistical static
timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(11):1758-1762, November 2011.
- [1332]
- E. A. Foreman,
P. A. Habitz, M.-C. Cheng, and C. Visweswariah.
A novel method for reducing metal variation with statistical static timing
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(8):1293-1297, August 2012.
- [1333]
- W. Fornaciari, P. Gubian, D. Suito, and C. Silvano.
Power estimation of embedded systems: A hardware/software codesign approach.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(2):266-275, June 1998.
- [1334]
- G. E. Forsythe and
R. A. Leibler.
Matrix inversion by a monte carlo method.
Mathematical Tables and Other Aids to Computation, (4):127-129,
1950.
- [1335]
- H. D. Foster.
Why the design productivity gap never happened.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 581-584, San Jose, CA, November 18-21 2013.
- [1336]
- R. Fraer,
G. Kamhi, and M. K. Mhameed.
A new paradigm for synthesis and propagation of clock gating conditions.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
658-663, Anaheim, CA, June 8-13 2008.
- [1337]
- D. J. Frank,
R. Puri, and D. Roma.
Design and CAD challenges in 45nm CMOS and beyond.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 329-333, San Jose, CA, November 5-9 2006.
- [1338]
- A. T. Freitas and
A. L. Oliveira.
Circuit partitioning techniques for power estimation using the full set of
input correlations.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 903-907, St. Julian, Malta, September 2-5 2001.
- [1339]
- R. S. French,
M. S. Lam, J. R. Levitt, and K. Olukotun.
A general method for compiling event-driven simulations.
In 32nd Design Automation Conference, pages 151-156, San Francisco,
CA, June 12-16 1995.
- [1340]
- J. Frenkil.
Issues and directions in low power design tools: an industrial perspective.
In 1997 International Symposium on Low Power Electronics and Design,
pages 152-157, Monterey, CA, August 18-20 1997.
- [1341]
- J. Frenkil.
Tools and methodologies for low power design.
In 34th Design Automation Conference, pages 76-81, Anaheim, CA, June
9-13 1997.
- [1342]
- R. W. Freund and
P. Feldmann.
Efficient small-signal circuit analysis and sensitivity computations with the
PVL algorithm.
In IEEE/ACM International Conference on Computer-Aided Design, pages
404-411, San Jose, CA, November 6-10 1994.
- [1343]
- R. W. Freund and
P. Feldmann.
Reduced-order modeling of large passive linear circuits by means of the sypvl
algorithm.
In IEEE/ACM International Conference on Computer-Aided Design, pages
280-287, San Jose, CA, November 10-14 1996.
- [1344]
- R. W. Freund.
Passive reduced-order models for interconnect simulation and their computation
via krylov-subspace algorithms.
In Design Automation Conference, pages 195-200, New Orleans, LA, June
21-25 1999.
- [1345]
- R. W. Freund.
SPRIM: structure-preserving reduced-order interconnect macromodeling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 80-87, San Jose, CA, November 7-11 2004.
- [1346]
- R. Fried.
Termination circuits for reducing reflections and crosstalk.
IEEE Transactions on Circuits and Systems I, 42(12):1017-1020,
December 1995.
- [1347]
- J. S.
Friedman, L. E. Calvet, P. Bessiere, J. Droulez, and D. Querlioz.
Bayesian inference with muller C-elements.
IEEE Transactions on Circuits and Systems, 63(6):895-904, June
2016.
- [1348]
- S. J. Friedman and
K. J. Supowit.
Finding the optimal variable ordering for binary decision diagrams.
IEEE Transactions on Computers, 39(5):710-713, May 1990.
- [1349]
- D. F. Frost, K. F.
Poole, and D. A. Haeussler.
RELIANT: a reliability analysis tool for VLSI interconnects.
In IEEE 1988 Custom Integrated Circuits Conference, pages
27.8.1-27.8.4, Rochester, NY, May 16-19 1988.
- [1350]
- D. F. Frost and K. F.
Poole.
A method for predicting VLSI-device reliability using series models for
failure mechanisms.
IEEE Transactions on Reliability, R-36(2):234-242, June 1987.
- [1351]
- F. Frustaci,
M. Alioto, and P. Corsonello.
Tapered-vth approach for energy-efficient CMOS buffers.
IEEE Transactions on Circuits and Systems, 58(11):2698-2707, November
2011.
- [1352]
- Y. Fu, R. Panda,
B. Reschke, S. Sundareswaran, and M. Zhao.
A novel technique for incremental analysis of on-chip power distribution
networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 817-823, San Jose, CA, November 5-8 2007.
- [1353]
- M. Fujita,
H. Fujisawa, and N. Kawato.
Evaluation and improvements of boolean comparison method based on binary
decision diagrams.
In IEEE International Conference on Computer-Aided Design, pages 2-5,
Santa Clara, CA, Nov. 7-10 1988.
- [1354]
- M. Fujita,
Y. Matsunaga, and T. Kakuda.
Automatic and semi-automatic verification of switch-level circuits with
temporal logic and binary decision diagrams.
In IEEE International Conference on Computer-Aided Design (ICCAD),
pages 38-41, Santa Clara, CA, Nov. 11-15 1990.
- [1355]
- H. Fujiwara,
K. Nii, J. Miyakoshi, Y. Murachi, Y. Morita, H. Kawaguchi, and M. Yoshimoto.
A two-port SRAM for real-time video processor saving 53% of bitline power
with majority logic and data-bit reordering.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 61-66, Tegernsee, Germany, October 4-6 2006.
- [1356]
- H. Fujiwara and
T. Shimono.
On the acceleration of test generation algorithms.
IEEE Transactions on Computers, C-32(12):1137-1144, December 1983.
- [1357]
- Hideo Fujiwara.
Logic Testing and Design for Testability.
The MIT Press, Cambridge, MA, 1985.
- [1358]
- H. Fuketa,
M. Hashimoto, Y. Mitsuyama, and T. Onoye.
Transistor variability modeling and its validation with ring-oscillation
frequencies for body-biased subthreshold circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(7):1118-1129, July 2010.
- [1359]
- H. Fuketa,
M. Hashimoto, Y. Mitsuyama, and T. Onoye.
Adaptive performance compensation with in-situ timing error predictive sensors
for subthreshold circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):333-343, February 2012.
- [1360]
- E. Gad, M. Nakhla,
R. Achar, and Y. Zhou.
A-stable and L-stable high-order integration methods for solving stiff
differential equations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(9):1359-1372, September 2009.
- [1361]
- M. Gaggero,
M. Parodi, and M. Storace.
Multiresolution PWL approximations.
In European Conference on Circuit Theory and Design (ECCTD), pages
III.393-III.396, Cork, Ireland, August 29 - September 2 2005.
- [1362]
- S. Gai, A. Lioy, and
P. L. Montessoro.
An accurate timing model for gate-level simulation of MOS circuits.
In IEEE International Symposium on Circuits and Systems, pages
2403-2406, June 1991.
- [1363]
- L. Gal.
On-chip cross talk - the new signal integrity challenge.
In IEEE Custom Integrated Circuits Conference, pages 251-254, Santa
Clara, CA, May 1-4 1995.
- [1364]
- K. Gala, V. Zolotov,
R. Panda, B. Young, J. Want, and D. Blaauw.
On-chip inductance modeling and analysis.
In Design Automation Conference, pages 63-68, Los Angeles, CA, June
5-9 2000.
- [1365]
- K. Gala, D. Blaauw,
J. Wang, V. Zolotov, and M. Zhao.
Inductance 101: Analysis and design issues.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
329-334, Las Vegas, NV, June 18-22 2001.
- [1366]
- K. Gala, D. Blaauw,
V. Zolotov, P. M. Vaidya, and A. Joshi.
Inductance model and analysis methodology for high-speed on-chip interconnect.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):730-745, December 2002.
- [1367]
- J. Galambos.
The Asymptotic Theory of Extreme Order Statistics.
Krieger, Melbourne, FL, 1987.
- [1368]
- M. Galceran-Oms, J. Cortadella, and M. Kishinevsky.
Speculation in elastic systems.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
292-295, San Francisco, CA, July 26-31 2009.
- [1369]
- J. Galiay,
Y. Crouzet, and M. Vergniault.
Physical versus logical fault models in MOS LSI circuits, impact on their
testability.
In IEEE International Symposium on Fault Tolerant Computing, pages
195-202, Madison, WI, June 20-22 1979.
- [1370]
- M. Gall, P. S. Ho,
C. Capasso, D. Jawarani, R. Hernandez, and H. Kawasaki.
Electromigration early failure distribution in submicron interconnects.
In Stress Induced Phenomena in Metallization Workshop, pages 3-14,
Stuttgart, 1999.
- [1371]
- H. Gan, Q. He, and
D. Jiao.
Hierarchical and adaptive finite-element reduction-recovery method for
large-scale power and signal integrity analysis of high-speed IC and
packaging structures.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 127-130, San Jose, CA, October 27-29 2008.
- [1372]
- M. J. Gander,
M. Al-Khaleel, and A. E. Ruehli.
Optimized waveform relaxation methods for longitudinal partitioning of
transmission lines.
IEEE Transactions on Circuits and Systems, 56(8):1732-1743, August
2009.
- [1373]
- M. J. Gander and A. E.
Ruehli.
Optimized waveform relaxation methods for RC type circuits.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(4):755-768, April 2004.
- [1374]
- R. Gandikota, K. Chopra, D. Blaauw, D. Sylvester, and M. Becer.
Top-k aggressors set in delay noise analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 124-129, Austin,
Texas, February 26-27 2007.
- [1375]
- R. Gandikota, K. Chopra, D. Blaauw, D. Sylvester, and M. Becer.
Top-k aggressors sets in delay noise analysis.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
174-179, San Diego, CA, June 4-8 2007.
- [1376]
- R. Gandikota, K. Chopra, D. Blaauw, D. Sylvester, M. Becer, and
J. Geada.
Victim alignment in crosstalk aware timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 698-704, San Jose, CA, November 5-8 2007.
- [1377]
- R. Gandikota, D. Blaauw, and D. Sylvester.
Modeling corsstalk in statistical static timing analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 86-91, Monterey, CA,
February 25-26 2008.
- [1378]
- R. Gandikota, D. Blaauw, and D. Sylvester.
Modeling crosstalk in statistical static timing analysis.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
974-979, Anaheim, CA, June 8-13 2008.
- [1379]
- R. Gandikota, L. Ding, P. Tehrani, and D. Blaauw.
Worst-case aggressor-victim alignment with current-source driver models.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 13-18,
San Francisco, CA, July 26-31 2009.
- [1380]
- R. Gandikota, K. Chopra, D. Blaauw, and D. Sylvester.
Victim alignment in crosstalk-aware timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(2):261-274, February 2010.
- [1381]
- F. R. Gantmacher.
The Theory of Matrices, volume 1 and 2.
Chelsea Publishing Company, New York, NY, 1860.
- [1382]
- F. R. Gantmacher.
Applications of the Theory of Matrices.
Interscience Publishers, Inc., New York, NY, 1959.
- [1383]
- X. F. Gao, J. J. Liou,
J. Bernier, G. Croft, and A. Ortiz-Conde.
Implementation of a comprehensive and robust MOSFET model in cadence SPICE
for ESD applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(12):1497-1502, December 2002.
- [1384]
- M. Gao, Z. Ye,
Y. Wang, and Z. Yu.
Efficient tail estimation for massive correlated log-normal sums - with
applications in statistical leakage analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
475-480, Anaheim, CA, June 13-18 2010.
- [1385]
- M. Gao, Z. Ye,
Y. Wang, and Z. Yu.
Efficient full-chip statistical leakage analysis based on fast matrix vector
product.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(3):356-369, March 2012.
- [1386]
- F. Gao and J. P. Hayes.
ILP-based optimization of sequential circuits for low power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 140-145, Seoul, Korea, August 25-27 2003.
- [1387]
- F. Gao and J. P. Hayes.
Exact and heuristic approaches to input vector control for leakage power
reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 527-532, San Jose, CA, November 7-11 2004.
- [1388]
- F. Gao and J. P. Hayes.
Total power reduction in CMOS circuits via gate sizing and multiple threshold
voltages.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 31-36,
Anaheim, CA, June 13-17 2005.
- [1389]
- F. Gao and J. P. Hayes.
Exact and heuristic approaches to input vector control for leakage power
reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2564-2571, November 2006.
- [1390]
- A. Garcia, L. D.
Kabulepa, and M. Glesner.
Efficient estimation of signal transition activity in MAC architecture.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 319-322, Monterey, California, August 12-14 2002.
- [1391]
- A. Garcia-Ortiz, L. Kabulepa, T. Murgan, and M. Glesner.
Moment-based power estimation in very deep submicron technologies.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 107-112, San Jose, CA, November 9-13 2003.
- [1392]
- D. S. Gardner,
J. D. Meindl, and K. Saraswat.
Interconnection and electromigration scaling theory.
Submitted to T. Electron Devices, March-87, March 1987.
TI circulation from D. Hocevar.
- [1393]
- M. R. Garey and D. S.
Johnson.
Approximation algorithms for combinatorial problems : an annotated
bibliography.
In J. F. Traub, editor, Algorithms and Complexity, pages 41-52.
Academic Press, Inc., New York, NY, 1976.
- [1394]
- Michael R. Garey and
David S. Johnson.
Computers and Intractability, A Guide to the Theory of
NP-Completeness.
W. H. Freeman and Company, San Fransicso, CA, 1979.
- [1395]
- R. Garg, C. Nagpal,
and S. Khatri.
A fast analytical estimator for the SEU-induced pulse width in combinational
designs.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 128-133, Monterey, CA,
February 25-26 2008.
- [1396]
- S. Garg,
D. Marculescu, and S. X. Herbert.
Process variation aware performance modeling and dynamic power management for
multi-core systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 89-92, San Jose, CA, November 7-11 2010.
- [1397]
- S. Garg and
D. Marculescu.
Mitigating the impact of process variation on the performance of 3-D
integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1903-1914, October 2013.
- [1398]
- V. Garg.
Common path pessimism removal: an industry perspective.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 592-595, San Jose, CA, November 2-6 2014.
- [1399]
- M. Garland.
Sparse matrix computations on manycore GPU's.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages 2-6,
Anaheim, CA, June 8-13 2008.
- [1400]
- A. Gattiker,
S. Nassif, R. Dinakar, and C. Long.
Timing yield estimation from static timing analysis.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 437-442, San Jose, CA, March 26-28 2001.
- [1401]
- A. Gattiker.
Using test data to improve IC quality and yield.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 771-777, San Jose, CA, November 10-13 2008.
- [1402]
- A. Gattiker.
System-level impact of chip-level failure mechanisms and screens.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 173-176, San Jose, CA, November 7-11 2010.
- [1403]
- C. Gebotys and R. J.
Gebotys.
An empirical comparison of algorithmic, instruction, and architectural power
prediction models for high performance embedded DSP processors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 121-123, Monterey, CA, August 10-12 1998.
- [1404]
- C. H. Gebotys.
Low energy memory and register allocation using network flow.
In 34th Design Automation Conference, pages 435-440, Anaheim, CA,
June 9-13 1997.
- [1405]
- A. Gebregiorgis, M. Ebrahimi, S. Kiamehr, F. Oboril,
S. Hamdioui, and M. B. Tahoori.
Aging mitigation in memory arrays using self-controlled bit-flipping technique.
In 20th Asia and South Pacific Design Automation Conference, pages
231-236, Chiba/Tokyo, Japan, January 19-22 2015.
- [1406]
- P. P. Gelsinger.
Microprocessors for the new millennium: challenges, opportunities, and new
frontiers.
In IEEE International Solid-State Circuits Conference (ISSCC), pages
22-25, 2001.
- [1407]
- H. Geng, J. Wu,
J. Liu, M. Choi, and Y. Shi.
Utilizing random noise in cryptography: where is the tofu?
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 163-167, San Jose, CA, November 5-8 2012.
- [1408]
- Y. Geng, H. Zou,
C. Li, J. Sun, H. Wang, and P. Wang.
Short pulse generation with on-chip pulse-forming lines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(9):1553-1564, September 2012.
- [1409]
- G. Georgakos, U. Schlichtmann, R. Schneider, and S. Chakraborty.
Reliability challenges for electric vehicles: from devices to architecture and
systems software.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1410]
- B. J. George,
G. Yeap, M. G. Wloka, S. C. Tyler, and D. Gossain.
Power analysis and characterization for semi-custom design.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
215-218, Napa, CA, April 24-27 1994.
- [1411]
- B. J. George,
G. Yeap, M. G. Wloka, S. C. Tyler, and D. Gossain.
Power analysis for semi-custom design.
In IEEE 1994 Custom Integrated Circuit Conference, pages 249-252, San
Diego, CA, May 1-4 1994.
- [1412]
- V. George,
H. Zhang, and J. Rabaey.
The design of a low energy FPGA.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 188-193, San Diego, CA, August 16-17 1999.
- [1413]
- A. George and J. W-H. Liu.
Computer solution of large sparse positive definite systems.
Prentice-Hall, Inc., Englewood Cliffs, NJ 07632, 1981.
- [1414]
- D. George.
How to make computers that work like the brain.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
420-423, San Francisco, CA, July 26-31 2009.
- [1415]
- J. Gergov and
C. Meinel.
Efficient boolean manipulation with OBDD's can be extended to FBDD's.
IEEE Transactionson Computers, 43(10):1197-1209, October 1994.
- [1416]
- A. Gerstlauer, J. Peng, D. Shin, D. Gajski, A. Nakamura,
D. Araki, and Y. Nishihara.
Specify-explore-refine (SER): from specification to implementation.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
586-591, Anaheim, CA, June 8-13 2008.
- [1417]
- G. Ghai and J. Mi.
Mean residual life and its association with failure rate.
IEEE Transactions on Reliability, 48(3):262-266, September 1999.
- [1418]
- R. S. Ghaida,
K. B. Agarwal, S. R. Nassif, X. Yuan, L. W. Liebmann, and P. Gupta.
A framework for double patterning-enabled design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 14-20, San Jose, CA, November 7-10 2011.
- [1419]
- N. H. Abdul Ghani and F. N.
Najm.
Handling inductance in early power grid verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 127-134, San Jose, CA, November 5-9 2006.
- [1420]
- N. H. Abdul Ghani and F. N.
Najm.
Fast vectorless power grid verification using an approximate inverse technique.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
184-189, San Francisco, CA, July 26-31 2009.
- [1421]
- N. Abdul Ghani and F. N.
Najm.
Power grid verification using node and branch dominance.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
682-687, San Diego, CA, June 5-9 2011.
- [1422]
- N. H. Abdul Ghani and
F. N. Najm.
Fast vectorless power grid verification under an RLC model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(5):691-703, May 2011.
- [1423]
- N. H. Abdul Ghani and
F. N. Najm.
Fast vectorless power grid verification under an RLC model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(5):691-703, May 2011.
- [1424]
- P. Ghanta,
S. Vrudhula, S. Bhardwaj, and R. Panda.
Stochastic variational analysis of large power grids considering intra-die
correlations.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
211-216, San Francisco, CA, July 24-28 2006.
- [1425]
- R. Gharpurey and
R. G. Meyer.
Modeling and analysis of substrate coupling in integrated circuits.
In IEEE Custom Integrated Circuits Conference, pages 125-128, Santa
Clara, CA, May 1-4 1995.
- [1426]
- M. Ghasemazar
and M. Pedram.
Minimizing the energy cost of throughput in a linear pipeline by opportunistic
time borrowing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 155-160, San Jose, CA, November 10-13 2008.
- [1427]
- M. S. Ghausi and J. J.
Kelly.
Introduction to distributed-parameter networks.
R. E. Krieger Pub. Co., 1968.
- [1428]
- S. Ghiasi,
E. Bozorgzadeh, S. Choudhuri, and M. Sarrafzadeh.
A unified theory of timing budget management.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 653-659, San Jose, CA, November 7-11 2004.
- [1429]
- S. Ghiasi,
E. Bozorgzadeh, P.-K. Huang, R. Jafari, and M. Sarrafzadeh.
A unified theory of timing budget management.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2364-2375, November 2006.
- [1430]
- M. A. Ghodrat,
K. Lahiri, and A. Raghunathan.
Accelerating system-on-chip power analysis using hybrid power estimation.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
883-886, San Diego, CA, June 4-8 2007.
- [1431]
- M. Ghoeima and Y. I.
Ismail.
Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 66-69, Newport Beach, CA, August 9-11 2004.
- [1432]
- M. Ghoneima, Y. I. Ismail, M. Khellah, J. Tschanz, and V. De.
Serial-link bus: a low-power on-chip bus architecture.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 541-546, San Jose, CA, November 6-10 2005.
- [1433]
- M. Ghoneima, Y. I. Ismail, M. M. Khellah, J. W. Tschanz, and
V. De.
Formal derivation of optimal active shielding for low-power on-chip buses.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):821-836, May 2006.
- [1434]
- M. Ghoneima, Y. I. Ismail, M. M. Khellah, J. W. Tschanz, and
V. De.
Reducing the effective coupling capacitance in buses using threshold voltage
adjustment techniques.
IEEE Transactions on Circuits and Systems, 53(9):1928-1933, September
2006.
- [1435]
- M. Ghoneima and
Y. I. Ismail.
Optimum positioning of interleaved repeaters in bidirectional buses.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
586-591, Anaheim, CA, June 2-6 2003.
- [1436]
- M. Ghoneima and
Y. I. Ismail.
Formal derivation of optimal active shielding for low-power on-chip buses.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 800-807, San Jose, CA, November 7-11 2004.
- [1437]
- M. Ghoneima and
Y. I. Ismail.
Utilizing the effect of relative delay on energy dissipation in low-power
on-chip buses.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1348-1359, December 2004.
- [1438]
- M. Ghoneima and
Y. I. Ismail.
Optimum positioning of interleaved repeaters in bidirectional buses.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):461-469, March 2005.
- [1439]
- A. Ghosh,
S. Devadas, K. Keutzer, and J. White.
Estimation of average switching activity in combinational and sequential
circuits.
In 29th ACM/IEEE Design Automation Conference, pages 253-259,
Anaheim, CA, June 8-12 1992.
- [1440]
- S. Ghosh,
S. Bhunia, and K. Roy.
A new paradigm for low-power, variation-tolerant circuit synthesis using
critical path isolation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 619-624, San Jose, CA, November 5-9 2006.
- [1441]
- S. Ghosh,
S. Mukhopadhyay, K. Kim, and K. Roy.
Self-calibration technique for reduction of hold failures in low-power
nano-scaled SRAM.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
971-976, San Francisco, CA, July 24-28 2006.
- [1442]
- S. Ghosh,
S. Bhunia, and K. Roy.
CRISTA: A new paradigm for low-power, variation-tolerant, and adaptive
circuit synthesis using critical path isolation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(11):1947-1956, November 2007.
- [1443]
- A. Ghosh, S. Boyd,
and A. Saberi.
Minimizing effective resistance of a graph.
SIAM Review, 50(1):37-66, 2008.
- [1444]
- G. Gielen,
E. Maricau, and P. De Wit.
Design automation towards reliable analog integrated circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 248-251, San Jose, CA, November 7-11 2010.
- [1445]
- J. Gil, M. Je, J. Lee,
and H. Shin.
A high speed and low power SOI inverter using active body-bias.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 59-63, Monterey, CA, August 10-12 1998.
- [1446]
- J. L.
Gilkinson, S. D. Lewis, B. B. Winter, and A. Hekmatpour.
Automated technology mapping.
IBM Journal of Research and Development, 28(5):546-556, September
1984.
- [1447]
- B. S. Gill,
C. Papashristou, and F. G. Wolff.
A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA.
Design, Automation and Test in Europe (DATE-07), pages 1460-1465,
April 16-20 2007.
- [1448]
- Arthur Gill.
Linear Sequential Circuits, Analysis, Synthesis, and Applications.
McGraw-Hill Book Company, New York, NY, 1966.
- [1449]
- B. P.
Ginsburg and A. P. Chandrakasan.
The mixed signal optimum energy point: voltage and parallelism.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
244-249, Anaheim, CA, June 8-13 2008.
- [1450]
- P. Girard,
C. Landrault, S. Pravossoudovitch, and D. Severac.
A gate resising technique for high reduction in power consumption.
In 1997 International Symposium on Low Power Electronics and Design,
pages 281-286, Monterey, CA, August 18-20 1997.
- [1451]
- T. D.
Givargis, J. Henkel, and F. Vahid.
Interface and cache power exploration for core-based embedded system design.
In IEEE/ACM International Conference on Computer-Aided Design, pages
270-273, San Jose, CA, November 7-11 1999.
- [1452]
- T. Givargis, F. Vahid, and J. Henkel.
Instruction-based system-level power evaluation of system-on-a-chip peripheral
cores.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):856-863, December 2002.
- [1453]
- T. Givargis and
F. Vahid.
Platune: A tuning framework for system-on-a-chip platforms.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(11):1317-1327, November 2002.
- [1454]
- E. Gizdarski
and H. Fujiwara.
SPIRIT: A highly robust combinational test generation algorithm.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(12):1446-1458, December 2002.
- [1455]
- M. Glass,
M. Lukasiewycz, C. Haubelt, and J. Teich.
Towards scalable system-level reliability analysis?
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
234-239, Anaheim, CA, June 13-18 2010.
- [1456]
- A. L. Glebov,
D. Blaauw, and L. G. Jones.
Transistor reordering for low power CMOS gates using an SP-BDD
representation.
In ACM/IEEE International Symposium on Low Power Design, pages
161-166, Dana Point, CA, April 23-26 1995.
- [1457]
- A. Glebov,
S. Gavrilov, D. Blaauw, S. Sirichotiyakul, C. Oh, and V. Zolotov.
False-noise analysis using logic implications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 515-521, San Jose, CA, November 4-8 2001.
- [1458]
- A. Glebov,
S. Gavrilov, D. Blaauw, V. Zolotov, R. Panda, and C. Oh.
False-noise analysis using resolution method.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 437-442, San Jose, CA, March 18-21 2002.
- [1459]
- A. Glebov,
S. Gavrilov, R. Soloviev, V. Zolotov, M. R. Becer, C. Oh, and R. Panda.
Delay noise pessimism reduction by logic correlations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 160-167, San Jose, CA, November 7-11 2004.
- [1460]
- C. T. Glover and M. R.
Mercer.
A method of delay fault test generation.
In 25th ACM/IEEE Design Automation Conference, pages 90-95, Anaheim,
CA, June 12-15 1988.
- [1461]
- S. Goel, M. A.
Elgamel, M. A. Bayoumi, and Y. Hanafy.
Design methodologies for high-performance noise-tolerant XOR-XNOR circuits.
IEEE Transactions on Circuits and Systems, 53(4):867-878, April
2006.
- [1462]
- M. Goel and N. R.
Shanbhag.
Low-power adaptive filter architectures via strength reduction.
In International Symposium on Low Power Electronics and Design, pages
217-220, Monterey, CA, August 12-14 1996.
- [1463]
- M. Goel and N. R.
Shanbhag.
Dynamic algorithm transformations (DAT) for low-power adaptive signal
processing.
In 1997 International Symposium on Low Power Electronics and Design,
pages 161-166, Monterey, CA, August 18-20 1997.
- [1464]
- M. Goel and N. R.
Shanbhag.
Dynamic algorithm transformations (DAT) - A systematic approach to
low-power reconfigurable signal processing.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(4):463-476, December 1999.
- [1465]
- A. Goel and S. Vrudhula.
Statistical waveform and current source based standard cell models for accurate
timing analysis.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
227-230, Anaheim, CA, June 8-13 2008.
- [1466]
- P. Goel.
An implicit enumeration algorithm to generate tests for combinational logic
circuits.
IEEE Transactions on Computers, C-30(3):215-222, March 1981.
- [1467]
- S. K. Goel.
Test challenges in designing complex 3d chips: what in on the horizon for EDA
industry?
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 273, San Jose, CA, November 5-8 2012.
- [1468]
- I. C. Goknar,
H. Kutuk, and S.-M. Kang.
MOMCO: Method of moment components for passive model order reduction of
RLCG interconnects.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(4):459-474, April 2001.
- [1469]
- E. I.
Goldberg, T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
Theory and algorithms for face hypercube embedding.
IEEE Transactions on Computer-Aided Design, 17(6):472-488, June
1998.
- [1470]
- E. I.
Goldberg, L. P. Carloni, T. Villa, R. K. Brayton, and A. L.
Sangiovanni-Vincentelli.
Negative thinking in branch-and-bound: the case of unate covering.
IEEE Transactions on Computer-Aided Design, 19(3):281-294, March
2000.
- [1471]
- A. V. Goldberg and
R. E. Tarjan.
A new approach to the maximum flow problem.
In ACM Symposium on the Theory of Computing, pages 136-146, May
1986.
- [1472]
- L. Goldstein.
Controllability/observability analysis of digital circuits.
IEEE Transactions on Circuits and Systems, CAS-26(9):685-693,
September 1979.
- [1473]
- S. C. Goldstein.
The impact of the nanoscale on computing systems.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 655-661, San Jose, CA, November 6-10 2005.
- [1474]
- G. H. Golub and C. F. Van
Loan.
Matrix Computations.
The Johns Hopkins University Press, Baltimore, MD, 3rd edition, 1996.
- [1475]
- M. C. Golumbic and
A. Mintz.
Factoring logic functions using graph partitioning.
In IEEE/ACM International Conference on Computer-Aided Design, pages
195-198, San Jose, CA, November 7-11 1999.
- [1476]
- A. F. Gomez.
Early selection of critical paths for reliable NBTI aging-delay monitoring.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(7):2438-2448, July 2016.
- [1477]
- M. Gong, H. Zhou,
J. Tao, and X. Zeng.
Binning optimization based on SSTA for transparently-latched circuits  .
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 328-335, San Jose, CA, November 2-5 2009.
- [1478]
- F. Gong, H. Yu,
Y. Shi, D. Kim, J. Ren, and L. He.
Quickyield: an efficient global-search based parametric yield estimation with
performance constraints.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
392-397, Anaheim, CA, June 13-18 2010.
- [1479]
- M. Gong, H. Zhou,
L. Li, J. Tao, and X. Zeng.
Binning optimization for transparently-latched circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(2):270-283, February 2011.
- [1480]
- F. Gong, H. Yu,
L. Wang, and L. He.
A parallel and incremental extraction of variational capacitance with
stochastic geometric moments.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(9):1729-1737, September 2012.
- [1481]
- F. Gong,
S. Basir-Kazeruni, L. He, and H. Yu.
Stochastic behavioral modeling and analysis for analog/mixed-signal circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):24-33, January 2013.
- [1482]
- N. Gong, J. Wang,
and R. Sridhar.
Variation aware sleep vector selection in dual vt dynamic or circuits for low
leakage register file design.
IEEE Transactions on Circuits and Systems, 61(7):1970-1983, July
2014.
- [1483]
- W.-B. Gong and H. Yang.
Rational approximants for some performance analysis problems.
IEEE Transactions on Computers, 44(12):1394-1404, December 1995.
- [1484]
- R. Gonzalez and
M. Horowitz.
Energy dissipation in general purpose microprocessors.
IEEE Journal of Solid-State Circuits, 31(9):1277-1284, September
1996.
- [1485]
- J. Goodenough
and R. Aitken.
Post-silicon is too late avoiding the 50 million paperweight starts with
validated designs.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages 8-11,
Anaheim, CA, June 13-18 2010.
- [1486]
- N. Gopal, D. P.
Neikirk, and L. T. Pillage.
Evaluating RC-interconnect using moment-matching approximations.
In IEEE International Conference on Computer-Aided Design, pages
74-77, Santa Clara, CA, November 11-14 1991.
- [1487]
- N. Gopal, C. L.
Ratzlaff, and L. T. Pillage.
Constrained approximation of dominant time constant(s) in RC circuit delay
models.
13th IMACS World Congress on Computation and Applied Mathematics,
pages ?--?, July 22-26 1991.
- [1488]
- P. Gopalakrishnan, A. Odabasioglu, L. Pileggi, and S. Raje.
An analysis of the wire-load model uncertainty problem.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(1):23-31, January 2002.
- [1489]
- B. Goplen and
S. Sapatnekar.
Efficient thermal placement of standard cells in 3d ics using a force directed
approach.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 86-89, San Jose, CA, November 9-13 2003.
- [1490]
- C. Gordon,
T. Blazeck, and R. Mittra.
Time-domain simulation of multiconductor transmission lines with
frequency-dependent losses.
IEEE Transactions on Computer-Aided Design, 11(11):1372-1387,
November 1992.
- [1491]
- W. Gosti,
A. Narayan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
Wireplanning in logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
26-33, San Jose, CA, November 8-12 1998.
- [1492]
- E. Goto, K. Murata,
K. Nakazawa, K. Nakagawa, T. Moto-Oka, Y. Matsuoka, Y. Ishibashi, H. Ishida,
T. Soma, and E. Wada.
Esaki diode high-speed logical circuits.
IRE Transactions on Electronic Computers, pages 25-29, March 1960.
- [1493]
- E. Gourdin,
P. Hansen, and B. Jaumard.
Finding maximum likelihood estimators for the three-parameter weibull
distribution.
Journal of Global Optimization, 5:373-397, 1994.
- [1494]
- N. C. Gov, M. K.
Mihcak, and S. Eurgun.
True random number generation via sampling from flat band-limited gaussian
process.
IEEE Transactions on Circuits and Systems, 58(5):1044-1051, May
2011.
- [1495]
- M. K. Gowan, L. L.
Biro, and D. B. Jackson.
Power considerations in the design of the alpha 21264 microprocessor.
In IEEE/ACM 35th Design Automation Conference, pages 726-731, San
Francisco, CA, June 15-19 1998.
- [1496]
- A. Goyal and F. N. Najm.
Efficient RC power grid verification using node elimination.
Design, Automation and Test in Europe (DATE-11), pages 257-260, March
14-18 2011.
- [1497]
- H. E. Graeb, C. U.
Wieser, and K. J. Antreich.
Improved methods for worst-case analysis and optimization incorporating
operating tolerances.
In 30th ACM/IEEE Design Automation Conference, pages 142-147, Dallas,
TX, June 14-18 1993.
- [1498]
- P. Gray and R. Meyer.
Analysis and Design of Analog Integrated Circuits.
John Wiley and Sons, New York, NY, 1984.
- [1499]
- C. Grecu, P. P.
Pande, A. Ivanov, and R. Saleh.
A scalable communication-centric soc interconnect architecture.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 343-350, San Jose, CA, March 22-24 2004.
- [1500]
- S. Greenberg, J. Rabinowicz, R. Tsechanski, and E. Paperno.
Selective state retention power gating based on gate-level analysis.
IEEE Transactions on Circuits and Systems, 61(4):1095-1104, April
2014.
- [1501]
- J. Gregg and T.-W. Chen.
Post silicon power/performance optimization in the presence of process
variations using individual well adaptive body biasing (IWABB).
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 453-458, San Jose, CA, March 22-24 2004.
- [1502]
- W. P. Griffin and
K. Roy.
CLIP: circuit level IC protection through direct injection of process
variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(5):791-803, May 2012.
- [1503]
- R. Griffith and
M. Nakhla.
A new high-order absolutely-stable explicit numerical integration algorithm for
the time-domain simulation of nonlinear circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
276-280, San Jose, CA, November 9-13 1997.
- [1504]
- S. Grivet-Talocia.
Passivity enforcement via perturbation of hamiltonian matrices.
IEEE Transactions on Circuits and Systems, 51(9):1755-1769, September
2004.
- [1505]
- E. Grochowski, D. Ayers, and V. Tiwari.
Microarchitectural di/dt control.
IEEE Design & Test of Computers, pages 40-47, May-June 2003.
- [1506]
- J. Grodstein, E. Lehman, H. Harkness, B. Grundmann, and
Y. Watanabe.
A delay model for logic synthesis of continuously-sized networks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
458-462, San Jose, CA, November 5-9 1995.
- [1507]
- P. D. Gross,
R. Arunachalam, K. Rajagopal, and L. T. Pileggi.
Determination of worst-case aggressor alignment for delay calculation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
212-219, San Jose, CA, November 8-12 1998.
- [1508]
- E. Grossar,
J. Croon, M. Stucchi, W. Dehaene, and K. Maex.
A yield-aware modeling methodology for nano-scaled SRAM designs.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 33-36, Austin, TX, May 9 - 11 2005.
- [1509]
- M. J. Grote and
T. Huckle.
Parallel preconditioning with sparse approximate inverses.
SIAM Journal on Scientific Computing, 18(3):838-853, May 1997.
- [1510]
- T. Grund,
P. Christie, and M. D. Butala.
Web-based tools for system-level interconnect prediction.
In Workshop on System-Level Interconnect Prediction, Monterey, CA,
April 10-11 1999.
- [1511]
- W. J.
Grundmann, D. Dobberpuhl, R. L. Allmon, and N. L. Rethman.
Designing high performance CMOS microprocessors using full custom techniques.
In 34th Design Automation Conference, pages 722-727, Anaheim, CA,
June 9-13 1997.
- [1512]
- J. Gu, J. Keane, and
C. Kim.
Modeling and analysis of leakage induced damping effect in low voltage lsis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 382-387, Tegernsee, Germany, October 4-6 2006.
- [1513]
- J. Gu, H. Eom, and
C.-H. Kim.
Sleep transistor sizing and control for resonant supply noise damping.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 80-85, Portland, Oregon, August 27-29 2007.
- [1514]
- J. Gu, S. S.
Sapatnekar, and C. Kim.
Width-dependent statistical leakage modeling for random dopant induced
threshold voltage shift.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 87-92,
San Diego, CA, June 4-8 2007.
- [1515]
- J. Gu, J. Keane,
S. Sapatnekar, and C. H. Kim.
Statistical leakage estimation of double gate finfet devices considering the
width quantization property.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(2):206-209, February 2008.
- [1516]
- J. Gu, R. Harjani, and
C. H. Kim.
Design and implementation of active decoupling capacitor circuits for power
supply regulation in digital ics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):292-301, February 2009.
- [1517]
- J. Gu, J. Keane, and
C.-H. Kim.
Modeling, analysis and application of leakage induced damping effect of power
supply integrity.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(1):128-136, January 2009.
- [1518]
- C. Gu, E. Chiprout, and
X. Li.
Efficient moment estimation with extremely small sample size via bayesian
inference for analog/mixed-signal validation.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1519]
- Y. Gu and S. Chakraborty.
Control theory-based DVS for interactive 3d games.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
740-745, Anaheim, CA, June 8-13 2008.
- [1520]
- R. X. Gu and M. I. Elmasry.
Power dissipation analysis and optimization of deep submicron CMOS digital
circuits.
IEEE Journal of Solid-State Circuits, 31(5):707-713, May 1996.
- [1521]
- J. Gu and C.-H. Kim.
Multi-story power delivery for supply noise reduction and low voltage
operation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 192-197, San Diego, CA, August 8-10 2005.
- [1522]
- C. Gu and
J. Roychowdhury.
Model reduction via projection onto nonlinear manifolds, with applications to
analog circuits and biochemical systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 85-92, San Jose, CA, November 10-13 2008.
- [1523]
- C. Gu and
J. Roychowdhury.
Generalized nonlinear timing/phase macromodeling: theory, numerical methods and
applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 284-291, San Jose, CA, November 7-11 2010.
- [1524]
- C. Gu.
QLMOR: a new projection-based approach for nonlinear model order reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 389-396, San Jose, CA, November 2-5 2009.
- [1525]
- C. Gu.
QLMOR: a projection-based nonlinear model order reduction approach using
quadratic-linear representation of nonlinear systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(9):1307-1320, September 2011.
- [1526]
- C. Gu.
Challenges in post-silicon validation of high-speed I/O links.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 547-550, San Jose, CA, November 5-8 2012.
- [1527]
- S.-U. Guan,
S. Zhang, and M. T. Quieta.
2-D CA variation with asymmetric neighborship for pseudorandom number
generation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(3):378-388, March 2004.
- [1528]
- Z. Guan and
M. Marek-Sadowska.
An efficient and accurate algorithm for computing RC current response with
applications to EM reliability evaluation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [1529]
- C. Guardiani, A. Macii, E. Macii, M. Poncino, M. Rossello,
R. Scarsi, C. Silvano, and R. Zafalon.
RTL power estimation in an industrial design flow.
In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages
91-96, Como, Italy, March 4-5 1999.
- [1530]
- C. Guardiani, S. Saxena, P. McNamara, P. Schumaker, and
D. Coder.
An assymptotically constant, linearly bounded methodology for the statistical
simulation of analog circuits including component mismatch effects.
In Design Automation Conference, pages 15-18, Los Angeles, CA, June
5-9 2000.
- [1531]
- C. Guardiani, M. Bertoletti, N. Dragone, M. Malcotti, and
P. McNamara.
An effective DFM strategy requires accurate process and IP
pre-characterization.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
760-761, Anaheim, CA, June 13-17 2005.
- [1532]
- N. Guilar,
A. Chen, T. Kleeburg, and R. Amirtharajah.
Integrated solar energy harvesting and storage.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 20-24, Tegernsee, Germany, October 4-6 2006.
- [1533]
- R. S. Guindi,
R. C. Kordasiewicz, and F. N. Najm.
Optimization technique for FB/TB assignment in PD-SOI digital CMOS
circuits.
In The First Annual Northeast Workshop on Circuits and Systems
(NEWCAS-03), pages 157-160, Montreal, Quebec, June 17-20 2003.
- [1534]
- R. S. Guindi and F. N.
Najm.
Design techniques for gate-leakage reduction in CMOS circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 61-65, San Jose, CA, March 24-26 2003.
- [1535]
- K. Gulati,
N. Jayakumar, and S. P. Khatri.
An algebraic decision diagram (ADD) based technique to find leakage
histograms of combinational designs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 111-114, San Diego, CA, August 8-10 2005.
- [1536]
- U. Guler and G. Dundar.
Modeling CMOS ring oscillator performance as a randomness source.
IEEE Transactions on Circuits and Systems, 61(3):712-724, March
2014.
- [1537]
- R. Guo, S. M. Reddy,
and I. Pomeranz.
PROPTEST: a property-based test generator for synchronous sequential
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(8):1080-1091, August 2003.
- [1538]
- W. Guo, Y. Zhong, and
T. Burd.
Context-sensitive static transistor-level IR analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 797-803, San Jose, CA, November 10-13 2008.
- [1539]
- Q. Guo, T. Chen,
Y. Chen, and F. Franchetti.
Accelerating architectural simulation via statistical techniques: a survey.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(3):433-446, March 2016.
- [1540]
- R. Gupta,
B. Krauter, B. Tutuianu, J. Willis, and L. T. Pileggi.
The elmore delay as a bound for RC trees with generalized input signals.
In 32nd Design Automation Conference, pages 364-369, San Francisco,
CA, June 12-16 1995.
- [1541]
- R. Gupta,
B. Tutuianu, and L. T. Pileggi.
The elmore delay as a bound for RC trees with generalized input signals.
IEEE Transactions on Computer-Aided Design, 16(1):95-104, January
1997.
- [1542]
- R. Gupta,
J. Willis, and L. T. Pileggi.
Analytic termination metrics for pin-to-pin lossy transmission lines with
nonlinear drivers.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(3):457-463, September 1998.
- [1543]
- P. Gupta,
L. Zhong, and N. K. Jha.
A high-level interconnect power model for design space exploration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 551-558, San Jose, CA, November 9-13 2003.
- [1544]
- P. Gupta, A. B.
Kahng, P. Sharma, and D. Sylvester.
Selective gate-length biasing for cost-effective runtime leakage control.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
327-330, San Diego, CA, June 7-11 2004.
- [1545]
- P. Gupta, A. B.
Kahng, Y. Kim, and D. Sylvester.
Self-compensating design for focus variation.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
365-368, Anaheim, CA, June 13-17 2005.
- [1546]
- P. Gupta, A. B.
Kahng, P. Sharma, and D. Sylvester.
Gate-length biasing for runtime-leakage control.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(8):1475-1485, August 2006.
- [1547]
- M. S. Gupta,
J. L. Oatley, R. Joseph, G.-Y. Wei, and D. M. Brooks.
Understanding voltage variations in chip multiprocessors using a distributed
power-delivery network.
Design, Automation and Test in Europe (DATE-07), pages 624-629, April
16-20 2007.
- [1548]
- P. Gupta, A. B.
Kahng, Y. Kim, and D. Sylvester.
Self-compensating design for reduction of timing and leakage sensitivity to
systematic pattern-dependent variation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(9):1614-1624, September 2007.
- [1549]
- P. Gupta,
Y. Agarwal, L. Dolecek, N. Dutt, R. K. Gupta, R. Kumar, S. Mitra, A. Nicolau,
T. S. Rosing, M. B. Srivastava, S. Swanson, and D. Sylvester.
Underdesigned and opportunistic computing in presence of hardware variability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):8-23, January 2013.
- [1550]
- V. Gupta,
D. Mohapatra, A. Raghunathan, and K. Roy.
Low-power digital signal processing using approximate adders.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):124-137, January 2013.
- [1551]
- V. Gupta and M. Anis.
Statistical design of the 6t SRAM bit cell.
IEEE Transactions on Circuits and Systems, 57(1):93-104, January
2010.
- [1552]
- P. Gupta and F.-L. Heng.
Toward a systematic-variation aware timing methodology.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
321-326, San Diego, CA, June 7-11 2004.
- [1553]
- P. Gupta and A. B.
Kahng.
Manufacturing-aware physical design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 681-687, San Jose, CA, November 9-13 2003.
- [1554]
- P. Gupta and A. B. Kahng.
Quantifying error in dynamic power estimation of CMOS circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 273-278, San Jose, CA, March 24-26 2003.
- [1555]
- P. Gupta and A. B. Kahng.
Bounded-lifetime integrated circuits.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
347-348, Anaheim, CA, June 8-13 2008.
- [1556]
- S. Gupta and
S. Katkoori.
Intrabus crosstalk estimation using word-level statistics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):469-478, March 2005.
- [1557]
- S. Gupta and F. N. Najm.
Power macromodeling for high level power estimation.
In 34th Design Automation Conference, pages 365-370, Anaheim, CA,
June 9-13 1997.
- [1558]
- S. Gupta and F. N. Najm.
Analytical model for high level power modeling of combinational and sequential
circuits.
In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages
164-172, Como, Italy, March 4-5 1999.
- [1559]
- S. Gupta and F. N. Najm.
Energy-per-cycle estimation at RTL.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 121-126, San Diego, CA, August 16-17 1999.
- [1560]
- S. Gupta and F. N. Najm.
Power macro-models for DSP blocks with application to high-level synthesis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 103-105, San Diego, CA, August 16-17 1999.
- [1561]
- S. Gupta and F. N. Najm.
Analytical models for RTL power estimation of combinational and sequential
circuits.
IEEE Transactions on Computer-Aided Design, 19(7):808-814, July
2000.
- [1562]
- S. Gupta and F. N. Najm.
Power modeling for high-level power estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(1):18-29, February 2000.
- [1563]
- S. Gupta and F. N. Najm.
Energy and peak-current per-cycle estimation at RTL.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):525-537, August 2003.
- [1564]
- S. Gupta and S. S.
Sapatnekar.
Compact current source models for timing analysis under temperature and body
bias variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(11):2104-2117, November 2012.
- [1565]
- S. Gupta and
S. Sapatnekar.
Variation-aware variable latency design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1106-1117, May 2014.
- [1566]
- N. Gupte and J. Wang.
Secure power grid simulation on cloud.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(3):422-432, March 2015.
- [1567]
- N. Gupte and J. Wang.
Transient noise bounds using vectorless power grid verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 713-720, Austin TX, November 2-6 2015.
- [1568]
- M. R. Guthaus,
N. Venkateswaran, C. Visweswariah, and V. Zolotov.
Gate sizing using incremental parameterized statistical timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 1029-1036, San Jose, CA, November 6-10 2005.
- [1569]
- M. R. Guthaus,
J. E. Stine, S. Ataei, B. Chen, B. Wu, and M. Sarwar.
Openram: an open-source memory compiler.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [1570]
- M. R. Guthaus and
B. Taskin.
High-performance, low-power resonant clocking.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 742-745, San Jose, CA, November 5-8 2012.
- [1571]
- W. E. Guthrie,
M. Pedram, W. Dai, R. Chadha, J. Cong, C. X. Huang, A. Devgan, T. Mozdzen,
and A. Yang.
Panel: Noise and signal integrity in deep submicron design.
In 34th Design Automation Conference, pages 720-721, Anaheim, CA,
June 9-13 1997.
- [1572]
- H. Gutierrez-Pulido, V. Aguirre-Torres, and J. A. Christen.
A practical method for obtaining prior distributions in reliability.
IEEE Transactions on Reliability, 54(2):262-269, June 2005.
- [1573]
- K. h. Chang,
I. L. Markov, and V. Bertacco.
Automating post-silicon debugging and repair.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 91-98, San Jose, CA, November 5-8 2007.
- [1574]
- M. Ha, K. Srinivasan,
and M. Swaminathan.
Chip-package co-simulation with multiscale structures.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 339-342, San Jose, CA, October 27-29 2008.
- [1575]
- H. Habal,
K. Mayaram, and T. S. Fiez.
Accurate and efficient simulation of synchronous digital switching noise in
systems on a chip.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):330-338, March 2005.
- [1576]
- H. Habal and H. Graeb.
Constraint-based layout-driven sizing of analog circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(8):1089-1102, August 2011.
- [1577]
- G. D.
Hachtel, M. Hermida, A. Pardo, M. Poncino, and F. Somenzi.
Re-encoding sequential circuits to reduce power dissipation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
70-73, San Jose, CA, November 6-10 1994.
- [1578]
- G. D.
Hachtel, E. Macii, A. Pardo, and F. Somenzi.
Probabilistic analysis of large finite state machines.
In 31st ACM/IEEE Design Automation Conference, pages 270-275, San
Diego, CA, June 6-10 1994.
- [1579]
- G. D.
Hachtel, E. Macii, A. Pardo, and F. Somenzi.
Symbolic algorithms to calculate steady-state probabilities of a finite state
machine.
In European Design Automation Conference, pages 214-218, Paris,
France, February 1994.
- [1580]
- G. D.
Hachtel, M. H. De La Rica, A. Pardo, M. Poncino, and F. Somenzi.
Re-encoding sequential circuits to reduce power dissipation.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
69-74, Napa, CA, April 24-27 1994.
- [1581]
- G. D. Hachtel,
E. Macii, A. Pardo, and F. Somenzi.
Markovian analysis of large finite state machines.
IEEE Transactions on Computer-Aided Design, 15(12):1479-1493,
December 1996.
- [1582]
- G. D. Hachtel and
R. A. Rohrer.
Techniques for the optimal design and synthesis of switching circuits.
In Proceedings of the IEEE, pages 1864-1877, November 1967.
Published as Proceedings of the IEEE, volume 55, number 11.
- [1583]
- P. Al Haddad and F. N.
Najm.
Power grid correction using sensitivity analysis under an RC model.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
688-693, San Diego, CA, June 5-9 2011.
- [1584]
- G. Hadjiyiannis and S. Devadas.
Techniques for accurate performance evaluation in architecture exploration.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):601-615, August 2003.
- [1585]
- W. Haensch.
Why should we do 3d integration?
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
674-675, Anaheim, CA, June 8-13 2008.
- [1586]
- M. Hafed,
M. Oulmane, and N. C. Rumin.
Delay and current estimation in a CMOS inverter with an RC load.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(1):80-89, January 2001.
- [1587]
- F. B. Hagedorn and
P. M. Hall.
Right-angle bends in thin strip conductors.
Journal of Applied Physics, 34(1):128-133, January 1963.
- [1588]
- L. Hagen and A. Kahng.
Fast spectral methods for ratio cut partitioning and clustering.
In IEEE International Conference on Computer-Aided Design, pages
10-13, Santa Clara, CA, November 11-14 1991.
- [1589]
- K. Haghdad and M. Anis.
Design-specific optimization considering supply and threshold voltage
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1891-1901, October 2008.
- [1590]
- K. Haghdad and M. Anis.
Power yield analysis under process and temperature variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(10):1794-1803, October 2012.
- [1591]
- A. Hagiescu,
W.-F. Wong, D. F. Bacon, and R. Rabbah.
A computing origami: folding streams in fpgas.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
282-287, San Francisco, CA, July 26-31 2009.
- [1592]
- A. Hajimiri.
Generalized time- and transfer-constant circuit analysis.
IEEE Transactions on Circuits and Systems, 57(6):1105-1121, June
2010.
- [1593]
- I. N. Hajj, V. B.
Rao, R. Iimura, H. Cha, and R. Burch.
A system for electromigration analysis in VLSI metal patterns.
In IEEE Custom Integrated Circuits Conference, pages 4.4.1-4.4.4,
1991.
- [1594]
- I. N. Hajj and F. N. Najm.
Test generation for physical faults in MOS VLSI circuits.
In IEEE Comp-Euro Conference, pages 386-389, Hamburg, West Germany,
May 11-15 1987.
- [1595]
- I. N. Hajj and D. G. Saab.
Fault modeling and logic simulation of MOS VLSI circuits based on logic
expression extraction.
In IEEE International Conference on Computer-Aided Design, pages
99-100, Santa Clara, CA, September 1983.
- [1596]
- I. N. Hajj and D. G. Saab.
Symbolic logic simulation of MOS circuits.
In IEEE International Symposium on Circuits and Systems, pages
246-249, Newport Beach, CA, May 1983.
- [1597]
- I. N. Hajj and D. G. Saab.
On the functional logic representation of digital transistor circuits.
In IEEE International Symposium on Circuits and Systems, pages
1281-1284, Kyoto, Japan, 1985.
- [1598]
- I. N. Hajj and D. Saab.
Switch-level logic simulation of digital bipolar circuits.
IEEE Transactions on Computer-Aided Design, CAD-6(2):251-258, March
1987.
- [1599]
- I. N. Hajj.
A path algebra for switch-level simulation.
In IEEE International Conference on Computer-Aided Design, pages
153-155, Santa Clara, CA, Nov. 18-21 1985.
- [1600]
- I. N. Hajj.
An algebra for labeled weighted graphs.
private communication, 1986.
- [1601]
- I. N. Hajj.
An algebra for switch-level simulation.
In IEEE International Conference on Computer-Aided Design (ICCAD),
pages 488-491, Santa Clara, CA, November 11-15 1990.
- [1602]
- I. N. Hajj.
Extended nodal analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(1):89-100, January 2012.
- [1603]
- I. N. Hajj.
On device modeling for circuit simulation with application to carbon-nanotube
and graphene nano-ribbon field-effect transistors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(3):495-499, March 2015.
- [1604]
- A. Hajjar,
T. Chen, I. Munn, A. Andrews, and M. Bjorkman.
Stopping criteria comparison: towards high quality behavioral verification.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 31-37, San Jose, CA, March 26-28 2001.
- [1605]
- H.Albalawi, Y. Li, and X. Li.
Computer-aided design of machine learning algorithm: training fixed-point
classifier for on-chip low-power implementation.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [1606]
- J. E. Hall, D. E.
Hocevar, P. Yang, and M. J. McGraw.
SPIDER - a CAD system for checking current density and voltage drop in
VLSI metallization patterns.
In IEEE International Conference on Computer-Aided Design, pages
278-281, Santa Clara, CA, Nov. 11-13 1986.
- [1607]
- J. E. Hall, D. E.
Hocevar, P. Yang, and M. McGraw.
SPIDER - a CAD system for modeling VLSI metallization patterns.
IEEE Transactions on Computer-Aided Design, CAD-6(6):1023-1031,
November 1987.
- [1608]
- P. Hallschmid
and R. Saleh.
Fast design space exploration using local regression modeling with application
to asips.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(3):508-515, March 2008.
- [1609]
- P. Hallschmid
and S. J. E. Wilton.
Routing architecture optimizations for high-density embedded programmable IP
cores.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1320-1324, November 2005.
- [1610]
- J. P. Halter and F. N.
Najm.
A gate-level leakage power reduction method for ultra-low-power CMOS
circuits.
In IEEE 1997 Custom Integrated Circuits Conference, pages 475-478,
Santa Clara, CA, May 5-8 1997.
- [1611]
- T. Hamada, C-K
Cheng, and P. M. Chau.
A wire length estimation technique utilizing neighborhood density equations.
In 29th ACM/IEEE Design Automation Conference, pages 57-61, Anaheim,
CA, June 8-12 1992.
- [1612]
- T. Hamada, C-K.
Cheng, and P. M. Chau.
A wire length estimation technique using neighborhood density equations.
IEEE Transactions on Computer-Aided Design, 15(8):912-922, August
1996.
- [1613]
- S. Hamdioui,
Z. Al-Ars, A. J. van de Goor, and M. Rodgers.
Linked faults in ramdom access memories: concept, fault models, test
algorithms, and industrial results.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):737-757, May 2004.
- [1614]
- R. W. Hamming.
Coding and Information Theory, 2nd Ed..
Prentice-Hall, 1986.
- [1615]
- F. Hamzaoglu and
M. R. Stan.
Circuit-level techniques to control gate leakage for sub- 100nm CMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 60-63, Monterey, California, August 12-14 2002.
- [1616]
- D. Han, B.-S. Kim, and
A. Chatterjee.
DSP-driven self-tuning of RF circuits for process-induced performance
variability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):305-314, February 2010.
- [1617]
- S. Han, J. Choung,
B.-S. Kim, B.-H. Lee, H. Choi, and J. Kim.
Statistical aging analysis with process variation consideration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 412-419, San Jose, CA, November 7-10 2011.
- [1618]
- S. Han, V. Sirigiri,
D. G. Saab, and M. Tabib-Azar.
Ultra-low power NEMS FPGA.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 533-538, San Jose, CA, November 5-8 2012.
- [1619]
- L. Han, X. Zhao, and
Z. Feng.
An efficient graph sparsification approach to scalable harmonic balance (HB)
analysis of strongly nonlinear RF circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 494-499, San Jose, CA, November 18-21 2013.
- [1620]
- L. Han, X. Zhao, and
Z. Feng.
Tinyspice: a parallel SPICE simulator on GPU for massively repeated small
circuit simulations.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1621]
- S. Han, B.-S. Kim,
and J. Kim.
Variation-aware aging analysis in digital ics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(12):2214-2225, December 2013.
- [1622]
- K. Han, A. B. Kahng,
and H. Lee.
Scalable detailed placement legalization for complex sub-14nm constraints.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 867-873, Austin TX, November 2-6 2015.
- [1623]
- L. Han and Z. Feng.
Tinyspice plus: scaling up statistical SPICE simulations on GPU leveraging
shared-memory based sparse matrix solution techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [1624]
- N. Hanchate
and N. Ranganathan.
LECTOR: a technique for leakage reduction in CMOS circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(2):196-205, February 2004.
- [1625]
- H. Hanson, M. S.
Hrishikesh, V. Agarwal, S. W. Keckler, and D. Burger.
Static energy reduction techniques for microprocessor caches.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):303-313, June 2003.
- [1626]
- S. Hanson,
D. Sylvester, and D. Blaauw.
A new technique for jointly optimizing gate sizing and supply voltage in
ultra-low energy circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 338-341, Tegernsee, Germany, October 4-6 2006.
- [1627]
- S. Hanson,
B. Zhai, D. Blaauw, D. Sylvester, A. Bryant, and X. Wang.
Energy optimality and variability in subthreshold design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 363-365, Tegernsee, Germany, October 4-6 2006.
- [1628]
- S. Hanson,
M. Seok, D. Sylvester, and D. Blaauw.
Nanometer device scaling in subthreshold circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
700-705, San Diego, CA, June 4-8 2007.
- [1629]
- V. Hanumaiah, S. Vrudhula, and K. S. Chatha.
Performance optimal online DVFS and task migration techniques for thermally
constrained multi-core processors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(11):1677-1690, November 2011.
- [1630]
- Z. Hao, S.-X.-D. Tan,
R. Shen, and G. Shi.
Performance bound analysis of analog circuits considering process variations.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
310-315, San Diego, CA, June 5-9 2011.
- [1631]
- Z. Hao, G. Shi,
S.-X.-D. Tan, and E. Tlelo-Cuautle.
Symbolic moment computation for statistical analysis of large interconnect
networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(5):944-957, May 2013.
- [1632]
- G. Harber,
S. Bass, and X. Hu.
Maximal solution of linear systems of equations and an application in VLSI.
In IEEE International Symposium on Circuits and Systems (ISCAS), pages
2337-2340, 1990.
- [1633]
- M. G. Harbour and
J. M. Drake.
Calculation of multiterminal resistances in integrated circuits.
IEEE Transactions on Circuits and Systems, CAS-33(4):462-465, April
1986.
- [1634]
- M. G. Harbour and
J. M. Drake.
Calculation of signal delay in integrated interconnections.
IEEE Transactions on Circuits and Systems, 36(2):272-276, February
1989.
- [1635]
- B. P. Harish,
N. Bhat, and M. B. Patil.
On a generalized framework for modeling the effects of process variations on
circuit delay performance using response surface methodology.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(3):606-614, March 2007.
- [1636]
- H. Harizi,
R. Haubler, M. Olbrich, and E. Barke.
Efficient modeling techniques for dynamic voltage drop analysis.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
706-711, San Diego, CA, June 4-8 2007.
- [1637]
- C. L. Harkness
and D. P. Lopresti.
Modeling uncertainty in RC timing analysis.
In IEEE International Conference on Computer-Aided Design, pages
516-519, 1989.
- [1638]
- C. L. Harkness
and D. P. Lopresti.
Interval methods for modeling uncertainty in RC timing analysis.
IEEE Transactions on Computer-Aided Design, 11(11):1388-1401,
November 1992.
- [1639]
- J. E. Harlow, III and
F. Brglez.
Design of experiments in BDD variable ordeing: lessons learned.
In IEEE/ACM International Conference on Computer-Aided Design, pages
646-652, San Jose, CA, November 8-12 1998.
- [1640]
- D. Harris,
M. Horowitz, and D. Liu.
Timing analysis including clock skew.
IEEE Transactions on Computer-Aided Design, 18(11):1608-1618,
November 1999.
- [1641]
- D. Harris,
M. Horowitz, and D. Liu.
Timing analysis with clock skew.
In ACM/IEEE 1999 International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU-99), pages 15-20,
Monterey, CA, March 8-9 1999.
- [1642]
- D. Harris and
S. Naffziger.
Statistical clock skew modeling with data delay variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(6):888-898, December 2001.
- [1643]
- D. M. Harris.
Sequential element timing parameter definition considering clock uncertainty.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(11):2705-2708, November 2015.
- [1644]
- M. A. Hasan, A. H.
Namin, and C. Negre.
Toeplitz matrix approach for binary field multiplication using quadrinomials.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(3):449, March 2012.
- [1645]
- J. Y. Hasani.
Three-port model of a modern MOS transistor in millimeter wave bank,
considering distributed effects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(9):1509-1518, September 2016.
- [1646]
- S. Hashemi,
R. I. Bahar, and S. Reda.
DRUM: a dynamic range unbiased multiplier for approximate applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 418-425, Austin TX, November 2-6 2015.
- [1647]
- M. Hashimoto, H. Onodera, and K. Tamaru.
A power optimization method considering glitch reduction by gate sizing.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 221-226, Monterey, CA, August 10-12 1998.
- [1648]
- M. Hashimoto, H. Onodera, and K. Tamaru.
A practical gate resizing technique considering glitch reduction for low power
design.
In Design Automation Conference, pages 446-451, New Orleans, LA, June
21-25 1999.
- [1649]
- M. Hashimoto, Y. Yamada, and H. Onodera.
Equivalent waveform propagation for static timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 169-175, San Jose, CA, November 9-13 2003.
- [1650]
- M. Hashimoto, Y. Yamada, and H. Onodera.
Equivalent waveform propagation for static timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(4):498-508, April 2004.
- [1651]
- M. Hashimoto, J. Yamaguchi, and H. Onodera.
Timing analysis considering spatial power/ground level variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 814-820, San Jose, CA, November 7-11 2004.
- [1652]
- H. Hassan,
M. Anis, and M. Elmasry.
LAP: a logic activity packing methodology for leakage power-tolerant fpgas.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 257-262, San Diego, CA, August 8-10 2005.
- [1653]
- H. Hassan,
M. Anis, and M. Elmasry.
Input vector reordering for leakage power reduction in fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(9):1555-1564, September 2008.
- [1654]
- H. A. Hassan,
M. Anis, and M. Elmasry.
Total power modeling in fpgas under spatial correlation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(4):578-587, April 2009.
- [1655]
- Z. Hassan,
N. Allec, F. Yang, L. Shang, R. P. Dick, and X. Zeng.
Full-spectrum spatial-temporal dynamic thermal analysis for nanometer-scale
integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(12):2276-2289, December 2011.
- [1656]
- S. Hassoun,
C. Cromer, and E. Calvillo-Gamez.
Static timing analysis for level-clocked circuits in the presence of crosstalk.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(9):1270-1277, September 2003.
- [1657]
- S. Hassoun.
Critical path analysis using a dynamically bounded delay model.
In Design Automation Conference, pages 260-265, Los Angeles, CA, June
5-9 2000.
- [1658]
- N. A. J. Hastings
and H. J. G. Bartlett.
Estimating the failure order-number from reliability data with suspended items.
IEEE Transactions on Reliability, 46(2):266-268, June 1997.
- [1659]
- H. Hatamkhani, F. Lambrecht, V. Stojanovic, and C.-K. K. Yang.
Power-centric design of high-speed I/os.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
867-872, San Francisco, CA, July 24-28 2006.
- [1660]
- T. Hattori,
T. Irita, M. Ito, E. Yamamoto, H. Kato, G. Sado, T. Yamada, K. Nishiyama,
H. Yagi, T. Koike, Y. Tsuchihashi, M. Higashida, H. Asano, I. Hayashibara,
K. Tatezawa, Y. Shimazaki, N. Morino, Y. Yasu, T. Hoshi, Y. Miyairi,
K. Yanagisawa, K. Hirose, S. Tamaki, S. Yoshioka, T. Ishii, Y. Kanno,
H. Mizuno, T. Yamada, N. Irie, R. Tsuchihashi, N. Arai, T. Akiyama, and
K. Ohno.
Hierarchical power distribution and power management scheme for a single chip
mobile processor.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
292-295, San Francisco, CA, July 24-28 2006.
- [1661]
- C. Haubelt,
T. Schlichte, J. Keinert, and M. Meredith.
Systemcodesigner: automatic design space exploration and rapid prototyping from
behavioral models.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
580-585, Anaheim, CA, June 8-13 2008.
- [1662]
- S. Hayashi and
M. Yamada.
EMI-noise analysis under ASIC design environment.
IEEE Transactions on Computer-Aided Design, 19(11):1337-1346,
November 2000.
- [1663]
- Seymour Hayden and
John F. Kennison.
Zermelo-Fraenkel Set Theory.
Charles E. Merrill Publishing Company, Columbus, OH, 1968.
- [1664]
- John P. Hayes.
Computer Architecture and Organization.
McGraw-Hill Book Company, 1978.
- [1665]
- J. P. Hayes.
Digital simulation with multiple logic values.
IEEE Transactions on Computer-Aided Design, CAD-5(2):274-283, April
1986.
- [1666]
- J. P. Hayes.
Pseudo-boolean logic circuits.
IEEE Transactions on Computers, C-35(7):602-612, July 1986.
- [1667]
- J. P. Hayes.
Uncertainty, energy, and multiple-valued logics.
IEEE Transactions on Computers, C-35(2):107-114, February 1986.
- [1668]
- J. P. Hayes.
An introduction to switch-level modeling.
IEEE Design & Test of Computers, 4(4):18-25, August 1987.
- [1669]
- H. Haznedar,
M. Gall, V. Zolotov, P.-S. Ku, C. Oh, and R. Panda.
Impact of stress-induced backflow on full-chip electromigration risk
assessment.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(6):1038-1046, June 2006.
- [1670]
- A. Hazra,
S. Goyal, P. Dasgupta, and A. Pal.
Formal verification of architectural power intent.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(1):78-91, January 2013.
- [1671]
- L. He, W. Liao, and
M. R. Stan.
System level leakage reduction considering the interdependence of temperature
and leakage.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 12-17,
San Diego, CA, June 7-11 2004.
- [1672]
- X. He, T. Huang,
L. Xiao, H. Tian, and E. F.-Y. Young.
Ripple: a robust and effective routability-driven placer.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1546-1556, October 2013.
- [1673]
- X. He, P. Du, S.-H.
Weng, and C.-K. Cheng.
Worst case noise prediction with nonzero current transition times for power
grid planning.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(3):607-620, March 2014.
- [1674]
- K. He, S.-X.-D. Tan,
H. Wang, and G. Shi.
GPU-accelerated parallel sparse LU factorization method for fast circuit
analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(3):1140-1150, March 2016.
- [1675]
- C. He and M. F. Jacome.
Defect-aware high-level synthesis targeted at reconfigurable nanofabrics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(5):817-833, May 2007.
- [1676]
- Z. He and L. T. Pileggi.
A simple algorithm for calculating frequency-dependent inductance bounds.
In IEEE Custom Integrated Circuits Conference, pages 199-202, Santa
Clara, CA, May 11-14 1998.
- [1677]
- R. Heald and P. Wang.
Variability in sub-100nm SRAM designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 347-352, San Jose, CA, November 7-11 2004.
- [1678]
- M. B. Healy and S.-K. Lim.
Distributed TSV topology for 3-D power-supply networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(11):2066-2079, November 2012.
- [1679]
- J. R. Heath.
A systems approach to molecular electronics.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, page 359, Seoul, Korea, August 25-27 2003.
- [1680]
- R. Hegde and
N. Shanbhag.
Energy efficiency in presence of deep submicron noise.
In IEEE/ACM International Conference on Computer-Aided Design, pages
228-234, San Jose, CA, November 8-12 1998.
- [1681]
- R. Hegde and N. R.
Shanbhag.
Energy-efficient signal processing via algorithmic noise-tolerance.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 30-35, San Diego, CA, August 16-17 1999.
- [1682]
- R. Hegde and N. R.
Shanbhag.
Soft digital signal processing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(6):813-823, December 2001.
- [1683]
- W. Heidergott.
SEU tolerant device, circuit and processor design.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 5-10,
Anaheim, CA, June 13-17 2005.
- [1684]
- H. T.
Heineken, J. Khare, W. Maly, P. K. Nag, C. Ouyang, and W. A. Pleskacz.
CAD at the design-manufacturing interface.
In 34th Design Automation Conference, pages 321-326, Anaheim, CA,
June 9-13 1997.
- [1685]
- H. T. Heineken and
W. Maly.
Interconnect yield model for manufacturability prediction in synthesis of
standard cell designs.
In IEEE/ACM International Conference on Computer-Aided Design, pages
368-373, San Jose, CA, November 10-14 1996.
- [1686]
- H. T. Heineken and
W. Maly.
Standard cell interconnect length prediction from structural circuit
attributes.
In IEEE 1996 Custom Integrated Circuits Conference, pages 167-170,
San Diego, CA, May 5-8 1996.
- [1687]
- J. A. Heinen.
Sufficient conditions for stability of interval matrices.
International Journal of Control, 39(6):1323-1328, 1984.
- [1688]
- A. E. Helal, A. M.
Bayoumi, and Y. Y. Hanafy.
Parallel circuit simulation using the direct method on a heterogeneous cloud.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [1689]
- S. Held, B. Korte,
J. Mabberg, M. Ringe, and J. Vygen.
Clock scheduling and clocktree construction for high performance asics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 232-239, San Jose, CA, November 9-13 2003.
- [1690]
- A. Heldring,
J. M. Rius, J. M. Tamayo, and J. Parron.
Compressed block-decomposition algorithm for fast capacitance extraction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):265-271, February 2008.
- [1691]
- L. Hellerman.
A measure of computational work.
IEEE Transactions on Computers, C-21(5):439-446, May 1972.
- [1692]
- D. Helms,
G. Ehmen, and W. Nebel.
Analysis and modeling of subthreshold leakage of RT-components under PTV
and state variation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 220-225, Tegernsee, Germany, October 4-6 2006.
- [1693]
- K. R. Heloue,
N. Azizi, and F. N. Najm.
Modeling and estimation of full-chip leakage current considering within-die
correlation.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 93-98,
San Diego, CA, June 4-8 2007.
- [1694]
- K. R. Heloue,
S. Onaissi, and F. N. Najm.
Efficient block-based parameterized timing analysis covering all potentially
critical paths.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 173-180, San Jose, CA, November 10-13 2008.
- [1695]
- K. R. Heloue,
N. Azizi, and F. N. Najm.
Full-chip model for leakage-current estimation considering within-die
correlation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(6):874-887, June 2009.
- [1696]
- K. R. Heloue,
C. V. Kashyap, and F. N. Najm.
Quantifying robustness metrics in parameterized static timing analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-09), pages 49-54, Austin, TX,
February 23-24 2009.
- [1697]
- K. R. Heloue,
C. V. Kashyap, and F. N. Najm.
Quantifying robustness metrics in parameterized static timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 209-216, San Jose, CA, November 2-5 2009.
- [1698]
- K. R. Heloue,
S. Onaissi, and F. N. Najm.
Efficient block-based parameterized timing analysis covering all potenially
critical paths.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):472-484, April 2012.
- [1699]
- K. R. Heloue,
S. Onaissi, and F. N. Najm.
Efficient block-based parameterized timing analysis covering all potentially
critical paths.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):472-484, April 2012.
- [1700]
- K. R. Heloue and F. N.
Najm.
Effect of statistical clock skew variations on chip timing yield.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 211-214, Quebec City, Quebec, June 19-22 2005.
- [1701]
- K. R. Heloue and F. N.
Najm.
Statistical timing analysis with two-sided constraints.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 829-836, San Jose, CA, November 6-10 2005.
- [1702]
- K. R. Heloue and F. N.
Najm.
Early analysis of timing margins and yield.
In 20th Canadian Conference on Electrical and Computer Engineering
(CCECE), pages 1114-1120, Vancouver, BC, April 22-26 2007.
- [1703]
- K. R. Heloue and F. N.
Najm.
Early statistical timing analysis with unknown within-die correlations.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 13-18, Austin, Texas,
February 26-27 2007.
- [1704]
- K. R. Heloue and F. N.
Najm.
Early analysis and budgeting of margins and corners using two-sided analytical
yield models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1826-1839, October 2008.
- [1705]
- K. R. Heloue and F. N.
Najm.
Parameterized timing analysis with general delay models and arbitrary variation
sources.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 14-19, Monterey, CA,
February 25-26 2008.
- [1706]
- K. R. Heloue and F. N.
Najm.
Parameterized timing analysis with general delay models and arbitrary variation
sources.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
403-408, Anaheim, CA, June 8-13 2008.
- [1707]
- J. Henkel and
H. Lekatsas.
A2bc: Adaptive address bus coding for low power deep sub-micron designs.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
744-749, Las Vegas, NV, June 18-22 2001.
- [1708]
- J. Henkel and Y. Li.
Avalanche: an environment for design space exploration and optimization of
low-power embedded systems.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(4):454-468, August 2002.
- [1709]
- J. Henkel.
A low power hardware/software partitioning approach for core-based embedded
systems.
In Design Automation Conference, pages 122-127, New Orleans, LA, June
21-25 1999.
- [1710]
- S. Henzler,
T. Nirschl, J. Berthold, G. Georgakos, and D. Schmitt-Landsiedel.
Design and technology of fine-grained sleep transistor circuits in ultra-deep
sub-micron CMOS technologies.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 223-228, Austin, TX, May 9 - 11 2005.
- [1711]
- S. Heo, K. Barr, and
K. Asanovic.
Reducing power density through activity migration.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 217-222, Seoul, Korea, August 25-27 2003.
- [1712]
- S. Heo and K. Asanovic.
Power-optimal pipelining in deep submicron technology.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 218-223, Newport Beach, CA, August 9-11 2004.
- [1713]
- S. Heo and K. Asanovic.
Replacing global wires with an on-chip network: a power analysis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 369-374, San Diego, CA, August 8-10 2005.
- [1714]
- S. Herbert and
D. Marculescu.
Analysis of dynamic voltage/frequency scaling nchip-multiprocessors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 38-43, Portland, Oregon, August 27-29 2007.
- [1715]
- S. Herbert and
D. Marculescu.
Characterizing chip-multiprocessor variability-tolerance.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
313-318, Anaheim, CA, June 8-13 2008.
- [1716]
- S. Herbert and
D. Marculescu.
Mitigating the impact of variability on chip-multiprocessor power and
performance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(10):1520-1533, October 2009.
- [1717]
- S. Hertz,
D. Sheridan, and S. Vasudevan.
Mining hardware assertions with guidance from static analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):952-965, June 2013.
- [1718]
- P. Heydari,
A. Abbaspour, and M. Pedram.
Interconnect energy dissipation in high-speed ULSI circuits.
IEEE Transactions on Circuits and Systems, 51(8):1501-1514, August
2004.
- [1719]
- P. Heydari and
R. Mohanavelu.
Design of ultrahigh-speed low-voltage CMOS CML buffers and latches.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1081-1093, October 2004.
- [1720]
- P. Heydari and
M. Pedram.
Model reduction of variable-geometry interconnects using variational
spectrally-weighted balanced truncation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 586-591, San Jose, CA, November 4-8 2001.
- [1721]
- P. Heydari and
M. Pedram.
Ground bounce in digital VLSI circuits.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(2):180-193, April 2003.
- [1722]
- P. Heydari and
M. Pedram.
Capacitive coupling noise in high-speed VLSI circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):478-488, March 2005.
- [1723]
- P. Heydari and
M. Pedram.
Model-order reduction using variational balanced truncation with spectral
shaping.
IEEE Transactions on Circuits and Systems, 53(4):879-891, April
2006.
- [1724]
- P. Heydari.
Design and analysis of low-voltage current-mode logic buffers.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 293-298, San Jose, CA, March 24-26 2003.
- [1725]
- K. Heyrman,
A. Papanikolaou, F. Gatthoor, P. Veelaert, and W. Philips.
Control for power gating of wires.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(9):1287-1300, September 2010.
- [1726]
- P. Hicks,
M. Walnock, and R. M. Owens.
Analysis of power consumption in memory hierarchies.
In 1997 International Symposium on Low Power Electronics and Design,
pages 239-242, Monterey, CA, August 18-20 1997.
- [1727]
- D. D. Hill and E. Detjens.
FPGA design principles (a tutorial).
In 29th ACM/IEEE Design Automation Conference, pages 45-46, Anaheim,
CA, June 8-12 1992.
- [1728]
- A. M. Hill and S-M. Kang.
Accuracy bounds in switching activity estimation.
In IEEE Custom Integrated Circuits Conference, pages 73-76, Santa
Clara, CA, May 1-4 1995.
- [1729]
- A. M. Hill and S-M. Kang.
Determining accuracy bounds for simulation-based switching activity estimation.
In ACM/IEEE International Symposium on Low Power Design, pages
215-220, Dana Point, CA, April 23-26 1995.
- [1730]
- A. M. Hill and S-M. Kang.
Determining accuracy bounds for simulation-based switching activity estimation.
IEEE Transactions on Computer-Aided Design, 15(6):611-618, June
1996.
- [1731]
- F. J. Hill and G. R.
Peterson.
Digital Logic and Microprocessors.
John Wiley & Sons, Inc., New York, NY, 1984.
- [1732]
- M. Hirabayashi, K. Nose, and T. Sakurai.
Design methodology and optimization strategy for dual-vth scheme using
commercially available tools.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 283-286, Huntington Beach, California, August 6-7
2001.
- [1733]
- A. Hirata,
H. Onodera, and K. Tamaru.
Proposal of a timing model for CMOS logic gates driving a CRC pi load.
In IEEE/ACM International Conference on Computer-Aided Design, pages
537-544, San Jose, CA, November 8-12 1998.
- [1734]
- H. Hirose.
Parameter estimation for the 3-parameter gamma distribution using the
continuation method.
IEEE Transactions on Reliability, 47(2):188-196, June 1998.
- [1735]
- I. A. Hiskens.
Power system modeling for inverse problems.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(3):539-551, March 2004.
- [1736]
- I. A. Hiskens.
What's smart about the smart grid?
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
937-939, Anaheim, CA, June 13-18 2010.
- [1737]
- R. B.
Hitchcock, Sr., G. L. Smith, and D. D. Cheng.
Timing analysis of computer hardware.
IBM Journal of Research and Development, 26(1):100-105, January
1982.
- [1738]
- R. B. Hitchcock, Sr.
Timing verification and the timing analysis program.
In IEEE 19th Design Automation Conference, pages 594-604, 1982.
- [1739]
- J. Hlavicka and
P. Fiser.
BOOM - a heuristic boolean minimizer.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 439-442, San Jose, CA, November 4-8 2001.
- [1740]
- P. S. Ho, F. M.
d'Heurle, and A. Gangulee.
Implications of electromigration on device reliability.
In R. E. Hummel and H. B. Huntington, editors, Electro- and
Thermo-Transport in Metals and Alloys, pages 109-139. American Society
for Metals, Niagara Falls, NY, Sept. 22 1976.
- [1741]
- R. Ho, K. Mai,
H. Kapadia, and M. Horowitz.
Interconnect scaling implications for CAD.
In IEEE/ACM International Conference on Computer-Aided Design, pages
425-429, San Jose, CA, November 7-11 1999.
- [1742]
- T.-Y. Ho, J. Zeng, and
K. Chakrabarty.
Digital microfluidic biochips: a vision for functional diversity and more than
moore.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 578-585, San Jose, CA, November 7-11 2010.
- [1743]
- M.-H. Ho, Y.-Q. Ai,
T.-C.-P. Chau, S.-C.-L. Yuen, C.-S. Choy, P.-H.-W. Leong, and K.-P. Pun.
Architecture and design flow for a highly efficient structured ASIC.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(3):424-433, March 2013.
- [1744]
- H. H. Hoang and J. M.
McDavid.
Electromigration in multilayer metallization systems.
Solid State Technology, pages 121-126, October 1987.
- [1745]
- A. Hochman,
B. N. Bond, and J. K. White.
A stabilized discrete empirical interpolation method for model reduction of
electrical, thermal, and microelectromechanical systems.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
540-545, San Diego, CA, June 5-9 2011.
- [1746]
- D. A. Hodges and H. G.
Jackson.
Analysis and Design of Digital Integrated Circuits.
McGraw-Hill, 1988.
- [1747]
- R. V. Hogg and A. T. Craig.
Introduction to Mathematical Statistics.
Prentice-Hall, Inc., Englewood Cliffs, NJ, 5th edition, 1995.
- [1748]
- F. E. Hohn and L. R.
Schissler.
Boolean matrices and the design of combinational relay switching circuits.
The Bell System Technical Journal, pages 177-202, January 1955.
- [1749]
- T. S. Hohol and L. A.
Glasser.
Relic: a reliability simulator for integrated circuits.
In IEEE International Conference on Computer-Aided Design, pages
517-520, Santa Clara, CA, Nov. 11-13 1986.
- [1750]
- D. E. Holcomb and
S. A. Seshia.
Compositional performance verification of network-on-chip designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(9):1370-1383, September 2014.
- [1751]
- I. Hong,
D. Kirovski, G. Qu, M. Potkonjak, and M. B. Srivastava.
Power optimization of variable voltage core-based systems.
In IEEE/ACM 35th Design Automation Conference, pages 176-181, San
Francisco, CA, June 15-19 1998.
- [1752]
- I. Hong,
D. Kirovski, G. Qu, M. Potkonjak, and M. B. Srivastava.
Power optimization of variable-voltage core-based systems.
IEEE Transactions on Computer-Aided Design, 18(12):1702-1714,
December 1999.
- [1753]
- S. Hong and T. Kim.
Bus optimization for low-power data path synthesis based on network flow
method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 312-317, San Jose, CA, November 5-9 2000.
- [1754]
- T. B. Hook,
J. Brown, and X. Tian.
Proximity effects and VLSI design.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 167-170, Austin, TX, May 9 - 11 2005.
- [1755]
- J. Hopcroft and
J. Ullman.
Introduction to Automata Theory, Languages and Computation.
Addison-Wesley, Reading, MA, 1979.
- [1756]
- B. Hoppe,
G. Neuendorf, D. Schmitt-Landsiedel, and W. Specks.
Optimization of high-speed CMOS logic circuits with analytical models for
signal delay, chip area, and dynamic power dissipation.
IEEE Transactions on Computer-Aided Design, 9(3):236-247, March
1990.
- [1757]
- M. Horowitz,
M. Jeeradit, F. Lau, S. Liao, B. Lim, and J. Mao.
Fortifying analog models with equivalence checking and coverage analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
425-430, Anaheim, CA, June 13-18 2010.
- [1758]
- M. Horowitz.
Timing models for MOS pass networks.
In IEEE International Symposium on Circuits and Systems, pages
198-201, 1983.
- [1759]
- R. Hossain,
L. D. Wronski, and A. Albicki.
Low power design using double edge triggered flip-flops.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2(2):261-265, June 1994.
- [1760]
- R. Hossain,
M. Zheng, and A. Albicki.
Reducing power dissipation in CMOS circuits by signal probability based
reordering.
IEEE Transactions on Computer-Aided Design, 15(3):361-368, March
1996.
- [1761]
- R. Hossain,
F. Viglione, and M. Cavalli.
Designing fast on-chip interconnects for deep submicrometer technologies.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(2):276-280, April 2003.
- [1762]
- C. Hough, T. Xue,
and E. Kuh.
New approaches for on-chip power switching noise reduction.
In IEEE Custom Integrated Circuits Conference, pages 133-136, Santa
Clara, CA, May 1-4 1995.
- [1763]
- A. S. Householder.
The Theory of Matrices in Numerical Analysis.
Dover Publications, Inc., New York, NY, 1964.
- [1764]
- M. S. Hsiao,
E. M. Rudnick, and J. H. Patel.
Effects of delay models on peak power estimation of VLSI sequential circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
45-51, San Jose, CA, November 9-13 1997.
- [1765]
- M. S. Hsiao,
E. M. Rudnick, and J. H. Patel.
K2: An estimator for peak sustainable power of VLSI circuits.
In 1997 International Symposium on Low Power Electronics and Design,
pages 178-183, Monterey, CA, August 18-20 1997.
- [1766]
- M. S. Hsiao, E. M.
Rudnick, and J. H. Patel.
Peak power estimation of VLSI circuits: new peak power measures.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(4):435-439, August 2000.
- [1767]
- K.-S. Hsiao and C.-H. Chen.
Wake-up logic optimizations through selective match and wakeup range
limitation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(10):1089-1102, October 2006.
- [1768]
- C.-T. Hsieh,
Q. Wu, C.-S. Ding, and M. Pedram.
Statistical sampling and regression analysis for RT-level power evaluation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
583-588, San Jose, CA, November 10-14 1996.
- [1769]
- C-T Hsieh,
M. Pedram, G. Mehta, and F. Rastgar.
Profile-driven program synthesis for evaluation of system power dissipation.
In 34th Design Automation Conference, pages 576-581, Anaheim, CA,
June 9-13 1997.
- [1770]
- C.-T. Hsieh, J.-C.
Lin, and S.-C. Chang.
A vectorless estimation of maximum instantaneous current for sequential
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 537-540, San Jose, CA, November 7-11 2004.
- [1771]
- C.-T. Hsieh, J.-C.
Lin, and S.-C. Chang.
Vectorless estimation of maximum instantaneous current for sequential circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2341-2352, November 2006.
- [1772]
- W.-W. Hsieh, P.-Y.
Chen, C.-Y. Wang, and T. T. Hwang.
A bus-encoding scheme for crosstalk elimination in high-performance processor
design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(12):2222-2227, December 2007.
- [1773]
- A.-C. Hsieh and T. Hwang.
TSV redundancy: architecture and design issues in 3-D ic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(4):711-722, April 2012.
- [1774]
- C.-T. Hsieh and
M. Pedram.
Microprocessor power estimation using profile-driven program synthesis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 17(11):1080-1089, November 1998.
- [1775]
- C.-T. Hsieh and
M. Pedram.
Architectural energy optimization by bus splitting.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(4):408-414, April 2002.
- [1776]
- W-J. Hsu, C-C. Shih,
and B. J. Sheu.
RELY: a reliability simulator for VLSI circuits.
In IEEE 1988 Custom Integrated Circuits Conference, pages
27.4.1-27.4.4, Rochester, NY, May 16-19 1988.
- [1777]
- C-H. Hsu, U. Kremer,
and M. Hsiao.
Compiler-directed dynamic voltage/frequency scheduling for energy reduction in
microprocessors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 275-278, Huntington Beach, California, August 6-7
2001.
- [1778]
- J. Hsu, S. Zahedi,
A. Kansal, M. Srivastava, and V. Raghunathan.
Adaptive duty cycling for energy harvesting systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 180-185, Tegernsee, Germany, October 4-6 2006.
- [1779]
- S.-H. Hsu, Y.-S.
Cheng, W.-D. Guo, H.-H. Cheng, C.-C. Wang, and R.-B. Wu.
Placement of shorting vias for power integrity in multi-layered structures.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 91-94, San Jose, CA, October 27-29 2008.
- [1780]
- C.-H. Hsu, C. Liu,
E.-H. Ma, and J. C.-M. Li.
Static timing analysis for flexible TFT circuits.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
799-802, Anaheim, CA, June 13-18 2010.
- [1781]
- H.-C. Hsu and J. Lin.
Analysis of entire power distribution system of chip, package and board for
high speed IO design.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 99-102, San Jose, CA, October 27-29 2008.
- [1782]
- W.-J. Hsu and W.-Z. Shen.
Coalgebraic division for multilevel synthesis.
In 29th ACM/IEEE Design Automation Conference, pages 438-442,
Anaheim, CA, June 8-12 1992.
- [1783]
- Y. Hu, X. Duan, and
K. Mayaram.
A comparison of time-domain and harmonic balance steady-state analyses for
coupled device and circuit simulation.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 93-96, Montreal, Quebec, June 20-23 2004.
- [1784]
- M. Hu, H. Li, and
R. E. Pino.
Fast statistical model of tio2 thin-film memristor and design implication.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 345-352, San Jose, CA, November 7-10 2011.
- [1785]
- W. Hu, J. Oberg,
A. Irturk, M. Tiwari, T. Sherwood, D. Mu, and R. Kastner.
Theoretical fundamentals of gate level information flow tracking.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(8):1128-1139, August 2011.
- [1786]
- W. Hu, J. Oberg, D. Mu,
and R. Kastner.
Simultaneous information flow security and circuit redundancy in boolean gates.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 585-590, San Jose, CA, November 5-8 2012.
- [1787]
- J. Hu, M.-C. Kim, and
I. L. Markov.
Taming the complexity of coordinated place and route.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [1788]
- X. Hu, P. Du, J. F.
Buckwalter, and C.-K. Cheng.
Modeling and analysis of power distribution networks in 3-D ics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(2):354-366, February 2013.
- [1789]
- J. Hu, D. Sinha, and
I. Keller.
TAU 2014 contest on removing common path pessimism during timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 591, San Jose, CA, November 2-6 2014.
- [1790]
- F. Hu and V. A. Agrawal.
Input-specific dynamic power optimization for VLSI circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 232-237, Tegernsee, Germany, October 4-6 2006.
- [1791]
- A. J. Hu and D. L. Dill.
Reducing BDD size by exploiting functional dependencies.
In 30th ACM/IEEE Design Automation Conference, pages 266-271, Dallas,
Texas, June 14-18 1993.
- [1792]
- S. Hu and J. Hu.
Unified adaptivity optimization of clock and logic signals.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 125-130, San Jose, CA, November 5-8 2007.
- [1793]
- J. Hu and R. Marculescu.
Energy- and performance-aware mapping for regular noc architectures.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(4):551-562, April 2005.
- [1794]
- Y. Hu and K. Mayaram.
Comparison of algorithms for frequency domain coupled device and circuit
simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2571-2578, November 2006.
- [1795]
- J. Hu and S. S. Sapatnekar.
Simultaneous buffer insertion and non-hanan optimization for VLSI
interconnect under a higher order AWE model.
In 1999 International Symposium on Physical Design, pages 133-138,
Monterey, CA, April 12-14 1999.
- [1796]
- J. Hu and S. Sapatnekar.
A timing-constrained algorithm for simultaneous global routing of multiple
nets.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 99-103, San Jose, CA, November 5-9 2000.
- [1797]
- J. Hu and S. S.
Sapatnekar.
Algorithms for non-hanan-based optimization for VLSI interconnect under a
higher-order AWE model.
IEEE Transactions on Computer-Aided Design, 19(4):446-458, April
2000.
- [1798]
- H. Hu and S. S.
Sapatnekar.
Efficient inductance extraction using circuit-aware techniques.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):746-761, December 2002.
- [1799]
- J. Hu and S. S.
Sapatnekar.
A timing-constrained simultaneous global routing algorithm.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(9):1025-1036, September 2002.
- [1800]
- B. Hu and C.-J. R. Shi.
Fast-yet-accurate PVT simulation by combined direct and iterative methods.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 495-501, San Jose, CA, November 6-10 2005.
- [1801]
- B. Hu and C.-J. Richard Shi.
Simulation of closely related dynamic nonlinear systems with application to
process-voltage-temperature corner analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(5):883-892, May 2008.
- [1802]
- C. Hu.
Reliability issues of MOS and bipolar ics.
In IEEE International Conference on Computer Design, pages 438-442,
1989.
- [1803]
- C. Hu.
IC reliability prediction.
In IEEE Custom Integrated Circuits Conference, pages 4.1.1-4.1.4,
1991.
- [1804]
- C. Hu.
New sub-20nm transistors -- why and how.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
460-463, San Diego, CA, June 5-9 2011.
- [1805]
- S. Hua and G. Qu.
Approaching the maximum energy saving on embedded systems with multiple
voltages.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 26-29, San Jose, CA, November 9-13 2003.
- [1806]
- S. Hua and G. Qu.
Voltage setup problem for embedded systems with multiple voltages.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(7):869-877, July 2005.
- [1807]
- Y. Huai, Y. Zhou,
I. Tudosa, R. Malmhall, R. Ranjan, and J. Zhang.
Progress and outlook for STT-MRAM.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 235, San Jose, CA, November 7-10 2011.
- [1808]
- X. Huang,
V. Raghavan, and R. A. Rohrer.
Awesim: a program for the efficient analysis of linear(ized) circuits.
In IEEE International Conference on Computer-Aided Design (ICCAD),
pages 534-537, Santa Clara, CA, Nov. 11-15 1990.
- [1809]
- C. X. Huang,
B. Zhang, A-C. Deng, and B. Swirski.
The design and implementation of powermill.
In ACM/IEEE International Symposium on Low Power Design, pages
105-109, Dana Point, CA, April 23-26 1995.
- [1810]
- S-Y. Huang, K-C.
Chen, K-T. Cheng, and T-C. Lee.
Compact vector generation for accurate power simulation.
In 33rd Design Automation Conference, pages 161-164, Las Vegas, NV,
June 3-7 1996.
- [1811]
- S-Y. Huang, K-T.
Cheng, K-C. Chen, and M. T-C. Lee.
A novel methodology for transistor-level power estimation.
In International Symposium on Low Power Electronics and Design, pages
67-72, Monterey, CA, August 12-14 1996.
- [1812]
- C.-T. Huang, C.-F.
Wu, J.-F. Li, and C.-W. Wu.
Built-in redundancy analysis for memory yield improvement.
IEEE Transactions on Reliability, 52(4):386-399, December 2003.
- [1813]
- L.-D. Huang,
X. Tang, H. Xiang, D. F. Wong, and I.-M. Liu.
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna
problem.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):141-147, January 2004.
- [1814]
- W. Huang, M. R.
Stan, K. Skadron, K. Sankaranarayanan, S. Ghosh, and S. Velusamy.
Compact thermal modeling for temperature-aware design.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
878-883, San Diego, CA, June 7-11 2004.
- [1815]
- H. Huang, K.-G.
Shin, C. Lefurgy, and T. Keller.
Improving energy efficiency by making DRAM less randomly accessed.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 393-398, San Diego, CA, August 8-10 2005.
- [1816]
- S.-H. Huang,
Y.-T. Nieh, and F.-P. Lu.
Race-condition-aware clock skew scheduling.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
475-478, Anaheim, CA, June 13-17 2005.
- [1817]
- S.-H. Huang,
C.-M. Chang, and Y.-T. Nieh.
State re-encoding for peak current minimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 33-38, San Jose, CA, November 5-9 2006.
- [1818]
- W. Huang,
S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, and M. R. Stan.
Hotspot: a compact thermal modeling methodology for early-stage VLSI design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(5):501-513, May 2006.
- [1819]
- C.-Y. Huang, G.-A.
Wu, and T.-H. Lin.
Qutesat: a robust circuit-based SAT solver for complex circuit structure.
Design, Automation and Test in Europe (DATE-07), pages 1313-1318,
April 16-20 2007.
- [1820]
- W. Huang, M. R.
Stan, K. Sankaranarayanan, R. J. Ribando, and K. Skadron.
Many-core design from a thermal perspective.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
746-749, Anaheim, CA, June 8-13 2008.
- [1821]
- T.-W. Huang,
P.-C. Wu, and M.-D.-F. Wong.
Fast path-based timing analysis for CPPR.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 596-599, San Jose, CA, November 2-6 2014.
- [1822]
- X. Huang, T. Yu,
V. Sukharev, and S.-X.-D. Tan.
Physics-based electromigration assessment for power grid networks.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [1823]
- Z.-C. Huang,
C.-K. Chen, and R.-S. Tsay.
AROMA: a highly accurate microcomponent-based approach for embedded processor
power analysis.
In 20th Asia and South Pacific Design Automation Conference, pages
761-766, Chiba/Tokyo, Japan, January 19-22 2015.
- [1824]
- Q. Huang,
C. Fang, F. Yang, X. Zeng, D. Zhou, and X. Li.
Efficient performance modeling via dual-prior bayesian model fusion for analog
and mixed-signal circuits.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [1825]
- T.-W. Huang,
M.-D.-F. Wong, D. Sinha, K. Kalafala, and N. Venkateswaran.
A distributed timing analysis framework for large designs.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [1826]
- X. Huang,
A. Kteyan, S.-X.-D. Tan, and V. Sukharev.
Physics-based electromigration models and full-chip assessment for power grid
networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(11):1848-1861, November 2016.
- [1827]
- H.-Y. Huang and S.-L.
Chen.
Interconnect accelerating techniques for sub-100-nm gigascale systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(11):1192-1200, November 2004.
- [1828]
- D. Huang and T.-W.-S. Chow.
Efficiently searching the important input variables using bayesian
discriminant.
IEEE Transactions on Circuits and Systems, 52(4):785-793, April
2005.
- [1829]
- Y.-J. Huang and J.-F. Li.
Built-in self-repair scheme for the tsvs in 3-D ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(10):1600-1613, October 2012.
- [1830]
- T.-W. Huang and M.-D.-F.
Wong.
Accelerated path-based timing analysis with mapreduce.
In ACM International Symposium on Physical Design 2015, pages
103-110, Monterey, California, March 29 - April 1 2015.
- [1831]
- T.-W. Huang and M.-D.-F.
Wong.
UI-timer 1.0: an ultrafast path-based timing analysis algorithm for CPPR.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(11):1862-1875, November 2016.
- [1832]
- S. Huda and
A. Sheikholeslami.
A novel STT-MRAM cell with disturbance-free read operation.
IEEE Transactions on Circuits and Systems, 60(6):1534-1547, June
2013.
- [1833]
- F. Huebbers,
A. Dasdan, and Y. I. Ismail.
Computation of accurate interconnect process parameter values for performance
corners under process variations.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
797-800, San Francisco, CA, July 24-28 2006.
- [1834]
- F. Huebbers,
A. Dasdan, and Y. I. Ismail.
Multi-layer interconnect performance corners for variation-aware timing
analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 713-718, San Jose, CA, November 5-8 2007.
- [1835]
- D. A. Huffman.
A method for the construction of minimum-redundancy codes.
In Proceedings of the IRE, pages 1098-1101, September 1952.
- [1836]
- L. M. Huisman.
Diagnosing arbitrary defects in logic designs using single location at a time
(SLAT).
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):91-101, January 2004.
- [1837]
- C. M. Huizer.
Power dissipation analysis of CMOS VLSI circuits by means of switch- level
simulation.
In IEEE European Solid State Circuits Conference, pages 61-64,
Grenoble, France, 1990.
- [1838]
- H. Hulgaard,
P. F. Williams, and H. R. Andersen.
Equivalence checking of combinational circuits using boolean expression
diagrams.
IEEE Transactions on Computer-Aided Design, 18(7):903-917, July
1999.
- [1839]
- W. Hung, Y. Xie,
N. Vijaykrishnan, M. Kandemir, M. J. Irwin, and Y. Tsai.
Total power optimization through simultaneously multiple-VDD multiple-VTH
assignment and device sizing with stack forcing.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 144-149, Newport Beach, CA, August 9-11 2004.
- [1840]
- W.-N.-N. Hung,
X. Song, G. Yang, J. Yang, and M. Perkowski.
Quantum logic synthesis by symbolic reachability analysis.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
838-841, San Diego, CA, June 7-11 2004.
- [1841]
- W.-N.-N. Hung,
X. Song, G. Yang, J. Yang, and M. Perkowski.
Optimal synthesis of multiple output boolean functions using a set of quantum
gates by symbolic reachability analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1652-1663, September 2006.
- [1842]
- S. L. Hurst, D. M.
Miller, and J. C. Muzio.
Spectral Techniques in Digital Logic.
Academic Press Inc., Orlando, FL, 1985.
- [1843]
- S. L. Hurst.
The logical processing of digital signals.
Crane, Russack & Company, Inc., New York, NY, 1978.
- [1844]
- A. P. Hurst.
Automatic synthesis of clock gating logic with controlled netlist perturbation.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
654-657, Anaheim, CA, June 8-13 2008.
- [1845]
- A. Hussain.
Models for interconnect capacitance extraction.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 167-172, San Jose, CA, March 26-28 2001.
- [1846]
- M. D. Hutton,
J. S. Rose, and D. G. Corneil.
Automatic generation of synthetic sequential benchmark circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(8):928-940, August 2002.
- [1847]
- S. H. Hwang,
Y. H. Kim, and A. R. Newton.
An accurate delay modeling technique for switch-level timing verification.
In IEEE 23rd Design Automation Conference, pages 227-233, 1986.
- [1848]
- M.-E. Hwang,
T. Cakici, and K. Roy.
Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling.
Design, Automation and Test in Europe (DATE-07), pages 1550-1555,
April 16-20 2007.
- [1849]
- M.-E. Hwang,
S.-O. Jung, and K. Roy.
Slope interconnect effort: gate-interconnect interdependent delay model for
CMOS logic gates with scaled supply voltage.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 387-390, Portland, Oregon, August 27-29 2007.
- [1850]
- M.-E. Hwang, S.-O.
Jung, and K. Roy.
Slope interconnect effort: gate-interconnect interdependent delay modeling for
early CMOS circuit simulation.
IEEE Transactions on Circuits and Systems, 56(7):1427-1440, July
2009.
- [1851]
- Y.-T. Hwang, J.-F.
Lin, and M.-H. Sheu.
Low-power pulse-triggered flip-flop design with conditional pulse-enhancement
scheme.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):361-366, February 2012.
- [1852]
- E.-J. Hwang,
W. Kim, and Y.-H. Kim.
Timing yield slack for timing yield-constrained optimization and its
application to statistical leakage minimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1783-1796, October 2013.
- [1853]
- K. S. Hwang and M. R.
Mercer.
Derivation and refinement of fan-out constraints to generate tests in
combinational logic circuits.
IEEE Transactions on Computer-Aided Design, CAD-5(4):564-572, October
1986.
- [1854]
- J. P. Hwang.
REX - A VLSI parasitic extraction tool for electromigration and signal
analysis.
In 28th ACM/IEEE Design Automation Conference, pages 717-722,
1991.
- [1855]
- R. Hyman,
N. Ranganathan, T. Bingel, and D.-T. Vo.
A clock control strategy for peak power and RMS current reduction using path
clustering.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(2):259-269, February 2013.
- [1856]
- O. H. Ibarra and S. K.
Sahni.
Polynomially complete fault detection problems.
IEEE Transactions on Computers, C-24(3):242-249, March 1975.
- [1857]
- W. Ibrahim,
V. Beiu, and A. Beg.
GREDA: a fast and more accurate gate reliability EDA tool.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):509-521, April 2012.
- [1858]
- K. Ibuki,
K. Naemura, and A. Nozaki.
General theory of complete sets of logical functions.
Electronics and Communications in Japan, (IEEE Translation),
46(7):55-65, July 1963.
- [1859]
- M. Igarashi,
K. Usami, K. Nogami, F. Minami, Y. Kawasaki, T. Aoki, M. Takano, C. Mizuno,
T. Ishikawa, M. Kanazawa, S. Sonoda, M. Ichida, and N. Hatanaka.
A low-power design method using multiple supply voltages.
In 1997 International Symposium on Low Power Electronics and Design,
pages 36-41, Monterey, CA, August 18-20 1997.
- [1860]
- T. Iizuka,
M. Ikeda, and K. Asada.
Timing-aware cell layout de-compaction for yield optimization by critical area
minimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(6):716-720, June 2007.
- [1861]
- A. Ilumoka.
Chip level signal integrity analysis & crosstalk prediction using artificial
neural nets.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 175-180, San Jose, CA, March 18-21 2002.
- [1862]
- H. Im, T. Inukai,
H. Gomyo, T. Hiramoto, and T. Sakurai.
VTCMOS characteristics and its optimum conditions predicted by a compact
analytical model.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 123-128, Huntington Beach, California, August 6-7
2001.
- [1863]
- H. Im, T. Inukai,
H. Gomyo, T. Hiramoto, and T. Sakurai.
VTCMOS characteristics and its optimum conditions predicted by a compact
analytical model.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(5):755-761, October 2003.
- [1864]
- Y. Im and K. Roy.
Cash: A novel "clock as shield" design methodology for noise immune
precharge-evaluate logic.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 337-341, San Jose, CA, November 4-8 2001.
- [1865]
- Y. Im and K. Roy.
O2aba: A novel high-performance predictable circuit architecture for the deep
submicron era.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):221-229, June 2002.
- [1866]
- M. Imai, T. Sato,
N. Nakayama, and K. Masu.
Non-parametric statistical static timing analysis: an SSTA framework for
arbitrary distribution.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
698-701, Anaheim, CA, June 8-13 2008.
- [1867]
- S. Iman and M. Pedram.
Multi-level network optimization for low power.
In IEEE/ACM International Conference on Computer-Aided Design, pages
372-377, San Jose, CA, November 6-10 1994.
- [1868]
- S. Iman and M. Pedram.
Logic extraction and factorization for low power.
In 32nd Design Automation Conference, pages 248-253, San Francisco,
CA, June 12-16 1995.
- [1869]
- S. Iman and M. Pedram.
Two-level logic minimization for low power.
In IEEE/ACM International Conference on Computer-Aided Design, pages
433-438, San Jose, CA, November 5-9 1995.
- [1870]
- S. Iman and M. Pedram.
An approach for multilevel logic optimization targeting low power.
IEEE Transactions on Computer-Aided Design, 15(8):889-901, August
1996.
- [1871]
- S. Iman and M. Pedram.
POSE: Power optimization and synthesis environment.
In 33rd Design Automation Conference, pages 21-26, Las Vegas, NV,
June 3-7 1996.
- [1872]
- C. Inacio,
H. Schmit, D. Nagle, A. Ryan, D. E. Thomas, Y. Tong, and B. Klass.
Vertical benchmarks for CAD.
In Design Automation Conference, pages 408-413, New Orleans, LA, June
21-25 1999.
- [1873]
- T. Inukai,
T. Hiramoto, and T. Sakurai.
Variable threshold voltage CMOS (VTCMOS) in series connected circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 201-206, Huntington Beach, California, August 6-7
2001.
- [1874]
- R. Ionutiu,
J. Rommes, and W. H. A. Schilders.
Sparserc: sparsity preserving model reduction for RC circuits with many
terminals.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(12):1828-1841, December 2011.
- [1875]
- I. C. F. Ipsen and C. D.
Meyer.
The idea behind krylov methods.
American Mathematical Monthly, 105(10):889-899, December 1998.
- [1876]
- N. Iqbal and J. Henkel.
SETS: stochastic execution time scheduling for multicore systems by joint
state space and monte carlo.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 123-130, San Jose, CA, November 7-11 2010.
- [1877]
- S. Irani,
G. Singh, S. K. Shukla, and R. K. Gupta.
An overview of the competitive and adversarial approaches to designing dynamic
power management strategies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(12):1349-1361, December 2005.
- [1878]
- A. Iranli and
M. Pedram.
Cycle-based decomposition of markov chains with applications to low-power
synthesis and sequence compaction for finite state machines.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2712-2725, December 2006.
- [1879]
- F. Ishihara,
F. Sheikh, and B. Nikolic.
Level conversion for dual-supply systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(2):185-195, February 2004.
- [1880]
- T. Ishihara and
H. Yasuura.
Basic experimentation on accuracy of power estimation for CMOS VLSI
circuits.
In International Symposium on Low Power Electronics and Design, pages
117-120, Monterey, CA, August 12-14 1996.
- [1881]
- R. Islam,
A. Brand, and D. Lippincott.
Low power SRAM techniques for handheld products.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 198-202, San Diego, CA, August 8-10 2005.
- [1882]
- A. A. Ismaeel and
M. A. Breuer.
The probability of error detection in sequential circuits using random test
vectors.
Journal of Electronic Testing, 1:245-256, January 1991.
- [1883]
- Y. I. Ismail,
E. G. Friedman, and J. L. Neves.
Figures of merit to characterize the importance of on-chip inductance.
In IEEE/ACM 35th Design Automation Conference, pages 560-565, San
Francisco, CA, June 15-19 1998.
- [1884]
- Y. I. Ismail,
E. G. Friedman, and J. L. Neves.
Power dissipated by CMOS gates driving lossless transmission lines.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 139-141, Monterey, CA, August 10-12 1998.
- [1885]
- Y. I. Ismail,
E. G. Friedman, and J. L. Neves.
Equivalent elmore delay for RLC trees.
In Design Automation Conference, pages 715-720, New Orleans, LA, June
21-25 1999.
- [1886]
- Y. I. Ismail,
E. G. Friedman, and J. L. Neves.
Equivalent elmore delay for RLC trees.
IEEE Transactions on Computer-Aided Design, 19(1):83-97, January
2000.
- [1887]
- M. Ismail,
O. Hasan, T. Ebi, M. Shafique, and J. Henkel.
Formal verification of distributed dynamic thermal management.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 248-255, San Jose, CA, November 18-21 2013.
- [1888]
- Y. I. Ismail and C. S.
Amin.
Computation of signal-threhold crossing times directly from higher order
moments.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1264-1276, August 2004.
- [1889]
- Y. I. Ismail and C. S.
Amin.
Computation of signal threshold crossing times directly from higher order
moments.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 246-253, San Jose, CA, November 7-11 2004.
- [1890]
- Y. I. Ismail and
E. G. Friedman.
DTT: Direct truncation of the transfer function - an alternative to moment
matching for tree structured interconnect.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(2):131-144, February 2002.
- [1891]
- Y. I. Ismail.
On-chip inductance cons and pros.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):685-694, December 2002.
- [1892]
- Y. I. Ismail.
Improved model-order reduction by using spacial information in moments.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(5):900-908, October 2003.
- [1893]
- K. Itoh, K. Osada,
and T. Kawahara.
Trends in low-voltage embedded rams.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 45-48, Montreal, Quebec, June 20-23 2004.
- [1894]
- K. Itoh.
Low-voltage memories for power-aware systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 1-6, Monterey, California, August 12-14 2002.
- [1895]
- K. Itoh.
Low-voltage embedded rams in the nanometer era.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 235-242, Austin, TX, May 9 - 11 2005.
- [1896]
- A. Iyer and
D. Marculescu.
Microarchitecture-level power management.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):230-239, June 2002.
- [1897]
- A. Iyer and
D. Marculescu.
Power efficiency of voltage scaling in multiple clock, multiple voltage cores.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 379-386, San Jose, CA, November 10-14 2002.
- [1898]
- R. K. Iyer.
Hierarchical application aware error detection and recovery.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 79-79,
San Diego, CA, June 7-11 2004.
- [1899]
- R. Jacobi,
N. Calazans, and C. Trullemans.
Incremental reduction of binary decision diagrams.
In IEEE International Symposium on Circuits and Systems, pages
3174-3177, June 1991.
- [1900]
- M. Jacome,
C. He, G. de Veciana, and S. Bijansky.
Defect tolerant probabilistic design paradigm for nanotechnologies.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
596-601, San Diego, CA, June 7-11 2004.
- [1901]
- N. Jafarzadeh, M. Palesi, A. Khademzadeh, and A. Afzali-Kusha.
Data encoding techniques for reducing energy consumption in network-on-chip.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(3):675-685, March 2014.
- [1902]
- J. Jaffair and M. Anis.
On efficient LHS-based yield analysis of analog circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(1):159-163, January 2011.
- [1903]
- J. Jaffari and M. Anis.
Variability-aware device optimization under ion and leakage current
constraints.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 119-122, Tegernsee, Germany, October 4-6 2006.
- [1904]
- J. Jaffari and
M. Anis.
On efficient monte carlo-based statistical static timing analysis of digital
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 196-203, San Jose, CA, November 10-13 2008.
- [1905]
- J. Jaffari and
M. Anis.
Statistical thermal profile considering process vairations: analysis and
applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(6):1027-1040, June 2008.
- [1906]
- J. Jaffari and M. Anis.
Advanced variance reduction and sampling techniques for efficient statistical
timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(12):1894-1907, December 2010.
- [1907]
- U. Jagau.
SIMCURRENT - an efficient program for the estimation of the current flow of
complex CMOS circuits.
In IEEE International Conference on Computer-Aided Design (ICCAD),
pages 396-399, Santa Clara, CA, Nov. 11-15 1990.
- [1908]
- J. Jain, J. Bitner,
D. S. Fussell, and J. A. Abraham.
Probabilistic design verification.
In IEEE International Conference on Computer-Aided Design, pages
468-471, Santa Clara, CA, November 11-14 1991.
- [1909]
- S. Jain, R. E.
Bryant, and A. Jain.
Automatic clock abstraction from sequential circuits.
In 32nd Design Automation Conference, pages 707-711, San Francisco,
CA, June 12-16 1995.
- [1910]
- J. Jain, C.-K. Koh,
and V. Balakrishnan.
Fast simulation of VLSI interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 93-98, San Jose, CA, November 7-11 2004.
- [1911]
- A. Jain, D. Blaauw,
and V. Zolotov.
Accurate delay computation for noisy waveform shapes.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 947-953, San Jose, CA, November 6-10 2005.
- [1912]
- P. Jain, F. Cano,
B. Pudi, and N. V. Arvind.
Asymmetric aging: introduction and solution for power-managed mixed-signal
socs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(3):691-695, March 2014.
- [1913]
- P. Jain, S. S.
Sapatnekar, and J. Cortadella.
A retargetable and accurate methodology for logic-IP-internal
electromigration assessment.
In 20th Asia and South Pacific Design Automation Conference, pages
346-351, Chiba/Tokyo, Japan, January 19-22 2015.
- [1914]
- S. K. Jain and V. D.
Agrawal.
Test generation for MOS circuits using D-algorithm.
In IEEE 20th Design Automation Conference, pages 64-70, Miami Beach,
FL, June 27-29 1983.
- [1915]
- S. K. Jain and V. D.
Agrawal.
STAFAN: an alternative to fault simulation.
In IEEE 21st Design Automation Conference, pages 18-23, 1984.
- [1916]
- P. Jain and A. Jain.
Accurate current estimation for interconnect reliability analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(9):1634-1644, September 2012.
- [1917]
- R. Jakushokas
and E. G. Friedman.
Multi-layer interdigitated power distribution networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(5):774-786, May 2011.
- [1918]
- R. Jakushokas
and E. G. Friedman.
Power network optimization based on link breaking methodology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(5):983-987, May 2013.
- [1919]
- S. Jallepalli, R. Mooraka, S. Parihar, E. Hunter, and
E. Maalouf.
Employing scaled sigma sampling for efficient estimation of rare event
probabilities in the absence of input domain mapping.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(6):943-956, June 2016.
- [1920]
- S. Jallepalli, R. Mooraka, S. Parihar, E. Hunter, and
E. Maalouf.
Rapid assessment of design sensitivity to process excursions via scaled sigma
sampling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(6):957-970, June 2016.
- [1921]
- M. H. B. Jamaa,
K. E. Moselund, D. Atienza, D. Bouvet, A. M. Ionescu, Y. Leblebici, and G. De
Micheli.
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 765-772, San Jose, CA, November 5-8 2007.
- [1922]
- M. H. Ben Jamaa,
Y. Leblebici, and G. De Micheli.
Decoding nanowire arrays fabricated with the multi-spacer patterning technique.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 77-82,
San Francisco, CA, July 26-31 2009.
- [1923]
- F. James.
Monte carlo theory and practice.
Reports on Progress in Physics, 43:1145-1189, 1980.
- [1924]
- P. Jamieson and
J. Rose.
Mapping multiplexers onto hard multipliers in fpgas.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 323-326, Quebec City, Quebec, June 19-22 2005.
- [1925]
- P. A. Jamieson and
J. Rose.
Enhancing the area efficiency of fpgas with hard circuits using shadow
clusters.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(12):1696-1709, December 2010.
- [1926]
- R. K. Jana, G. L.
Snider, and D. Jena.
Energy-efficient clocking based on resonant switching for low-power
computation.
IEEE Transactions on Circuits and Systems, 61(5):1400-1408, May
2014.
- [1927]
- V. Janakiraman, A. Bharadwaj, and V. Visvanathan.
Voltage and temperature aware statistical leakage analysis framework using
artificial neural networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(7):1056-1069, July 2010.
- [1928]
- V. Jandhyala.
Physics-based field-theoretic design automation tools for social networks and
web search.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
280-281, San Diego, CA, June 5-9 2011.
- [1929]
- J.-W. Jang, S.-B.
Choi, and V. K. Prasanna.
Energy- and time-efficient matrix multiplication on fpgas.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1305-1319, November 2005.
- [1930]
- H. Jang and T. Kim.
Simultaneous clock buffer sizing and polarity assignment for power/ground noise
minimization.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
794-799, San Francisco, CA, July 26-31 2009.
- [1931]
- K. Jasrotia and
J. Zhu.
Stacked FSMD: a power efficient micro-architecture for high level synthesis.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 425-432, San Jose, CA, March 22-24 2004.
- [1932]
- H. Javaid,
A. Ignjatovic, and S. Parameswaran.
Fidelity metrics for estimation models.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 1-8, San Jose, CA, November 7-11 2010.
- [1933]
- N. Jayakumar, S. Dhar, and S. P. Khatri.
A self-adjusting scheme to determine the optimum RBB by monitoring leakage
currents.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 43-46,
Anaheim, CA, June 13-17 2005.
- [1934]
- N. Jayakumar and
S. P. Khatri.
An ASIC design methodology with predictably low leakage, using leakage-immune
standard cells.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 128-133, Seoul, Korea, August 25-27 2003.
- [1935]
- N. Jayakumar and
S. P. Khatri.
A variation-tolerant sub-threshold design approach.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
716-719, Anaheim, CA, June 13-17 2005.
- [1936]
- N. Jayakumar and
S. P. Khatri.
An algorithm to minimize leakage through simultaneous input vector control and
circuit modification.
Design, Automation and Test in Europe (DATE-07), pages 618-623, April
16-20 2007.
- [1937]
- R. Jejurikar, C. Pereira, and R. Gupta.
Leakage aware dynamic voltage scaling for real-time embedded systems.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
275-280, San Diego, CA, June 7-11 2004.
- [1938]
- G. Jennings and
E. Jennings.
A discrete syntax for level-sensitive latched circuits having n clocks and m
phases.
IEEE Transactions on Computer-Aided Design, 15(1):111-126, January
1996.
- [1939]
- D. Jenson and
M. Riedel.
A deterministic approach to stochastic computation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [1940]
- S-W. Jeong,
B. Plessier, G. Hachtel, and F. Somenzi.
Extended bdds: trading off canonicity for structure in verification algorithms.
In IEEE International Conference on Computer-Aided Design, pages
464-467, Santa Clara, CA, November 11-14 1991.
- [1941]
- K. Jeong, A. B.
Kahng, C.-H. Park, and H. Yao.
Dose map and placement co-optimization for timing yield enhancement and leakage
power reduction.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
516-521, Anaheim, CA, June 8-13 2008.
- [1942]
- K. Jeong, A. B.
Kahng, C.-H. Park, and H. Yao.
Dose map and placement co-optimization for improved timing yield and leakage
power.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(7):1070-1082, July 2010.
- [1943]
- G. Jerke,
J. Lienig, and J. Scheible.
Reliability-driven layout decompaction for electromigration failure avoidance
in complex mixed-signal IC designs.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
181-184, San Diego, CA, June 7-11 2004.
- [1944]
- G. Jerke and J. Lienig.
Hierarchical current-density verification in arbitrarily shaped metallization
patterns of analog circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):80-90, January 2004.
- [1945]
- J. A. G. Jess,
K. Kalafala, W. R. Naidu, R. H. J. M. Otten, and C. Visweswariah.
Statistical timing for parametric yield prediction of digital integrated
circuits.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
932-937, Anaheim, CA, June 2-6 2003.
- [1946]
- J. A. G. Jess,
K. Kalafala, S. R. Naidu, R. H. J. M. Otten, and C. Visweswariah.
Statistical timing for parametric yield prediction of digital integrated
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2376-2392, November 2006.
- [1947]
- J. A. G. Jess.
Designing electronic engines with electronic engines: 40 years of bootstrapping
of a technology upon itself.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1404-1427, December 2000.
- [1948]
- M. Jessa and
M. Walentynowicz.
Statistical properties of number sequences generated by 1d chaotic maps
considered as a potential source of pseudorandom number sequences.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 449-455, St. Julian, Malta, September 2-5 2001.
- [1949]
- N. K. Jha.
Low power system scheduling and synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 259-263, San Jose, CA, November 4-8 2001.
- [1950]
- T. Jhaveri,
V. Rovner, L. Liebmann, L. Pileggi, A. J. Strojwas, and J. D. Hibbeler.
Co-optimization of circuits, layout and lithography for predictive technology
scaling beyond gratings.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):509-527, April 2010.
- [1951]
- Y-M Jiang, K-T
Cheng, and A. Krstic.
Estimation of maximum power and instantaneous current using a genetic
algorithm.
In IEEE 1997 Custom Integrated Circuits Conference, pages 135-138,
Santa Clara, CA, May 5-8 1997.
- [1952]
- Y-M. Jiang, K-T.
Cheng, and A-C. Deng.
Estimation of maximum power supply noise for deep sub-micron designs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 233-238, Monterey, CA, August 10-12 1998.
- [1953]
- Y.-M. Jiang,
T. K. Young, and K.-T. Cheng.
VIP - an input pattern generator for identifying critical voltage drop for
deep sub-micron designs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 156-161, San Diego, CA, August 16-17 1999.
- [1954]
- Y.-M. Jiang,
A. Krstic, and K.-T. Cheng.
Estimation of maximum instantaneous current through supply lines for CMOS
circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(1):61-73, February 2000.
- [1955]
- Y-M Jiang,
A. Krstic, and K-T (Tim) Cheng.
Dynamic timing analysis considering power supply noise effects.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 137-143, San Jose, CA, March 20-22 2000.
- [1956]
- Y.-M. Jiang, H.-Y.
Koh, and K.-T. Cheng.
HRM - A hierarchical simulator for full-chip power network reliability
analysis.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 307-312, San Jose, CA, March 26-28 2001.
- [1957]
- R. Jiang, W. Fu,
J.-M. Wang, V. Lin, and C. C.-P. Chen.
Efficient statistical capacitance variability modeling with orthogonal
principle factor analysis.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 683-690, San Jose, CA, November 6-10 2005.
- [1958]
- Z. Jiang, S. Hu,
and W. Shi.
A new twisted differential line structure in global bus design.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
180-183, San Diego, CA, June 4-8 2007.
- [1959]
- I. H.-R. Jiang,
H.-Y. Chang, L.-G. Chang, and H.-B. Hung.
New spare cell design for IR drop minimization in engineering change order.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
408-411, San Francisco, CA, July 26-31 2009.
- [1960]
- J.-H. R. Jiang,
H.-P. Lin, and W.-L. Hung.
Interpolating functions from large boolean relations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 779-784, San Jose, CA, November 2-5 2009.
- [1961]
- I.-H.-R. Jiang,
G.-J. Nam, H.-Y. Chang, S. R. Nassif, and J. Hayes.
Smart grid load balancing techniques via simultaneous switch/tie-line/wire
configurations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 382-388, San Jose, CA, November 2-6 2014.
- [1962]
- J.-H. R. Jiang and R. K.
Brayton.
On the verification of sequential equivalence.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(6):686-697, June 2003.
- [1963]
- J.-H.-R. Jiang and R. K.
Brayton.
Retiming and resynthesis: a complexity perspective.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2674-2686, December 2006.
- [1964]
- I.-H.-R. Jiang and H.-Y.
Chang.
Wit: optimal wiring topology for electromigration avoidance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(4):581-592, April 2012.
- [1965]
- Y.-L. Jiang and H.-B.
Chen.
Application of general orthogonal polynomials to fast simulation of nonlinear
descriptor systems through piecewise-linear approximation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(5):804-808, May 2012.
- [1966]
- Y.-M. Jiang and K.-T.
Cheng.
Analysis of performance impact cause by power supply noise in deep submicron
devices.
In Design Automation Conference, pages 760-765, New Orleans, LA, June
21-25 1999.
- [1967]
- Y.-M. Jiang and K. T.
Cheng.
Vector generation for power supply noise estimation and verification of deep
submicron designs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(2):329-340, April 2001.
- [1968]
- X. Jiang and
S. Horiguchi.
Statistical skew modeling for general clock distribution networks in presence
of process variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(5):704-717, October 2001.
- [1969]
- H. Jiang and
M. Marek-Sadowska.
Power gating scheduling for power/ground noise reduction.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
980-985, Anaheim, CA, June 8-13 2008.
- [1970]
- R. Jiang and D. N. P.
Murthy.
The exponentiated weibull family: A graphical approach.
IEEE Transactions on Reliability, 48(1):68-72, March 1999.
- [1971]
- Y.-L. Jiang.
A general approvah to waveform relaxation solutions of nonlinear
differential-algebraic equations: the continuous-time and discrete-time
cases.
IEEE Transactions on Circuits and Systems, 51(9):1770-1780, September
2004.
- [1972]
- W. Jigang,
T. Srikanthan, and X. Han.
Preprocessing and partial rerouting techniques for accelerating reconfiguration
of degradable VLSI arrays.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):315-319, February 2010.
- [1973]
- W. Jin, P. C. H. Chan,
and M. Chan.
On the power dissipation in dynamic threshold silicon-on-insulator CMOS
inverter.
In 1997 International Symposium on Low Power Electronics and Design,
pages 247-250, Monterey, CA, August 18-20 1997.
- [1974]
- H.-S. Jin, M.-S. Jang,
J.-S. Song, J.-Y. Lee, T.-S. Kim, and J.-T. Kong.
Dynamic power estimation using the probabilistic contribution measure (PCM).
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 279-281, San Diego, CA, August 16-17 1999.
- [1975]
- T. Jindal, C. J.
Alpert, J. Hu, Z. Li, G.-J. Nam, and C. B. Winn.
Detecting tangled logic structures in VLSI netlists.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
603-608, Anaheim, CA, June 13-18 2010.
- [1976]
- G. Jochens,
L. Kruse, E. Schmidt, and W. Nebel.
A new parametrizable power macro-model for datapath components.
IEEE Design Automation and Test in Europe (DATE), pages 29-36,
1999.
- [1977]
- J. John and C. Riddle.
Smart phone power.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
935-936, Anaheim, CA, June 13-18 2010.
- [1978]
- M. Johnson,
D. Somasekhar, and K. Roy.
Leakage control with efficient use of transistor stacks in single threshold
CMOS.
In Design Automation Conference, pages 442-445, New Orleans, LA, June
21-25 1999.
- [1979]
- M. C.
Johnson, D. Somasekhar, and K. Roy.
Models and algorithms for bounds on leakage in CMOS circuits.
IEEE Transactions on Computer-Aided Design, 18(6):714-725, June
1999.
- [1980]
- M. C. Johnson,
D. Somasekhar, L.-Y. Chiou, and K. Roy.
Leakage control with efficient use of transistor stacks in single threshold
CMOS.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(1):1-5, February 2002.
- [1981]
- Norman L. Johnson and
Samuel Kotz.
Continuous Univariate Distributions, volume 1 and 2.
John Wiley & Sons, New York, NY, 1970.
- [1982]
- Norman L. Johnson and
Samuel Kotz.
Discrete Distributions.
John Wiley & Sons, New York, NY, 1970.
- [1983]
- J. Jones and J. Hayes.
A comparison of electronic-reliability prediction models.
IEEE Transactions on Reliability, 48(2):127-134, June 1999.
- [1984]
- D. De Jonghe and
G. Gielen.
Efficient analytical macromodeling of large analog circuits by transfer
function trajectories.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 91-94, San Jose, CA, November 7-10 2011.
- [1985]
- D. De Jonghe and
G. Gielen.
Characterization of analog circuits using transfer function trajectories.
IEEE Transactions on Circuits and Systems, 59(8):1796-1804, August
2012.
- [1986]
- Y. Joo, Y. Choi, and
H. Shim.
Energy exploration and reduction of SDRAM memory systems.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
892-897, New Orleans, LA, June 10-14 2002.
- [1987]
- R. Joseph,
Z. Hu, and M. Martonosi.
Wavelet analysis for microprocessor design: Experiences with wavelet-based
di/dt characterization.
In 10th International Symposium on High Performance Computer Architecture
(HPCA-04), pages 36-46, Madrid, Spain, Feb. 14-18 2004.
- [1988]
- A. Joseph,
A. Haridass, C. Lefurgy, S. Pai, S. Rachamalla, and F. Campisano.
Freqleak: a frequency step based method for efficient leakage power
characterization in a system.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 195-200, Rome, Italy, July 22-24 2015.
- [1989]
- V. Joshi,
D. Blaauw, and D. Sylvester.
Soft-edge flip-flops for improved timing yield: design and optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 667-673, San Jose, CA, November 5-8 2007.
- [1990]
- V. Joshi,
B. Cline, D. Sylvester, D. Blaauw, and K. Agarwal.
Leakage power reduction using stress-enhanced layouts.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
912-917, Anaheim, CA, June 8-13 2008.
- [1991]
- R. Joshi, R. Kanj,
P. Wang, and H. Li.
Universal statistical cure for predicting memory loss.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 236-239, San Jose, CA, November 7-10 2011.
- [1992]
- S. Joshi and S. Boyd.
An efficient method for large-scale gate sizing.
IEEE Transactions on Circuits and Systems, 55(9):2760-2773, October
2008.
- [1993]
- N. P. Jouppi.
TV: An nmos timing analyzer.
In 3rd Caltech Conference on VLSI, pages 71-85, 1983.
- [1994]
- N. P. Jouppi.
Derivation of signal flow direction in MOS VLSI.
IEEE Transactions on Computer-Aided Design, CAD-6(3):480-490, May
1987.
- [1995]
- N. P. Jouppi.
Timing analysis and performance improvements of MOS VLSI designs.
IEEE Transactions on Computer-Aided Design, CAD-6(4):650-665, July
1987.
- [1996]
- J. W. Joyner,
P. Zarkesh-Ha, and J. D. Meindl.
Global interconnect design in a three-dimensional system-on-a-chip.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):367-372, April 2004.
- [1997]
- Y-C Ju, V. B. Rao, and
R. A. Saleh.
Consistency checking and optimization of time-domain macromodels.
Submitted to ICCAD-89, rejected., 1989.
- [1998]
- Y-C. Ju, V. B. Rao, and
R. A. Saleh.
Consistency checking and optimization of macromodels.
IEEE Transactions on Computer-Aided Design, 10(8):957-967, August
1991.
- [1999]
- D.-C. Juan, Y.-T.
Chen, M.-C. Lee, and S.-C. Chang.
An efficient wake-up strategy considering spurious glitches phenomenon for
power gating designs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):246-255, February 2010.
- [2000]
- P. Julian.
The complete canonical piecewise-linear representation: functional form for
minimal degenerate intersections.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(3):387-396, March 2003.
- [2001]
- Y-H. Jun, K. Jun, and
S-B. Park.
An accurate and efficient delay time modeling for MOS logic circuits using
polynomial approximation.
IEEE Transactions on Computer-Aided Design, 8(9):1027-1032, September
1989.
- [2002]
- S.-O. Jung, K.-W.
Kim, and S.-M. (Steve) Kang.
Noise constrained transistor sizing and power optimization for dual vt domino
logic.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):532-541, October 2002.
- [2003]
- S.-O. Jung, K.-W.
Kim, and S.-M. Kang.
Timing constraints for domino logic gates with timing-dependent keepers.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(1):96-104, January 2003.
- [2004]
- K. Jung, W. R.
Eisenstadt, and R. M. Fox.
SPICE-based mixed-model S-parameter calculations for four-port and
three-port circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):909-913, May 2006.
- [2005]
- H. Jung, P. Rong,
and M. Pedram.
Stochastic modeling of a thermally-managed multi-core system.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
728-733, Anaheim, CA, June 8-13 2008.
- [2006]
- M. Jung, J. Mitra,
D.-Z. Pan, and S.-K. Lim.
TSV stress-aware full-chip mechanical reliability analysis and optimization
for 3d IC.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
188-193, San Diego, CA, June 5-9 2011.
- [2007]
- M. Jung, D. Pan,
and S.-K. Lim.
Chip/package co-analysis of thermo-mechanical stress and reliability in
TSV-based 3-D ics.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
317-326, San Francisco, CA, June 3-7 2012.
- [2008]
- S. Jung, Y. Choi,
and J. Kim.
Variability-aware, discrete optimization for analog circuits.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
536-541, San Francisco, CA, June 3-7 2012.
- [2009]
- M. Jung, D. Z. Pan,
and S. K. Lim.
Chip/package mechanical stress impact on 3-D IC reliability and mobility
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(11):1694-1707, November 2013.
- [2010]
- J. Jung, I.-H.-R
Jiang, G.-J. Nam, V. N. Kravets, L. Behjat, and Y.-L. Li.
Opendesign flow database: the infrastructure for VLSI design and design
automation research.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [2011]
- J. Jung and T. Kim.
Variation-aware false path analysis based on statistical dynamic timing
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(11):1684-1697, November 2012.
- [2012]
- J. Jung and T. Kim.
Statistical viability analysis for detecting false paths under delay variation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):111-123, January 2013.
- [2013]
- H. Jung and M. Pedram.
Supervised learning based power management for multicore processors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(9):1395-1408, September 2010.
- [2014]
- H.-F. Jyu, S. Malik,
S. Devadas, and K. W. Keutzer.
Statistical timing analysis of combinational logic circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
1(2):126-137, June 1993.
- [2015]
- A. Kabbani,
D. Al-Khalili, and A. J. Al-Khalili.
Technology-portable analytical model for DSM CMOS inverter transition-time
estimation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(9):1177-1187, September 2003.
- [2016]
- A. Kabbani,
D. Al-Khalili, and A. J. Al-Khalili.
Delay analysis of CMOS gates using modified logical effort model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(6):937-947, June 2005.
- [2017]
- A. Kabbani and
A. J. Al-Khalili.
A technique for dynamic CMOS noise immunity evaluation.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(1):74-88, January 2003.
- [2018]
- D. Kagaris.
MOTO-X: a multiple-output transistor-level synthesis CAD tool.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(1):114-127, January 2016.
- [2019]
- B. Kagstrom.
Bounds and perturbation bounds for the matrix exponential.
BIT Numerical Mathematics, 17(1):39-57, March 1977.
- [2020]
- A. B. Kahng,
K. Masuko, and S. Muddu.
Analytical delay models for VLSI interconnects under ramp inputs.
In IEEE/ACM International Conference on Computer-Aided Design, pages
30-36, San Jose, CA, November 10-14 1996.
- [2021]
- A. B. Kahng,
S. Mantik, and D. Stroobandt.
Requirements for models of achievable routing.
In International Symposium on Physical Design, pages 4-11, San Diego,
CA, April 9-12 2000.
- [2022]
- A. B. Kahng,
S. Muddu, and E. Sarto.
On switch factor based analysis of coupled RC interconnects.
In Design Automation Conference, pages 79-84, Los Angeles, CA, June
5-9 2000.
- [2023]
- A. B. Kahng,
S. Muddu, N. Pol, and D. Vidhani.
Noise model for multiple segmented coupled RC interconnects.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 145-150, San Jose, CA, March 26-28 2001.
- [2024]
- A. B. Kahng,
B. Liu, and I. I. Mandoiu.
Non-tree routing for reliability and yield improvement.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 260-266, San Jose, CA, November 10-14 2002.
- [2025]
- A. B. Kahng,
B. Liu, and I. I. Mandoiu.
Non-tree routing for reliability and yield improvement.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):148-156, January 2004.
- [2026]
- A. B. Kahng,
S. Muddu, and P. Sharma.
Defocus-aware leakage estimation and control.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 263-268, San Diego, CA, August 8-10 2005.
- [2027]
- A. B. Kahng,
S. Reda, and Q. Wang.
Architecture and details of a high quality, large-scale analytical placer.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 891-898, San Jose, CA, November 6-10 2005.
- [2028]
- A. B. Kahng,
B. Liu, and Q. Wang.
Stochastic power/ground supply voltage prediction and optimization via
analytical placement.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(8):904-912, August 2007.
- [2029]
- A. B. Kahng,
B. Liu, and X. Xu.
Statistical timing analysis in the presence of signal-integrity effects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(10):1873-1877, October 2007.
- [2030]
- A. B. Kahng,
P. Sharma, and R. O. Topaloglu.
Exploiting STI stress for performance.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 83-90, San Jose, CA, November 5-8 2007.
- [2031]
- A. B. Kahng,
S. Muddu, and P. Sharma.
Defocus-aware leakage estimation and control.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):230-240, February 2008.
- [2032]
- A. B. Kahng,
S. Kang, H. Lee, I. L. Markov, and P. Thapar.
High-performance gate sizing with a signoff timer.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 450-457, San Jose, CA, November 18-21 2013.
- [2033]
- A. B. Kahng,
M. Luo, G.-J. Nam, S. Nath, D.-Z. Pan, and G. Robins.
Toward metrics of design automation research impact.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 263-270, Austin TX, November 2-6 2015.
- [2034]
- A. B. Kahng,
J. Li, and L. Wang.
Improved flop tray-based design implementation for power reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [2035]
- A. B. Kahng and
F. Koushanfar.
Evolving EDA beyond its e-roots: an overview.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 247-254, Austin TX, November 2-6 2015.
- [2036]
- A. B. Kahng and
S. Mantik.
Measurement of inherent noise in EDA tools.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 206-211, San Jose, CA, March 18-21 2002.
- [2037]
- A. B. Kahng and S. Muddu.
New efficient algorithms for computing effective capacitance.
In ACM/IEEE International Symposium on Physical Design, pages
147-151, Monterey, CA, April 6-8 1998.
- [2038]
- A. B. Kahng and S. Reda.
Intrinsic shortest path length: a new, accurate a priori wirelength estimator.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 173-180, San Jose, CA, November 6-10 2005.
- [2039]
- A. B. Kahng and
K. Samadi.
CMP fill synthesis: a survey of recent studies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(1):3-19, January 2008.
- [2040]
- A. B. Kahng.
The ITRS design technology and system drivers roadmap: process and status.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2041]
- A. B. Kahng.
New game, new goal posts: a recent history of timing closure.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [2042]
- T. Kailath.
Linear Systems.
Prentice-Hall, Englewood Cliffs, NJ, 1980.
- [2043]
- A. Kaizerman, S. Fisher, and A. Fish.
Subthreshold dual mode logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(5):979-983, May 2013.
- [2044]
- S. Kajihara and
K. Miyase.
On identifying don't care inputs of test patterns for combinational circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 364-369, San Jose, CA, November 4-8 2001.
- [2045]
- C. Kalonakis, C. Antoniadis, P. Giannakou, D. Dioudis,
G. Pinitas, and G. Stamoulis.
Tktimer: fast & accurate clock network pessimism removal.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 606-610, San Jose, CA, November 2-6 2014.
- [2046]
- T. Kam, S. Rawat,
D. Kirkpatrick, R. Roy, G. S. Spirakis, N. Sherwani, and C. Peterson.
EDA challenges facing future microprocessor design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1498-1506, December 2000.
- [2047]
- M. B. Kamble and
K. Ghose.
Analytical energy dissipation models for low power caches.
In 1997 International Symposium on Low Power Electronics and Design,
pages 143-148, Monterey, CA, August 18-20 1997.
- [2048]
- M. Kamon,
S. McCormick, and K. Shepard.
Interconnect parasitic extraction in the digital IC design methodology.
In IEEE/ACM International Conference on Computer-Aided Design, pages
223-230, San Jose, CA, November 7-11 1999.
- [2049]
- M. Kandemir,
N. Vijaykrishnana, M. J. Irwin, and W. Ye.
Influence of compile optimizations on system power.
In Design Automation Conference, pages 304-307, Los Angeles, CA, June
5-9 2000.
- [2050]
- A. Kanduri,
M.-H. Haghbayan, A. M. Rahmani, P. Liljeberg, A. Jantsch, N. Dutt, and
H. Tenhunen.
Approximation knob: power capping meets energy efficiency.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [2051]
- K. Kang, K. Kim,
A. E. Islam, M. A. Alam, and K. Roy.
Characterization and estimation of circuit reliability degradation under NBTI
using on-line IDDQ measurement.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
358-363, San Diego, CA, June 4-8 2007.
- [2052]
- K. Kang, K. Kim,
and K. Roy.
Variation resilient low-power circuit design methodology using on-chip phase
locked loop.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
934-939, San Diego, CA, June 4-8 2007.
- [2053]
- K. Kang, S.-P.
Park, K. Roy, and M. A. Alam.
Estimation of statistical variation in temporal NBTI degradation and its
impact on lifetime circuit performance.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 730-734, San Jose, CA, November 5-8 2007.
- [2054]
- K. Kang, S.-P. Park,
K. Kim, and K. Roy.
On-chip variability sensor using phase-locked loop for detecting and correcting
parametric timing failures.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):270-280, February 2010.
- [2055]
- M. Z. Kang and W. W-M Dai.
Arbitrary rectilinear block packing based on sequence pair.
In IEEE/ACM International Conference on Computer-Aided Design, pages
259-266, San Jose, CA, November 8-12 1998.
- [2056]
- S.-M. (Steve) Kang.
Elements of low power design for integrated systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 205-210, Seoul, Korea, August 25-27 2003.
- [2057]
- R. Kanj, T. Lehner,
B. Agrawal, and E. Rosenbaum.
Noise characterization of static CMOS gates.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
888-893, San Diego, CA, June 7-11 2004.
- [2058]
- R. Kanj, R. Joshi,
and S. Nassif.
Mixture importance sampling and its application to the analysis of SRAM
designs in the presence of rare failure events.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 69-72,
San Francisco, CA, July 24-28 2006.
- [2059]
- R. Kanj, R. Joshi,
C. Adams, J. Warnock, and S. Nassif.
An elegant hardware-corroborated statistical repair and test methodology for
conquering aging effects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 497-504, San Jose, CA, November 2-5 2009.
- [2060]
- R. Kanj, T. Li,
R. Joshi, K. Agarwal, A. Sadigh, D. Winston, and S. Nassif.
Accelerated statistical simulation via on-demand hermite spline interpolations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 353-360, San Jose, CA, November 7-10 2011.
- [2061]
- R. Kanj, R. Joshi,
Z. Li, J. Hayes, and S. Nassif.
Yield estimation via multi-cones.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1107-1112, San Francisco, CA, June 3-7 2012.
- [2062]
- R. Kanj and
E. Rosenbaum.
Critical evaluation of SOI design guidelines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(9):885-894, September 2004.
- [2063]
- P. Kannan,
S. Balachandran, and D. Bhatia.
On metrics for comparing interconnect estimation methods for fpgas.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):381-385, April 2004.
- [2064]
- P. Kannan and
D. Bhatia.
Interconnect estimation for fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(8):1523-1534, August 2006.
- [2065]
- I. Kantorovich and C. Honghton.
Effectiveness of on-die decoupling capacitance in improving chip performance.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 165-168, San Jose, CA, October 27-29 2008.
- [2066]
- A. Kanuma.
CMOS circuit optimization.
Solid State Electronics, 26(1):47-58, 1983.
- [2067]
- J. Kao,
A. Chandrakasan, and D. Antoniadis.
Transistor sizing issues and tool for multi-threshold CMOS technology.
In 34th Design Automation Conference, pages 409-414, Anaheim, CA,
June 9-13 1997.
- [2068]
- J. Kao, S. Narendra,
and A. Chandrakasan.
Subthreshold leakage modeling and reduction techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 141-148, San Jose, CA, November 10-14 2002.
- [2069]
- J. T. Kao and A. P.
Chandrakasan.
Dual-threshold voltage techniques for low-power digital circuits.
IEEE Journal of solid-state circuits, 35(7):1009-1017, July 2000.
- [2070]
- H. Kapadia,
G. De Micheli, and L. Benini.
Reducing switching activity on datapath buses with control-signal gating.
In IEEE Custom Integrated Circuits Conference, pages 589-592, Santa
Clara, CA, May 11-14 1998.
- [2071]
- H. Kapadia and
M. Horowitz.
Using partitioning to help convergence in the standard-cell design automation
methodology.
In Design Automation Conference, pages 592-597, New Orleans, LA, June
21-25 1999.
- [2072]
- A. Kapare,
H. Cherupalli, and J. Sartori.
Automated error prediction for approximate sequential circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [2073]
- A. Kapoor,
N. Jayakumar, and S. P. Khatri.
A novel clock distribution and dynamic de-skewing methodology.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 626-631, San Jose, CA, November 7-11 2004.
- [2074]
- A. Kapoor,
N. Jayakumar, and S. P. Khatri.
Dynamically de-skewable clock distribution methodology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(9):1220-1229, September 2008.
- [2075]
- A. Kapoor,
Y. Hu, and R. Bashirullah.
A current-density centric logical effort delay and power model for high-speed
CML gates.
IEEE Transactions on Circuits and Systems, 60(10):2618-2630, October
2013.
- [2076]
- B. Kapoor.
Improving the accuracy of circuit activity measurement.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
111-116, Napa, CA, April 24-27 1994.
- [2077]
- B. Kapoor.
Improving the accuracy of circuit activity measurement.
In 31st ACM/IEEE Design Automation Conference, pages 734-739, San
Diego, CA, June 6-10 1994.
- [2078]
- N. Kapre and A. DeHon.
SPICE: spatial processors interconnected for concurrent execution for
accelerating the SPICE circuit simulator using an FPGA.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(1):9-22, January 2012.
- [2079]
- S. Kapur and D. E. Long.
Large-scale full-wave simulation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
806-809, San Diego, CA, June 7-11 2004.
- [2080]
- I. Karafyllidis.
Design and simulation of a single-electron random-access memory array.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(9):1370-1375, September 2002.
- [2081]
- G. Karakonstantis, N. Banerjee, K. Roy, and C. Chakrabarti.
Design methodology to trade off power, output quality and error resiliency:
application to color interpolation filtering.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 199-204, San Jose, CA, November 5-8 2007.
- [2082]
- G. Karakonstantis, N. Bellas, C. Antonopoulos, G. Tziantzioulis,
V. Gupta, and K. Roy.
Significance driven computation on next-generation unreliable platforms.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
290-291, San Diego, CA, June 5-9 2011.
- [2083]
- S. K.
Karandikar and S. S. Sapatnekar.
Logical effort based technology mapping.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 419-422, San Jose, CA, November 7-11 2004.
- [2084]
- S. K.
Karandikar and S. S. Sapatnekar.
Fast comparisons of circuit implementations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(12):1329-1339, December 2005.
- [2085]
- S. K.
Karandikar and S. S. Sapatnekar.
Technology mapping using logical effort for solving the load-distribution
problem.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(1):45-58, January 2008.
- [2086]
- K. Karmarkar
and S. Tragoudas.
On-chip codeword generation to cope with crosstalk.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(2):237-250, February 2014.
- [2087]
- T. Karnik, C-C.
Teng, and S-M. Kang.
High-level hot carrier reliability-driven synthesis using macro-models.
In IEEE Custom Integrated Circuits Conference, pages 65-68, Santa
Clara, CA, May 1-4 1995.
- [2088]
- T. Karnik,
S. Borkar, and V. De.
Sub-90nm technologies - challenges and opportunities for CAD.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 203-206, San Jose, CA, November 10-14 2002.
- [2089]
- T. Karnik,
Y. Ye, J. Tschanz, L. Wei, and S. Burns.
Total power optimization by simultaneous dual-vt allocation and device sizing
in high performance microprocessors.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
486-491, New Orleans, LA, June 10-14 2002.
- [2090]
- T. Karnik,
M. Pant, and S. Borkar.
Power management and delivery for high-performance microprocessors.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2091]
- R. M. Karp.
The probabilistic analysis of some combinatorial search algorithms.
In J. F. Traub, editor, Algorithms and Complexity, pages 1-19.
Academic Press, Inc., New York, NY, 1976.
- [2092]
- A. V. Karthik,
S. Ray, and J. Roychowdhury.
BEE: predicting realistic worst case and stochastic eye diagrams by
accounting for correlated bitstreams and coding strategies.
In 20th Asia and South Pacific Design Automation Conference, pages
366-371, Chiba/Tokyo, Japan, January 19-22 2015.
- [2093]
- A. V. Karthik
and J. Roychowdhury.
ABCD-L: approximating continuous linear systems using boolean models.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2094]
- K. Kasamsetty, M. Ketkar, and S. S. Sapatnekar.
A new class of convex functions for delay modeling and its appliction to the
transistor sizing problem.
IEEE Transactions on Computer-Aided Design, 19(7):779-788, July
2000.
- [2095]
- C. V. Kashyap,
C. J. Alpert, and A. Devgan.
An "effective" capacitance based delay metric for RC interconnect.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 229-234, San Jose, CA, November 5-9 2000.
- [2096]
- C. V. Kashyap,
C. J. Alpert, F. (Y.) Liu, and A. Devgan.
Closed-form expressions for extending step delay and slew metrics to ramp
inputs for RC trees.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(4):509-516, April 2004.
- [2097]
- C. Kashyap,
C. Amin, N. Menezes, and E. Chiprout.
A nonlinear cell macromodel for digital applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 678-685, San Jose, CA, November 5-8 2007.
- [2098]
- C. Kashyap1,
P. Bastani, K. Killpack, and C. Amin1.
Silicon feedback to improve frequency of high-performance microprocessors - an
overview.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 778-782, San Jose, CA, November 10-13 2008.
- [2099]
- A. Kasnavi,
J.-W. Wang, M. Shahram, and J. Zejda.
Analytical modeling of crosstalk noise waveforms using weibull function.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 141-146, San Jose, CA, November 7-11 2004.
- [2100]
- R. Kastner,
E. Bozorgzadeh, and M. Sarrafzadeh.
Predictable routing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 110-113, San Jose, CA, November 5-9 2000.
- [2101]
- S. Katkoori and
R. Vemuri.
Simulation based architectural power estimation for PLA-based controllers.
In International Symposium on Low Power Electronics and Design, pages
121-124, Monterey, CA, August 12-14 1996.
- [2102]
- K. Katoh,
K. Namba, and H. Ito.
An on-chip delay measurement technique using signature registers for
small-delay defect detection.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(5):804-817, May 2012.
- [2103]
- H. Kaul,
d. Sylvester, M. Anders, and R. Krishnamurthy.
Spatial encoding circuit techniques for peak power reduction of on-chip
high-performance buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 194-199, Newport Beach, CA, August 9-11 2004.
- [2104]
- H. Kaul,
D. Sylvester, and D. Blaauw.
Performance optimization of critical nets through active shielding.
IEEE Transactions on Circuits and Systems, 51(12):2417-2435, December
2004.
- [2105]
- H. Kaul,
D. Sylvester, M. A. Anders, and R. K. Krishnamurthy.
Design and analysis of spatial encoding circuits for peak power reduction in
on-chip buses.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1225-1238, November 2005.
- [2106]
- H. Kaul, M. Anders,
S. Hsu, A. Agarwal, R. Krishnamurthy, and S. Borkar.
Near-threshold voltage (NTV) design - opportunities and challenges.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1149-1154, San Francisco, CA, June 3-7 2012.
- [2107]
- H. Kaul and
D. Sylvester.
Low-power on-chip communication based on transition-aware global signaling
(TAGS).
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):464-476, May 2004.
- [2108]
- B. K. Kaushik and
S. Sankar.
Crosstalk analysis for a CMOS-gate-driven coupled interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(6):1150-1154, June 2008.
- [2109]
- R. Kawakami,
H. Galvao, S. Hadjiloucas, K. H. Kienitz, H. M. Paiva, and R. J. M. Afonso.
Fractional order modeling of large three-dimensional RC networks.
IEEE Transactions on Circuits and Systems, 60(3):624-637, March
2013.
- [2110]
- S. Kaxiras,
P. Xekalakis, and G. Keramidas.
A simple mechanism to adapt leakage-control policies to temperature.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 54-59, San Diego, CA, August 8-10 2005.
- [2111]
- S. Kaxiras and
P. Xekalakis.
4t-decay sensors: a new class of small, fast, robust, and low-power,
temperature/leakage sensors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 108-113, Newport Beach, CA, August 9-11 2004.
- [2112]
- R. Kay and L. T. Pileggi.
PRIMO: Probability interpretation of moments for delay calculation.
In IEEE/ACM 35th Design Automation Conference, pages 463-468, San
Francisco, CA, June 15-19 1998.
- [2113]
- R. Kay and R. A. Rutenbar.
Wire packing - A strong formulation of crosstalk-aware chip-level track/layer
assignment with an efficient integer programming solution.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(5):672-679, May 2001.
- [2114]
- M. K. Kazimierczuk, V. G. Krizhanovski, J. V. Rassokhina, and
D. V. Chernov.
Injection-locked class-E oscillator.
IEEE Transactions on Circuits and Systems, 53(6):1214-1222, June
2006.
- [2115]
- J. Keane, H. Eom,
T.-H. Kim, S. Sapatnekar, and C. Kim.
Subthreshold logical effort: a systematic framework for optimal subthreshold
device sizing.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
425-428, San Francisco, CA, July 24-28 2006.
- [2116]
- J. Keane, T.-H.
Kim, and C. H. Kim.
An on-chip NBTI sensor for measuring PMOS threshold voltage degradation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 189-194, Portland, Oregon, August 27-29 2007.
- [2117]
- I. Keller,
K. Tseng, and N. Verghese.
A robust cell-level crosstalk delay change analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 147-154, San Jose, CA, November 7-11 2004.
- [2118]
- I. Keller, K.-H.
Tam, and V. Kariat.
Challenges in gate level modeling for delay and SI at 65nm and below.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
468-473, Anaheim, CA, June 8-13 2008.
- [2119]
- S. Keller, D. M.
Harris, and A. J. Martin.
A compact transregional model for digital CMOS circuits operating near
threshold.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(10):2041-2053, October 2014.
- [2120]
- E. Kellerman.
A formula for logical network cost.
IEEE Transactions on Computers, C-17(9):881-884, September 1968.
- [2121]
- J. G. Kemeny and J. L.
Snell.
Finite Markov Chains.
Van Nostrand, Princeton, NJ, 1960.
- [2122]
- B. Keng,
S. Safarpour, and A. Veneris.
Bounded model debugging.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1790-1803, November 2010.
- [2123]
- M. P. Kennedy.
Three steps to chaos - part I: Evolution.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 40(10):640-656, October 1993.
- [2124]
- M. P. Kennedy.
Three steps to chaos - part II: A chua's circuit primer.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 40(10):657-674, October 1993.
- [2125]
- M.-D. Ker, S.-L. Chen,
and C.-S. Tsai.
Overview and design of mixed voltage i/o buffers with low-voltage thin-oxide
CMOS transistors.
IEEE Transactions on Circuits and Systems, 53(9):1934-1945, September
2006.
- [2126]
- O. Keren and R. S.
Stankovic.
Determining the number of paths in decision diagrams by using autocorrelation
coefficients.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(1):31-44, January 2011.
- [2127]
- K. J. Kerns and A. T. Yang.
Preservation of passivity during RLC network reduction via split congruence
transformations.
In 34th Design Automation Conference, pages 34-39, Anaheim, CA, June
9-13 1997.
- [2128]
- J. Keshava,
N. Hakim, and C. Prudvi.
Post-silicon validation challenges: how EDA and academia can help.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages 3-7,
Anaheim, CA, June 13-18 2010.
- [2129]
- A. Keshavarzi, K. Roy, and C. F. Hawkins.
Intrinsic leakage in deep submicron CMOS ics - measurement-based test
solutions.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(6):717-723, December 2000.
- [2130]
- A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry,
T. Ghani, S. Borkar, and V. De.
Effectiveness of referse body bias for leakage control in scaled dual vt CMOS
ics.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 207-212, Huntington Beach, California, August 6-7
2001.
- [2131]
- A. Keshavarzi, G. Schrom, S. Tang, S. Ma, K. Bowman, S. Tyagi,
K. Zhang, T. Linton, N. Hakim, S. Duvall, J. Brews, and V. De.
Measurements and modeling of intrinsic fluctuations in MOSFET threshold
voltage.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 26-29, San Diego, CA, August 8-10 2005.
- [2132]
- M. Ketkar,
K. Kasamsetty, and S. Sapatnekar.
Convex delay models for transistor sizing.
In Design Automation Conference, pages 655-660, Los Angeles, CA, June
5-9 2000.
- [2133]
- M. Ketkar and
E. Chiprout.
A microarchitecture-based framework for pre- and post-silicon power delivery
analysis.
In IEEE/ACM International Symposium on Microarchitecture (MICRO-42),
New York, NY, December 12-16 2009.
- [2134]
- M. Ketkar and S. S.
Sapatnekar.
Standby power optimization via transistor sizing and dual threshold voltage
assignment.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 375-378, San Jose, CA, November 10-14 2002.
- [2135]
- H. Kettani and B. R.
Barmish.
A new monte carlo circuit simulation paradigm with specific results for
resistive networks.
IEEE Transactions on Circuits and Systems, 53(6):1289-1299, June
2006.
- [2136]
- K.-M. Keung,
V. Manne, and A. Tyagi.
A novel charge recycling design scheme based on adiabatic charge pump.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(7):733-745, July 2007.
- [2137]
- K. Keutzer,
S. Malik, A. R. Newton, J. M. Rabaey, and A. L. Sangiovanni-Vincentelli.
System-level design: Orthogonalization of concerns and platform-based design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1523-1543, December 2000.
- [2138]
- K. Keutzer and
D. Sylvester.
Chip-level assembly (and not the integration of synthesis and physical) is the
key to DSM design.
In ACM/IEEE 1999 International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU-99), pages 23-24,
Monterey, CA, March 8-9 1999.
- [2139]
- K. Keutzer.
Three competing design methodologies for asics: architectural synthesis, logic
synthesis and module generation.
In 26th ACM/IEEE Design Automation Conference, pages 308-313, June
25-29 1989.
- [2140]
- D. Khalil,
M. Khellah, N.-S. Kim, Y. I. Ismail, T. Karnik, and V. K. De.
Accurate estimation of SRAM dynamic stability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(12):1639-1647, December 2008.
- [2141]
- D. Khalil,
D. Sinha, H. Zhou, and Y. I. Ismail.
A timing-dependent power estimation framework considering coupling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(6):843-847, June 2009.
- [2142]
- M. U. K. Khan,
M. Shafique, and J. Henkel.
Hierarchical power budgeting for dark silicon chips.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 213-218, Rome, Italy, July 22-24 2015.
- [2143]
- V. Khandelwal, A. Davoodi, and A. Srivastava.
Efficient statistical timing analysis through error budgeting.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 473-477, San Jose, CA, November 7-11 2004.
- [2144]
- V. Khandelwal, A. Davoodi, and A. Srivastava.
Simultaneous vt selection and assignment for leakage optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):762-765, June 2005.
- [2145]
- S. Khandelwal, H. Agarwal, J. P. Duarte, K. Chan, S. Dey, Y. S.
Chauhan, and C. Hu.
Modeling STI edge parasitic current for accurate circuit simulations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(8):1291-1294, August 2015.
- [2146]
- V. Khandelwal and A. Srivastava.
Active mode leakage reduction using fine-grained forward body biasing strategy.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 150-155, Newport Beach, CA, August 9-11 2004.
- [2147]
- V. Khandelwal and A. Srivastava.
Leakage control through fine-grained placement and sizing of sleep transistors.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 533-536, San Jose, CA, November 7-11 2004.
- [2148]
- V. Khandelwal and A. Srivastava.
A general framework for accurate statistical timing analysis considering
correlations.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 89-94,
Anaheim, CA, June 13-17 2005.
- [2149]
- V. Khandelwal and A. Srivastava.
Leakage control through fine-grained placement and sizing of sleep transistors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(7):1246-1255, July 2007.
- [2150]
- V. Khandelwal and A. Srivastava.
Monte-carlo driven stochastic optimization framework for handling fabrication
variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 105-110, San Jose, CA, November 5-8 2007.
- [2151]
- V. Khandelwal and A. Srivastava.
A quadratic modeling-based framework for accurate statistical timing analysis
considering correlations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(2):206-215, February 2007.
- [2152]
- A. B. Khang and S. Muddu.
An analytical delay model for RLC interconnects.
IEEE Transactions on Computer-Aided Design of Circuits and Systems,
16(12):1507-1514, December 1997.
- [2153]
- S. Khanna,
C. Lursinsap, A. Pitaksanonkul, and V. Techangam.
Analytical models for sizing of VLSI power/ground nets under
electromigration, inductive, and resistive constraints.
In 1991 IEEE International Symposium on Circuits and Systems, pages
2272-2275, June 1991.
- [2154]
- S. P. Khatri,
A. Mehrotra, R. K. Brayton, A. Sangiovanni-Vincentelli, and R. H. J. M.
Otten.
A novel VLSI layout fabric for deep sub-micron applications.
In Design Automation Conference, pages 491-496, New Orleans, LA, June
21-25 1999.
- [2155]
- S. P. Khatri,
R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
Cross-talk immune VLSI design using a network of plas embedded in a regular
layout fabric.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 412-418, San Jose, CA, November 5-9 2000.
- [2156]
- V. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani, Y. Takegawa,
A. J. Strojwas, and L. Pileggi.
Design methodology for IC manufacturability based on regular logic-bricks.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
353-358, Anaheim, CA, June 13-17 2005.
- [2157]
- G. Khodabandehloo, M. Mirhassani, and M. Almadi.
Analog implementation of a novel resistive-type sigmoidal neuron.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(4):750-754, April 2012.
- [2158]
- K. S. Khouri,
G. Lakshminarayana, and N. K. Jha.
Fast high-level estimation for control-flow intensive designs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 299-304, Monterey, CA, August 10-12 1998.
- [2159]
- K. S. Khouri,
G. Lakshminarayana, and N. K. Jha.
High-level synthesis of low-power control-flow intensive circuits.
IEEE Transactions on Computer-Aided Design, 18(12):1715-1729,
December 1999.
- [2160]
- K. S. Khouri and N. K.
Jha.
Leakage power analysis and reduction during behavioral synthesis.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):876-885, December 2002.
- [2161]
- R. A. Kiehl.
Information processing in nanoscale arrays: DNA assembly, molecular devices,
nano-array architectures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 828-829, San Jose, CA, November 5-9 2006.
- [2162]
- J. Kil, J. Gu, and
C.-H. Kim.
A high-speed variation-tolerant interconnectd technique for sub-threshold
circuits using capacitive boosting.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 67-72, Tegernsee, Germany, October 4-6 2006.
- [2163]
- D. Kilinc and A. Demir.
Simulation of noise in neurons and neuronal circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 589-596, Austin TX, November 2-6 2015.
- [2164]
- K. Killpack, C. Kashyap, and E. Chiprout.
Silicon speedpath measurement and feedback into EDA flows.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
390-395, San Diego, CA, June 4-8 2007.
- [2165]
- K. Killpack.
A fast tolerance-based incremental timing analysis algorithm.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 137-142, Austin,
Texas, February 26-27 2007.
- [2166]
- Y. H. Kim, S. H.
Hwang, and A. R. Newton.
Electrical-logic simulation and its applications.
IEEE Transactions on Computer-Aided Design, 8(1):8-22, January
1989.
- [2167]
- S-Y Kim, N. Gopal, and
L. T. Pillage.
AWE macromodels of VLSI interconnect for circuit simulation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
64-70, Santa Clara, CA, November 8-12 1992.
- [2168]
- S-Y Kim, N. Gopal, and
L. T. Pillage.
Time-domain macromodels for VLSI interconnect analysis.
IEEE Transactions on Computer-Aided Design, 13(10):1257-1270, October
1994.
- [2169]
- K.-W. Kim, C. L. Liu,
and S.-M. Kang.
Implication graph based domino logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
111-114, San Jose, CA, November 7-11 1999.
- [2170]
- K.-W. Kim, K.-H. Baek,
N. Shanbhag, C.-L. Liu, and S.-M. Kang.
Coupling-driven signal encoding scheme for low-power interface design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 318-321, San Jose, CA, November 5-9 2000.
- [2171]
- K.-W. Kim, S.-O.
Jung, P. Saxena, C. L. Liu, and S.-M. Kang.
Coupling delay optimization by temporal decorrelation using dual threshold
voltage technique.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
732-737, Las Vegas, NV, June 18-22 2001.
- [2172]
- S. Kim, C. H.
Ziesler, and M. C. Papaefthymiou.
A true single-phase 8-bit adiabatic multiplier.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
758-763, Las Vegas, NV, June 18-22 2001.
- [2173]
- T. Kim, K.-S. Chung,
and C. L. Liu.
A static estimation technique of power sensitivity in logic circuits.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
215-219, Las Vegas, NV, June 18-22 2001.
- [2174]
- J. Kim, C. H. Ziesler,
and M. C. Papaefthymiou.
Energy recovering static memory.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 92-97, Monterey, California, August 12-14 2002.
- [2175]
- C. Kim, K.-W. Kim,
and S.-M. (Steve) Kang.
Energy-efficient skewed static logic with dual vt: design and synthesis.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
11(1):64-70, February 2003.
- [2176]
- C. H. Kim, J.-J.
Kim, S. Mukhopadhyay, and K. Roy.
A forward body-biased low-leakage SRAM cache: device and architecture
considerations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 6-9, Seoul, Korea, August 25-27 2003.
- [2177]
- C. H. Kim, K. Roy,
S. Hsu, A. Alvandpour, R. K. Krishnamurthy, and S. Borkar.
A process variation compensating technique for sub-90nm dynamic circuits.
In VLSI Symposium, Japan, June 2003.
- [2178]
- C. H.-I. Kim,
H. Soeleman, and K. Roy.
Ultra-low-power DLMS adaptive filter for hearing aid applications.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(6):1058-1067, December 2003.
- [2179]
- H.-S. Kim,
N. Vijaykrishnan, M. Kandemir, E. Brockmeyer, F. Catthoor, and M. J. Irwin.
Estimating influence of data layout optimizations on SDRAM energy
consumption.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 40-43, Seoul, Korea, August 25-27 2003.
- [2180]
- K. Kim, R. V. Joshi,
and C.-T. Chuang.
Strained-si devices and circuits for low-power applications.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 180-183, Seoul, Korea, August 25-27 2003.
- [2181]
- N. S. Kim,
D. Blaauw, and T. Mudge.
Leakage power optimization techniques for ultra deep sub-micron multi-level
caches.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 627-632, San Jose, CA, November 9-13 2003.
- [2182]
- S. Kim, S. V.
Kosonocky, and D. R. Knebel.
Understanding and minimizing ground bounce during mode transition of power
gating structures.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 22-25, Seoul, Korea, August 25-27 2003.
- [2183]
- N.-S. Kim,
K. Flautner, D. Blaauw, and T. Mudge.
Circuit and microarchitectural techniques for reducing cache leakage power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(2):167-184, February 2004.
- [2184]
- N.-S. Kim,
K. Flautner, D. Blaauw, and T. Mudge.
Single-VDD and single-VT super-drowsy techniques for low-leakage
high-performance instruction caches.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 54-57, Newport Beach, CA, August 9-11 2004.
- [2185]
- N.-S. Kim, T. Kgil,
V. Bertacco, T. Austin, and T. Mudge.
Microarchitectural power modeling techniques for deep sub-micron
microprocessors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 212-217, Newport Beach, CA, August 9-11 2004.
- [2186]
- S. Kim, S. V.
Kosonocky, D. R. Knebel, and K. Stawizsa.
Experimental measurement of a novel power gating structure with intermediate
power saving mode.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 20-25, Newport Beach, CA, August 9-11 2004.
- [2187]
- T. Kim, X. Li, and
D. J. Allstot.
Compact model generation for on-chip transmission lines.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(3):459-470, March 2004.
- [2188]
- C.-H. Kim, K. Roy,
S. Hsu, R. K. Krishnamurthy, and S. Borkar.
An on-die CMOS leakage current sensor for measuring process variation in
sub-90nm generations.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 221-222, Austin, TX, May 9 - 11 2005.
- [2189]
- C. H.-I. Kim, J.-J.
Kim, S. Mukhopadhyay, and K. Roy.
A forward body-biased low-leakage SRAM cache: device, circuit and
architecture considerations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):349-357, March 2005.
- [2190]
- K.-O. Kim, M.-J.
Zuo, and W. Kuo.
On the relationship of semiconductor yield and reliability.
IEEE Transactions on Semiconductor Manufacturing, 18(3):422-429,
August 2005.
- [2191]
- N.-S. Kim,
D. Blaauw, and T. Mudge.
Quantitative analysis and optimization techniques for on-chip cache leakage
power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(10):1147-1156, October 2005.
- [2192]
- N.-S. Kim, T. Kgil,
K. Bowman, V. De, and T. Mudge.
Total power-optimal pipelining and parallel processing under process variations
in nanometer technology.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 535-540, San Jose, CA, November 6-10 2005.
- [2193]
- C.-H. Kim, K. Roy,
S. Hsu, R. Krishnamurthy, and S. Borkar.
A process variation compensating technique with an on-die leakage current
sensor for nanometer scale dynamic circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(6):646-649, June 2006.
- [2194]
- T.-H. Kim, H. Eom,
J. Keane, and C. Kim.
Utilizing reverse short channel effect for optimal subthreshold circuit design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 127-130, Tegernsee, Germany, October 4-6 2006.
- [2195]
- J. Kim, K. D. Jones,
and M. A. Horowitz.
Fast, non-monte-carlo estimation of transient performance variation due to
device mismatch.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
440-443, San Diego, CA, June 4-8 2007.
- [2196]
- J. Kim, K. D. Jones,
and M. A. Horowitz.
Variable domain transformation for linear PAC analysis of mixed-signal
systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 887-894, San Jose, CA, November 5-8 2007.
- [2197]
- K. Kim, H. Mahmoodi,
and K. Roy.
A low-power SRAM using bit-line charge-recycling technique.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 177-182, Portland, Oregon, August 27-29 2007.
- [2198]
- J. Kim, J. Ren, and
M. A. Horowitz.
Stochastic steady-state and AC analyses of mixed-signal systems.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
376-381, San Francisco, CA, July 26-31 2009.
- [2199]
- J. Kim, K. D. Jones,
and M. A. Horowitz.
Fast, non-monte-carlo estimation of transient performance variaton due to
device mismatch.
IEEE Transactions on Circuits and Systems, 57(7):1746-1755, July
2010.
- [2200]
- J. Kim,
L. Vandenberghe, and C.-K. K. Yang.
Convex piecewise-linear modeling method for circuit optimization via geometric
programming.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1823-1827, November 2010.
- [2201]
- W. Kim, K. T. Do, and
Y. H. Kim.
Statistical leakage estimation based on sequential addition of cell leakage
currents.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(4):602-615, April 2010.
- [2202]
- D. Kim, H. Kim, and
Y. Eo.
Analytical eye-diagram determination for the efficient and accurate signal
integrity verification of single interconnect lines.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(10):1536-1545, October 2012.
- [2203]
- H. Kim, M. P. Sah,
C. Yang, S. Cho, and L.-0. Chua.
Memristor emulator for memristor circuit applications.
IEEE Transactions on Circuits and Systems, 59(10):2422-2431, October
2012.
- [2204]
- J. Kim, P. M.
Solomon, and S. Tiwari.
Adaptive circuit design using independently biased back-gated double-gate
MOSFETS.
IEEE Transactions on Circuits and Systems, 59(4):806-819, April
2012.
- [2205]
- D. Kim,
M. Ciesielski, and S. Yang.
MULTES: multilevel temporal-parallel event-driven simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):845-857, June 2013.
- [2206]
- Y. Kim, D. Shin,
M. Petricca, S. Park, M. Poncino, and N. Chang.
Computer-aided design of electrical energy systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 194-201, San Jose, CA, November 18-21 2013.
- [2207]
- T. Kim, B. Zheng,
H.-B. Chen, Q. Zhu, V. Sukharev, and S.-X.-D. Tan.
Lifetime optimization for real-time embedded systems considering
electromigration effects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 434-439, San Jose, CA, November 2-6 2014.
- [2208]
- J.-H. Kim, W. Kim, and
Y.-H. Kim.
Efficient statistical timing analysis using deterministic cell delay models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(11):2709-2713, November 2015.
- [2209]
- T. Kim, Z. Sun,
C. Cook, J. Gaddipati, H. Wang, H. Chen, and S.-X.-D. Tan.
Dynamic reliability management for near-threshold dark silicon processors.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [2210]
- V. Kim and P. Banerjee.
Parallel algorithms for power estimation.
In IEEE/ACM 35th Design Automation Conference, pages 672-677, San
Francisco, CA, June 15-19 1998.
- [2211]
- D. Kim and K. Choi.
Power-conscious high level synthesis using loop folding.
In 34th Design Automation Conference, pages 441-445, Anaheim, CA,
June 9-13 1997.
- [2212]
- J. Kim and D. H. C. Du.
Performance optimization by gate sizing and path sensitization.
IEEE Transactions on Computer-Aided Design, 17(5):459-462, May
1998.
- [2213]
- K. Kim and G. Jeong.
Memory technologies in the nano-era : challenges and opportunities.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 63-67, Austin, TX, May 9 - 11 2005.
- [2214]
- T. Kim and W. Kuo.
Modeling manufacturing yield and reliability.
IEEE Transactions on Semiconductor Manufacturing, 12(4):485-492,
November 1999.
- [2215]
- N. S. Kim and T. Mudge.
The microarchitecture of a low power register file.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 384-389, Seoul, Korea, August 25-27 2003.
- [2216]
- C. H. Kim and K. Roy.
Dynamic vt SRAM: A leakage tolerant cache memory for low voltage
microprocessors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 251-254, Monterey, California, August 12-14 2002.
- [2217]
- J.-J. Kim and K. Roy.
A leakage-tolerant low-swing circuit style in partially depleted
silicon-on-insulator CMOS technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(5):549-552, May 2006.
- [2218]
- H.-O. Kim and Y. Shin.
Physical design methodology of power gating circuits for standard-cell-based
design.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
109-112, San Francisco, CA, July 24-28 2006.
- [2219]
- J. Kim and Y. Shin.
Minimizing leakage power in sequential circuits by using mixed vt flip-flops.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 797-802, San Jose, CA, November 5-8 2007.
- [2220]
- S. Y. Kim and S. S. Wong.
Closed-form RC and RLC delay models considering input rise time.
IEEE Transactions on Circuits and Systems, 54(9):2001-2010, September
2007.
- [2221]
- M. Kimura,
S. Inoue, and T. Shimoda.
Table look-up model of thin-film transistors for circuit simulation using
spline interpolation with transformation by y=x+log(x).
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(9):1101-1104, September 2002.
- [2222]
- J. Kin, C. Lee, W. H.
Mangione-Smith, and M. Potkonjak.
Power efficient mediaprocessors: design space exploration.
In Design Automation Conference, pages 321-326, New Orleans, LA, June
21-25 1999.
- [2223]
- T. I.
Kirkpatrick and N. R. Clark.
PERT as an aid to logic design.
IBM Journal of Research and Development, 10(2):135-141, March
1966.
- [2224]
- D. A. Kirkpatrick and A. L. Sangiovanni-Vincentelli.
Digital sensitivity: predicting signal interaction using functional analysis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
536-541, San Jose, CA, November 10-14 1996.
- [2225]
- D. A. Kirkpatrick.
The deep sub-micron signal integrity challenge.
In 1999 International Symposium on Physical Design, pages 4-7,
Monterey, CA, April 12-14 1999.
- [2226]
- D. Kirovski,
Y.-Y. Hwang, M. Potkonjak, and J. Cong.
Protecting combinational logic synthesis solutions.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2687-2696, December 2006.
- [2227]
- C. M. Kirsch and
H. Payer.
Incorrect systems: it's not the problem, it's the solution.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
913-917, San Francisco, CA, June 3-7 2012.
- [2228]
- M. Kishor and
J. Pineda de Gyvez.
Threshold voltage and power-supply tolerance of CMOS logic design families.
In IEEE International Symposium on Defect and Fault Tolerance in VLSI
Systems, pages 329-357, Yamanashi, Japan, October 25-27 2000.
- [2229]
- G. Kissin.
Upper and lower bounds on switching energy in VLSI.
Journal of the Association for Computing Machinery, 38(1):222-254,
January 1991.
- [2230]
- N. Kitchen and
A. Kuehlmann.
Stimulus generation for constrained random simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 258-265, San Jose, CA, November 5-8 2007.
- [2231]
- J. Kitchin.
Statistical electromigration budgeting for reliable design and verification in
a 300-mhz microprocessor.
In 1995 Symposium on VLSI Circuits, pages 115-116, 1995.
- [2232]
- H. Klauk and
U. Zschieschang.
Manufacturing and characteristics of low-voltage organic thin-film transistors.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 493-495, San Jose, CA, November 7-11 2010.
- [2233]
- V. B.
Kleeberger, H. Graeb, and U. Schlichtmann.
Predicting future product performance: modeling and evaluation of standard
cells in finfet technologies.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2234]
- V. B.
Kleeberger, S. Rutkowski, and R. Coppens.
Design & verification of automotive soc firmware.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [2235]
- F. Klein,
G. Araujo, and R. Azevedo.
A multi-model power estimation engine for accuracy optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 280-285, Portland, Oregon, August 27-29 2007.
- [2236]
- F. Klein, R. Leao,
G. Araujo, L. Santos, and R. Azevedo.
A multi-model engine for high-level power estimation accuracy optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(5):600-673, May 2009.
- [2237]
- T. Klemas,
L. Daniel, and J. K. White.
Segregation by primary phase factors: a full-wave algorithm for model order
reduction.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
943-946, Anaheim, CA, June 13-17 2005.
- [2238]
- G.-A. Klutte,
P. C. Kiessler, and M. A. Wortman.
A critical look at the bathtub curve.
IEEE Transactions on Reliability, 52(1):125-129, March 2003.
- [2239]
- M. C. Knapp, P. J.
Kindlmann, and M. C. Papaefthymiou.
Implementing and evaluating adiabatic arithmetic units.
In IEEE 1996 Custom Integrated Circuits Conference, pages 115-118,
San Diego, CA, May 5-8 1996.
- [2240]
- D. W. Knapp.
Fasolt: A program for feedback-driven data-path optimization.
IEEE Transactions on Computer-Aided Design, 11(6):677-695, June
1992.
- [2241]
- J. Knechtel, I. L. Markov, and J. Lienig.
Assembling 2-D blocks into 3-D chips.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(2):228-241, February 2012.
- [2242]
- J. Knechtel, I. L. Markov, J. Lienig, and M. Thiele.
Multiobjective optimization of deadspace, a critical resource for 3d-IC
integration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 705-712, San Jose, CA, November 5-8 2012.
- [2243]
- L. Knockaert, G. Lippens, and D. De Zutter.
Reduced-order modeling via oblique projections on a bandlimited kautz basis.
IEEE Transactions on Circuits and Systems, 53(7):1544-1555, July
2006.
- [2244]
- L. Knockaert and
T. Dhaene.
Orthonormal bandlimited kautz sequences for global system modeling from
piecewise rational models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1377-1391, July 2006.
- [2245]
- D. E. Knuth.
The Art of Computer Programming. Volume I: Fundamental Algorithms,
volume I.
Addison-Wesley, Reading, MA, 1968.
- [2246]
- D. E. Knuth.
The Art of Computer Programming. Volume III: Sorting and Searching,
volume III.
Addison-Wesley, Reading, MA, 1973.
- [2247]
- U. Ko, P. T. Balsara,
and W. Lee.
Low-power design techniques for high-performance CMOS adders.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
3(2):327-333, June 1995.
- [2248]
- U. Ko, A. Hill, and
P. T. Balsara.
Design techniques for high-performance, energy efficient control logic.
In International Symposium on Low Power Electronics and Design, pages
97-100, Monterey, CA, August 12-14 1996.
- [2249]
- U. Ko, A. Pua, A. Hill,
and P. Srivastava.
Hybrid dual-threshold design techniques for high-performance processors with
low-power features.
In 1997 International Symposium on Low Power Electronics and Design,
pages 307-311, Monterey, CA, August 18-20 1997.
- [2250]
- U. Ko and T. Balsara.
Short-circuit driven gate sizing technique for reducing power dissipation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
3(3):450-455, September 1995.
- [2251]
- U. Ko and P. T. Balsara.
High-performance energy-efficient D-flip-flop circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(1):94-98, February 2000.
- [2252]
- N. Kobayashi and
S. Malik.
Delay abstraction in combinational logic circuits.
IEEE Transactions on Computer-Aided Design of Circuits and Systems,
16(10):1205-1212, October 1997.
- [2253]
- L. Kocarev,
J. Szczepanski, J. M. Amigo, and I. Tomovski.
Discrete chaos - I: theory.
IEEE Transactions on Circuits and Systems, 53(6):1300-1309, June
2006.
- [2254]
- M. Kocher and
G. Rappitsch.
Statistical methods for the determination of process corners.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 133-137, San Jose, CA, March 18-21 2002.
- [2255]
- C. Kodama,
H. Ichikawa, K. Nakayama, F. Nakajima, S. Nojima, T. Kotani, T. Thara, and
A. Takahashi.
Self-aligned double and quadruple pattering aware grid routing methods.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(5):753-765, May 2015.
- [2256]
- K. L.
Kodandapani and D. K. Pradhan.
Undetectability of bridging faults and validity of stuck at fault test sets.
IEEE Transactions on Computers, C-29(1):55-59, January 1980.
- [2257]
- Zvi Kohavi.
Switching and Finite Automata Theory.
McGraw-Hill Book Company, 1978.
- [2258]
- K. Kohno,
Y. Inouye, and M. Kawamoto.
A matrix pseudo-inversion lemma for positive semidefinite hermitian matrices
and its application to adaptive blind deconvolution of MIMO systems.
IEEE Transactions on Circuits and Systems, 55(2):412-423, February
2008.
- [2259]
- A. A. Kokrady and
C. P. Ravikumar.
Static verification of test vectors for IR drop failure.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 760-764, San Jose, CA, November 9-13 2003.
- [2260]
- J.-T. Kong, S. Z.
Hussain, and D. Overhauser.
Performance estimation of complex CMOS gates.
IEEE Transactions on Circuits and Systems I, 44(9):785-795, September
1997.
- [2261]
- J-T. Kong and
D. Overhauser.
Methods to improve digital MOS macromodel accuracy.
IEEE Transactions on Computer-Aided Design, 14(7):868-881, July
1995.
- [2262]
- J.-T. Kong.
CAD for nanometer silicon design challenges and success.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(11):1132-1147, November 2004.
- [2263]
- J.-E. Koo, K.-H. Lee,
Y.-H. Cheon, J.-H. Choi, M.-H. Yoo, and J.-T. Kong.
A variable reduction technique for the analysis of ultra large-scale power
distribution networks.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 137-142, San Jose, CA, March 22-24 2004.
- [2264]
- M. A.
Korhonen, P. Borgesen, D. D. Brown, and C.-Y. Li.
Microstructure based statistical model of electromigration damaage in confined
line metallizations in the presence of thermally induced stresses.
Journal of Applied Physics, 74(8):4995-5004, October 15 1993.
- [2265]
- M. A.
Korhonen, P. Borgesen, K. N. Tu, and C.-Y. Li.
Stress evolution due to electromigration in confined metal lines.
Journal of Applied Physics, 73(8):3790-3799, April 15 1993.
- [2266]
- M. A.
Korhonen, T. M. Korhonen, D. D. Brown, and C.-Y. Li.
Simulation of electromigration damage in chip level interconnect lines: A
grain structure based statistical approach.
In IEEE 37th Annual International Reliability Physics Symposium, pages
227-232, San Diego, CA, March 23-25 1999.
- [2267]
- P. Korkmaz,
B. E. S. Akgul, and K. V. Palem.
Energy, performance, and probability tradeoffs for energy-efficient
probabilistic CMOS circuits.
IEEE Transactions on Circuits and Systems, 55(8):2249-2262, September
2008.
- [2268]
- A. Korobkov,
A. Agarwal, and S. Venkateswaran.
Efficient finfet device model implementation for SPICE simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(10):1696-1699, October 2015.
- [2269]
- A. Korshak and J.-C.
Lee.
An effective current source cell model for VDSM delay calculation.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 296-300, San Jose, CA, March 26-28 2001.
- [2270]
- A. Korshak.
Noise-rejection model based on charge-transfer equation for digital CMOS
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(10):1460-1465, October 2004.
- [2271]
- T. Korsmeyer, J. Zeng, and K. Greiner.
Design tools for biomems.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
622-627, San Diego, CA, June 7-11 2004.
- [2272]
- S. Kose, E. Salman,
and E. G. Friedman.
Shielding methodologies in the presence of power/ground noise.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(8):1458-1468, August 2011.
- [2273]
- S. Kose and E. G.
Friedman.
Fast algorithms for IR voltage drop analysis exploiting locality.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
996-1001, San Diego, CA, June 5-9 2011.
- [2274]
- S. Kose.
Thermal implications of on-chip voltage regulation: upcoming challenges and
possible solutions.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [2275]
- S. V.
Kosonocky, M. Immediato, P. Cottrell, T. Hook, R. Mann, and J. Brown.
Enhanced multi-threshold (MTCMOS) circuits using variable well bias.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 165-169, Huntington Beach, California, August 6-7
2001.
- [2276]
- D. Kouroussis, R. Ahmadi, and F. N. Najm.
Worst-case circuit delay taking into account power supply variations.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
652-657, San Diego, CA, June 7-11 2004.
- [2277]
- D. Kouroussis, R. Ahmadi, and F. N. Najm.
A worst-case circuit delay verification technique considering power grid
voltage variations.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 157-160, Montreal, Quebec, June 20-23 2004.
- [2278]
- D. Kouroussis, I. A. Ferzli, and F. N. Najm.
Incremental partitioning-based vectorless power grid verification.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 358-364, San Jose, CA, November 6-10 2005.
- [2279]
- D. Kouroussis, R. Ahmadi, and F. N. Najm.
Voltage-aware static timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2156-2169, October 2006.
- [2280]
- D. Kouroussis and
F. N. Najm.
A static pattern-independent technique for power grid voltage integrity
verification.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 99-104,
Anaheim, CA, June 2-6 2003.
- [2281]
- F. Koushanfar, P. Boufounos, and D. Shamsi.
Post-silicon timing characterization by compressed sensing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 185-189, San Jose, CA, November 10-13 2008.
- [2282]
- F. Koushanfar, A. Mirhoseini, G. Qu, and Z. Zhang.
DA systemization of knowledge: a catalog of prior forward-looking
initiatives.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 255-262, Austin TX, November 2-6 2015.
- [2283]
- F. Koushanfar.
Hierarchical hybrid power supply networks.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
629-630, Anaheim, CA, June 13-18 2010.
- [2284]
- J. Kozhaya,
S. R. Nassif, and F. N. Najm.
I/O buffer placement methodology for asics.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 245-248, St. Julian, Malta, September 2-5 2001.
- [2285]
- J. N.
Kozhaya, S. R. Nassif, and F. N. Najm.
Multigrid-like technique for power grid analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 480-487, San Jose, CA, November 4-8 2001.
- [2286]
- J. N. Kozhaya,
S. R. Nassif, and F. N. Najm.
A multigrid-like technique for power grid analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(10):1148-1160, October 2002.
- [2287]
- J. Kozhaya,
P. Restle, and H. Qian.
Myth busters: microprocessor clocking is from mars, ASIC's clocking is from
venus.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 271-275, San Jose, CA, November 7-10 2011.
- [2288]
- J. N. Kozhaya and F. N.
Najm.
Accurate power estimation for large sequential circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
488-493, San Jose, CA, November 9-13 1997.
- [2289]
- J. N. Kozhaya and
F. N. Najm.
Power estimation for large sequential circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(2):400-407, April 2001.
- [2290]
- A. Kozik.
Fully dynamic evaluation of sequence pair.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):894-904, June 2013.
- [2291]
- S. Koziol,
S. Brink, and J. Hasler.
A neuromorphic approach to path planning using a reconfigurable neuron array
IC.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(12):2724-2737, December 2014.
- [2292]
- B. Krauter and
D. Widiger.
Variable frequency crosstalk noise analysis: A methodology to guarantee
functionality from dc to fmax.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
665-668, New Orleans, LA, June 10-14 2002.
- [2293]
- J. L.
Krichmar, N. Dutt, J. M. Nageswaran, and M. Richert.
Neuromorphic modeling abstractions and simulation of large-scale cortical
networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 334-338, San Jose, CA, November 7-10 2011.
- [2294]
- H. Kriplani,
F. Najm, and I. Hajj.
Maximum current estimation in CMOS circuits.
In 29th ACM/IEEE Design Automation Conference, pages 2-7, Anaheim,
CA, June 8-12 1992.
- [2295]
- H. Kriplani,
F. Najm, and I. Hajj.
Improved delay and current models for estimating maximum currents in CMOS
VLSI circuits.
In IEEE International Symposium on Circuits and Systems, pages
435-438, London, England, June 1994.
- [2296]
- H. Kriplani,
F. N. Najm, and I. N. Hajj.
Pattern independent maximum current estimation in power and ground bus of
CMOS VLSI circuits: algorithms, signal correlations, and their
resolution.
IEEE Transactions on Computer-Aided Design, 14(8):998-1012, August
1995.
- [2297]
- S. Krishnamoorthy and A. Khouja.
Efficient power analysis of combinational circuits.
In IEEE 1996 Custom Integrated Circuits Conference, pages 393-396,
San Diego, CA, May 5-8 1996.
- [2298]
- B. Krishnamurthy and I. G. Tollis.
Improved techniques for estimating signal probabilities.
In IEEE International Test Conference, pages 244-251, Sept. 8-11
1986.
- [2299]
- B. Krishnamurthy and I. G. Tollis.
Improved techniques for estimating signal probabilities.
IEEE Transactions on Computers, 38(7):1041-1045, July 1989.
- [2300]
- S. Krishnan and
J. G. Fossum.
Grasping SOI floating-body effects.
IEEE Circuits and Devices Magazine, 14(4):32-37, July 1998.
- [2301]
- S. Krishnaswamy, S. M. Plaza, I. L. Markov, and J. P. Hayes.
Enhancing design robustness with reliability-aware resynthesis and logic
simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 149-154, San Jose, CA, November 5-8 2007.
- [2302]
- S. Krishnaswamy, I. L. Markov, and J. P. Hayes.
On the role of timing masking in reliable logic circuit design.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
924-949, Anaheim, CA, June 8-13 2008.
- [2303]
- T. H. Krodel.
Powerplay - fast dynamic power estimation based on logic simulation.
In IEEE International Conference on Computer Design, pages 96-100,
October 1991.
- [2304]
- D. Kroft.
All paths through a maze.
In Proceedings of the IEEE, pages 88-90, January 1967.
Published as Proceedings of the IEEE, volume 55, number 1.
- [2305]
- S. J. Krolikoski.
Standardizing ASIC libraries in VHDL using VITAL: a tutorial.
In IEEE Custom Integrated Circuits Conference, pages 603-610, Santa
Clara, CA, May 1-4 1995.
- [2306]
- A. Krstic and K-T Cheng.
Vector generation for maximum instantaneous current through supply lines for
CMOS circuits.
In 34th Design Automation Conference, pages 383-388, Anaheim, CA,
June 9-13 1997.
- [2307]
- L. Kruse,
E. Schmidt, G. Jochens, and W. Nebel.
Lower and upper bounds on the switching activity in scheduled data flow graphs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 115-120, San Diego, CA, August 16-17 1999.
- [2308]
- L. Kruse,
E. Schmidt, G. Jochens, A. Stammermann, A. Schulz, E. Macii, and W. Nebel.
Estimation of lower and upper bounds on the power consumption from scheduled
data flow graphs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(1):3-14, February 2001.
- [2309]
- J. C. Ku and Y. I. Ismail.
Area optimization for leakage reduction and thermal stability in
nanometer-scale technologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):241-248, February 2008.
- [2310]
- K. Kucukcakar.
Analysis of emerging core-based design lifecycle.
In IEEE/ACM International Conference on Computer-Aided Design, pages
445-449, San Jose, CA, November 8-12 1998.
- [2311]
- P. Kudva,
A. Sullivan, and W. Dougherty.
Metrics for structural logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 551-556, San Jose, CA, November 10-14 2002.
- [2312]
- M. Kuhlmann and
S. S. Sapatnekar.
Exact and efficient crosstalk estimation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(7):858-866, July 2001.
- [2313]
- K. J. Kuhn.
CMOS scaling beyond 32nm: challenges and opportunities.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
310-313, San Francisco, CA, July 26-31 2009.
- [2314]
- Y. Kukimoto, W. Gosti, A. Saldanha, and R. K. Brayton.
Approximate timing analysis of combinational circuits under the xbd0 model.
In IEEE/ACM International Conference on Computer-Aided Design, pages
176-181, San Jose, CA, November 9-13 1997.
- [2315]
- Y. Kukimoto and
R. K. Brayton.
Exact required time analysis via false path detection.
In 34th Design Automation Conference, pages 220-225, Anaheim, CA,
June 9-13 1997.
- [2316]
- S. H.
Kulkarni, A. N. Srivastava, and D. Sylvester.
A new algorithm for improved VDD assignment in low power dual VDD systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 200-205, Newport Beach, CA, August 9-11 2004.
- [2317]
- S. H.
Kulkarni, D. Sylvester, and D. Blaauw.
A statistical framework for post-silicon tuning through body bias clustering.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 39-46, San Jose, CA, November 5-9 2006.
- [2318]
- S. H.
Kulkarni, D. M. Sylvester, and D. T. Blaauw.
Design-time optimization of post-silicon-tuned circuits using adaptive body
bias.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(3):481-494, March 2008.
- [2319]
- N. Kulkarni, N. Nukala, and S. Vrudhula.
Minimizing area and power of sequential CMOS circuits using threshold
decomposition.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 605-612, San Jose, CA, November 5-8 2012.
- [2320]
- N. Kulkarni,
J. Yang, J.-S. Seo, and S. Vrudhula.
Reducing power, leakage, and area of standard-cell asics using threshold logic
flip-flops.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(9):2873-2886, September 2016.
- [2321]
- M. Kulkarni and
T. Chen.
A sensitivity-based approach to analyzing signal delay uncertainty of coupled
interconnect.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(9):1336-1346, September 2005.
- [2322]
- J. P. Kulkarni and
K. Roy.
Ultralow-voltage process-variation-tolerant schmitt-trigger-based SRAM
design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):319-332, February 2012.
- [2323]
- S. H. Kulkarni
and D. Sylevster.
High performance level conversion for dual VDD design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(9):926-936, September 2004.
- [2324]
- P. Kulshreshtha, R. Palermo, M. Mortazavi, C. Bamji, and
H. Yalcin.
Transistor-level timing analysis using embedded simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 344-348, San Jose, CA, November 5-9 2000.
- [2325]
- T. Kumakura.
8k LCD : technologies and challenges toward the realization of SUPER
hi-VISION TV.
In 20th Asia and South Pacific Design Automation Conference, pages
680-683, Chiba/Tokyo, Japan, January 19-22 2015.
- [2326]
- S. V. Kumar, C.-H.
Kim, and S. S. Sapatnekar.
An analytical model for negative bias temperature instability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 493-496, San Jose, CA, November 5-9 2006.
- [2327]
- S. V. Kumar,
C.-H. Kim, and S. S. Sapatnekar.
NBTI-aware synthesis of digital circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
370-375, San Diego, CA, June 4-8 2007.
- [2328]
- S. V. Kumar,
C. V. Kashyap, and S. S. Sapatnekar.
A framework for block-based timing sensitivity analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 1-6, Monterey, CA,
February 25-26 2008.
- [2329]
- S. V. Kumar,
C. V. Kashyap, and S. S. Sapatnekar.
A framework for block-based timing sensitivity analysis.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
688-693, Anaheim, CA, June 8-13 2008.
- [2330]
- S. V. Kumar,
C. H. Kim, and S. S. Sapatnekar.
Body bias voltage computations for process and temperature compensation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(3):249-262, March 2008.
- [2331]
- S. V. Kumar, C. H.
Kim, and S. S. Sapatnekar.
Adaptive techniques for overcoming performance degradation due to aging in
CMOS circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(4):603-614, April 2011.
- [2332]
- J. A. Kumar,
S. Vasudevan, and S. N. Ahmadyan.
Goal-oriented stimulus generation for analog circuits.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1018-1023, San Francisco, CA, June 3-7 2012.
- [2333]
- A. Kumar and M. Anis.
Dual-threshold CAD framework for subthreshold leakage power aware fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):53-66, January 2007.
- [2334]
- A. Kumar and M. Anis.
FPGA design for timing yield under process variations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(3):423-435, March 2010.
- [2335]
- A. Kumar and M. Anis.
IR-drop management in fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(6):988-993, June 2010.
- [2336]
- S. K. Kumar and M. A.
Breuer.
Probabilistic aspects of boolean switching functions via a new transform.
Journal of the Association for Computing Machinery, 28(3):502-520,
July 1981.
- [2337]
- J. A. Kumar and
S. Vasudevan.
Formal probabilistic timing verification in RTL.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(5):788-801, May 2013.
- [2338]
- R. Kumar.
Interconnect and noise immunity design for the pentium 4 processor.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
938-943, Anaheim, CA, June 2-6 2003.
- [2339]
- B. Kumthekar, I.-H. Moon, and F. Somenzi.
A symbolic algorithm for low power sequential synthesis.
In 1997 International Symposium on Low Power Electronics and Design,
pages 56-61, Monterey, CA, August 18-20 1997.
- [2340]
- P. D.
Kundarewich and J. Rose.
Synthetic circuit generation using clustering and iteration.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):869-887, June 2004.
- [2341]
- K. Kundert,
H. Chang, D. Jeffereis, G. Lamant, E. Malavasi, and F. Sendig.
Design of mixed-signal systems-on-a-chip.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1561-1571, December 2000.
- [2342]
- K. Kundert and
H. Chang.
Model-based functional verification.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
421-424, Anaheim, CA, June 13-18 2010.
- [2343]
- K. Kundert.
Simulation methods for RF integrated circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
752-765, San Jose, CA, November 9-13 1997.
- [2344]
- S. Kundu, S. T.
Zachariah, Y.-S. Chang, and C. Tirumurti.
On modeling crosstalk faults.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(12):1909-1915, December 2005.
- [2345]
- S. Kundu,
M. Ganai, and R. Gupta.
Partial order reduction for scalable testing of systemc TLM designs.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
936-941, Anaheim, CA, June 8-13 2008.
- [2346]
- R. Kundu and
R. D. (Shawn) Blanton.
ATPG for noise-induced switch failures in domino logic.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 765-768, San Jose, CA, November 9-13 2003.
- [2347]
- S. Kundu.
Pitfalls of hierachical fault simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(2):312-314, February 2004.
- [2348]
- J. Kung, I. Han,
S. Sapatnekar, and Y. Shin.
Thermal signature: a simple yet accurate thermal index for floorplan
optimization.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
108-113, San Diego, CA, June 5-9 2011.
- [2349]
- D. S. Kung and R. Puri.
Optimal P/N width ratio selection for standard cell libraries.
In IEEE/ACM International Conference on Computer-Aided Design, pages
178-184, San Jose, CA, November 7-11 1999.
- [2350]
- D.-K. Kung.
Timing closure for low-fo4 microprocessor design.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
265-266, San Diego, CA, June 7-11 2004.
- [2351]
- W. Kunz, D. Stoffel,
and P. R. Menon.
Logic optimization and equivalence checking by implication analysis.
IEEE Transactions on Computer-Aided Design, 16(3):266-281, March
1997.
- [2352]
- C.-C. Kuo, Y.-L. Chen,
I-C. Tsai, L.-Y. Chan, and C. N.-J. Liu.
Behavior-level yield enhancement approach for large-scaled analog circuits.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
903-908, Anaheim, CA, June 13-18 2010.
- [2353]
- S.-H. Kuo and J. White.
A spectrally accurate integral equation solver for molecular surface
electrostatics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 899-906, San Jose, CA, November 5-9 2006.
- [2354]
- C.-C. Kuo and A. C.-H. Wu.
Delay budgeting for a timing-closure-driven design method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 202-207, San Jose, CA, November 5-9 2000.
- [2355]
- W. Kuo.
Reliability, yield and stress burn-in: a unified approach.
Kluwer Academic Publishers, Boston, MA, 1998.
- [2356]
- I. Kuon and J. Rose.
Measuring the gap between fpgas and asics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(2):203-215, February 2007.
- [2357]
- I. Kuon and J. Rose.
Exploring area and delay tradeoffs in fpgas with architecture and automated
transistor design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(1):71-84, January 2011.
- [2358]
- F. Kurdahi and A. C.
Parker.
Techniques for area estimation of VLSI layouts.
IEEE Transactions on Computer-Aided Design, 8(1):81-92, January
1989.
- [2359]
- M. Kurimoto,
H. Suzuki, R. Akiyama, T. Yamanaka, H. Ohkuma, H. Takata, and H. Shinohara.
Phase-adjustable error detection flip-flops with 2-stage hold driven
optimization and slack based grouping scheme for dynamic voltage scaling.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
884-889, Anaheim, CA, June 8-13 2008.
- [2360]
- T. Kuroda.
Optimization and control of vdd and vth for low-power, high-speed CMOS
design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 28-34, San Jose, CA, November 10-14 2002.
- [2361]
- R. P. Kurshan and
K. L. McMillan.
Analysis of digital circuits through symbolic reduction.
IEEE Transactions on Computer-Aided Design, 10(11):1356-1371,
November 1991.
- [2362]
- E. Kursun,
S. Ghiasi, and M. Sarrafzadeh.
Transistor level budgeting for power optimization.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 116-121, San Jose, CA, March 22-24 2004.
- [2363]
- V. Kursun,
S. G. Narendra, V. K. De, and E. G. Friedman.
High input voltage step-down DC-DC converters for integration in a low
voltage CMOS process.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 517-521, San Jose, CA, March 22-24 2004.
- [2364]
- V. Kursun and E. G.
Friedman.
Domino logic with variable threshold voltage keeper.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(6):1080-1093, December 2003.
- [2365]
- V. Kursun and E. G.
Friedman.
Node voltage dependent subthreshold leakage current characteristics of dynamic
circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 104-109, San Jose, CA, March 22-24 2004.
- [2366]
- V. Kursun and E. G.
Friedman.
Sleep switch dual threshold voltage domino logic with reduced standby leakage
current.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):485-496, May 2004.
- [2367]
- V. Kuruvilla, D. Sinha, J. Piaget, C. Visweswariah, and
N. Chandrachoodan.
Speeding up computation of the max/min of a set of gaussians for statistical
timing analysis and optimization.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2368]
- E. Kusse and J. Rabaey.
Low-energy embedded FPGA structures.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 155-160, Monterey, CA, August 10-12 1998.
- [2369]
- T. Kutzschebauch and L. Stok.
Regularity driven logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 439-446, San Jose, CA, November 5-9 2000.
- [2370]
- S. B. Kuusinen and
C. Hu.
Hot-carrier induced degradation of critical paths modeled by rule-based
analysis.
In IEEE Custom Integrated Circuits Conference, pages 69-72, Santa
Clara, CA, May 1-4 1995.
- [2371]
- H. H. Kwak, I.-H.
Moon, J. H. Kukula, and T. R. Shiple.
Combinational equivalence checking through function transformation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 526-533, San Jose, CA, November 10-14 2002.
- [2372]
- B. Kwak and E. S. Park.
An optimization-based error calculation for statistical power estimation of
CMOS logic circuits.
In IEEE/ACM 35th Design Automation Conference, pages 690-693, San
Francisco, CA, June 15-19 1998.
- [2373]
- W.-C. Kwon and T. Kim.
Optimal voltage allocation techniques for dynamically variable voltage
processors.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
125-130, Anaheim, CA, June 2-6 2003.
- [2374]
- J. Kwong and A. P.
Chandrakasan.
Variation-driven device sizing for minimum energy sub-threshold circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 8-13, Tegernsee, Germany, October 4-6 2006.
- [2375]
- E. D. Kyriakis-Bitzaros, S. Nikolaidis, and A. Tatsaki.
Accurate calculation of bit-level transition activity using word-level
statistics and entropy function.
In IEEE/ACM International Conference on Computer-Aided Design, pages
607-610, San Jose, CA, November 8-12 1998.
- [2376]
- C. Labrecque.
Near-term industrial perspective of analog CAD.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 456-457, San Jose, CA, November 5-9 2006.
- [2377]
- A. Labun.
Rapid method to account for process variation in full-chip capacitance
extraction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):941-951, June 2004.
- [2378]
- D. E. Lackey,
P. S. Zuchowski, and T. R. Bednar.
Managing power and performance for system-on-chip designs using voltage
islands.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 195-202, San Jose, CA, November 10-14 2002.
- [2379]
- V. Laddha and
M. Swaminathan.
Correlation of PDN impedance with jitter and voltage margin for high speed
channels.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 73-76, San Jose, CA, October 27-29 2008.
- [2380]
- S. Ladenheim, Y.-C. Chen, M. Mihajlovic, and V. Pavlidis.
IC thermal analyzer for versatile 3-D structures using multigrid
preconditioned krylov methods.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [2381]
- C. M. Lagoa,
F. Dabbene, and R. Tempo.
Hard bounds on the probability of performance with application to circuit
analysis.
IEEE Transactions on Circuits and Systems, 55(10):3178-3187, November
2008.
- [2382]
- K. Lahiri,
A. Raghunathan, and S. Dey.
Efficient power profiling for battery-driven embedded system design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):919-932, June 2004.
- [2383]
- S. Lai, B. Yan, and
P. Li.
Stability assurance and design optimization of large power delivery networks
with multiple on-chip voltage regulators.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 247-254, San Jose, CA, November 5-8 2012.
- [2384]
- S. Lai, B. Yan, and
P. Li.
Localized stability checking and design of IC power delivery with distributed
voltage regulators.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(9):1321-1334, September 2013.
- [2385]
- X. Lai and
J. Roychowdhury.
Automated oscillator macromodelling techniques for capturing amplitude
variations and injection locking.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 687-694, San Jose, CA, November 7-11 2004.
- [2386]
- M. Lajolo,
A. Raghunathan, S. Dey, and L. Lavagno.
Cosimulation-based power estimation for system-on-chip design.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):253-266, June 2002.
- [2387]
- Z. Lak and N. Nicolici.
In-system and on-the-fly clock tuning mechanism to combat lifetime performance
degradation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 434-441, San Jose, CA, November 7-10 2011.
- [2388]
- G. Lakshminarayana, A. Raghunathan, K. S. Khouri, N. K. Jha, and
S. Dey.
Common-case computations: a high-level energy and performance-optimization
technique.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(1):33-49, January 2004.
- [2389]
- G. Lakshminarayana and N. K. Jha.
FACT: A framework for the application of throughput and power optimizing
transformations to control-flow intensive behavioral descriptions.
In IEEE/ACM 35th Design Automation Conference, pages 102-107, San
Francisco, CA, June 15-19 1998.
- [2390]
- G. Lakshminarayana and N. K. Jha.
FACT: A framework for applying throughput and power optimizing
transformations to control-flow-intensive behavioral descriptions.
IEEE Transactions on Computer-Aided Design, 18(11):1577-1594,
November 1999.
- [2391]
- M. Lal and R. Mitra.
Simplification of large system dynamics using a moment evaluation algorithm.
IEEE Transactions on Automatic Control, AC-19(10):602-603, October
1974.
- [2392]
- Parag K. Lala.
Fault Tolerant & Fault Testable Hardware Design.
Prentice/Hall International, Englewood Cliffs, NJ, 1985.
- [2393]
- S. N. Lalgudi,
M. Swaminathan, and Y. Kretchmer.
On-chip power-grid simulation using latency insertion method.
IEEE Transactions on Circuits and Systems, 55(3):914-931, April
2008.
- [2394]
- K. N. Lalgudi
and M. C. Papaefthymiou.
Fixed-phase retiming for low power design.
In International Symposium on Low Power Electronics and Design, pages
259-264, Monterey, CA, August 12-14 1996.
- [2395]
- P. Lall.
Temperature as an input to microelectronics-reliability models.
IEEE Transactions on Reliability, 45(1):3-9, March 1996.
- [2396]
- W. K. C. Lam, R. K.
Brayton, and A. L. Sangiovanni-Vincentelli.
Circuit delay models and their exact computation using timed boolean functions.
In 30th ACM/IEEE Design Automation Conference, pages 128-134, Dallas,
Texas, June 14-18 1993.
- [2397]
- W.-C. D. Lam, J. Jain,
C.-K. Koh, V. Balakrishnan, and Y. Chen.
Statistical based link insertion for robust clock network design.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 588-591, San Jose, CA, November 6-10 2005.
- [2398]
- J. Lamoureux, G. G. F. Lemieux, and S. J. E. Wilton.
Glithless: dynamic power minimization in the fpgas through edge alignment and
glitch filtering.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(11):1521-1534, November 2008.
- [2399]
- J. Lamoureux and
S. J. E. Wilton.
On the interaction between power-aware FPGA CAD algorithms.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 701-708, San Jose, CA, November 9-13 2003.
- [2400]
- P. E. Landman and
J. M. Rabaey.
Power estimation for high-level synthesis.
In European Design Automation Conference (EDAC), pages 361-366,
1993.
- [2401]
- P. E. Landman and
J. M. Rabaey.
Black-box capacitance models for architectural power analysis.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
165-170, Napa, CA, April 24-27 1994.
- [2402]
- P. E. Landman and
J. M. Rabaey.
Activity-sensitive architectural power analysis for the control path.
In ACM/IEEE International Symposium on Low Power Design, pages 93-98,
Dana Point, CA, April 23-26 1995.
- [2403]
- P. E. Landman and
J. M. Rabaey.
Architectural power analysis: the dual bit type method.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
3(2):173-187, June 1995.
- [2404]
- P. E. Landman and
J. M. Rabaey.
Activity-sensitive architectural power analysis.
IEEE Transactions on Computer-Aided Design, 15(6):571-587, June
1996.
- [2405]
- P. Landman.
High-level power estimation.
In International Symposium on Low Power Electronics and Design, pages
29-35, Monterey, CA, August 12-14 1996.
- [2406]
- A. Lange,
C. Sohrmann, R. Jancke, J. Haase, B. Cheng, A. Asenov, and U. Schlichtmann.
Multivariate modeling of variability supporting non-gaussian and correlected
parameters.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(2):197-210, February 2016.
- [2407]
- M. Y.
Lanzerotti, G. Fiorenza, and R. A. Rand.
Assessment of on-chip wire-length distribution models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1108-1112, October 2004.
- [2408]
- M. Y.
Lanzerotti, G. Fiorenza, and R. A. Rand.
Interpretation of rent's rule for ultralarge-scale integrated circuit designs,
with an application to wirelength distribution models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1330-1347, December 2004.
- [2409]
- T. Larrabee.
Efficient generation of test patterns using boolean difference.
In IEEE International Test Conference, pages 795-801, 1989.
- [2410]
- T. Larrabee.
A framework for evaluating test pattern generation strategies.
In IEEE International Conference on Computer Design, pages 44-47,
1989.
- [2411]
- T. Larrabee.
Test pattern generation using boolean satisfiability.
IEEE Transactions on Computer-Aided Design, 11(1):4-15, January
1992.
- [2412]
- B. Lasbouygues, S. Engels, R. Wilson, P. Maurine, N. Azemard,
and D. Auvergne.
Logical effort model extension to propagation delay representation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1677-1684, September 2006.
- [2413]
- B. Lasbouygues, R. Wilson, N. Azemard, and P. Maurine.
Temperature and voltage-aware timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):801-815, April 2007.
- [2414]
- B. Lasbouygues, R. Wilson, N. Azemard, and P. Maurine.
Temperature and voltage aware timing analysis: application to voltage drops.
Design, Automation and Test in Europe (DATE-07), pages 1012-1017,
April 16-20 2007.
- [2415]
- L. Latorre,
V. Beroulle, and P. Nouet.
Design of CMOS MEMS based on mechanical resonators using a RF simulation
approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):962-967, June 2004.
- [2416]
- R. Lauwereins.
Biomedical electronics serving as physical environmental and emotional
watchdogs.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages 1-5,
San Francisco, CA, June 3-7 2012.
- [2417]
- J. Lavaei,
A. Babakhani, A. Hajimiri, and J. C. Doyle.
Solving large-scale hybrid circuit-antenna problems.
IEEE Transactions on Circuits and Systems, 58(2):374-387, February
2011.
- [2418]
- L. Lavagno,
P. C. McGeer, A. Saldanha, and A. L. Sangiovanni-Vincentelli.
Timed shannon circuits: a power-efficient design style and synthesis tool.
In 32nd Design Automation Conference, pages 254-260, San Francisco,
CA, June 12-16 1995.
- [2419]
- L. Lavagno,
C. W. Moon, R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
An efficient heuristic procedure for solving the state assignment problem for
event-based specifications.
IEEE Transactions on Computer-Aided Design, 14(1):45-60, January
1995.
- [2420]
- M. Lavin and
L. Liebmann.
CAD computation for manufacturability: Can we save VLSI technology from
itself.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 424-431, San Jose, CA, November 10-14 2002.
- [2421]
- E. L. Lawler.
Combinatorial optimization: networks and matroids.
Holt, Rinehart and Winston, New York, NY, 1976.
- [2422]
- J. F. Lawless.
Statistical Models and Methods for Lifetime Data.
John Wiley & Sons, New York, NY, 1982.
- [2423]
- J. Le, X. Li, and L. T.
Pileggi.
STAC: statistical timing analysis with correlation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
343-348, San Diego, CA, June 7-11 2004.
- [2424]
- J. Le, C. Hanken,
M. Held, M. S. Hagedorn, K. Mayaram, and T. S. Fiez.
Experimental characterization and analysis of an asynchronous approach for
reduction of substrate noise in digital circuitry.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):344-356, February 2012.
- [2425]
- Y. Leblebici and
S. M. Kang.
An integrated hot-carrier degradation simulator for VLSI reliability
analysis.
In IEEE International Conference on Computer-Aided Design (ICCAD),
pages 400-403, Santa Clara, CA, Nov. 11-15 1990.
- [2426]
- Y. Leblebici and
S-M. Kang.
Modeling of nmos transistors for simulation of hot-carrier-induced device and
circuit degradation.
IEEE Transactions on Computer-Aided Design, 11(2):235-246, February
1992.
- [2427]
- R. J. Lechner.
Harmonic analysis of switching functions.
In A. Mukhopadhyay, editor, Recent Developments in Switching Theory,
pages 121-228. Academic Press, New York, NY, 1971.
- [2428]
- K-J Lee, R. Gupta, and
M. A. Breuer.
A new method for assigning signal flow directions to MOS transistors.
In IEEE International Conference on Computer-Aided Design (ICCAD),
pages 492-495, Santa Clara, CA, November 11-15 1990.
- [2429]
- K.-J. Lee, C.-N. Wang,
R. Gupta, and M. A. Breuer.
An integrated system for assigning signal flow directions to CMOS
transistors.
IEEE Transactions on Computer-Aided Design, 14(12):1445-1458,
December 1995.
- [2430]
- J.-F. Lee, D. L.
Ostapko, J. Soreff, and C. K. Wong.
On the signal bounding problem in timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 507-514, San Jose, CA, November 4-8 2001.
- [2431]
- D. Lee, W. Kwong,
D. Blaauw, and D. Sylvester.
Analysis and minimization techniques for total leakage considering gate oxide
leakage.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
175-180, Anaheim, CA, June 2-6 2003.
- [2432]
- D. Lee, W. Kwong,
D. Blaauw, and D. Sylvester.
Simultaneous subthreshold and gate-oxide tunneling leakage current analysis in
nanometer CMOS design.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 287-292, San Jose, CA, March 24-26 2003.
- [2433]
- H. G. Lee, S. Nam,
and N. Chang.
Cycle-accurate energy measurment and high-level energy characterization of
fpgas.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 267-272, San Jose, CA, March 24-26 2003.
- [2434]
- J. Lee, K.-W. Kim,
Y. Huh, P. Bendix, and S.-M. Kang.
Chip-level charged-device modeling and simulation in CMOS integrated
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(1):67-81, January 2003.
- [2435]
- S. Lee, Y. Cheon,
and M. D. F. Wong.
A min-cost flow based detailed router for fpgas.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 388-393, San Jose, CA, November 9-13 2003.
- [2436]
- D. Lee, D. Blaauw,
and D. Sylvester.
Gate oxide leakage current analysis and reduction for VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(2):155-166, February 2004.
- [2437]
- D. Lee, V. Zolotov,
and D. Blaauw.
Static timing analysis using backward signal propagation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
664-669, San Diego, CA, June 7-11 2004.
- [2438]
- K. Lee, S.-J. Lee,
and H.-J. Yoo.
SILENT: serialized low energy transmission coding for on-chip interconnection
networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 448-451, San Jose, CA, November 7-11 2004.
- [2439]
- S. Lee, S. Das,
V. Bertacco, and T. Austin.
Circuit-aware architectural simulation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
305-310, San Diego, CA, June 7-11 2004.
- [2440]
- W.-H. Lee, S. Pant,
and D. Blaauw.
Analysis and reduction of on-chip inductance effects in power supply grids.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 131-136, San Jose, CA, March 22-24 2004.
- [2441]
- D. Lee, D. Blaauw,
and D. Sylvester.
Static leakage reduction through simultaneous vt/tox and state assignment.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):1014-1029, July 2005.
- [2442]
- D.-U. Lee, A. Abdul
Gaffar, O. Mencer, and W. Luk.
Minibit: bit-width optimization via affine arithmetic.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
837-840, Anaheim, CA, June 13-17 2005.
- [2443]
- K.-I. Lee, C. Lee,
H. Shin, Y.-J. Park, and H.-S. Min.
Efficient frequency-domain simulation technique for short-channel MOSFET.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(6):862-868, June 2005.
- [2444]
- Y.-M. Lee, Y. Cao,
T.-H. Chen, J.-M. Wang, and C. C.-P. Chen.
Hiprime: hierarchical and passivity preserved interconnect macromodeling engine
for RLKC power delivery.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(6):797-806, June 2005.
- [2445]
- B. N. Lee, L.-C.
Wang, and M. S. Abadir.
Refined statistical static timing analysis through learning spatial delay
correlations.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
149-154, San Francisco, CA, July 24-28 2006.
- [2446]
- D. Lee, D. Blaauw,
and D. Sylvester.
Runtime leakage minimization through probability-aware optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(10):1075-1088, October 2006.
- [2447]
- D.-U. Lee, A. A.
Guffar, R. C.-C. Cheung, O. Mencer, W. Luk, and G. A. Constantinides.
Accuracy-guaranteed bit-width optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):1990-2000, October 2006.
- [2448]
- Y. Lee, D.-K. Jeong,
and T. Kim.
Simultaneous control of power/ground current, wakeup time and transistor
overhead in power gated circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 169-172, San Jose, CA, November 10-13 2008.
- [2449]
- W.-P. Lee, H.-Y. Liu,
and Y.-W. Chang.
Voltage-island partitioning and floorplanning under timing constraints.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(5):690-702, May 2009.
- [2450]
- D.-J. Lee, M.-C.
Kim, and I. L. Markov.
Low-power clock trees for cpus.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 444-451, San Jose, CA, November 7-11 2010.
- [2451]
- H. Lee, S. Paik, and
Y. Shin.
Pulse width allocation and clock skew scheduling: optimizing sequential
circuits based on pulsed latches.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(3):355-366, March 2010.
- [2452]
- M.-S.-M. Lee, W.-T.
Liao, and C.-N.-J. Liu.
Levelized high-level current model of logic blocks for dynamic supply noise
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(6):845-857, June 2012.
- [2453]
- Y. Lee, D. Kim,
J. Cai, I. Lauer, L. Chang, S. J. Koester, D. Blaauw, and D. Sylvester.
Low-power circuit analysis and design based on heterojunction tunneling
transistors (hetts).
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(9):1632-1643, September 2013.
- [2454]
- Y.-J. Lee,
D. Limbrick, and S.-K. Lim.
Power benefit study for ultra-high density transistor-level monolithic 3d ics.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2455]
- D. Lee, T. Kim,
K. Han, Y. Hoskote, L. K. John, and A. Gerstlauer.
Learning-based power modeling of system-level black-box ips.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 847-853, Austin TX, November 2-6 2015.
- [2456]
- W. Lee, Y. Wang, and
M. Pedram.
Optimizing a reconfigurable power distribution network in a multicore platform.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(7):1110-1123, July 2015.
- [2457]
- W. Lee, Y. Wang,
D. Shin, S. Nazarian, and M. Pedram.
Design and optimization of a reconfigurable power delivery network for
large-area, DVS-enabled oled displays.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 159-164, Rome, Italy, July 22-24 2015.
- [2458]
- H.-I. Lee, C.-Y. Han,
and J.-C.-M. Li.
A multicircuit simulator based on inverse jacobian matrix reuse.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(7):1130-1137, July 2016.
- [2459]
- D. Lee and D. Blaauw.
Static leakage reduction through simultaneouos threshold voltage and state
assignment.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
191-194, Anaheim, CA, June 2-6 2003.
- [2460]
- H.-C. Lee and Y.-W. Chang.
A chip-package-board co-design methodology.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1082-1087, San Francisco, CA, June 3-7 2012.
- [2461]
- H.-G. Lee and N. Chang.
Powering the iot: storage-less and converter-less energy harvesting.
In 20th Asia and South Pacific Design Automation Conference, pages
124-129, Chiba/Tokyo, Japan, January 19-22 2015.
- [2462]
- Y.-M. Lee and C. C.-P. Chen.
Power grid transient simulation in linear time based on
tranmission-line-modeling alternating-direction-implicit method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 75-80, San Jose, CA, November 4-8 2001.
- [2463]
- Y.-M. Lee and C. C.-P. Chen.
Power grid transient simulation in linear time based on
transmission-line-modeling alternating-direction-implicit method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(11):1343-1352, November 2002.
- [2464]
- Y.-M. Lee and C. C.-P. Chen.
A hierarchical analysis methodology for chip-level power delivery with
realizable model reduction.
In IEEE/ACM Asia and South Pacific Design Automation Conference
(ASP-DAC), pages 614-618, Kitakyushu, Japan, January 21-24 2003.
- [2465]
- Y.-M. Lee and C. C.-P. Chen.
The power grid transient simulation in linear time based on 3-D
alternating-direction-implicit method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(11):1545-1550, November 2003.
- [2466]
- C.-Y. Lee and N. K. Jha.
Fincanon: a PVT-aware integrated delay and power modeling framework of
finfet-based caches and on-chip networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1150-1163, May 2014.
- [2467]
- Y.-J. Lee and S. K. Lim.
Co-optimization and analysis of signal, power, and thermal interconnects in
3-D ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(11):1635-1648, November 2011.
- [2468]
- Y.-S. Lee and P. M. Maurer.
Bit-parallel multidelay simulation.
IEEE Transactions on Computer-Aided Design, 15(12):1547-1554,
December 1996.
- [2469]
- J. Y. Lee and R. A. Rohrer.
Awesymbolic: compiled analysis of linear(ized) circuits using asymptotic
waveform evaluation.
In 29th ACM/IEEE Design Automation Conference, pages 213-218,
Anaheim, CA, June 8-12 1992.
- [2470]
- S. Lee and T. Sakurai.
Run-time voltage hopping for low-power real-time systems.
In Design Automation Conference, pages 806-809, Los Angeles, CA, June
5-9 2000.
- [2471]
- E. A. Lee
and A. L. Sangiovanni-Vincentelli.
Comparing models of computation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
234-241, San Jose, CA, November 10-14 1996.
- [2472]
- J. Lee and
A. Shrivastava.
Static analysis of register file vulnerability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(4):607-616, April 2011.
- [2473]
- S.-H. Lee and
S. Vishwanath.
Boolean functions over nano-fabrics: improving resilience through coding.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(11):2054-2065, November 2012.
- [2474]
- L. Lee and L.-C. Wang.
On bounding the delay of a critical path.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 81-88, San Jose, CA, November 5-9 2006.
- [2475]
- H. B. Lee.
Matrix filtering as an aid to numerical integration.
In Proceedings of the IEEE, pages 1826-1831, November 1967.
Published as Proceedings of the IEEE, volume 55, number 11.
- [2476]
- E. A. Lee.
CPS foundations.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
737-742, Anaheim, CA, June 13-18 2010.
- [2477]
- L. Leem, H. Cho,
H.-H. Lee, Y.-M. Kim, Y. Li, and S. Mitra1.
Cross-layer error resilience for robust systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 177-180, San Jose, CA, November 7-11 2010.
- [2478]
- D. M. W. Leenaerts.
Application of interval analysis for circuit design.
IEEE Transactions on Circuits and Systems, 37(6):803-807, June
1990.
- [2479]
- D. M. W. Leenaerts.
Low power RF IC design for wireless communication.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 428-433, Seoul, Korea, August 25-27 2003.
- [2480]
- S. Lefteriu and
A. C. Antoulas.
A new approach to modeling multiport systems from frequency-domain data.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(1):14-27, January 2010.
- [2481]
- S. Lefteriu and
J. Mohring.
Generating parametric models from tabulated data.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
679-682, Anaheim, CA, June 13-18 2010.
- [2482]
- E. Lehman,
Y. Watanabe, J. Grodstein, and H. Harkness.
Logic decomposition during technology mapping.
In IEEE/ACM International Conference on Computer-Aided Design, pages
264-271, San Jose, CA, November 5-9 1995.
- [2483]
- E. Lehman,
Y. Watanabe, J. Grodstein, and H. Harkness.
Logic decomposition during technology mapping.
IEEE Transactions on Computer-Aided Design, 16(8):813-834, August
1997.
- [2484]
- L. Lei, F. Xie, and
K. Cong.
Post-silicon conformance checking with virtual prototypes.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2485]
- L. Lei and T. Nakamura.
A fast algorithm for evaluating the matrix polynomial
I+A+...+a^lbraceN-1rbrace.
IEEE Transactions on Circuits and Systems, Vol. I, 39(4):299-300,
April 1992.
- [2486]
- C. E. Leiserson.
The cilk++ concurrency platform.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
522-527, San Francisco, CA, July 26-31 2009.
- [2487]
- H. Lekatsas,
J. Henkel, and W. Wolf.
Approximate arithmetic coding for bus transition reduction in low power
designs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):696-707, June 2005.
- [2488]
- T. Lengauer and
R. E. Tarjan.
A fast algorithm for finding dominators in a flowgraph.
ACM Transactions on Programming Languages and Systems, 1(1):121-141,
July 1979.
- [2489]
- T. Lengauer.
Combinatorial Algorithms for Integrated Circuit Layout.
John Wiley & Sons, New York, NY, 1990.
- [2490]
- C. K.
Lennard, P. Buch, and A. R. Newton.
Logic synthesis using power-sensitive don't care sets.
In International Symposium on Low Power Electronics and Design, pages
293-296, Monterey, CA, August 12-14 1996.
- [2491]
- C. K. Lennard and
A. R. Newton.
An estimation technique to guide low power resynthesis algorithms.
In ACM/IEEE International Symposium on Low Power Design, pages
227-232, Dana Point, CA, April 23-26 1995.
- [2492]
- C. K. Lennard and
A. R. Newton.
On estimation accuracy for guiding low-power resynthesis.
IEEE Transactions on Computer-Aided Design, 15(6):644-664, June
1996.
- [2493]
- K.-S. Leung.
SPIDER: simultaneous post-layout IR-drop and metal density enhancement wire
redundant fill.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 33-38, San Jose, CA, November 6-10 2005.
- [2494]
- I. Levi, A. Belenky,
and A. Fish.
Logical effort for CMOS-based dual model logic gates.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1042-1053, May 2014.
- [2495]
- S. P. Levitan,
J. A. Martinez, T. P. Kurzweg, A. J. Davare, M. Kahrs, M. Bails, and D. M.
Chiarulli.
System simulation of mixed-signal multi-domain microsystems with piecewise
linear models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(2):139-154, February 2003.
- [2496]
- S. P. Levitan and
D. M. Chiarulli.
Massively parallel processing: It's deja vu all over again.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
534-538, San Francisco, CA, July 26-31 2009.
- [2497]
- S. P. Levitan.
You can get there from here: connectivity of random graphs on grids.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
272-273, San Diego, CA, June 4-8 2007.
- [2498]
- H. Levy, W. Scott,
D. MacMillen, and J. White.
A rank-one update method for efficient processing of interconnect parasitics in
timing analysis.
In Design Automation Conference, pages 75-78, Los Angeles, CA, June
5-9 2000.
- [2499]
- R. Levy,
D. Blaauw, G. Braca, A. Dasgupta, A. Grinshpon, C. Oh, B. Orshav,
S. Sirichotiyakul, and V. Zolotov.
Clarinet: A noise analysis tool for deep submicron design.
In Design Automation Conference, pages 233-238, Los Angeles, CA, June
5-9 2000.
- [2500]
- D. M. Lewis.
Device model approximation using 2^N trees.
IEEE Transactions on Computer-Aided Design, 9(1):30-38, January
1990.
- [2501]
- P-C. Li, G. I.
Stamoulis, and I. N. Hajj.
A probabilistic timing approach to hot-carrier effect estimation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
210-213, Santa Clara, CA, November 8-12 1992.
- [2502]
- T. Li, C-H Tsai, and
S-M Kang.
Efficient transient electrothermal simulation of CMOS VLSI circuits under
electrical overstress.
In IEEE/ACM International Conference on Computer-Aided Design, pages
6-11, San Jose, CA, November 8-12 1998.
- [2503]
- C.-S. Li, K. N.
Sivarajan, and D. G. Messerschmitt.
Statistical analysis of timing rules for high-speed synchronous VLSI systems.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(4):477-482, December 1999.
- [2504]
- W. Li, Q. Li, J. S.
Yuan, J. McConkey, Y. Chen, S. Chetlur, J. Zhou, and A. S. Oates.
Hot-carrier-induced circuit degradation for 0.18um CMOS technology.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 284-289, San Jose, CA, March 26-28 2001.
- [2505]
- X. Li, X. Zeng,
D. Zhou, and X. Ling.
Behavioral modeling of analog circuits by wavelet collocation method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 65-69, San Jose, CA, November 4-8 2001.
- [2506]
- X. Li, B. Hu, X. Ling,
and X. Zeng.
A wavelet-balance approach for steady-state analysis of nonlinear circuits.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(5):688-694, May 2002.
- [2507]
- L. Li, N. Vijaykrishnan,
M. Kandemir, and M. J. Irwin.
Adaptive error protection for energy efficiency.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 2-7, San Jose, CA, November 9-13 2003.
- [2508]
- F. Li, Y. Lin, and
L. He.
FPGA power reduction using configurable dual-vdd.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
735-740, San Diego, CA, June 7-11 2004.
- [2509]
- F. Li, Y. Lin, and
L. He.
Vdd programmability to reduce FPGA interconnect power.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 760-765, San Jose, CA, November 7-11 2004.
- [2510]
- F. Li, Y. Lin, L. He,
and J. Cong.
Low-power FPGA using pre-defined dual-vdd/dual-vt fabrics.
In ACM/SIGDA International Symposium on Field Programmable Gate
Arrays, pages 42-50, Monterey, CA, February 22-24 2004.
- [2511]
- H. Li, S. Bhunia,
Y. Chen, K. Roy, and T. N. Vijaykumar.
DCG: deterministic clock-gating for low-power microprocessor design.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(3):245-254, March 2004.
- [2512]
- P. Li, L. T. Pileggi,
M. Asheghi, and R. Chandra.
Efficient full-chip thermal modeling and analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 319-326, San Jose, CA, November 7-11 2004.
- [2513]
- X. Li,
P. Gopalakrishnan, Y. Xu, and L. T. Pileggi.
Robust analog/RF circuit design with projection-based posynomial modeling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 855-862, San Jose, CA, November 7-11 2004.
- [2514]
- X. Li, J. Le,
P. Gopalakrishnan, and L. T. Pileggi.
Asymptotic probability extraction for non-normal distributions of circuit
performance.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 2-9, San Jose, CA, November 7-11 2004.
- [2515]
- X. Li, Y. Xu, P. Li,
P. Gopalakrishnan, and L. T. Pileggi.
A frequency relaxation approach for analog/RF system-level simulation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
842-847, San Diego, CA, June 7-11 2004.
- [2516]
- F. Li, Y. Lin, L. He,
D. Chen, and J. Cong.
Power modeling and characteristics of field programmable gate arrays.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(11):1712-1724, November 2005.
- [2517]
- H. Li, C.-Y. Cher, and
T. N. Vijaykumar.
Combined circuit and architectural level variable supply-voltage scaling for
low power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(5):564-576, May 2005.
- [2518]
- H. Li, Z. Qi, S. X.-D.
Tan, L. Wu, Y. Cai, and X. Hong.
Partitioning-based approach to fast on-chip decap budgeting and minimization.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
170-175, Anaheim, CA, June 13-17 2005.
- [2519]
- X. Li, J. Le,
M. Celik, and L. T. Pileggi.
Defining statistical sensitivity for timing optimization of logic circuits with
large-scale process and environmental variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 844-851, San Jose, CA, November 6-10 2005.
- [2520]
- X. Li, J. Le, L. T.
Pileggi, and A. Strojwas.
Projection-based performance modeling for inter/intra-die variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 721-727, San Jose, CA, November 6-10 2005.
- [2521]
- X. Li, P. Li, and
L. T. Pileggi.
Parameterized interconnect order reduction with explicit-and-implicit
multi-parameter moment matching for inter/intra-die variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 806-812, San Jose, CA, November 6-10 2005.
- [2522]
- H. Li, J. Fan, Z. Qi,
S. X.-D. Tan, L. Wu, Y. Cai, and X. Hong.
Partitioning-based approach to fast on-chip decouping capacitor budgeting and
minimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2402-2412, November 2006.
- [2523]
- H. Li, W.-Y. Yin, and
J.-F. Mao.
Comments on "modeling of metallic carbon-nanotube interconnects for circuit
simulations and a comparison with cu interconnects for sealed technologies".
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):3042-3044, December 2006.
- [2524]
- H. Li, C. E. Zemke,
G. Manetas, V. I. Okhmatovski, E. Rosenbaum, and A. C. Cangellaris.
An automated and efficient substrate noise analysis tool.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(3):454-468, March 2006.
- [2525]
- P. Li, L. T. Pileggi,
M. Asheghi, and R. Chandra.
IC thermal simulation and modeling via efficient multigrid-based approaches.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1763-1776, September 2006.
- [2526]
- X. Li, J. Le, and
L. T. Pileggi.
Projection-based statistical analysis of full-chip leakage power with
non-log-normal distributions.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
103-108, San Francisco, CA, July 24-28 2006.
- [2527]
- F. Li, Y. Lin, and
L. He.
Field programmability of supply voltages for FPGA power reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):752-764, April 2007.
- [2528]
- X. Li,
P. Gopalakrishnan, Y. Xu, and L. T. Pileggi.
Robust analog/RF circuit design with projection-based performance modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):2-15, January 2007.
- [2529]
- X. Li, J. Le,
P. Gopalakrishnan, and L. T. Pileggi.
Asymptotic probability extraction for nonnormal performance distributions.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):16-37, January 2007.
- [2530]
- X. Li, B. Taylor,
Y.-T. Chien, and L. T. Pileggi.
Adaptive post-silicon tuning for analog circuits: concept, analysis and
optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 450-457, San Jose, CA, November 5-8 2007.
- [2531]
- Y.-T. Li, Z. Bai,
Y. Su, and X. Zeng.
Parameterized model order reduction via a two-directional arnoldi process.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 868-873, San Jose, CA, November 5-8 2007.
- [2532]
- T. Li, W. Zhang, and
Z. Yu.
Full-chip leakage analysis in nano-scale technologies: mechanisms, variation
sources, and verification.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
594-599, Anaheim, CA, June 8-13 2008.
- [2533]
- X. Li, J. Le,
M. Celik, and L. T. Pileggi.
Defining statistical timing sensitivity for logic circuits with large-scale
process and environmental variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(6):1041-1054, June 2008.
- [2534]
- X. Li, Y. Zhan, and
L. T. Pileggi.
Quadratic statistical MAX approximation for parametric yield estimation of
analog/RF integrated circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(5):831-843, May 2008.
- [2535]
- Y.-T. Li, Z. Bai,
Y. Su, and X. Zeng.
Model order reduction of parameterized interconnect networks via a
two-directional arnoldi process.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(9):1571-1582, September 2008.
- [2536]
- B. Li, N. Chen, and
U. Schlichtmann.
Timing model extraction for sequential circuits considering process variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 333-343, San Jose, CA, November 2-5 2009.
- [2537]
- K. S.-M. Li, C.-L. Lee,
C. Su, and J.-E. Chen.
A unified detection scheme for crosstalk effects in interconnection bus.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):306-311, February 2009.
- [2538]
- X. Li, R. R. Rutenbar,
and R. D. Blanton.
Virtual probe: a statistically optimal framework for minimum-cost silicon
characterization of nanoscale integrated circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 433-440, San Jose, CA, November 2-5 2009.
- [2539]
- B. Li, N. Chen, and
U. Schlichtmann.
Fast statistical timing analysis of latch-controlled circuits for arbitrary
clock periods.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 524-531, San Jose, CA, November 7-11 2010.
- [2540]
- X. Li, C. C. McAndrew,
W. Wu, S. Chaudhry, J. Victory, and G. Gildenblat.
Statistical modeling with the PSP MOSFET model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):599-606, April 2010.
- [2541]
- B. Li, N. Chen, and
U. Schlichtmann.
Fast statistical timing analysis for circuits with post-silicon tunable clock
buffers.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 111-117, San Jose, CA, November 7-10 2011.
- [2542]
- B. Li, P. S.
McLaughlin, J. P. Bickford, P. Habitz, D. Netrabile, and T. Sullivan.
Statistical evaluation of electromigration reliability at chip level.
IEEE Transactions on Device and Materials Reliability, 11(1):86-91,
March 2011.
- [2543]
- S. Li, K. Chen, J.-H.
Ahn, J. B. Brockman, and N. P. Jouppi.
CACTI-P: architecture-level modeling for SRAM-based structures with
advanced leakage reduction techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 694-701, San Jose, CA, November 7-10 2011.
- [2544]
- X.-C. Li, J.-F. Mao,
and M. Swaminathan.
Transient analysis of CMOS-gate-driven RLGC interconnects based on FDTD.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(4):574-583, April 2011.
- [2545]
- Y. Li, H. Schneider,
F. Schnabel, R. Thewes, and D. Schmitt-Landsiedel.
DRAM yield analysis and optimization by a statistical design approach.
IEEE Transactions on Circuits and Systems, 58(12):2906-2918, December
2011.
- [2546]
- Z. Li,
R. Balasubramanian, F. Liu, and S. Nassif.
2011 TAU power grid simulation contest: benchmark suite and results.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 478-481, San Jose, CA, November 7-10 2011.
- [2547]
- B. Li, N. Chen, and
U. Schlichtmann.
Statistical timing analysis for latch-controlled circuits with reduced
iterations and graph transformations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(11):1670-1683, November 2012.
- [2548]
- Z. Li, M. Mohamed,
X. Chen, E. Dudley, K. Meng, L. Shang, A. R. Mickelson, R. Joseph,
M. Vachharajani, B. Schwartz, and Y. Sun.
Reliability modeling and management of nanophotonic on-chip networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(1):98-111, January 2012.
- [2549]
- B. Li, N. Chen, Y. Xu,
and U. Schlichtmann.
On timing model extraction and hierarchical statistical timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(2):367-380, February 2013.
- [2550]
- Y. Li, P. Chow,
J. Jiang, M. Zhang, and S. Wei.
Software/handware parallel long-period random number generation framework based
on the WELL method.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1054-1059, May 2014.
- [2551]
- D.-A. Li,
M. Marek-Sadowska, and S. R. Nassif.
A method for improving power grid resilience to electromigration-caused via
failures.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(1):118-130, January 2015.
- [2552]
- D.-A. Li,
M. Marek-Sadowska, and S. R. Nassif.
T-VEMA: a temperature- and variation-aware electromigration power grid
analysis tool.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(10):2327-2331 K electromigration (EM), jL product, process variation,
thermal analysis, October 2015.
- [2553]
- X. Li, F. Yang, D. Wu,
Z. Zhou, and X. Zeng.
MOS table models for fast and accurate simulation of analog and mixed-signal
circuits using efficient oscillation-diminishing interpolations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(9):1481-1494, September 2015.
- [2554]
- S. Li, L. Liu, P. Gu,
C. Xu, and Y. Xie.
Nvsim-CAM: a circuit-level simulator for emerging nonvolatile memory based
content-addressable memory.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [2555]
- S. Li, Y. Wang,
W. Wen, Y. Wang, Y. Chen, and H. Li.
A data locality-aware design framework for reconfigurable sparse matrix-vector
multiplication kernel.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [2556]
- J. Li and J. Draper.
Accelerating soft-error-rate (SER) estimation in the presence of single event
transients.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [2557]
- P.-C. Li and I. N. Hajj.
Computer-aided redesign of VLSI circuits for hot-carrier reliability.
IEEE Transactions on Computer-Aided Design, 15(5):453-464, May
1996.
- [2558]
- Y. Li and J. Henkel.
A framework for estimating and minimizing energy dissipation of embedded
HW/SW systems.
In IEEE/ACM 35th Design Automation Conference, pages 188-193, San
Francisco, CA, June 15-19 1998.
- [2559]
- D.-A. Li and
M. Marek-Sadowska.
Variation-aware electromigration analysis of power/ground networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 571-576, San Jose, CA, November 7-10 2011.
- [2560]
- J. C.-M. Li and E. J.
McCluskey.
Diagnosis of resistive-open and stuck-open defects in digital CMOS ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(11):1748-1759, November 2005.
- [2561]
- P. Li and L. T. Pileggi.
Compact reduced-order modeling of weakly nonlinear analog and RF circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(2):184-203, February 2005.
- [2562]
- Z. Li and C.-J. R. Shi.
SILCA: fast-yet-accurate time-domain simulation of VLSI circuits with
strong parasitic coupling effects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 793-799, San Jose, CA, November 9-13 2003.
- [2563]
- P. Li and W. Shi.
Model order reduction of linear networks with massive ports via
frequency-dependent port packing.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
267-272, San Francisco, CA, July 24-28 2006.
- [2564]
- Z. Li and C.-J. R. Shi.
A quasi-newton preconditioned newton-krylov method for robust and efficient
time-domain simulation of integrated circuits with strong parasitic
couplings.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2868-2881, December 2006.
- [2565]
- Z. Li and C.-J. R. Shi.
SILCA: SPICE-accurate iterative linear-centric analysis for efficient
time-domain simulation of VLSI circuits with strong parasitic couplings.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(6):1087-1103, June 2006.
- [2566]
- J.-R. Li and J. White.
Efficient model reduction of interconnect via approximate system gramians.
In IEEE/ACM International Conference on Computer-Aided Design, pages
380-383, San Jose, CA, November 7-11 1999.
- [2567]
- T. Li and Z. Yu.
Statistical analysis of full-chip leakage power considering junction tunneling
leakage.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 99-102,
San Diego, CA, June 4-8 2007.
- [2568]
- P. Li.
Power grid simulation via efficient sampling-based sensitivity analysis and
hierarchical symbolic relaxation.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
664-669, Anaheim, CA, June 13-17 2005.
- [2569]
- P. Li.
Variational analysis of large power grids by exploring statistical sampling
sharing and spatial locality.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 645-651, San Jose, CA, November 6-10 2005.
- [2570]
- P. Li.
Statistical sampling-based parametric analysis of power grids.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2852-2867, December 2006.
- [2571]
- X. Li.
Finding deterministic solution from underdetermined equation: large-scale
performance modeling by least angle regression.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
364-369, San Francisco, CA, July 26-31 2009.
- [2572]
- X. Li.
Finding deterministic solution from underdetermined equation: large-scale
performance variability modeling of analog/RF circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1661-1668, November 2010.
- [2573]
- P. Li.
Design analysis of IC power delivery.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 664-666, San Jose, CA, November 5-8 2012.
- [2574]
- B. Li.
Statistical timing analysis and criticality computation for circuits with
post-silicon clock tuning elements.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(11):1784-1797, November 2015.
- [2575]
- X. Liang,
K. Turgay, and D. Brooks.
Architectural power models for SRAM and CAM structures based on hybrid
analytical/empirical techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 824-830, San Jose, CA, November 5-8 2007.
- [2576]
- X. Liang and D. Brooks.
Microarchitecture parameter selection to optimize system performance under
process variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 429-436, San Jose, CA, November 5-9 2006.
- [2577]
- Y. Liang and D. Chen.
Clusred: clustering and network reduction based probabilistic optimal power
flow analysis for large-scale smart grids.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [2578]
- H. Liao, W. W-M Dai,
R. Wang, and F-Y Chang.
S-parameter based macro model of distributed-lumped networks using
exponentially decayed polynomial function.
In ACM/IEEE Design Automation Conference, pages 726-731, Dallas, TX,
June 14-18 1993.
- [2579]
- W. Liao, J. M.
Basile, and L. He.
Leakage power modeling and reduction with data reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 714-719, San Jose, CA, November 10-14 2002.
- [2580]
- W. Liao, J. M.
Basile, and L. He.
Microarchitecture-level leakage reduction with data retention.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1324-1328, November 2005.
- [2581]
- W. Liao, L. He, and
K. M. Lepak.
Temperature and supply voltage aware performance and power modeling at
microarchitecture level.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):1042-1053, July 2005.
- [2582]
- K.-Y. Liao, C.-Y.
Chang, and J.-C.-M. Li.
A parallel test pattern generation algorithm to meet multiple quality
objectives.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(11):1767-1772, November 2011.
- [2583]
- H.-T. Liaw and C.-S. Lin.
On the OBDD-representation of general boolean functions.
IEEE Transactions on Computers, 41(6):661-664, June 1992.
- [2584]
- D. Lidsky and J. M.
Rabaey.
Early power exploration - a world wide web application.
In 33rd Design Automation Conference, pages 27-32, Las Vegas, NV,
June 3-7 1996.
- [2585]
- L. W. Liebmann
and R. O. Topaloglu.
Design and technology co-optimization near single-digit nodes.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 582-585, San Jose, CA, November 2-6 2014.
- [2586]
- B. K. Liew, N. W.
Cheung, and C. Hu.
Electromigration interconnect lifetime under AC and pulse DC stress.
In IEEE International Reliability Physics Symposium, pages 215-219,
1989.
- [2587]
- B. K. Liew, P. Fang,
N. W. Cheung, and C. Hu.
Reliability simulator for interconnect and intermetallic contact
electromigration.
In IEEE 28th International Reliability Physics Symposium, pages
111-118, New Orleans, LA, March 27-29 1990.
- [2588]
- M. R. Lightner and
G. D. Hachtel.
Implication algorithms for MOS switch-level functional macromodeling,
implication and testing.
In IEEE 19th Design Automation Conference, pages 691-698, Las Vegas,
NV, June 1982.
- [2589]
- Y. J. Lim, K-I. Son,
H-J. Park, and M. Soma.
A statistical approach to the estimation of delay-dependent switching activity
in CMOS combinational circuits.
In 33rd Design Automation Conference, pages 445-450, Las Vegas, NV,
June 3-7 1996.
- [2590]
- D. Lim, J.-W. Lee,
B. Gassend, G. E. Suh, M. van Dijk, and S. Devadas.
Extracting secret keys from integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(10):1200-1205, October 2005.
- [2591]
- S.-K. Lim, X. Zhao,
and M. Scheuermann.
Analysis of DC current crowding in through-silicon-vias and its impact on
power integrity in 3-D ics.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
157-162, San Francisco, CA, June 3-7 2012.
- [2592]
- A. Lim and Y-M. Chee.
Graph partitioning using tabu search.
In IEEE International Symposium on Circuits and Systems, pages
1164-1167, June 1991.
- [2593]
- Y. J. Lim and M. Soma.
Statistical estimation of delay-dependent switching activities in embedded
CMOS combinational circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
5(3):309-319, September 1997.
- [2594]
- S. Lin, E. S. Kuh, and
M. Marek-Sadowska.
Stepwise equivalent conductance circuit simulation technique.
IEEE Transactions on Computer-Aided Design, 12(5):672-683, May
1993.
- [2595]
- J-Y. Lin, T-C. Liu,
and W-Z. Shen.
A cell-based power estimation in CMOS combinational circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
304-309, San Jose, CA, November 6-10 1994.
- [2596]
- J.-Y. Lin, W.-Z. Shen,
and J.-Y. Jou.
A power modeling and characterization method for the CMOS standard cell
library.
In IEEE/ACM International Conference on Computer-Aided Design, pages
400-404, San Jose, CA, November 10-14 1996.
- [2597]
- J-Y Lin, W-Z Shen, and
J-Y Jou.
A power modeling and characterization method for macrocells using structure
information.
In IEEE/ACM International Conference on Computer-Aided Design, pages
502-506, San Jose, CA, November 9-13 1997.
- [2598]
- T. Lin, E. Acar, and
L. Pileggi.
h-gamma: An RC delay metric based on a gamma distribution approximation of
the homogeneous response.
In IEEE/ACM International Conference on Computer-Aided Design, pages
19-25, San Jose, CA, November 8-12 1998.
- [2599]
- J.-Y. Lin, W.-Z. Shen,
and J.-Y. Jou.
A structure-oriented power modeling technique for macrocells.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(3):380-391, September 1999.
- [2600]
- T. Lin, M. W. Beattie,
and L. T. Pileggi.
On the efficacy of simplified 2d on-chip inductance models.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
757-762, New Orleans, LA, June 10-14 2002.
- [2601]
- Y. Lin, F. Li, and
L. He.
Circuits and architectures for field programmable gate array with configurable
supply voltage.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(9):1035-1047, September 2005.
- [2602]
- Y. Lin, Y. Hu, L. He,
and V. Raghunat.
An efficient chip-level time slack allocation algorithm for dual-vdd FPGA
power reduction.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 168-173, Tegernsee, Germany, October 4-6 2006.
- [2603]
- S. Lin, H. Yang, and
R. Luo.
A novel gamma.d/n RLCG transmission line model considering complex RC(L)
loads.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(5):970-977, May 2007.
- [2604]
- H.-P. Lin, J.-H. R.
Jiang, and R.-R. Lee.
To SAT or not to SAT: Ashenhurst decomposition in a large scale.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 32-37, San Jose, CA, November 10-13 2008.
- [2605]
- M.-P.-H. Lin, C.-C.
Hsu, and Y.-T. Chang.
Post-placement power optimization with multi-bit flip-flops.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(12):1870-1882, December 2011.
- [2606]
- P.-C.-K. Lin,
A. Mandal, and S. Khatri.
Boolean satisfiability using noise based logic.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1256-1257, San Francisco, CA, June 3-7 2012.
- [2607]
- C.-C. Lin,
A. Chakrabarti, and N. K. Jha.
Optimized quantum gate library for various physical machine descriptions.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(11):2055-2068, November 2013.
- [2608]
- H. Lin, P. Li, and
C. J. Myers.
Verification of digitally-intensive analog circuits via kernel ridge regression
and hybrid reachability analysis.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2609]
- I.-C. Lin, C.-H. Lin,
and K.-H. Li.
Leakage and aging optimization using transmission gate-based technique.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):87-99, January 2013.
- [2610]
- T. Lin, C. Chu,
J. R. Shinnerl, I. Bustany, and I. Nedelchev.
POLAR: placement based on novel rough legalization and refinement.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 357-362, San Jose, CA, November 18-21 2013.
- [2611]
- X. Lin, Y. Wang, and
M. Pedram.
Joint sizing and adaptive independent gate control for finfet circuits
operating in multiple voltage regimes using the logical effort method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 444-449, San Jose, CA, November 18-21 2013.
- [2612]
- H.-T. Lin, Y.-L.
Chuang, Z.-H. Yang, and T.-Y. Ho.
Pulsed-latch utilization for clock-tree power optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(4):721-733, April 2014.
- [2613]
- I.-C. Lin, K.-H. Li,
C.-H. Lin, and K.-C. Wu.
NBTI and leakage reduction using ILP-based approach.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(9):2034-2038, September 2014.
- [2614]
- L. Lin, Y. Saad, and
C. Yang.
Approximating spectral densities of large matrices.
SIAM Review, 58(1):34-65, March 2016.
- [2615]
- S.-C. Lin and K. Banerjee.
An electrothermally-aware full-chip substrate temperature gradient evaluation
methodology for leakage dominant technologies with implications for power
estimation and hot-spot management.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 568-574, San Jose, CA, November 5-9 2006.
- [2616]
- S.-C. Lin and K. Banerjee.
A design-specific and thermally-aware methodology for trading-off power and
performance in leakage-dominant CMOS technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(11):1488-1498, November 2008.
- [2617]
- S. Lin and N. Chang.
Challenges in power-ground integrity.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 651-654, San Jose, CA, November 4-8 2001.
- [2618]
- I-J. Lin and Y.-W. Chang.
An efficient algorithm for statistical circuit optimization using lagrangian
relaxation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 119-124, San Jose, CA, November 5-8 2007.
- [2619]
- Y. Lin and E. Gad.
Formulation of the obreshkov-based transient circuit simulator in the presence
of nonlinear memory elements.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(1):86-94, January 2015.
- [2620]
- M. Lin and A. El Gamal.
A low-power field-programmable gate array routing fabric.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(10):1481-1494, October 2009.
- [2621]
- Y. Lin and L. He.
Leakage efficient chip-level dual vdd assignment with time slack allocation for
FPGA power reduction.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
720-725, Anaheim, CA, June 13-17 2005.
- [2622]
- Y. Lin and L. He.
Dual-vdd interconnect with chip-level time slack allocation for FPGA power
reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2023-2034, October 2006.
- [2623]
- Y. Lin and L. He.
Statistical dual-vdd assignment for FPGA interconnect power reduction.
Design, Automation and Test in Europe (DATE-07), pages 636-641, April
16-20 2007.
- [2624]
- H.-M. Lin and J.-Y. Jou.
On computing the minimum feedback vertex set of a directed graph by contraction
operations.
IEEE Transactions on Computer-Aided Design, 19(3):295-307, March
2000.
- [2625]
- P.-C.-K. Lin and S. Khatri.
Application of logic synthesis to the understanding and cure of genetic
diseases.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
734-740, San Francisco, CA, June 3-7 2012.
- [2626]
- S. Lin and E. Kuh.
Transient simulation of lossy interconnect.
In 29th ACM/IEEE Design Automation Conference, pages 81-86, Anaheim,
CA, June 8-12 1992.
- [2627]
- H. Lin and P. Li.
Classifying circuit performance using active-learning guided support vector
machines.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 187-194, San Jose, CA, November 5-8 2012.
- [2628]
- H. Lin and P. Li.
Relevance vector and feature machine for statistical analog circuit
characterization and built-in self-test optimization.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [2629]
- S.-H. Lin and M.-P.-H. Lin.
More effective power-gated circuit optimization with multi-bit retention
registers.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 213-217, San Jose, CA, November 2-6 2014.
- [2630]
- J.-M. Lin and C.-C. Lin.
Placement density aware power switch planning methodology for power gating
designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(5):766-777, May 2015.
- [2631]
- B. Lin and H. De Man.
Low-power driven technology mapping under timing constraints.
In International Workshop on Logic Synthesis, pages 9a-1 -- 9a-16,
1993.
- [2632]
- T-M. Lin and C. A. Mead.
Signal delay in general RC networks.
IEEE Transactions on Computer-Aided Design, CAD-3(4):331-349, October
1984.
- [2633]
- T.-M. Lin and C. A. Mead.
A hierarchical timing simulation model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, CAD-5(1):188-197, January 1986.
- [2634]
- R.-B. Lin and C.-M. Tsai.
Theoretical analysis of bus-invert coding.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):929-935, December 2002.
- [2635]
- C.-A. Lin and C.-H. Wu.
Second-order approximations for RLC trees.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(7):1124-1128, July 2004.
- [2636]
- C. Lin and H. Zhou.
Retiming for wire pipelining in system-on-chip.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 215-220, San Jose, CA, November 9-13 2003.
- [2637]
- C. Lin and H. Zhou.
Wire retiming as fixpoint computation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(12):1340-1348, December 2005.
- [2638]
- M.-B. Lin.
On the design of fast large fan-in CMOS multiplexers.
IEEE Transactions on Computer-Aided Design, 19(8):963-967, August
2000.
- [2639]
- J.-F. Lin.
Low-power pulse-triggered flip-flop design based on a signal feed-through
scheme.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(1):181-185, January 2014.
- [2640]
- B. Linares-Barranco and T. Serrano-Gotarredonna.
On an efficient CAD implementation of the distance term in pelgrom's mismatch
model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(8):1534-1538, August 2007.
- [2641]
- M. Linderman and
M. Leeser.
Simulation of digital circuits in the presence of uncertainty.
In IEEE/ACM International Conference on Computer-Aided Design, pages
248-251, San Jose, CA, November 6-10 1994.
- [2642]
- A. Ling, D. P.
Singh, and S. D. Brown.
FPGA technology mapping: a study of optimality.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
427-432, Anaheim, CA, June 13-17 2005.
- [2643]
- A. C. Ling, D. P.
Singh, and S. D. Brown.
FPGA PLB architecture evaluation and area optimization techniques using
boolean satisfiability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(7):1196-1210, July 2007.
- [2644]
- D. D. Ling,
C. Visweswariah, P. Feldmann, and S. Abbaspour.
A moment-based effective characterization waveform for static timing analysis.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 19-24,
San Francisco, CA, July 26-31 2009.
- [2645]
- L. Lingappan, S. Ravi, and N. K. Jha.
Satisfiability-based test generation for nonseparable RTL controller-datapath
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(3):544-557, March 2006.
- [2646]
- J.-J. Liou,
A. Krstic, Y.-M. Jiang, and K.-T. Cheng.
Path selection and pattern generation for dynamic timing analysis considering
power supply noise effects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 493-496, San Jose, CA, November 5-9 2000.
- [2647]
- J.-J. Liou, K.-T.
Cheng, S. Kundu, and A. Krstic.
Fast statistical timing analysis by probabilistic event propagation.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
661-666, Las Vegas, NV, June 18-22 2001.
- [2648]
- J.-J. Liou,
A. Krstic, L.-C. Wang, and K.-T. Cheng.
False-path-aware statistical timing analysis and efficient path selection for
delay testing and timing validation.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
566-569, New Orleans, LA, June 10-14 2002.
- [2649]
- L. Lipsky and S. C. Seth.
Signal probabilities in AND-OR trees.
IEEE Transactions on Computers, 38(11):1558-1563, November 1989.
- [2650]
- R. Lisanke,
F. Brglez, A. J. Degeus, and D. Gregory.
Testability-driven random test-pattern generation.
IEEE Transactions on Computer-Aided Design, CAD-6(6):1082-1087,
November 1987.
- [2651]
- S. Little,
D. Walter, C. Myers, R. Thacker, and T. Yoneda.
Verification of analog/mixed-signal circuits using labeled hybrid petri nets.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(4):617-630, April 2011.
- [2652]
- S. Liu, M. Pedram, and
A. M. Despain.
A fast state assignment procedure for large fsms.
In 32nd Design Automation Conference, pages 327-332, San Francisco,
CA, June 12-16 1995.
- [2653]
- Y. Liu, L. T. Pileggi,
and A. J. Strojwas.
ftd: An exact frequency to time domain conversion for reduced order RLC
interconnect models.
In IEEE/ACM 35th Design Automation Conference, pages 469-472, San
Francisco, CA, June 15-19 1998.
- [2654]
- X. Liu, M. C.
Papaefthymiou, and E. G. Friedman.
Maximizing performance by retiming and clock skew scheduling.
In ACM/IEEE Design Automation Conference, pages 231-236, 1999.
- [2655]
- Y. Liu, L. T.
Pileggi, and A. J. Strojwas.
Model order-reduction of RC(L) interconnect including variational analysis.
In Design Automation Conference, pages 201-206, New Orleans, LA, June
21-25 1999.
- [2656]
- Y. Liu, S. R. Nassif,
L. T. Pileggi, and A. J. Strojwas.
Impact of interconnect variations on the clock skew of a gigahertz processor.
In Design Automation Conference, pages 168-171, Los Angeles, CA, June
5-9 2000.
- [2657]
- Y. Liu, L. T. Pileggi,
and A. J. Strojwas.
ftd: Frequency to time domain conversion for reduced-order interconnect
simulation.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(4):500-506, April 2001.
- [2658]
- F. Liu, C. Kashyap,
and C. J. Alpert.
A delay metric for RC circuits based on the weibull distribution.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 620-624, San Jose, CA, November 10-14 2002.
- [2659]
- J. Liu, S. Zhou,
H. Zhu, and C.-K. Cheng.
An algorithmic approach for generic parallel adders.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 734-740, San Jose, CA, November 9-13 2003.
- [2660]
- F. Liu, C. Kashyap,
and C. J. Alpert.
A delay metric for RC circuits based on the weibull distribution.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(3):443-447, March 2004.
- [2661]
- M. Liu, W.-S. Wang,
and M. Orshansky.
Leakage power reduction by dual-vth designs under probabilistic analysis of vth
variation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 2-7, Newport Beach, CA, August 9-11 2004.
- [2662]
- Q. Liu, B. Hu, and
M. Marek-Sadowska.
Individual wire-length prediction with appreciation to timing-driven placement.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1004-1014, October 2004.
- [2663]
- Q.-H. Liu, C. Cheng,
and H. Z. Massoud.
The special grid method: a novel fast schrodinger-equation solver for
semiconductor nanodevice simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1200-1208, August 2004.
- [2664]
- X. Liu, Y. Peng, and
M. C. Papaefthymiou.
Practical repeater insertion for low power: what repeater library do we need.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 30-35,
San Diego, CA, June 7-11 2004.
- [2665]
- P. Liu, Z. Qi,
H. Li, L. Jin, W. Wu, S. X.-D. Tan, and J. Yang.
Fast thermal simulation for architecture level dynamic thermal management.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 639-644, San Jose, CA, November 6-10 2005.
- [2666]
- P. Liu, S. X.-D.
Tan, H. Li, Z. Qi, J. Kong, B. McGaughly, and L. He.
An efficient method for terminal reduction of interconnect circuits considering
delay variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 821-826, San Jose, CA, November 6-10 2005.
- [2667]
- H.-Y. Liu, C.-W.
Lin, S.-J. Chou, W.-T. Tu, C.-H. Liu, Y.-W. Chang, and S.-Y. Kuo.
Current path analysis for electrostatic discharge protection.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 510-515, San Jose, CA, November 5-9 2006.
- [2668]
- X. Liu, Y. Peng, and
M. C. Papaefthymiou.
Practical repeater insertion for low power: what repeater library do we need?
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):917-924, May 2006.
- [2669]
- Z. Liu, B. W.
McGaughy, and J.-Z. Ma.
Design tools for reliability analysis.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
182-187, San Francisco, CA, July 24-28 2006.
- [2670]
- H.-Y. Liu, W.-P.
Lee, and Y.-W. Chang.
A provably good approximation algorithm for power optimization using multiple
supply voltages.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
887-890, San Diego, CA, June 4-8 2007.
- [2671]
- P. Liu, S. X.-D.
Tan, B. McGaughy, L. Wu, and L. He.
Termmerg: an efficient terminal-reduction method for interconnect circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(8):1382-1392, August 2007.
- [2672]
- J.-H. Liu, Z.-Y.
Jiang, L. Chen, and C. C.-P. Chen.
Singular value decomposition based spatial correlation extraction for VLSI
DFM applications.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 80-85, Monterey, CA,
February 25-26 2008.
- [2673]
- J.-H. Liu, M.-F.
Tsai, L. Chen, and C.-C.-P. Chen.
Accurate and analytical statistical spatial correlation modeling for VLSI
DFM applications.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
694-697, Anaheim, CA, June 8-13 2008.
- [2674]
- S. Liu, G. Chen,
T.-T. Jing, L. He, T. Zhang, R. Dutta, and X.-L. Hong.
Topological routing to maximize routability for package substrate.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
566-569, Anaheim, CA, June 8-13 2008.
- [2675]
- Y.-F. Liu, B. Wang,
M. Xu, X. Liu, J.-Z. Chen, and M. Desmith.
Correlation of on-die capacitance for power delivery network.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 123-126, San Jose, CA, October 27-29 2008.
- [2676]
- T.-T. Liu, L. P.
Alarcon, M. D. Pierson, and J. M. Rabaey.
Asynchronous computing in sense amplifier-based pass transistor logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(7):883-892, July 2009.
- [2677]
- J.-H. Liu, M.-F.
Tsai, L. Chen, and C.-C.-P. Chen.
Accurate and analytical statistical spatial correction modeling based on
singular value decomposition for VLSI DFM applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):580-589, April 2010.
- [2678]
- S. Liu, Y. Zhang,
S. O. Memik, and G. Memik.
An approach for adaptive DRAM temperature and power management.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(4):684-688, April 2010.
- [2679]
- X.-X. Liu, H. Yu,
and S. X.-D. Tan.
A robust periodic arnoldi shooting algorithm for efficient analysis of
large-scale RF/MM ics.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
573-578, Anaheim, CA, June 13-18 2010.
- [2680]
- X.-X. Liu, H. Wang,
and S.-X.-D. Tan.
Parallel power grid analysis using preconditioned GMRES solver on CPU-GPU
platforms.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 561-568, San Jose, CA, November 18-21 2013.
- [2681]
- B. Liu, H. Li,
Y. Chen, X. Li, T. Huang, Q. Wu, and M. Barnell.
Reduction and IR-drop compensations techniques for reliable neuromorphic
computing systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 63-70, San Jose, CA, November 2-6 2014.
- [2682]
- S.-S.-Y. Liu, R.-G.
Luo, S. Aroonsantidecha, C.-Y. Chin, and H.-M. Chen.
Fast thermal aware placement with accurate thermal anaylsis based on green
function.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(6):1404-1415, June 2014.
- [2683]
- W.-H. Liu, M.-S.
Chang, and T.-C. Wang.
Floorplanning and signal assignment for silicon interposer-based 3d ics.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [2684]
- J. Liu, D.-C. Juan,
and Y. Shi.
Effective CAD research in the sea of papers.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 781-785, Austin TX, November 2-6 2015.
- [2685]
- X. Liu, S. Sun,
P. Zhou, X. Li, and H. Qian.
A statistical methodology for noise sensor placement and full-chip voltage map
generation.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [2686]
- X.-X. Liu, H. Yu, and
S.-X.-D. Tan.
A GPU-accelerated parallel shooting algorithms for analysis of radio
frequency and microwave circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(3):480-492, March 2015.
- [2687]
- C.-W. Liu and Y.-W. Chang.
Power/ground network and floorplan cosynthesis for fast design convergence.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):693-704, April 2007.
- [2688]
- F-J Liu and C-K Cheng.
Extending moment computation to 2-port circuit representations.
In IEEE/ACM 35th Design Automation Conference, pages 473-476, San
Francisco, CA, June 15-19 1998.
- [2689]
- C.-C. Liu and C.-K. Cheng.
Low-power and high-speed interconnect using serial passive compensation.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 68-73, Monterey, CA,
February 25-26 2008.
- [2690]
- J. Liu and P. H. Chou.
Optimizing model transition sequences in idle intervals for component-level and
system-level energy minimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 21-28, San Jose, CA, November 7-11 2004.
- [2691]
- F. Liu and P. Feldmann.
MAISE: An interconnect simulation engine for timing and noise analysis.
In IEEE International Conference on Quality Electronic Design (ISQED),
pages 621-626, San Jose, CA, March 17-19 2008.
- [2692]
- F. Liu and P. Feldmann.
A time-unrolling method to compute sensitivity of dynamic systems.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [2693]
- F. Liu and B. R. Hodges.
Dynamic river network simulation at large scale.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
723-728, San Francisco, CA, June 3-7 2012.
- [2694]
- Q. Liu and
M. Marek-Sadowska.
Pre-layout wire length and congestion estimation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
582-587, San Diego, CA, June 7-11 2004.
- [2695]
- F. Liu and S. Ozev.
Statistical test development for analog circuits under high process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(8):1465-1477, August 2007.
- [2696]
- X. Liu and M. C.
Papaefthymiou.
A markov chain sequence generator for power macromodeling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 404-411, San Jose, CA, November 10-14 2002.
- [2697]
- X. Liu and M. C.
Papaefthymiou.
A markov chain sequence generator for power macromodeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(7):1048-1062, July 2004.
- [2698]
- X. Liu and M. C.
Papaefthymiou.
Hype: hybrid power estimation for IP-based system-on-chip.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):1089-1103, July 2005.
- [2699]
- Q. Liu and S. S.
Sapatnekar.
Confidence scalable post-silicon statistical delay prediction under process
variations.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
497-502, San Diego, CA, June 4-8 2007.
- [2700]
- Q. Liu and S. S.
Sapatnekar.
A framework for scalable postsilicon statistical delay prediction under process
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(8):1201-1212, August 2008.
- [2701]
- Q. Liu and S. S.
Sapatnekar.
Capturing post-silicon variations using a representative critical path.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(2):211-222, February 2010.
- [2702]
- B. Liu and S. X.-D. Tan.
Minimum decoupling capacitor insertion in VLSI power/ground supply networks
by semidefinite and linear programs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(11):1284-1287, November 2007.
- [2703]
- J.-B. Liu and A. Veneris.
Incremental fault diagnosis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(2):240-251, February 2005.
- [2704]
- H. Liu and N. Wong.
Autonomous volterra algorithm for steady-state analysis of nonlinear circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(6):858-868, June 2013.
- [2705]
- X. Liu and Q. Xu.
Interconnection fabric design for tracing signals in post-silicon validation.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
352-357, San Francisco, CA, July 26-31 2009.
- [2706]
- F. Liu.
An efficient method for statistical circuit simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 719-724, San Jose, CA, November 5-8 2007.
- [2707]
- F. Liu.
A general framework for spatial correlation modeling in VLSI design.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
817-822, San Diego, CA, June 4-8 2007.
- [2708]
- F. Liu.
How to construct spatial correlation models: a mathematical approach.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 106-111, Austin,
Texas, February 26-27 2007.
- [2709]
- Y. Liu.
Dynamically resilient and agile fine-grained replication configuration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 786-793, Austin TX, November 2-6 2015.
- [2710]
- P. Liy, D. J. Liljay,
W. Qianz, K. Bazargany, and M. Riedely.
The synthesis of complex arithmetic computation on stochastic bit streams using
sequential logic.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 480-487, San Jose, CA, November 5-8 2012.
- [2711]
- R. P. LLopis,
R. J. H. Koopman, H. G. Kerkhoff, and J. A. Braat.
A performance analysis tool for performance-driven micro-cell generation.
In European Conference on Design Automation, pages 576-580, February
1991.
- [2712]
- R. P. Llopis and
K. Goossens.
The petrol approach to high-level power estimation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 130-132, Monterey, CA, August 10-12 1998.
- [2713]
- R. P. Llopis and
M. Sachdev.
Low power, testable dual edge triggered flip-flops.
In International Symposium on Low Power Electronics and Design, pages
341-345, Monterey, CA, August 12-14 1996.
- [2714]
- J. R. Lloyd and
J. Kitchin.
The electromigration failure distribution: The fine-line case.
Journal of Applied Physics, 69(4):2117-2127, February 1991.
- [2715]
- J. R. Lloyd.
Electromigration and mechanical stress.
Microelectronics Engineering, 49:51-64, 1999.
- [2716]
- C-Y. Lo, H. N. Nham, and
A. K. Bose.
A data structure for MOS circuits.
In IEEE 20th Design Automation Conference, pages 619-624, Miami
Beach, FL, June 27-29 1983.
- [2717]
- J. Long, J.-C. Ku,
S. O. Memik, and Y. I. Ismail.
A self-adjusting clock tree architecture to cope with temperature variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 75-82, San Jose, CA, November 5-8 2007.
- [2718]
- J. Long, J.-C. Ku,
S. O. Memik, and Y. Ismail.
SACTA: a self-adjusting clock tree architecture for adapting to
thermal-induced delay variation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(9):1323-1336, September 2010.
- [2719]
- J. Long, D. Li,
S. O. Memik, and S. Ulgen.
Theory and analysis for optimization of on-chip thermoelectric cooling systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1628-1632, October 2013.
- [2720]
- C. Long and L. He.
Distributed sleep transistor network for power reduction.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
181-186, Anaheim, CA, June 2-6 2003.
- [2721]
- C. Long and L. He.
Distributed sleep transistor network for power reduction.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(9):937-946, September 2004.
- [2722]
- J. Long and S. O. Memik.
Automated design of self-adjusting pipelines.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
211-216, Anaheim, CA, June 8-13 2008.
- [2723]
- D. E. Long.
The design of a cache-friendly BDD library.
In IEEE/ACM International Conference on Computer-Aided Design, pages
639-645, San Jose, CA, November 8-12 1998.
- [2724]
- D. Lorenz,
M. Barke, and U. Schlichtmann.
Aging analysis at gate and macro cell level.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 77-84, San Jose, CA, November 7-11 2010.
- [2725]
- K. K. Low and S. W.
Director.
A new methodology for the design centering of IC fabrication processes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 10(7):895-903, July 1991.
- [2726]
- K. S. Lowe and P. G. Gulak.
Gate sizing and buffer insertion for optimizing performance in power
constrained bicmos circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
216-219, Santa Clara, CA, November 7-11 1993.
- [2727]
- K. S. Lowe and P. G. Gulak.
A joint gate sizing and buffer insertion method for optimizing delay and power
in CMOS and bicmos combinational logic.
IEEE Transactions on Computer-Aided Design, 17(5):419-434, May
1998.
- [2728]
- Y.-H. Lu, L. Benini, and
G. De Micheli.
Dynamic frequency scaling with buffer insertion for mixed workloads.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(11):1284-1305, November 2002.
- [2729]
- Z. Lu, W. Huang,
J. Lach, M. Stan, and K. Skadron.
Interconnect lifetime prediction under dynamic stress for reliability-aware
design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 327-334, San Jose, CA, November 7-11 2004.
- [2730]
- X. Lu, Z. Li, W. Qiu,
D. M. H. Walker, and W. Shi.
Longest-path selection for delay test under process variation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(12):1924-1929, December 2005.
- [2731]
- P.-F. Lu, N. Cao,
L. Sigal, P. Woltgens, R. Robertazzi, and D. Heidel.
A pulsed low-voltage swing latch for reduced power dissipation in
high-frequency microprocessors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 85-88, Tegernsee, Germany, October 4-6 2006.
- [2732]
- Z. Lu, W. Huang, M. R.
Stan, K. Skadron, and J. Lach.
Interconnect lifetime prediction for reliability-aware systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(2):159-172, February 2007.
- [2733]
- Y. Lu, L. Shang,
H. Zhou, H. Zhu, F. Yang, and X. Zeng.
Statistical reliability analysis under process variation and aging effects.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
514-519, San Francisco, CA, July 26-31 2009.
- [2734]
- Y. Lu, H. Zhou,
L. Shang, and X. Zeng.
Multicore parallelization of min-cost flow for CAD applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(10):1546-1557, October 2010.
- [2735]
- S.-L. Lu, T. Karnik,
G. Srinivasa, K.-Y. Chao, D. Carmean, and J. Held.
Scaling the "memory wall".
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 271-272, San Jose, CA, November 5-8 2012.
- [2736]
- S.-K. Lu, H.-H. Huang,
J.-L. Huang, and P. Ning.
Synergistic reliability and yield enhancement techniques for embedded srams.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):165-169, January 2013.
- [2737]
- J. Lu, P.Chen, C.-C.
Chang, L. Sha, D.-J.-H. Huang, C.-C. Teng, and C.-K. Cheng.
eplace: electrostatics based placement using nesterov's method.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [2738]
- C.-P. Lu, I.-H.-R Jiang,
and C.-H. Hsu.
Gasstation: power and area efficient buffering for multiple power domain
design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 861-866, Austin TX, November 2-6 2015.
- [2739]
- N. Lu and I. N. Hajj.
A hierarchical based approach for coupling aware delay analysis of
combinational logic blocks.
In 7th IEEE International Conference on Electronics, Circuits and
Systems, pages 1012-1015, Beirut, Lebanon, December 17-19 2000.
- [2740]
- N. Lu and I. N. Hajj.
A fast coupling aware delay estimation scheme based on simplified circuit
model.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 133-138, San Jose, CA, March 26-28 2001.
- [2741]
- R. Lu and C.-K. Koh.
SAMBA-bus: a high performance bus architecture for system-on-chips.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 8-12, San Jose, CA, November 9-13 2003.
- [2742]
- Y. Lu and H. Zhou.
Efficient design space exploration for component-based system design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 466-472, San Jose, CA, November 5-8 2012.
- [2743]
- J. T. Ludwig,
S. H. Nawab, and A. Chandrakasan.
Low power filtering using approximate processing for DSP applications.
In IEEE Custom Integrated Circuits Conference, pages 185-188, Santa
Clara, CA, May 1-4 1995.
- [2744]
- F. Luellau,
T. Hoepken, and E. Barke.
A technology independent block extraction algorithm.
In IEEE 21st Design Automation Conference, pages 610-615, 1984.
- [2745]
- J. Luo, L. Zhong,
Y. Fei, and N.-K. Jha.
Register binding-based RTL power management for control-flow intensive
designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1175-1183, August 2004.
- [2746]
- Y. Luo, J. Yu,
J. Yang, and L. Bhuyan.
Low power network processor design using clock gating.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
712-715, Anaheim, CA, June 13-17 2005.
- [2747]
- J. Luo, S. Sinha,
Q. Su, J. Kawa, and C. Chiang.
An IC manufacturing yield model considering intra-die variations.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
749-754, San Francisco, CA, July 24-28 2006.
- [2748]
- J. Luo, N. K. Jha, and
L.-S. Peh.
Simultaneous dynamic voltage scaling processors and communication links in
real-time distributed embedded systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(4):427-437, April 2007.
- [2749]
- P.-W. Luo, J.-E. Chen,
C.-L. Wey, L.-C. Cheng, J.-J. Chen, and W.-C. Wu.
Impact of capacitance correlation on yield enhancement of mixed-signal/analog
integrated circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(11):2097-2101, November 2008.
- [2750]
- Y. Luo,
K. Chakrabarty, and T.-Y. Ho.
Error recovery in cyberphysical digital microfluidic biochips.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(1):59-72, January 2013.
- [2751]
- S. Luo and Z.-D. Chen.
Extraction of causal time-domain network parameters from their band-limited
frequency-domain counterparts using rational functions.
IEEE Transactions on Circuits and Systems, 52(6):1205-1210, June
2005.
- [2752]
- C. Lursinsap and
D. Gajski.
An optimal power routing for top-down design architecture.
In IEEE International Conference on Computer-Design, pages 345-348,
1987.
- [2753]
- A. Lvov and U. Finkler.
Exact basic geometric operations on arbitrary angle polygons using only fixed
size integer coordinates.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 494-498, San Jose, CA, November 10-13 2008.
- [2754]
- C.-G. Lyuh and T. Kim.
High-level synthesis for low power based on network flow method.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):364-375, June 2003.
- [2755]
- S. Rao M. and S. K. Nandy.
Power minimization using control generated clocks.
In Design Automation Conference, pages 794-799, Los Angeles, CA, June
5-9 2000.
- [2756]
- W. m. Hwu, S. Ryoo,
S.-Z. Ueng, J. H. Kelm, I. Gelado, S. S. Stone, R. E. Kidd, S. S. Baghsorkhi,
A. A. Mahesri, S. C. Tsao, N. Navarro, S. S. Lumetta, M. I. Frank, and S. J.
Patel.
Implicitly parallel programming models for thousand-vore microprocessors.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
754-759, San Diego, CA, June 4-8 2007.
- [2757]
- D. Ma, J. Wang, and
P. Vozqua.
Adaptive on-chip power supply with robust one-cycle control technique.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 394-399, Tegernsee, Germany, October 4-6 2006.
- [2758]
- J. D. Ma and R. A. Rutenbar.
Interval-valued reduced order statistical interconnect modeling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 460-467, San Jose, CA, November 7-11 2004.
- [2759]
- J.-D. Ma and R. A. Rutenbar.
Fast interval-valued statistical modeling of interconnect and effective
capacitance.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(4):710-724, April 2006.
- [2760]
- J. D. Ma and R. A. Rutenbar.
Interval-valued reduced-order statistical interconnect modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(9):1602-1613, September 2007.
- [2761]
- Q. Ma and E. F.-Y. Young.
Network flow-based power optimization under timing constraints in MSV-driven
floorplanning.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 1-8, San Jose, CA, November 10-13 2008.
- [2762]
- Q. Ma and E. F. Y. Young.
Multivoltage floorplan design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):607-617, April 2010.
- [2763]
- F. Maamari and
J. Rajski.
A reconvergent fanout analysis for efficient exact fault simulation of
combinational circuits.
In IEEE 18th International Fault Tolerant Computing Symposium, pages
122-126, June 1988.
- [2764]
- M. Maasoumy and A. Sangiovanni-Vincentelli.
Buildings to grid integration: a dynamic contract approach.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 473-478, Austin TX, November 2-6 2015.
- [2765]
- L. Macchiarulo, E. Macii, and M. Poncino.
Low-energy encoding for deep-submicron address buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 176-181, Huntington Beach, California, August 6-7
2001.
- [2766]
- E. Macii,
M. Pedram, and F. Somenzi.
High-level power modeling, estimation, and optimization.
In 34th Design Automation Conference, pages 504-511, Anaheim, CA,
June 9-13 1997.
- [2767]
- A. Macii,
E. Macii, M. Poncino, and R. Scarsi.
Stream synthesis for efficient power simulation based on spectral transforms.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 30-35, Monterey, CA, August 10-12 1998.
- [2768]
- E. Macii,
M. Pedram, and F. Somenzi.
High-level power modeling, estimation, and optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 17(11):1061-1079, November 1998.
- [2769]
- A. Macii,
E. Macii, M. Poncino, and R. Scarsi.
Stream synthesis for efficient power simulation based on spectral techniques.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(3):417-426, June 2001.
- [2770]
- E. Macii and M. Poncino.
Predicting the functional complexity of combinational circuits by symbolic
spectral analysis of boolean functions.
In European Design Automation Conference, pages 294-299, 1996.
- [2771]
- C. MacInnes.
The use of small pivot perturbation in circuit analysis.
IEEE Transactions on Computer-Aided Design, 10(11):1441-1446,
November 1991.
- [2772]
- D. MacMillen, M. Butts, R. Camposano, D. Hill, and T. W.
Williams.
An industrial view of electronic design automation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1428-1448, December 2000.
- [2773]
- R. Macys and
S. McCormick.
A new algorithm for computing the "effective capacitance" in deep sub-micron
circuits.
In IEEE Custom Integrated Circuits Conference, pages 313-316, Santa
Clara, CA, May 11-14 1998.
- [2774]
- C. Madigan and
V. Bulovic.
Organic electronic device modeling at the nanoscale.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 832-833, San Jose, CA, November 5-9 2006.
- [2775]
- P. Maffezzoni and A. Brambilla.
Study of statistical approaches to the solution of linear discrete and integral
problems.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(9):1153-1161, September 2003.
- [2776]
- P. Maffezzoni and A. Brambilla.
Statistical approach to derive an electrical port model of capacitively coupled
interconnects.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(4):797-807, April 2004.
- [2777]
- Nir Magen, Avinoam
Kolodny, Uri Weiser, and Nachum Shamir.
Interconnect-power dissipation in a microprocessor.
In ACM/IEEE International Workshop on System-Level Interconnect Prediction
(SLIP-04), pages 7-13, February 14-15 2004.
- [2778]
- M. Magerl,
V. Ceperic, and A. Baric.
Echo state networks for black-box modeling of integrated circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(8):1309-1317, August 2016.
- [2779]
- M. Maggio,
A. Chandrakasan, A. Agarwal, Y. Sinangil, M. Sinangil, S. Devadas, E. Lau,
G. Kurian, J. Holt, H. Hoffman, S. Neuman, and J. Miller.
Self-aware computing in the angstrom processor.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
259-264, San Francisco, CA, June 3-7 2012.
- [2780]
- B. Magnhagen.
Practical experience from signal probability simulation of digital designs.
In IEEE 14th Design Automation Conference, pages 216-219, 1977.
- [2781]
- V. Mahalingam, N. Ranganathan, and J. E. Harlow, III.
A novel approach for variation aware power minimization during gate sizing.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 174-179, Tegernsee, Germany, October 4-6 2006.
- [2782]
- V. Mahalingam, N. Ranganathan, and J. E. Harlow.
A fuzzy optimization approach for variation aware power minimization during
gate sizing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(8):975-984, August 2008.
- [2783]
- H. Mahawar,
V. Sarin, and W. Shi.
A solenoidal basis method for efficient inductance extraction.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
751-756, New Orleans, LA, June 10-14 2002.
- [2784]
- A. Maheshwari, W. Burleson, and R. Tessier.
Trading off transient fault tolerance and power consumption in deep submicron
(DSM) VLSI circuits.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(3):299-311, March 2004.
- [2785]
- A. Maheshwari and W. Burleson.
Differential current-sensing for on-chip interconnects.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1321-1329, December 2004.
- [2786]
- Z. Mahmood,
S. Grivet-Talocia, A. Chinea, G. C. Clalfiore, and L. Daniel.
Efficient localization methods for passivity enforcement of linear dynamical
models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(9):1328-1341, September 2014.
- [2787]
- H. Mahmoodi,
V. Tirumalashetty, M. Cooke, and K. Roy.
Ultra low-power clocking scheme using energy recovery and clock gating.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(1):33-44, January 2009.
- [2788]
- H. Mahmoodi-Meimand and K. Roy.
Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design
style.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(3):495-503, March 2004.
- [2789]
- A. G. Mahmutoglu
and A. Demir.
Modeling and analysis of nonstationary low-frequency noise in circuit
simulators: enabling non monte carlo techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 309-315, San Jose, CA, November 2-6 2014.
- [2790]
- A. G. Mahmutoglu
and A. Demir.
Non-monte carlo analysis of low-frequency noise: exposition of intricate
nonstationary behavior and comparision with legacy models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(11):1825-1835, November 2016.
- [2791]
- A. Majumdar,
W.-Y. Chen, and J. Guo.
Hold time validation on silicon and the relevance of hazards in timing
analysis.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
326-331, San Francisco, CA, July 24-28 2006.
- [2792]
- A. Majumdar and
S. B. K. Vrudhula.
Analysis of signal probability in logic circuits using stochastic models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
1(3):365-379, September 1993.
- [2793]
- W.-K. Mak and C. Chu.
Rethinking the wirelength benefit of 3-D integration.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(12):2346-2351, December 2012.
- [2794]
- T. Makimoto and
Y. Sakai.
Evolution of low power electronics and its future applications.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 2-5, Seoul, Korea, August 25-27 2003.
- [2795]
- E. Malavasi,
S. Zancella, and M. Cao.
Impact analysis of process variability on clock skew.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 129-132, San Jose, CA, March 18-21 2002.
- [2796]
- J. S. Malik,
A. Hemani, J. N. Malik, B. Silmane, and N. D. Gohar.
Revisiting central limit theorem: accurate gaussian random number generation in
VLSI.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(5):842-855, May 2015.
- [2797]
- S. Malik.
Analysis of cyclic combinational circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
618-625, Santa Clara, CA, November 7-11 1993.
- [2798]
- C. H. Malley and
M. Dieudonne.
Logic verification methodology for powerpc microprocessors.
In 32nd Design Automation Conference, pages 234-240, San Francisco,
CA, June 12-16 1995.
- [2799]
- W. Maly, P. K. Nag,
and P. Nigh.
Testing oriented analysis of CMOS ics with opens.
In IEEE International Conference on Computer-Aided Design, pages
344-347, Santa Clara, CA, Nov. 7-10 1988.
- [2800]
- W. Maly, Y.-W. Lin,
and M. Marek-Sadowska.
OPC-free and minimally irregular IC design style.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
954-957, San Diego, CA, June 4-8 2007.
- [2801]
- M. Mamidipaka, D. Hirschberg, and N. Dutt.
Low power address encoding using self-organizing lists.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 188-193, Huntington Beach, California, August 6-7
2001.
- [2802]
- M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir.
IDAP: a tool for high level power estimation of custom array structures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 113-119, San Jose, CA, November 9-13 2003.
- [2803]
- M. N.
Mamidipaka, D. S. Hirschberg, and N. D. Dutt.
Adaptive low-power address encoding techniques using self-organizing lists.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(5):827-834, October 2003.
- [2804]
- M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir.
IDAP: a tool for high-level power estimation of custom array structures.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1361-1369, September 2004.
- [2805]
- P. Manfredi,
D. V. Ginste, D. De Zutter, and F. G. Canavero.
On the passivity of polynomial chaos-based augmented models for stochastic
circuits.
IEEE Transactions on Circuits and Systems, 60(11):2998-3007, November
2013.
- [2806]
- O. L.
Mangasarian and T.-H. Shiau.
Variable complexity norm maximization problem.
SIAM Journal on Algebraic and Discrete Methods, 7(3):455-461,
1986.
- [2807]
- H. Mangassarian, A. Veneris, S. Safarpour, F. N. Najm, and M. S.
Abadir.
Maximum circuit activity estimation using pseudo-boolean satisfiability.
Design, Automation and Test in Europe (DATE-07), pages 1538-1543,
April 16-20 2007.
- [2808]
- H. Mangassarian, A. Veneris, D. E. Smith, and S. Safarpour.
Debugging with dominance: on-the-fly RTL debug solution implications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 587-594, San Jose, CA, November 7-10 2011.
- [2809]
- H. Mangassarian, A. Veneris, and F. N. Najm.
Maximum circuit activity estimation using pseudo-boolean satisfiability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(2):271-284, February 2012.
- [2810]
- M. Mani, A. Devgan,
and M. Orshansky.
An efficient algorithm for statistical minimization of total power under timing
yield constraints.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
309-314, Anaheim, CA, June 13-17 2005.
- [2811]
- M. Mani, A. Devgan,
M. Orshansky, and Y. Zhan.
A statistical algorithm for power- and timing-limited parametric yield
optimization of large integrated circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(10):1790-1802, October 2007.
- [2812]
- S. Manne,
A. Pardo, R. I. Bahar, G. D. Hachtel, F. Somenzi, E. Macii, and M. Poncino.
Computing the maximum power cycles of a sequential circuit.
In 32nd Design Automation Conference, pages 23-28, San Francisco, CA,
June 12-16 1995.
- [2813]
- V. Manohararajah, S. D. Brown, and Z. G. Vranesic.
Heuristics for area minimization in LUT-based FPGA technology mapping.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2331-2340, November 2006.
- [2814]
- M. M. Mansour and
A. Mehrotra.
Reduced-order modeling based on PRONY's and SHANK's methods via the
bilinear transformation.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 299-304, San Jose, CA, March 24-26 2003.
- [2815]
- W. Mao and M. D. Ciletti.
Correlation-reduced scan-path design to improve delay fault coverage.
In 28th ACM/IEEE Design Automation Conference, pages 73-79, San
Francisco, CA, June 17-21 1991.
- [2816]
- T. E. Marchok,
A. El-Maleh, W. Maly, and J. Rajski.
A complexity analysis of sequential ATPG.
IEEE Transactions on Computer-Aided Design, 15(11):1409-1423,
November 1996.
- [2817]
- R. Marculescu, D. Marculescu, and M. Pedram.
Switching activity analysis considering spatiotemporal correlations.
In IEEE/ACM International Conference on Computer-Aided Design, pages
294-299, San Jose, CA, November 6-10 1994.
- [2818]
- D. Marculescu, R. Marculescu, and M. Pedram.
Information theoretic measures of energy consumption at register transfer
level.
In ACM/IEEE International Symposium on Low Power Design, pages 81-86,
Dana Point, CA, April 23-26 1995.
- [2819]
- R. Marculescu, D. Marculescu, and M. Pedram.
Efficient power estimation for highly correlated input streams.
In 32nd Design Automation Conference, pages 628-634, San Francisco,
CA, June 12-16 1995.
- [2820]
- D. Marculescu, R. Marculescu, and M. Pedram.
Information theoretic measures for power analysis.
IEEE Transactions on Computer-Aided Design, 15(6):599-610, June
1996.
- [2821]
- D. Marculescu, R. Marculescu, and M. Pedram.
Stochastic sequential machine synthesis targeting constrained sequence
generation.
In 33rd Design Automation Conference, pages 696-701, Las Vegas, NV,
June 3-7 1996.
- [2822]
- D. Marculescu, R. Marculescu, and M. Pedram.
Sequence compaction for probabilistic analysis of finite-state machines.
In 34th Design Automation Conference, pages 12-15, Anaheim, CA, June
9-13 1997.
- [2823]
- R. Marculescu, D. Marculescu, and M. Pedram.
Composite sequence compaction for finite-state machines using block entropy and
high-order markov models.
In 1997 International Symposium on Low Power Electronics and Design,
pages 190-195, Monterey, CA, August 18-20 1997.
- [2824]
- R. Marculescu, D. Marculescu, and M. Pedram.
Hierarchical sequence compaction for power estimation.
In 34th Design Automation Conference, pages 570-575, Anaheim, CA,
June 9-13 1997.
- [2825]
- D. Marculescu, R. Marculescu, and M. Pedram.
Theoretical bounds for switching activity analysis in finite-state machines.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 36-41, Monterey, CA, August 10-12 1998.
- [2826]
- R. Marculescu, D. Marculescu, and M. Pedram.
Probabilistic modeling of dependencies during switching activity analysis.
IEEE Transactions on Computer-Aided Design of Circuits and Systems,
17(2):73-83, February 1998.
- [2827]
- R. Marculescu, D. Marculescu, and M. Pedram.
Non-stationary effects in trace-driven power analysis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 133-138, San Diego, CA, August 16-17 1999.
- [2828]
- R. Marculescu, D. Marculescu, and M. Pedram.
Sequence compaction for power estimation: Theory and practice.
IEEE Transactions on Computer-Aided Design, 18(7):973-993, July
1999.
- [2829]
- D. Marculescu, R. Marculescu, and M. Pedram.
Theoretical bounds for switching activity analysis in finite-state machines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):335-339, June 2000.
- [2830]
- D. Marculescu and
S. Garg.
System-level process-driven variability analysis for single and multi
voltage-frequency island systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 541-546, San Jose, CA, November 5-9 2006.
- [2831]
- R. Marculescu and D. Marculescu.
Does Q=mc2? (on the relationship between quality in electronic design and the
model of colloidal computing).
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 451-457, San Jose, CA, March 18-21 2002.
- [2832]
- D. Marculescu.
Profile-driven code execution for low power dissipation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 253-255, Italy, July 26-27 2000.
- [2833]
- S. K. Marella,
S. V. Kumar, and S. S. Sapatnekar.
A holistic analysis of circuit timing variations in 3d-ics with thermal and
TSV-induced stress considerations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 317-324, San Jose, CA, November 5-8 2012.
- [2834]
- G. Mariani,
G. Palermo, V. Zaccaria, and C. Silvano.
OSCAR: an optimization methodology exploiting spatial correlation in
multicore design spaces.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(5):740-753, May 2012.
- [2835]
- E. Maricau and
G. Gielen.
Efficient variability-aware NBTI and hot carrier circuit reliability
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(12):1884-1893, December 2010.
- [2836]
- P. N. Marinos.
Derivation of minimal complete sets of test-input sequences using boolean
differences.
IEEE Transactions on Computers, C-20(1):25-32, January 1971.
- [2837]
- C. A. Marinov and
C. Budianu.
Iteratively improved bounds for RC circuits.
IEEE Transactions on Circuits and Systems - I: Fundamental Theory and
Applications, 45(6):663-666, June 1998.
- [2838]
- C. A. Marinov
and P. Neittaanmaki.
A theory of electrical circuits with resistively coupled distributive
structures: delay time predicting.
IEEE Transactions on Circuits and Systems, 35(2):173-183, February
1988.
- [2839]
- I. L. Markov,
J. Hu, and M.-C. Kim.
Progress and challenges in VLSI placement research.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 275-282, San Jose, CA, November 5-8 2012.
- [2840]
- D. Markovic,
B. Nikolic, and R. W. Brodersen.
Analysis and design of low-energy flip-flops.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 52-55, Huntington Beach, California, August 6-7 2001.
- [2841]
- G. Markowsky.
Bounding signal probabilities in combinational circuits.
IEEE Transactions on Computers, C-36(10):1247-1251, October 1987.
- [2842]
- J. P.
Marques-Silva and K. A. Sakallah.
Boolean satisfiability in electronic design automation.
In Design Automation Conference, pages 675-680, Los Angeles, CA, June
5-9 2000.
- [2843]
- A. J. Martin.
Towards an energy complexity of computation.
Information Processing Letters, 77:181-187, 2001.
- [2844]
- K. W. Martin.
Complex signal processing is not complex.
IEEE Transactions on Circuits and Systems, 51(9):1823-1836, September
2004.
- [2845]
- G. Martin.
Overview of the mpsoc design challenge.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
274-279, San Francisco, CA, July 24-28 2006.
- [2846]
- A. M. Martinez.
Quick estimation of transient currents in CMOS integrated circuits.
IEEE Journal of Solid-State Circuits, 24(2):520-531, April 1989.
- [2847]
- K. Mase.
Comments on "A measure of computation work" and "logical network cost and
entropy".
IEEE Transactions on Computers, C-27(1):94-95, January 1978.
- [2848]
- D. Maslov, G. W.
Dueck, and D. M. Miller.
Fredkin/toffoli templates for reversible logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 256-261, San Jose, CA, November 9-13 2003.
- [2849]
- K. Masselos,
P. Merakos, S. Theoharis, T. Stouraitis, and C. E. Goutis.
Power efficient data path synthesis of sum-of-products computation.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):446-450, June 2003.
- [2850]
- Y. Masuda,
M. Hashimoto, and T. Onoye.
Performance evaluation of software-based error detection mechanisms for
localizing electrical timing failures under dynamic supply noise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 315-322, Austin TX, November 2-6 2015.
- [2851]
- P. Mateti and N. Deo.
On algorithms for enumerating all circuits of a graph.
SIAM Journal on Computing, 5(1):90-99, March 1976.
- [2852]
- T. Mattson and
M. Wrinn.
Parallel programming: can we PLEASE get it right this time?
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages 7-11,
Anaheim, CA, June 8-13 2008.
- [2853]
- P. M. Maurer.
The inversion algorithm for digital simulation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
258-261, San Jose, CA, November 6-10 1994.
- [2854]
- P. M. Maurer.
The inversion algorithm for digital simulation.
IEEE Transactions on Computer-Aided Design, 16(7):762-769, July
1997.
- [2855]
- P. M. Maurer.
Event driven simulation without loops or conditionals.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 23-26, San Jose, CA, November 5-9 2000.
- [2856]
- P. M. Maurer.
Efficient event-driven simulation by exploiting the output observability of
gate clusters.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(11):1471-1486, November 2003.
- [2857]
- P. Maurine,
M. Rezzoug, N. Azemard, and D. Auvergne.
Transition time modeling in deep submicron CMOS.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(11):1352-1363, November 2002.
- [2858]
- K. Mayaram,
D. C. Lee, S. Moinian, D. Rich, and J. Roychowdhury.
Overview of computer-aided analysis tools for RFIC simulation: algorithms,
features, and limitations.
In IEEE 1997 Custom Integrated Circuits Conference, pages 505-512,
Santa Clara, CA, May 5-8 1997.
- [2859]
- K. Mayaram.
Output voltage analysis for the MOS colpitts oscillator.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 47(2):260-263, February 2000.
- [2860]
- C. C. McAndrew.
Statistical modeling for circuit simulation.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 357-362, San Jose, CA, March 24-26 2003.
- [2861]
- C. C. McAndrew.
Statistical modeling for circuit simulation.
In IEEE International Symposium on Quality Electronic Design (ISQED),
San Jose, CA, March 24-26 2003.
- [2862]
- E. McCluskey.
Logic Design Principles.
Prentice Hall, Englewood Cliffs, NJ, 1986.
- [2863]
- T. McConaghy and
G. G. E. Gielen.
Globally reliable variation-aware sizing of analog intergated circuits via
response surfaces and structural homotopy.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(11):1627-1640, November 2009.
- [2864]
- S. McCormick and
J. Allen.
Waveform moment methods for improved interconnection analysis.
In 27th ACM/IEEE Design Automation Conference, pages 406-412,
Orlando, FL, June 24-28 1990.
- [2865]
- C. B. McDonald and
R. E. Bryant.
Symbolic functional and timing verification of transistor-level circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
526-530, San Jose, CA, November 7-11 1999.
- [2866]
- C. B. McDonald and
R. E. Bryant.
CMOS circuit verification with symbolic switch-level timing simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(3):458-474, March 2001.
- [2867]
- C. B. McDonald
and R. E. Bryant.
Computing logic-stage delays using circuit simulation and symbolic elmore
analysis.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
283-288, Las Vegas, NV, June 18-22 2001.
- [2868]
- C. B. McDonald
and R. E. Bryant.
A symbolic simulation-based methodology for generating black-box timing models
of custom macrocells.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 501-506, San Jose, CA, November 4-8 2001.
- [2869]
- M. C.
McFarland, A. C. Parker, and P. Camposano.
The high-level synthesis of digital systems.
In Proceedings of the IEEE, pages 301-318, February 1990.
Published as Proceedings of the IEEE, volume 78, number 2.
- [2870]
- P. McGeer and
R. Brayton.
Efficient algorithms for computing the longest viable path in a combinational
network.
In 25th ACM/IEEE Design Automation Conference, pages 561-567, Las
Vegas, NV, June 25-29 1989.
- [2871]
- P. McGeer and
R. Brayton.
Timing analysis in precharge/unate networks.
In 27th ACM/IEEE Design Automation Conference, pages 124-129,
Orlando, FL, June 24-28 1990.
- [2872]
- P. C. McGeer and R. K.
Brayton.
Integrating functional and temporal domains in logic design.
Kluwer Academic Publishers, Boston, MA, 1991.
- [2873]
- R. McGowen.
Adaptive designs for power and thermal optimization.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 118-121, San Jose, CA, November 6-10 2005.
- [2874]
- C. McMullen and
J. Shearer.
Prime implicants, minimum covers, and the complexity of logic simplification.
IEEE Transactions on Computers, C-35(8):761-762, August 1986.
- [2875]
- L. McMurchie and
C. Sechen.
WTA - waveform-based timing analysis for deep submicron circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 625-631, San Jose, CA, November 10-14 2002.
- [2876]
- R. McNaughton
and H. Yamada.
Regular expressions and state graphs for automata.
IRE Transactions on Electronic Computers, EC-9(1):39-47, March
1960.
- [2877]
- J. W. McPherson
and P. B. Ghate.
A methodology for the calculation of continuous DC electromigration
equivalents from transient current waveforms.
The Electrochemical Society, Proc. Symp. on Electromigration of
Metals, pages 64-74, October 7-12 1984.
- [2878]
- J. W. McPherson.
Stress dependent activation energy.
In IEEE 24th International Reliability Physics Symposium (IRPS), pages
12-18, New York, NY, 1986.
- [2879]
- J. W. McPherson.
Scaling-induced reductions in CMOS reliability margins and the escalating
need for increased design-in reliability efforts.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 123-130, San Jose, CA, March 26-28 2001.
- [2880]
- J. W. McPherson.
Reliability challenges for 45nm and beyond.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
176-181, San Francisco, CA, July 24-28 2006.
- [2881]
- J.W. McPherson.
Reliability Physics and Engineering.
Springer, New York, NY, 2010.
- [2882]
- C. Mead and L. Conway.
Introduction to VLSI Systems.
Addison-Wesley Publishing Company, 1979.
- [2883]
- H. Mecha,
M. Fernandez, F. Tirado, J. Septien, D. Mozos, and K. Olcoz.
A method for area estimation of data-path in high level synthesis.
IEEE Transactions on Computer-Aided Design, 15(2):258-265, February
1996.
- [2884]
- G. Medeiros-Ribeiro, J. H. Nickel, and J.-J. Yang.
Progress in CMOS-memristor integration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 246-249, San Jose, CA, November 7-10 2011.
- [2885]
- W. Meeker, Jr. and
L. Escobar.
Pitfalls of accelerated testing.
IEEE Transactions on Reliability, 47(2):114-118, June 1998.
- [2886]
- P. K. Meher.
Extended sequential logic for synchronous circuit optiimization and its
applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(4):469-477, April 2009.
- [2887]
- R. Mehra,
L. Guerra, and J. Rabaey.
Exploiting locality for low-power design.
In IEEE 1996 Custom Integrated Circuits Conference, pages 401-404,
San Diego, CA, May 5-8 1996.
- [2888]
- R. Mehra, L. M.
Guerra, and J. M. Rabaey.
A partitioning scheme for optimizing interconnect power.
IEEE Journal of Solid State Circuits, 32(3):433-443, March 1997.
- [2889]
- R. Mehra and J. Rabaey.
Behavioral level power estimation and exploration.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
197-202, Napa, CA, April 24-27 1994.
- [2890]
- R. Mehra and J. Rabaey.
Exploiting regularity for low-power design.
In IEEE/ACM International Conference on Computer-Aided Design, pages
166-172, San Jose, CA, November 10-14 1996.
- [2891]
- V. Mehrotra,
S. L. Sam, D. Boning, A. Chandrakasan, R. Vallishayee, and S. Nassif.
A methodology for modeling the effects of systematic within-die interconnect
and device variations on circuit performance.
In Design Automation Conference, pages 172-175, Los Angeles, CA, June
5-9 2000.
- [2892]
- A. Mehrotra and
A. Somani.
A robust and efficient harmonic balance (HB) using direct solution of HB
jacobian.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
370-375, San Francisco, CA, July 26-31 2009.
- [2893]
- A. Mehrotra.
Noise analysis of phase-locked loops.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 277-282, San Jose, CA, November 5-9 2000.
- [2894]
- A. Mehrotra.
Noise analysis of phase-locked loops.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(9):1309-1316, September 2002.
- [2895]
- H. Mehta, R. M.
Owens, and M. J. Irwin.
Energy characterization based on clustering.
In 33rd Design Automation Conference, pages 702-707, Las Vegas, NV,
June 3-7 1996.
- [2896]
- H. Mehta, R. M.
Owens, M. J. Irwin, R. Chen, and D. Ghosh.
Techniques for low energy software.
In 1997 International Symposium on Low Power Electronics and Design,
pages 72-75, Monterey, CA, August 18-20 1997.
- [2897]
- V. J. Mehta,
M. Marek-Sadowska, K.-H. Tsai, and J. Rajski.
Diagnosis of delay defects and delay variations.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 92-97, Monterey, CA,
February 25-26 2008.
- [2898]
- T. Mei,
J. Roychowdhury, T. S. Coffey, S. A Hutchinson, and D. M. Day.
Robust, stable time-domain methods for solving mpdes of fast/slow systems.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
848-853, San Diego, CA, June 7-11 2004.
- [2899]
- T. Mei,
J. Roychowdhury, T. S. Coffey, S. A. Hutchinson, and D. M. Day.
Robust, stable time-domain methods for solving mpdes of fast/slow systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(2):226-239, February 2005.
- [2900]
- T. Mei, H. Thornquist,
E. Keiter, and S. Hutchinson.
Structure preserving reduced-order modeling of linear periodic time-varying
systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 361-366, San Jose, CA, November 7-10 2011.
- [2901]
- P. C. H. Meier,
R. A. Rutenbar, and L. R. Carley.
Exploring multiplier architecture and layout for low power.
In IEEE 1996 Custom Integrated Circuits Conference, pages 513-516,
San Diego, CA, May 5-8 1996.
- [2902]
- M. Meijer,
F. Pessolano, and J. Pineda de Gyvez.
Technology exploration for adaptive power and frequency scaling in 90nm CMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 14-19, Newport Beach, CA, August 9-11 2004.
- [2903]
- I. Meilijson and
A. Nadas.
Convex majorization with an application to the length of critical paths.
Journal of Applied Probability, 16(3):671-677, September 1979.
- [2904]
- J. D. Meindl.
A history of low power electronics: how it began and where it's headed.
In 1997 International Symposium on Low Power Electronics and Design,
pages 149-151, Monterey, CA, August 18-20 1997.
- [2905]
- S. Mele and M. Favalli.
A SAT based test generation method for delay fault testing of macro based
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(4):631-635, April 2011.
- [2906]
- M. Menezes,
R. Baldick, and L. T. Pileggi.
A sequential quadratic programming approach to concurrent gate and wire sizing.
IEEE Transactions on Computer-Aided Design, 16(8):867-881, August
1997.
- [2907]
- N. Menezes,
C. Kashyap, and C. Amin.
A true electrical cell model for timing, noise, and power grid verification.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
462-467, Anaheim, CA, June 8-13 2008.
- [2908]
- Y. Meng,
T. Sherwood, and R. Kastner.
Leakage power reduction of embedded memories on fpgas through location
assignment.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
612-617, San Francisco, CA, July 24-28 2006.
- [2909]
- X. Meng, R. Saleh,
and K. Arabi.
Layout of decoupling capacitors in IP blocks for 90-nm CMOS.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(11):1581-1588, November 2008.
- [2910]
- K.-H. Meng,
V. Shukla, and E. Rosenbaum.
Full-component modeling and simulating of charged device model ESD.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(7):1105-1113, July 2016.
- [2911]
- K. Meng and R. Joseph.
Process variation aware cache leakage management.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 262-267, Tegernsee, Germany, October 4-6 2006.
- [2912]
- S. Meninger,
J. O. Mur-Miranda, R. Amirtharajah, A. Chandrakasan, and J. H. Lang.
Vibration-to-electric energy conversion.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(1):64-76, February 2001.
- [2913]
- M. R. Mercer.
Logic elements for universally testable circuits.
In IEEE International Test Conference, pages 493-497, Sept. 8-11
1986.
- [2914]
- D. Messerman, A. Gershtein, S. Goldenberg, and V. Tsipenyuk.
Advanced modeling techniques for accurate transistor-level timing analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 55-60, Austin, Texas,
February 26-27 2007.
- [2915]
- P. Metzgen and
D. Nancekievill.
Multiplexer restructuring for FPGA implementation cost reduction.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
421-426, Anaheim, CA, June 13-17 2005.
- [2916]
- A. V. Mezhiba and
E. G. Friedman.
Inductive characteristics of power distribution grids in high speed integrated
circuits.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 316-321, San Jose, CA, March 18-21 2002.
- [2917]
- A. V. Mezhiba and
E. G. Friedman.
Inductive properties of high-performance power distribution grids.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(6):762-776, December 2002.
- [2918]
- A. V. Mezhiba and
E. G. Friedman.
Impedance characteristics of power distribution grids in nanoscale integrated
circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(11):1148-1155, November 2004.
- [2919]
- A. V. Mezhiba and
E. G. Friedman.
Scaling trends of on-chip power distribution noise.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):386-394, April 2004.
- [2920]
- N. Mi, S. X.-D.Tan,
P. Liu, J. Cui, Y. Cai, and X. Hong.
Stochastic extended krylov subspace method for variational analysis of on-chip
power grid networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 48-53, San Jose, CA, November 5-8 2007.
- [2921]
- N. Mi, J. Fan, S. X.-D.
Tan, Y. Cai, and Y. Hong.
Statistical analysis of on-chip power delivery networks considering lognormal
leakage current variations with spatial correlation.
IEEE Transactions on Circuits and Systems, 55(7):2064-2075, August
2008.
- [2922]
- N. Mi, S. X.-D. Tan,
Y. Cai, and X. Hong.
Fast variational analysis of on-chip power grids by stochastic extended krylov
subspace method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(11):1996-2006, November 2008.
- [2923]
- X. Mi, D. Mandal,
V. Sathe, B. Bakkologlu, and J.-S. Seo.
Fully-integrated switched-capacitor voltage regulator with on-chip
current-sensing and workload optimization in 32nm SOI CMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 371-376, Rome, Italy, July 22-24 2015.
- [2924]
- J. Miao, K. He,
A. Gerstlauer, and M. Orshansky.
Modeling and synthesis of quality-energy optimal approximate adders.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 728-735, San Jose, CA, November 5-8 2012.
- [2925]
- G. Micheli.
Reliable communication in systems on chips.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 77-77,
San Diego, CA, June 7-11 2004.
- [2926]
- P. Miettinen, M. Honkala, J. Roos, and M. Valtonen.
Partmor: partitioning-based realizable model-order reduction method for RLC
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(3):374-387, March 2011.
- [2927]
- P. Miettinen, M. Honkala, J. Roos, and M. Valtonen.
Sparsification of dense capacitive coupling of interconnect models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1955-1959, October 2013.
- [2928]
- F. Milano and
M. Anghel.
Impact of time delays on power system stability.
IEEE Transactions on Circuits and Systems, 59(4):889-900, April
2012.
- [2929]
- P. Miliozzi,
I. Vassiliou, E. Charbon, E. Malavasi, and A. L. Sangiovanni-Vincentelli.
Use of sensitivities and generalized substrate models in mixed-signal IC
design.
In 33rd Design Automation Conference, pages 227-232, Las Vegas, NV,
June 3-7 1996.
- [2930]
- I. R. Miller,
J. E. Freund, and R. Johnson.
Probability and Statistics for Engineers.
Prentice-Hall, Inc., Englewood Cliffs, NJ, 4th edition, 1990.
- [2931]
- G. Miller,
B. Bhattarai, Y.-C. Hsu, J. Dutt, X. Chen, and G. Bakewell.
A method to leverage pre-silicon collateral and analysis for post-silicon
testing and validation.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
575-578, San Diego, CA, June 5-9 2011.
- [2932]
- R. E. Miller.
Formal analysis and synthesis of bilateral switching networks.
IRE Transactions on Electronic Computers, pages 231-244, September
1958.
- [2933]
- Raymond E. Miller.
Switching Theory, volume 2.
John Wiley and Sons, New York, NY, 1965.
- [2934]
- D. M. Miller.
An improved method for computing a generalized spectral coefficient.
IEEE Transactions on Computer-Aided Design, 17(3):233-238, March
1998.
- [2935]
- P. Milliozzi, L. Carloni, E. Charbon, and A. L.
Sangiovanni-Vincentelli.
SUBWAVE: A methodology for modeling digital substrate noise injection.
In IEEE 1996 Custom Integrated Circuits Conference, pages 385-388,
San Diego, CA, May 5-8 1996.
- [2936]
- O. Milter and
A. Kolodny.
Crosstalk noise reduction in synthesized digital logic circuits.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(6):1153-1158, December 2003.
- [2937]
- K.-S. Min, K. Kanda,
and T. Sakurai.
Row-by-row dynamic source-line voltage control (RRDSV) scheme for two orders
of magnitude leakage current reduction of sub-1-V-VDD SRAM's.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 66-71, Seoul, Korea, August 25-27 2003.
- [2938]
- K.-S. Min, H.-D.
Choi, H.-Y. Choi, H. Kawaguchi, and T. Sakurai.
Leaking-suppressed clock-gating circuit with zigzag super cut-off CMOS
(ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-v-vdd lsis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(4):430-435, April 2006.
- [2939]
- P. Min, H. Yi,
J. Song, S. Baeg, and S. Park.
Efficient interconnect test patterns for crosstalk and static faults.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2605-2608, November 2006.
- [2940]
- S-I Minato and G. De
Micheli.
Finding all simple disjunctive decompositions using irredundant sum-of-products
forms.
In IEEE/ACM International Conference on Computer-Aided Design, pages
111-117, San Jose, CA, November 8-12 1998.
- [2941]
- E. Mintarno,
J. Skaf, R. Zheng, J. B. Velamala, Y. Cao, S. Boyd, R. W. Dutton, and
S. Mitra.
Self-tuning for maximized lifetime energy-efficiency in the presence of circuit
aging.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(5):760-773, May 2011.
- [2942]
- M. Miranda,
P. Roussel, L. Brusamarello, and G. Wirth.
Statistical characterization of standard cells using design of experiments with
response surface modeling.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
77-82, San Diego, CA, June 5-9 2011.
- [2943]
- A. Mishchenko, S. Chatterjee, and R. Brayton.
DAG-aware AIG rewriting a fresh look at combinational logic synthesis.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
532-535, San Francisco, CA, July 24-28 2006.
- [2944]
- A. Mishchenko, J.-S. Zhang, S. Sinha, J. R. Burch, R. Brayton,
and M. Chrzanowska-Jeske.
Using simulation and satisfiability to compute flexibilities in boolean
networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):743-755, May 2006.
- [2945]
- A. Mishchenko, R. Brayton, and S. Chatterjee.
Boolean factoring and decomposition of logic networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 38-44, San Jose, CA, November 10-13 2008.
- [2946]
- A. Mishchenko
and R. K. Brayton.
A theory of non-deterministic networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 709-716, San Jose, CA, November 9-13 2003.
- [2947]
- A. Mishchenko
and R. K. Brayton.
A theory of nondeterministic networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(6):977-999, June 2006.
- [2948]
- A. Mishchenko
and T. Sasao.
Large-scale SOP minimization using decomposition and functional properties.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
149-154, Anaheim, CA, June 2-6 2003.
- [2949]
- A. Mishchenko.
Fast computation of symmetries in boolean functions.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(11):1588-1593, November 2003.
- [2950]
- V. Mishra and S. S.
Sapatnekar.
The impact of electromigration in copper interconnects on power grid integrity.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [2951]
- N. Miskov-Zivanov, J. R. Faeder, C. J. Myers, and H. M. Sauro.
Modeling and design automation of biological circuits and systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 291-293, San Jose, CA, November 5-8 2012.
- [2952]
- N. Miskov-Zivanov and D. Marculescu.
Circuit reliability analysis using symbolic techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2638-2649, December 2006.
- [2953]
- N. Miskov-Zivanov and D. Marculescu.
Formal modeling and reasoning for reliability analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
531-536, Anaheim, CA, June 13-18 2010.
- [2954]
- J. N. Mistry,
J. Myers, B. M. Al-Hashimi, D. Flynn, J. Biggs, and G. V. Merrett.
Active mode subclock power gating.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(9):1898-1908, September 2014.
- [2955]
- A. Mitev,
D. Ganesan, D. Shanmugasundaram, Y. Cao, and J.-M. Wang.
A robust finite-point based gate model considering process variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 692-697, San Jose, CA, November 5-8 2007.
- [2956]
- A. Mitev,
M. Marefat, D. Ma, and J.-M. Wang.
Principle hessian direction based parameter reduction with process variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 632-637, San Jose, CA, November 5-8 2007.
- [2957]
- A. Mitev,
M. Marefat, D. Ma, and J.-M. Wang.
Principle hessian direction-based parameter reduction for interconnect networks
with process variation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(9):1337-1347, September 2010.
- [2958]
- S. Mitra, R. A.
Rutenbar, L. R. Carley, and D. J. Allstot.
A methodology for rapid estimation of substrate-coupled switching noise.
In IEEE Custom Integrated Circuits Conference, pages 129-132, Santa
Clara, CA, May 1-4 1995.
- [2959]
- S. Mitra,
T. Karnik, N. Seifert, and M. Zhang.
Logic soft errors in sub-65nm technologies design and CAD challenges.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 2-4,
Anaheim, CA, June 13-17 2005.
- [2960]
- S. Mitra, S. A.
Seshia, and N. Nicolici.
Post-silicon validation opportunities, challenges and recent advances.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
12-17, Anaheim, CA, June 13-18 2010.
- [2961]
- R. S. Mitra.
Strategies for mainstream usage of formal verification.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
800-805, Anaheim, CA, June 8-13 2008.
- [2962]
- T. Mitsuhashi and
E. S. Kuh.
Power and ground network topology optimization for cell based vlsis.
In 29th ACM/IEEE Design Automation Conference, pages 524-529,
Anaheim, CA, June 8-12 1992.
- [2963]
- G. Mittal, D. C.
Zaratsky, X. Tang, and P. Banerjee.
Automatic translation of software binaries onto fpgas.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
389-394, San Diego, CA, June 7-11 2004.
- [2964]
- K. Miyase and
S. Kajihara.
XID: don't care identification of test patterns for combinational circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(2):321-326, February 2004.
- [2965]
- M. Miyazaki,
H. Tanaka, G. Ono, T. Nagano, and N. Ohkubo.
Electric-energy generation using variable-capacitive resonator for power-free
LSI: efficient analysis and fundamental experiment.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 193-198, Seoul, Korea, August 25-27 2003.
- [2966]
- L. Mizrukhin, J. Huey, and S. Mehta.
Prediction of product yield distributions from wafer parametric mesurements of
CMOS circuits.
IEEE Transactions on Semiconductor Manufacturing, 5(2):88-93, May
1992.
- [2967]
- F. Mo and R. K. Brayton.
Whirlpool plas: A regular logic structure and their synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 543-549, San Jose, CA, November 10-14 2002.
- [2968]
- F. Mo and R. Brayton.
PLA-based regular structures and their synthesis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(6):723-729, June 2003.
- [2969]
- B. C.
Mochocki, X.-S. Hu, and G. Quan.
A unified approach to variable voltage scheduling for nonideal DVS
processors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1370-1377, September 2004.
- [2970]
- H. D. Mogal,
H. Qian, S. S. Sapatnekar, and K. Bazargan.
Clustering based pruning for statistical criticality computation under process
variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 340-343, San Jose, CA, November 5-8 2007.
- [2971]
- H. D. Mogal,
H. Qian, S. S. Sapatnekar, and K. Bazargan.
Fast and accurate statistical criticality computation under process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(3):350-363, March 2009.
- [2972]
- V. Mohan,
T. Bunker, L. Grupp, S. Gurumurthi, M. R. Stan, and S. Swanson.
Modeling power consumption of NAND flash memories using flashpower.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(7):1031-1044, July 2013.
- [2973]
- C. R. Mohan and
P. P. Chakrabarti.
A new approach for factorizing fsms.
In IEEE/ACM International Conference on Computer-Aided Design, pages
698-701, San Jose, CA, November 6-10 1994.
- [2974]
- K. Mohanram and
J. Guo.
Graphene nanoribbon fets: technology exploration and CAD.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 412-415, San Jose, CA, November 10-13 2008.
- [2975]
- S. P. Mohanty
and N. Ranganathan.
A framework for energy and transient power reduction during behavioral
synthesis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(6):562-572, June 2004.
- [2976]
- M. Mohiyuddin, A. Prakash, A. Aziz, and W. Wolf.
Synthesizing interconnect-efficient low density parity check codes.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
488-491, San Diego, CA, June 7-11 2004.
- [2977]
- N. N.
Mojumder, S. Mukhopadhyay, J.-J. Kim, C.-T. Chuang, and K. Roy.
Self-repairing SRAM using on-chip detection and compensation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(1):75-84, January 2010.
- [2978]
- M. E. Mokari and
W. Patience.
Calculation of noise parameters by direct matrix analysis.
In 1991 IEEE International Symposium on Circuits and Systems, pages
2343-2346, June 1991.
- [2979]
- C. Moler and C. Van Loan.
Nineteen dubious ways to compute the exponential of a matrix.
SIAM Review, 20(4):801-836, October 1978.
- [2980]
- C. Moler and C. V. Loan.
Nineteen dubious ways to compute the exponential of a matrix, twenty-five years
later.
SIAM Review, 45(1):3-49, 2003.
- [2981]
- A. Mondal and
P. P. Chakrabarti.
Reasoning about timing behavior of digital circuits using symbolic event
propagation and temporal logic.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1793-1814, September 2006.
- [2982]
- W. S. Mong and J. Zhu.
A retargetable micro-architecture simulator.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
752-757, Anaheim, CA, June 2-6 2003.
- [2983]
- W.-S. Mong and J. Zhu.
Dynamosim: a trace-based dynamically compiled instruction set simulator.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 131-136, San Jose, CA, November 7-11 2004.
- [2984]
- J. Monteiro,
S. Devadas, and A. Ghosh.
Retiming sequential circuits for low power.
In IEEE International Conference on Computer-Aided Design, pages
398-402, Santa Clara, CA, 1993.
- [2985]
- J. Monteiro,
S. Devadas, B. Lin, C-Y. Tsui, and M. Pedram.
Exact and approximate methods of switching activity estimation in sequential
logic circuits.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
117-122, Napa, CA, April 24-27 1994.
- [2986]
- J. Monteiro,
S. Devadas, P. Ashar, and A. Mauskar.
Scheduling techniques to enable power management.
In 33rd Design Automation Conference, pages 349-352, Las Vegas, NV,
June 3-7 1996.
- [2987]
- J. Monteiro,
S. Devadas, A. Ghosh, K. Keutzer, and J. White.
Estimation of average switching activity in combinational logic circuits using
symbolic simulation.
IEEE Transactions on Computer-Aided Design, 16(1):121-127, January
1997.
- [2988]
- J. Monteiro, S. Devadas, and A. Gosh.
Sequential logic optimization for low power using input-disabling
precomputation architectures.
IEEE Transactions on Computer-Aided Design, 17(3):279-284, March
1998.
- [2989]
- J. Monteiro and
S. Devadas.
A methodology for efficient estimation of switching activity in sequential
logic circuits.
In 31st ACM/IEEE Design Automation Conference, pages 12-17, San
Diego, CA, June 6-10 1994.
- [2990]
- J. Monteiro and
S. Devadas.
Techniques for the power estimation of sequential logic circuits under
user-specified input sequences and programs.
In ACM/IEEE International Symposium on Low Power Design, pages 33-38,
Dana Point, CA, April 23-26 1995.
- [2991]
- J. C. Monteiro
and A. L. Oliveira.
Finite state machine decomposition for low power.
In IEEE/ACM 35th Design Automation Conference, pages 758-763, San
Francisco, CA, June 15-19 1998.
- [2992]
- J. C. Monteiro
and A. L. Oliveira.
Implicit FSM decomposition applied to low-power design.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):560-565, October 2002.
- [2993]
- J. C. Garcia Montesdeoca, J. A. Montiel-Nelson, and
S. Nooshabadi.
CMOS driver-receiver pair for low-swing signaling for low energy on-chip
interconnects.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):311-316, February 2009.
- [2994]
- C. W. Moon,
H. Kriplani, and K. P. Belkhale.
Timing model extraction of hierarchical blocks by graph reduction.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
152-157, New Orleans, LA, June 10-14 2002.
- [2995]
- C. W. Moon and R. K.
Brayton.
Elimination of dynamic hazards by factoring.
In 30th ACM/IEEE Design Automation Conference, pages 7-13, Dallas,
Texas, June 14-18 1993.
- [2996]
- S.-J. Moon and A. C.
Cangellaris.
Passivity enforcement via quadratic programming for element-by-element rational
function approximation of passive network matrices.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 203-206, San Jose, CA, October 27-29 2008.
- [2997]
- A. Morgenshtein, A. Fish, and I. A. Wagner.
Gate-diffusion input (GDI): a power-efficient method for digital
combinatorial circuits.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):566-581, October 2002.
- [2998]
- A. Morgenshtein, E. G. Friedman, R. Ginosar, and A. Kolodny.
Unified logical effort - a method for delay evaluation and minimization in
logic paths with RC interconnect.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(5):689-696, May 2010.
- [2999]
- C. A. Moritz,
T. Wang, P. Narayanan, M. Leuchtenburg, Y. Guo, C. Dezan, and M. Bennaser.
Fault-tolerant nanoscale processors on semiconductor nanowire grids.
IEEE Transactions on Circuits and Systems, 54(11):2422-2437, November
2007.
- [3000]
- P. B. Morton and W. Dai.
Crosstalk noise estimation for noise management.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
659-664, New Orleans, LA, June 10-14 2002.
- [3001]
- A. Moshovos,
B. Falsafi, F. N. Najm, and N. Azizi.
A case for asymmetric-cell cache memories.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(7):877-881, July 2005.
- [3002]
- A. Moshovos.
Checkpointing alternatives for high performance, power-aware processors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 318-321, Seoul, Korea, August 25-27 2003.
- [3003]
- H. Mostafa,
M. Anis, and M. Elmasry.
Novel timing yield improvement circuits for high-performance low-power wide
fan-in dynamic OR gates.
IEEE Transactions on Circuits and Systems, 58(8):1785-1797, August
2011.
- [3004]
- H. Mostafa,
M. H. Anis, and M. Elmasry.
Analytical soft error models accounting for die-to-die and within-die
variations in sub-threshold SRAM cells.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(2):182-195, February 2011.
- [3005]
- H. Mostafa,
M. Anis, and M. Elmasry.
Statistical SRAM read access yield improvement using negative capacitance
circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(1):92-101, January 2013.
- [3006]
- K. Motohashi.
The prospects of next generation television - japans initiative to 2020 -.
In 20th Asia and South Pacific Design Automation Conference, pages
677-679, Chiba/Tokyo, Japan, January 19-22 2015.
- [3007]
- M. Mottaghi-Dastjerdi, A. Afzali-Kusha, and M. Pedram.
BZ-FAD: a low-power low-area multiplier based on shift-and-add
architecture.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):302-306, February 2009.
- [3008]
- Z. Moudallal and
F. N. Najm.
Generating circuit current constraints to guarantee power grid safety.
In 20th Asia and South Pacific Design Automation Conference, pages
358-365, Chiba/Tokyo, Japan, January 19-22 2015.
- [3009]
- Z. Moudallal and
F. N. Najm.
Generating current budgets to guarantee power grid safety.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(11):1914-1927, November 2016.
- [3010]
- Z. Moudallal and
F. N. Najm.
Generating current constraints to guarantee RLC power grid safety.
ACM Transactions on Design Automation of Electronic Systems (TODAES),
22(4):66:1-66:39, June 2017.
- [3011]
- V. Mrazek, S. S.
Sarwar, L. Sekanina, Z. Vasicek, and K. Roy.
Design of power-efficient approximate multipliers for approximate artificial
neural networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [3012]
- S.-P. Mu, W.-H. Chang,
M.-C.-T. Chao, Y.-M. Wang, M.-T. Chang, and M.-H. Tsai.
Statistical methodology to identify optimal placement of on-chip process
monitors for predicting fmax.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [3013]
- Z. Mu.
Discussing impedance distribution with multiple stimulating sources in power
distribution system design and simulation.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 103-106, San Jose, CA, October 27-29 2008.
- [3014]
- T. Mudge.
Power: A first-class architectural design constraint.
IEEE Computer, pages 52-58, April 2001.
- [3015]
- E. I. Muehldorf
and A. D. Savkar.
LSI logic testing - an overview.
IEEE Transactions on Computers, C-30(1):1-17, January 1981.
- [3016]
- E. I. Muehldorf
and T. W. Williams.
Analysis of the switching behavior of combinational logic networks.
In IEEE International Test Conference, pages 379-390, Nov. 15-18
1982.
- [3017]
- M. L. Mui,
K. Banerjee, and A. Mehrotra.
Power supply optimization in sub-130 nm leakage dominant technologies.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 409-414, San Jose, CA, March 22-24 2004.
- [3018]
- M.-L. Mui,
K. Banerjee, and A. Mehrotra.
Supply and power optimization in leakage-dominant technologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(9):1362-1371, September 2005.
- [3019]
- T. Mukherjee, G. K. Fedder, D. Ramaswamy, and J. White.
Emerging simulation approaches for micromachined devices.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1572-1589, December 2000.
- [3020]
- P. Mukherjee, G.-P. Fang, R. Burt, and P. Li.
Automatic stability checking for large linear analog integrated circuits.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
304-309, San Diego, CA, June 5-9 2011.
- [3021]
- S. Mukherjee and
S. Roy.
Nearly-2-SAT solutions for segmented-channel routing.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(1):128-140, January 2016.
- [3022]
- T. Mukherjee.
Design automation issues for biofluidic microchips.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 463-470, San Jose, CA, November 6-10 2005.
- [3023]
- S. Mukhopadhyay, C. Neau, R. T. Cakici, A. Agarwal, C. H. Kim,
and K. Roy.
Gate leakage reduction for scaled devices using transistor stacking.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):716-730, August 2003.
- [3024]
- S. Mukhopadhyay, A. Raychowdhury, and K. Roy.
Accurate estimation of total leakage current in scaled CMOS logic circuits
based on compact current modeling.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
169-174, Anaheim, CA, June 2-6 2003.
- [3025]
- S. Mukhopadhyay, H. Mahmoodi, and K. Roy.
Statistical design and optimization of SRAM cell for yield enhancement.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 10-13, San Jose, CA, November 7-11 2004.
- [3026]
- S. Mukhopadhyay, H. Mahmoodi, and K. Roy.
Modeling of failure probability and statistical design of SRAM array for
yield enhancement in nanoscaled CMOS.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(12):1859-1880, December 2005.
- [3027]
- S. Mukhopadhyay, A. Raychowdhury, and K. Roy.
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits
based on device geometry and doping profile.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):363-381, March 2005.
- [3028]
- S. Mukhopadhyay, S. Bhunia, and K. Roy.
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS
logic circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(8):1486-1495, August 2006.
- [3029]
- S. Mukhopadhyay, K. Kim, C.-T. Chuang, and K. Roy.
Modeling and analysis of leakage currents in double-gate technologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2052-2061, October 2006.
- [3030]
- S. Mukhopadhyay and K. Roy.
Modeling and estimation of total leakage current in nano-scaled CMOS devices
considering the effect of parameter variation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 172-175, Seoul, Korea, August 25-27 2003.
- [3031]
- A. Mukhopadhyay.
Complete sets of logic primitives.
In A. Mukhopadhyay, editor, Recent Developments in Switching Theory,
pages 1-26. Academic Press, New York, NY, 1971.
- [3032]
- S. Mukhopadhyay.
A generic data-driven nonparametric framework for variability analysis of
integrated circuits in nanometer technologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(7):1038-1046, July 2009.
- [3033]
- A. V. Mule, E. N.
Glytsis, T. K. Gaylord, and J. D. Meindl.
Electrical and optical clock distribution networks for gigascale
microprocessors.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):582-594, October 2002.
- [3034]
- R. S. Muller and
Theodore Kamins.
Device Electronics for Integrated Circuits.
John Wiley & Sons, 1986.
- [3035]
- D. E. Muller.
Treatment of transition signals in electronic switching circuits by algebraic
methods.
IRE Transactions on Electronic Computers, EC-8(3):401, September
1959.
- [3036]
- T. Munakata,
S. Sinha, and W. L. Ditto.
Chaos computing: implementation of fundamental logical gates by chaotic
elements.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(11):1629-1633, November 2002.
- [3037]
- H. Murata and E. S. Kuh.
Sequence-pair based placement method for hard/soft/pre-placed modules.
In ACM/IEEE International Symposium on Physical Design, pages
167-172, Monterey, CA, April 6-8 1998.
- [3038]
- R. Murgai, R. K.
Brayton, and A. Sangiovanni-Vincentelli.
On clustering for minimum delay/area.
In IEEE International Conference on Computer-Aided Design, pages 6-9,
Santa Clara, CA, November 11-14 1991.
- [3039]
- R. Murgai, R. K.
Brayton, and A. Sangiovanni-Vincentelli.
Decomposition of logic functions for minimum transition activity.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
33-38, Napa, CA, April 24-27 1994.
- [3040]
- R. Murgai,
M. Fujita, and A. Oliveira.
Using complementation and resequencing to minimize transitions.
In IEEE/ACM 35th Design Automation Conference, pages 694-697, San
Francisco, CA, June 15-19 1998.
- [3041]
- T. Murgan,
M. Momeni, A. Garcia Ortiz, and M. Glesner.
A high-level compact pattern-dependent delay model for high-speed
point-to-point interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 323-328, San Jose, CA, November 5-9 2006.
- [3042]
- B. Murmann and
W. Xiong.
Design of analog circuits using organic field-effect transistors.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 504-507, San Jose, CA, November 7-11 2010.
- [3043]
- Saburo Muroga.
Logic Design and Switching Theory.
John Wiley & Son, New York, NY, 1979.
- [3044]
- A. K.
Murugavel, N. Ranganathan, R. Chandramouli, and S. Chavali.
Least-square estimation of average power in digital CMOS circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(1):55-58, February 2002.
- [3045]
- A. K.
Murugavel and N. Ranganathan.
Petri net modeling of gate and interconnect delays for power estimation.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
455-460, New Orleans, LA, June 10-14 2002.
- [3046]
- A. K.
Murugavel and N. Ranganathan.
A game theoretic approach for power optimization during behavioral synthesis.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(6):1031-1043, December 2003.
- [3047]
- A. K.
Murugavel and N. Ranganathan.
Petri net modeling of gate and interconnect delays for power estimation.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(5):921-927, October 2003.
- [3048]
- A. Mutlu, J. Le,
R. Molina, and M. Celik.
A parametric approach for handling local variation effects in timing analysis.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
126-129, San Francisco, CA, July 26-31 2009.
- [3049]
- M. Mutyam.
Selective shielding: a crosstalk-free bus encoding technique.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 618-621, San Jose, CA, November 5-8 2007.
- [3050]
- M. Mutyam.
Fibonacci codes for crosstalk avoidance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(10):1899-1903, October 2012.
- [3051]
- G. Nabaa,
N. Azizi, and F. N. Najm.
An adaptive FPGA architecture with process variation compensation and reduced
leakage.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
624-629, San Francisco, CA, July 24-28 2006.
- [3052]
- G. Nabaa and F. N. Najm.
Minimization of delay sensitivity to process induced voltage threshold
variations.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 171-174, Quebec City, Quebec, June 19-22 2005.
- [3053]
- A. Nabavi-Lishi and N. Rumin.
Delay and bus current evaluation in CMOS logic circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
198-203, Santa Clara, CA, November 8-12 1992.
- [3054]
- K. Nabors, T-T
Fang, H-W Chang, K. S. Kundert, and J. K. White.
Lumped interconnect models via gaussian quadrature.
In 34th Design Automation Conference, pages 40-45, Anaheim, CA, June
9-13 1997.
- [3055]
- K. Nabors and J. White.
Fastcap: A multipole accelerated 3-D capacitance extraction program.
IEEE Transactions on Computer-Aided Design, 10(11):1447-1459,
November 1991.
- [3056]
- J. A. Nachlas,
C. R. Cassady, and K. F. Rooney.
Hazard-function implications of stochastic-deterioration and distributed-defect
concentrations.
In Annual Reliability and Maintainability Symposium, pages 213-216,
Washington, DC, January 16-19 1995.
- [3057]
- S. Nadarajah and
S. Kotz.
Exact distribution of the max/min of two gaussian random variables.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(2):210-212, February 2008.
- [3058]
- A. Nadas.
Probabilistic PERT.
IBM Journal of Research and Development, 23(3):339-347, May 1979.
- [3059]
- A. Nadas.
Random critical paths.
In IEEE International Symposium on Circuits and Systems, pages 32-35,
1980.
- [3060]
- A. Naeemi,
Y. Joshi, F. Fedorov, P. Kohl, and J. D. Meindl.
The urgency of deep sub-ambient cooling for gigascale integration.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 171-174, Austin, TX, May 9 - 11 2005.
- [3061]
- A. Naeemi and J. D.
Meindl.
Physical models for electron transport in graphene nanoribbons and their
junctions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 400-405, San Jose, CA, November 10-13 2008.
- [3062]
- S. Naffziger, T. Grutkowski, and B. Stackhouse.
The implementation of a 2-core, multi-threaded itanium family processor.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 43-48, Austin, TX, May 9 - 11 2005.
- [3063]
- M. Nagata.
On-chip measurements complementary to design flows for integrity in socs.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
400-403, San Diego, CA, June 4-8 2007.
- [3064]
- B. Nagy and M. Matolcsi.
Algorithm for positive realization of transfer functions.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(5):699-702, May 2003.
- [3065]
- A. Nahir,
M. Dusanapudi, S. Kapoor, K. Reick, W. Roesner, K.-D. Schubert, K. Sharp, and
G. Wetli.
Post-silicon validation of the IBM power8 processor.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [3066]
- F. Najm, R. Burch,
P. Yang, and I. Hajj.
CREST - A current estimator for CMOS circuits.
In IEEE International Conference on Computer-Aided Design, pages
204-207, Santa Clara, CA, Nov. 7-10 1988.
- [3067]
- F. Najm, I. Hajj,
and P. Yang.
Computation of bus current variance for reliability estimation of VLSI
circuits.
In IEEE International Conference on Computer-Aided Design, pages
202-205, Santa Clara, CA, November 5-9 1989.
- [3068]
- F. Najm, I. Hajj,
and P. Yang.
Electromigration median time-to-failure based on a stochastic current waveform.
In 1989 IEEE International Conference on Computer Design, pages
447-450, Cambridge, MA, October 2-4 1989.
- [3069]
- F. Najm, R. Burch,
P. Yang, and I. Hajj.
Probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Transactions on Computer-Aided Design, 9(4):439-450, April
1990.
- [3070]
- F. Najm, I. Hajj,
and P. Yang.
An extension of probabilistic simulation for reliability analysis of CMOS
VLSI circuits.
IEEE Transactions on Computer-Aided Design, 10(11):1372-1381,
November 1991.
- [3071]
- F. N. Najm,
S. Goel, and I. N. Hajj.
Power estimation in sequential circuits.
In 32nd Design Automation Conference, pages 635-640, San Francisco,
CA, June 12-16 1995.
- [3072]
- F. N. Najm,
N. Menezes, and I. A. Ferzli.
A yield model for integrated circuits and its application to statistical timing
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(3):574-591, March 2007.
- [3073]
- F. Najm and I. Hajj.
The complexity of fault detection in MOS VLSI circuits.
IEEE Transactions on Computer-Aided Design, 9(9):995-1001, September
1990.
- [3074]
- F. Najm and I. Hajj.
Probabilistic simulation of very large scale integrated circuits and systems.
In 1990 Bilkent International Conference on New Trends in Communication,
Control, and Signal Processing, Bilkent University, Ankara, Turkey, July
2-5 1990.
- [3075]
- F. N. Najm and N. Menezes.
Statistical timing analysis based on a timing yield model.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
460-465, San Diego, CA, June 7-11 2004.
- [3076]
- F. N. Najm and M. Y. Zhang.
Extreme delay sensitivity and the worst-case switching activity in VLSI
circuits.
In 32nd Design Automation Conference, pages 623-627, San Francisco,
CA, June 12-16 1995.
- [3077]
- F. Najm.
Transition density, a stochastic measure of activity in digital circuits.
In 28th ACM/IEEE Design Automation Conference, pages 644-649, San
Francisco, CA, June 17-21 1991.
- [3078]
- F. Najm.
Transition density : a new measure of activity in digital circuits.
IEEE Transactions on Computer-Aided Design, 12(2):310-323, February
1993.
- [3079]
- F. Najm.
Improved estimation of the switching activity for reliability prediction in
VLSI circuits.
In IEEE 1994 Custom Integrated Circuit Conference, pages 429-432, San
Diego, CA, May 1-4 1994.
- [3080]
- F. Najm.
A survey of power estimation techniques in VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2(4):446-455, December 1994.
- [3081]
- F. N. Najm.
Low-pass filter for computing the transition density in digital circuits.
IEEE Transactions on Computer-Aided Design, 13(9):1123-1131,
September 1994.
- [3082]
- F. N. Najm.
Feedback, correlation, and delay concerns in the power estimation of VLSI
circuits.
In 32nd Design Automation Conference, pages 612-617, San Francisco,
CA, June 12-16 1995.
- [3083]
- F. N. Najm.
Power estimation techniques for integrated circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
492-499, San Jose, CA, November 5-9 1995.
- [3084]
- F. N. Najm.
Towards a high-level power estimation capability.
In ACM/IEEE International Symposium on Low Power Design, pages 87-92,
Dana Point, CA, April 23-26 1995.
- [3085]
- F. N. Najm.
On the need for statistical timing analysis.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
764-765, Anaheim, CA, June 13-17 2005.
- [3086]
- F. N. Najm.
Circuit Simulation.
John Wiley & Sons, Inc., Hoboken, NJ, 2010.
- [3087]
- F. N. Najm.
Overview of vectorless/early power grid verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 670-677, San Jose, CA, November 5-8 2012.
- [3088]
- F. N. Najm.
Physical design challenges in the chip power distribution network.
In ACM International Symposium on Physical Design 2015, page 101,
Monterey, California, March 29 - April 1 2015.
- [3089]
- S. Nakatake,
K. Sakanushi, Y. Kajitani, and M. Kawakita.
The channeled-BSG: A universal floorplan for simultaneous place/route with
IC applications.
In IEEE/ACM International Conference on Computer-Aided Design, pages
418-425, San Jose, CA, November 8-12 1998.
- [3090]
- Y. Nakatsukasa and R. W. Freund.
Computing fundamental matrix decompositions accurately via the matrix sign
function in two iterations: the power of zolotarev's functions.
Siam Review, 58(3):461-493, September 2016.
- [3091]
- N. Nakhla,
M. Nakhla, and R. Achar.
Sparse and passive reduction of massively coupled large multiport
interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 622-626, San Jose, CA, November 5-8 2007.
- [3092]
- A. Nalamalpu, S. Srinivasan, and W. P. Burleson.
Boosters for driving long onchip interconnects - design issues, interconnect
synthesis, and comparison with repeaters.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(1):50-62, January 2002.
- [3093]
- G.-J. Nam, S. Reda,
C. J. Alpert, P. G. Villarrubia, and A. B. Kahng.
A fast hierarchical quadratic placement algorithm.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(4):678-691, April 2006.
- [3094]
- A. Namazi,
M. Nourani, and M. Saquib.
A fault-tolerant interconnect mechanism for NMR nanoarchitectures.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(10):1433-1446, October 2010.
- [3095]
- A. Namazi and
M. Nourani.
Distributed voting for fault-tolerant nanoscale systems.
In IEEE International Conference on Computer Design (ICCD-07), pages
568-573, October 2007.
- [3096]
- A. Namazi and
M. Nourani.
Gate-level redundancy: a new design-for-reliability paradigm for
nanotechnologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(5):775-786, May 2010.
- [3097]
- A. Nani and
R. Marculescu.
System-level power/performance analysis for embedded systems design.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
599-604, Las Vegas, NV, June 18-22 2001.
- [3098]
- Simon Napper.
Static timing analysis - a demanding solution.
Electronic Engineering, pages 35-42, January 1996.
- [3099]
- M. Narasimhan and J. Ramanujan.
Improving the computational performance of ILP-based problems.
In IEEE/ACM International Conference on Computer-Aided Design, pages
593-596, San Jose, CA, November 8-12 1998.
- [3100]
- A. Narayan,
J. Jain, M. Fujita, and A. L. Sangiovanni-Vincentelli.
Partitioned robdds - A compact, canonical and efficiently manipulable
representation for boolean functions.
In IEEE/ACM International Conference on Computer-Aided Design, pages
547-554, San Jose, CA, November 10-14 1996.
- [3101]
- U. Narayanan, H. W. Leong, K.-S. Chung, and C. L. Liu.
Low power multiplexer decomposition.
In 1997 International Symposium on Low Power Electronics and Design,
pages 269-274, Monterey, CA, August 18-20 1997.
- [3102]
- U. Narayanan, P. Pan, and C. L. Liu.
Low power logic synthesis under a general delay model.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 209-214, Monterey, CA, August 10-12 1998.
- [3103]
- U. K. Narayanan and
C. L. Liu.
Low power logic synthesis for XOR based circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
570-574, San Jose, CA, November 9-13 1997.
- [3104]
- A. Nardi,
A. Neviani, E. Zanoni, M. Quarantelli, and C. Guardiani.
Impact of unrealistic worst case modeling on the performance of VLSI circuits
in deep submicron CMOS technologies.
IEEE Transactions on Semiconductor Manufacturing, 12(4):396-402,
November 1999.
- [3105]
- A. Nardi,
A. Neviani, and C. Guardiani.
Realistic worst-case modeling by performance level principal component
analysis.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 455-459, San Jose, CA, March 20-22 2000.
- [3106]
- A. Nardi, H. Zeng,
J. L. Garrett, L. Daniel, and A. L. Sangiovanni-Vincentelli.
A methodology for the computation of an upper bound and noise current spectrum
of CMOS switching activity.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 778-785, San Jose, CA, November 9-13 2003.
- [3107]
- A. Nardi,
E. Tuncer, S. Naidu, A. Antonau, S. Gradinaru, T. Lin, and J. Song.
Use of statistical timing analysis on real designs.
Design, Automation and Test in Europe (DATE-07), pages 1605-1610,
April 16-20 2007.
- [3108]
- S. Narendra,
S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan.
Scaling of stack effect and its application for leakage reduction.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 195-200, Huntington Beach, California, August 6-7
2001.
- [3109]
- S. Narendra,
V. De, S. Borkar, D. Antoniadis, and A. Chandrakasan.
Full-chip sub-threshold leakage power prediction model for sub-0.18um CMOS.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 19-23, Monterey, California, August 12-14 2002.
- [3110]
- E. Naroska,
S.-J. Ruan, U. Schwiegelshohn, and F. Lai.
Optimal permutation and spacing for unbiased random, counter, and instruction
address buses.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 111-114, Quebec City, Quebec, June 19-22 2005.
- [3111]
- E. Naroska,
S.-J. Ruan, and U. Schwiegelshohn.
Simultaneously optimizing crosstalk and power for instruction bus coupling
capacitance using wire pairing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(4):421-425, April 2006.
- [3112]
- N. Nassif, M. P.
Desai, and D. H. Hall.
Robust elmore delay models suitable for full chip timing verification of a 600
mhz CMOS microprocessor.
In IEEE/ACM 35th Design Automation Conference, pages 230-235, San
Francisco, CA, June 15-19 1998.
- [3113]
- S. Nassif,
D. Jamsek, A. Devgan, and T. Nguyen.
Timing uncertainty in SOI.
In ACM/IEEE 1999 International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU-99), pages 103-108,
Monterey, CA, March 8-9 1999.
- [3114]
- S. R. Nassif,
D. Boning, and N. Hakim.
The care and feeding of your statistical static timer.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 138-139, San Jose, CA, November 7-11 2004.
- [3115]
- S. R. Nassif and
J. N. Kozhaya.
Fast power grid simulation.
In Design Automation Conference, pages 156-161, Los Angeles, CA, June
5-9 2000.
- [3116]
- S. R. Nassif.
Design for variability in DSM technologies.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 451-454, San Jose, CA, March 20-22 2000.
- [3117]
- S. R. Nassif.
The impact of variability on power.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 350-350, Newport Beach, CA, August 9-11 2004.
- [3118]
- S. R. Nassif.
Model to hardware matching for nano-meter scale technologies.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 203-206, Tegernsee, Germany, October 4-6 2006.
- [3119]
- S. R. Nassif.
Power grid analysis benchmarks.
In 13th Asia and South Pacific Design Automation Conference
(ASPDAC-08), pages 376-381, Seoul, Korea, January 21-24 2008.
- [3120]
- K. Natarajan, H. Hanson, S. W. Keckler, C. R. Moore, and
D. Burger.
Microprocessor pipeline energy analysis.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 282-287, Seoul, Korea, August 25-27 2003.
- [3121]
- S. Nazarian,
H. Fatemi, and M. Pedram.
Accurate timing and noise analysis for combinational and sequential logic cells
using current source modeling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(1):92-103, January 2011.
- [3122]
- C. Neau and K. Roy.
Optimal body bias selection for leakage improvement and process compensation
over different technology generations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 116-121, Seoul, Korea, August 25-27 2003.
- [3123]
- J. A. Nedler and R. Mead.
A simplex method for function minimization.
Computer Journal, 7:308-313, 1965.
- [3124]
- N. Nedovic and
V. G. Oklobdzija.
Dual-edge triggered storage elements and clocking strategy for low-power
systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(5):577-590, May 2005.
- [3125]
- Wayne Nelson.
Acclerated Testing, Statistical Models, Test Plans, and Data Analyses.
John Wiley & Sons, New York, NY, 1990.
- [3126]
- W. B. Nelson.
A bibliography of accelerated test plans.
IEEE Transactions on Reliability, 54(2):194-197, June 2005.
- [3127]
- W. B. Nelson.
A bibliography of accelerated test plans part II - references.
IEEE Transactions on Reliability, 54(3):370-373, September 2005.
- [3128]
- M. Nemani and F. N.
Najm.
High-level power estimation and the area complexity of boolean functions.
In International Symposium on Low Power Electronics and Design, pages
329-334, Monterey, CA, August 12-14 1996.
- [3129]
- M. Nemani and F. N.
Najm.
Towards a high-level power estimation capability.
IEEE Transactions on Computer-Aided Design, 15(6):588-598, June
1996.
- [3130]
- M. Nemani and F. N.
Najm.
High-level area and power estimation for VLSI circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
114-119, San Jose, CA, November 9-13 1997.
- [3131]
- M. Nemani and F. N.
Najm.
High-level area prediction for power estimation.
In IEEE 1997 Custom Integrated Circuits Conference, pages 483-486,
Santa Clara, CA, May 5-8 1997.
- [3132]
- M. Nemani and F. N. Najm.
Delay estimation of VLSI circuits from a high-level view.
In IEEE/ACM 35th Design Automation Conference, pages 591-594, San
Francisco, CA, June 15-19 1998.
- [3133]
- M. Nemani and F. N. Najm.
High-level area and power estimation for VLSI circuits.
IEEE Transactions on Computer-Aided Design, 18(6):697-713, June
1999.
- [3134]
- M. Nemani and
V. Tiwari.
Macro-driven circuit design methodology for high-performance datapaths.
In Design Automation Conference, pages 661-666, Los Angeles, CA, June
5-9 2000.
- [3135]
- K. Nepal, R. I.
Bahar, B. J. Mundy, W. R. Patterson, and A. Zaslavsky.
Designing logic circuits for probabilistic computation in the presence of
noise.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
485-490, Anaheim, CA, June 13-17 2005.
- [3136]
- M. S. Nesro,
L. Sun, and I. M. Elfadel.
Compact modeling of microbatteries using behavioral linearization and
model-order reduction.
In 20th Asia and South Pacific Design Automation Conference, pages
713-718, Chiba/Tokyo, Japan, January 19-22 2015.
- [3137]
- A. R.
Newton and A. L. Sangiovanni-Vincentelli.
Relaxation-based electrical simulation.
IEEE Transactions on Electron Devices, ED-30(9):1184-1207, September
1983.
- [3138]
- A. R. Newton.
Timing, logic, and mixed-mode simulation for large MOS integrated circuits.
In P. Antognetti, D. O. Pederson, and H. De Man, editors, Computer design
aids for VLSI circuits, pages 175-239. Sijthoff & Noordhoff, Alphen
aan de Rijn, The Netherlands; Rockville, MD, USA, 1981.
- [3139]
- H.-T. Ng and D. J. Allstot.
CMOS current steering logic for low-voltage mixed-signal integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
5(3):301-308, September 1997.
- [3140]
- K. Ng.
Challenges in using system-level models for RTL verification.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
812-815, Anaheim, CA, June 8-13 2008.
- [3141]
- E. Ngoya,
J. Rousset, and J. J. Obregon.
Newton-raphson iteration speed-up algorithm for the solution of nonlinear
circuit equations in general-purpose CAD programs.
IEEE Transactions on Computer-Aided Design, 16(6):638-644, June
1997.
- [3142]
- T. Nguyen,
P. Feldmann, S. W. Director, and R. A. Rohrer.
SPECS simulation validation with efficient transient sensitivity.
In IEEE International Conference on Computer-Aided Design, pages
252-255, 1989.
- [3143]
- T. V. Nguyen,
A. Devgan, and A. Sadigh.
Simulation of coupling capacitances using matrix partitioning.
In IEEE/ACM International Conference on Computer-Aided Design, pages
12-18, San Jose, CA, November 8-12 1998.
- [3144]
- D. Nguyen,
A. Davare, M. Orshansky, D. Chinnery, B. Thompson, and K. Keutzer.
Minimization of dynamic and static power through joint assignment of threshold
voltages and sizing optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 158-163, Seoul, Korea, August 25-27 2003.
- [3145]
- T. V. Nguyen and J. Li.
Multipoint pade approximation using a rational block lanczos algorithm.
In IEEE/ACM International Conference on Computer-Aided Design, pages
72-75, San Jose, CA, November 9-13 1997.
- [3146]
- H. T. Nguyen and
Y. Yagil.
A systematic approach to SER estimation and solutions.
In International Reliability Physics Symposium (IRPS), pages 60-70,
Dallas, TX, March 30-April 4 2003.
- [3147]
- M. Ni and S. O. Memik.
Leakage power-aware clock skew scheduling: converting stolen time into leakage
power reduction.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
610-613, Anaheim, CA, June 8-13 2008.
- [3148]
- M. Ni and S. O. Memik.
A fast heuristic algorithm for multidomain clock skew scheduling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(4):630-637, April 2010.
- [3149]
- M. Nicolaidis, N. Achouri, and S. Boutobza.
Dynamic data-bit memory built-in self-repair.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 588-594, San Jose, CA, November 9-13 2003.
- [3150]
- Y.-T. Nieh, S.-H.
Huang, and S.-Y. Hsu.
Minimizing peak current via opposite-phase clock tree.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
182-185, Anaheim, CA, June 13-17 2005.
- [3151]
- M. Niemier,
M. Crocker, X.-S. Hu, and M. Lieberman.
Using CAD to shape experiments in molecular QCA.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 907-914, San Jose, CA, November 5-9 2006.
- [3152]
- M. T. Niemier,
X.-S. Hu, M. Alam, G. Bernstein, W. Porod, M. Putney, and J. DeAngelis.
Clocking structures and power analysis for nanomagnet-based logic devices.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 26-31, Portland, Oregon, August 27-29 2007.
- [3153]
- S. Nikolaidis, E. Karaolis, and E. D. Kyriakis-Bitzaros.
Estimation of signal transition activity in FIR filters implemented by a
MAC architecture.
IEEE Transactions on Computer-Aided Design, 19(1):164-169, January
2000.
- [3154]
- S. Nikolaidis and A. Chatzigeorgiou.
Modeling the transistor chain operation in CMOS gates for short channel
devices.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 46(10):1191-1202, October 1999.
- [3155]
- B. Nikolic,
J.-H. Park, J. Kwak, B. Giraud, Z. Guo, L.-T. Pang, S.-O. Toh, R. Jevtic,
K. Qian, and C. Spanos.
Technology variability from a design perspective.
IEEE Transactions on Circuits and Systems, 58(9):1996-2009, September
2011.
- [3156]
- L. Ning, T. T.
Georgiou, A. Tannenbaum, and S. P. Boyd.
Linear models based on noisy data and the frisch scheme.
SIAM Review, 57(2):167-197, June 2015.
- [3157]
- D. Niu, Y. Chen,
C. Xu, and Y. Xie.
Impact of process variations on emerging memristor.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
877-882, Anaheim, CA, June 13-18 2010.
- [3158]
- M. Nizam, F. N.
Najm, and A. Devgan.
Power grid voltage integrity verification.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 239-244, San Diego, CA, August 8-10 2005.
- [3159]
- V. Nookala,
Y. Chen, D. J. Lilja, and S. S. Sapatnekar.
Microarchitecture-aware floorplanning using a statistical design of experiments
approach.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
579-584, Anaheim, CA, June 13-17 2005.
- [3160]
- T. Nopper,
C. Scholl, and B. Becker.
Computation of minimal counterexamples by using black box techniques and
symbolic methods.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 273-280, San Jose, CA, November 5-8 2007.
- [3161]
- K. Nose, S.-I.
Chae, and T. Sakurai.
Voltage dependent gate capacitance and its impact in estimating power and delay
of CMOS digital circuits with low supply voltage.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 228-230, Italy, July 26-27 2000.
- [3162]
- K. Nose and T. Sakurai.
Analysis and future trend of short-circuit power.
IEEE Transactions on Computer-Aided Design, 19(9):1023-1030,
September 2000.
- [3163]
- W. Noth and R. Kolla.
Node normalization and decomposition in low power technology mapping.
In 1997 International Symposium on Low Power Electronics and Design,
pages 275-280, Monterey, CA, August 18-20 1997.
- [3164]
- B. Nouri, M. S.
Nakhla, and R. Achar.
Optimum order estimation of reduced macromodels based on a geometric approach
for projection-based MOR methods.
IEEE Transactions on Components, Packaging and Manufacturing
Technology, 3(7):1218-1227, July 2013.
- [3165]
- A. Nourivand, C. Wang, and M. O. Ahmad.
A VHDL-based technique for an accurate estimation of leakage power in digital
CMOS circuits.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 47-50, Quebec City, Quebec, June 19-22 2005.
- [3166]
- S. Novakovsky, S. Shyman, and Z. Hanna.
High capacity and automatic functional extraction tool for industrial VLSI
circuit designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 520-525, San Jose, CA, November 10-14 2002.
- [3167]
- M. Nowak and
R. Radojcic.
Are there economic benefits in DFM.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
767-768, Anaheim, CA, June 13-17 2005.
- [3168]
- N. NS, F. Cano,
H. Haznedar, and D. Young.
A practical approach to static signal electromigration analysis.
In IEEE/ACM 35th Design Automation Conference, pages 572-577, San
Francisco, CA, June 15-19 1998.
- [3169]
- N. NS, T. Bonifield,
A. Singh, C. Bittlestone, U. Narasimha, V. Le, and A. Hill.
BEOL variability and impact on RC extraction.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
758-759, Anaheim, CA, June 13-17 2005.
- [3170]
- J. Nyathi and B. Bero.
Logic circuits operating in subthreshold voltages.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 131-134, Tegernsee, Germany, October 4-6 2006.
- [3171]
- K. K. O, K. Kim, B. Floyd,
J. Mehta, H. Yoon, C.-M. Hung, D. Bravo, T. Dickson, X. Guo, R. Li,
N. Trichy, J. Caserta, W. Bomstad, J. Branch, D.-J. Yang, J. Bohorquez,
J. Chen, E.-Y. Seok, L. Gao, A. Sugavanam, J.-J. Lin, S. Yu, C. Cao, M.-H.
Hwang, Y.-P. Ding, S.-H. Hwang, H. Wu, N. Zhang, and J. E. Brewer.
The feasibility of on-chip interconnection using antennas.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 979-984, San Jose, CA, November 6-10 2005.
- [3172]
- J. Oberg, W. Hu,
A. Irturk, M. Tiwari, T. Sherwood, and R. Kastner.
Theoretical analysis of gate level information flow tracking.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
244-247, Anaheim, CA, June 13-18 2010.
- [3173]
- P. R. O'Brien and
T. L. Savarino.
Modeling the driving-point characteristic of resistive interconnect for
accurate delay estimation.
In IEEE International Conference on Computer-Aided Design, pages
512-515, 1989.
- [3174]
- I. O'Connor,
J. Liu, F. Gaffiot, F. Pregaldiny, C. Lallement, C. Maneux, J. Goguet,
F. Fegonese, T. Zimmer, L. Anghel, T.-T. Dang, and R. Leveugle.
CNTFET modeling and reconfigurable logic-circuit design.
IEEE Transactions on Circuits and Systems, 54(11):2365-2379, November
2007.
- [3175]
- A. Odabasioglu, M. Celik, and L. Pileggi.
PRIMA: passive reduced-order interconnect macromodeling algorithm.
In IEEE/ACM International Conference on Computer-Aided Design, pages
58-65, San Jose, CA, November 9-13 1997.
- [3176]
- A. Odabasioglu, M. Celik, and L. T. Pileggi.
PRIMA: Passive reduced-order interconnect macromodeling algorithm.
IEEE Transactions on Computer-Aided Design, 17(8):645-654, August
1998.
- [3177]
- A. Odabasioglu, M. Celik, and L. T. Pileggi.
Practical considerations for passive reduction of RLC circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
214-219, San Jose, CA, November 7-11 1999.
- [3178]
- K. O'Donoghue, M. P. Kennedy, and P. Forbes.
A fast and simple implementation of chua's oscillator using a "cube-like" chua
diode.
In European Conference on Circuit Theory and Design (ECCTD), pages
II.83-II.86, Cork, Ireland, August 29 - September 2 2005.
- [3179]
- Y. Ogasahara, M. Hashimoto, T. Kanamoto, and T. Onoye.
Supply noise suppression by triple-well structure.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(4):781-785, April 2013.
- [3180]
- U. Y. Ogras,
R. Marculescu, and D. Marculescu.
Variation-adaptive feedback control for networks-on-chip with multiple clock
domains.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
614-619, Anaheim, CA, June 8-13 2008.
- [3181]
- C. Oh, D. Blaauw,
M. Becer, V. Zolotov, R. Panda, and A. Dasgupta.
Static electromigration analysis for signal interconnects.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 377-382, San Jose, CA, March 24-26 2003.
- [3182]
- K.-I. Oh and L.-S. Kim.
A clock delayed sleep mode domino logic for wide dynamic OR gate.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 176-179, Seoul, Korea, August 25-27 2003.
- [3183]
- N. Ohba and K. Takano.
An soc design methodology using fpgas and embedded microprocessors.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
747-752, San Diego, CA, June 7-11 2004.
- [3184]
- M. Ohlrich,
C. Ebeling, E. Ginting, and L. Sather.
Subgemini: Identifying subcircuits using a fast subgraph isomorphism algorithm.
In 30th ACM/IEEE Design Automation Conference, pages 31-37, Dallas,
Texas, June 14-18 1993.
- [3185]
- S. Y. Ohm, F. J.
Kurdahi, and N. D. Dutt.
A unified lower bound estimation technique for high-level synthesis.
IEEE Transactions on Computer-Aided Design, 16(5):458-472, May
1997.
- [3186]
- M. Ohnishi,
A. Yamada, H. Noda, and T. Kambe.
A method of redundant clocking and power reduction at RT level design.
In 1997 International Symposium on Low Power Electronics and Design,
pages 131-136, Monterey, CA, August 18-20 1997.
- [3187]
- K. Okada,
K. Yamaoka, and H. Onodera.
A statistical gate-delay model considering intra-gate variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 908-913, San Jose, CA, November 9-13 2003.
- [3188]
- V. G.
Oklobdzija, B. R. Zeydel, H. O. Dao, S. Mathew, and R. Krishnamurthy.
Comparison of high-performance VLSI adders in the energy-delay space.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):754-758, June 2005.
- [3189]
- V. G.
Oklobdzija and P. G. Kovijanic.
On testability of CMOS-domino logic.
In IEEE 14th International Symposium on Fault-Tolerant Computing,
pages 50-55, Kissimee, FL, June 20-22 1984.
- [3190]
- S. W. Oldridge and
S. J. E. Wilton.
A novel FPGA architecture supporting wide, shallow memories.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):758-762, June 2005.
- [3191]
- M. Olivieri,
F. Pappalardo, and G. Visalli.
Bus-switch coding for reducing power dissipation in off-chip buses.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1374-1377, December 2004.
- [3192]
- M. Olivieri,
G. Scotti, and A. Trifiletti.
A novel yield optimization technique for digital CMOS circuits design by
means of process parameters run-time estimation and body bias active control.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(5):630-638, May 2005.
- [3193]
- M. Olivieri.
Theoretical system-level limits of power dissipation reduction under a
performance constraint in VLSI microprocessor design.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):595-600, October 2002.
- [3194]
- E. Olson and S. M. Kang.
Low-power state assignment for finite state machines.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
63-68, Napa, CA, April 24-27 1994.
- [3195]
- E. Olson and S. M. Kang.
State assignment for low-power FSM synthesis using genetic local search.
In IEEE 1994 Custom Integrated Circuit Conference, pages 140-143, San
Diego, CA, May 1-4 1994.
- [3196]
- F. O'Mahony,
C. P. Yue, M. A. Horowitz, and S. S. Wong.
Design of a 10ghz clock distribution network using coupled standing-wave
oscillators.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
682-687, Anaheim, CA, June 2-6 2003.
- [3197]
- O. Omedes,
M. Robert, and M. Ramdani.
A flexibility aware budgeting for hierarchical flow timing closure.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 261-266, San Jose, CA, November 7-11 2004.
- [3198]
- S. Onaissi,
K. R. Heloue, and F. N. Najm.
Clock skew optimization via wiresizing for timing sign-off covering all process
corners.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
196-201, San Francisco, CA, July 26-31 2009.
- [3199]
- S. Onaissi,
K. R. Heloue, and F. N. Najm.
PSTA-based branch and bound approach to the silicon speedpath isolation
problem.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 217-224, San Jose, CA, November 2-5 2009.
- [3200]
- S. Onaissi,
F. Taraporevala, J. Liu, and F. N. Najm.
A fast approach for static timing analysis covering all PVT corners.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
777-782, San Diego, CA, June 5-9 2011.
- [3201]
- S. Onaissi and F. N.
Najm.
A linear-time approach for static timing analysis covering all process corners.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 217-224, San Jose, CA, November 5-9 2006.
- [3202]
- S. Onaissi and F. N.
Najm.
A linear-time approach for static timing analysis covering all process corners.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(7):1291-1304, July 2008.
- [3203]
- Z.-Z. Oo, X.-C. Wei,
E.-X. Liu, E.-P. Li, and L.-W. Li.
Efficient analysis for multilayer power-ground planes with multiple vias and
signal traces in an advanced electronic package.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 95-98, San Jose, CA, October 27-29 2008.
- [3204]
- M. Oppeneer,
P. Sumant, and A. C. Cangellaris.
Robust iterative finite element solver for multi-terminal power distribution
network resistance extraction.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 181-184, San Jose, CA, October 27-29 2008.
- [3205]
- M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu.
Impact of systematic spatial intra-chip gate length variability on performance
of high-speed digital circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 62-67, San Jose, CA, November 5-9 2000.
- [3206]
- M. Orshansky, L. Milor, P. Chen, K. Keutzer, and C. Hu.
Impact of spatial intrachip gate length variability on the performance of
high-speed digital circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(5):544-553, May 2002.
- [3207]
- M. Orshansky, L. Milor, and C. Hu.
Characterization of spatial intrafield gate CD variability, its impact on
circuit performance, and spatial mask-level correction.
IEEE Transactions on Semiconductor Manufacturing, 17(1):2-11,
February 2004.
- [3208]
- M. Orshansky and A. Bandyopadhyay.
Fast statistical timing analysis handling arbitrary delay correlations.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
337-342, San Diego, CA, June 7-11 2004.
- [3209]
- M. Orshansky and
K. Keutzer.
A general probabilistic framework for worst case timing analysis.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
556-561, New Orleans, LA, June 10-14 2002.
- [3210]
- Ortega and
Rheinboldt.
Iterative Solutions of Non-Linear Equations in Several Variables.
Academic Press, New York, NY, 1970.
- [3211]
- J. M. Ortega.
Matrix Theory, A Second Course.
Plenum Press, New York, NY, 1987.
- [3212]
- R. R. Ortiz and J. P.
Knight.
Compatible cell connections for multifamily dynamic logic gates.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):327-340, June 2002.
- [3213]
- R. H. J. M. Otten and
R. K. Brayton.
Planning for performance.
In IEEE/ACM 35th Design Automation Conference, pages 122-127, San
Francisco, CA, June 15-19 1998.
- [3214]
- R. H. J. M. Otten and
P. Sravers.
Challenges in physical chip design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 84-91, San Jose, CA, November 5-9 2000.
- [3215]
- R. H. J. M. Otten.
Global wires harmful?
In ACM/IEEE International Symposium on Physical Design, pages
104-109, Monterey, CA, April 6-8 1998.
- [3216]
- R. J. M. Otten.
What is a floorplan?
In International Symposium on Physical Design, pages 201-206, San
Diego, CA, April 9-12 2000.
- [3217]
- H.-C. Ou, H.-C. Chang
Chien, and Y.-W. Chang.
Simultaneous analog placement and routing with current flow and current density
considerations.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [3218]
- J. K. Ousterhout.
Crystal: A timing analyzer for nmos VLSI circuits.
In 3rd Caltech Conference on VLSI, pages 57-69, 1983.
- [3219]
- J. K. Ousterhout.
Switch-level delay models for digital MOS VLSI.
In IEEE 21st Design Automation Conference, pages 542-548,
Albuquerque, NM, June 24-27 1984.
- [3220]
- J. K. Ousterhout.
A switch-level timing verifier for digital MOS VLSI.
IEEE Transactions on Computer-Aided Design, CAD-4(3):336-349, July
1985.
- [3221]
- D. Overhauser, J. R. Lloyd, S. Rochel, G. Steele, and S. Z.
Hussain.
Full-chip reliability analysis.
Microelectronics Reliability, 38:851-859, 1998.
- [3222]
- D. Overhauser and
I. Hajj.
Multi-level circuit partitioning for switch-level timing simulation.
In IEEE International Symposium on Circuits and Systems, pages
1361-1364, 1988.
- [3223]
- D. Overhauser and
I. Hajj.
Feedback processing in fast timing simulation on a multiprocessor system.
In 32nd Midwest Symposium on Circuit and Systems, pages 466-469,
August 1989.
- [3224]
- D. Overhauser
and R. Saleh.
Evaluating mixed-signal simulators.
In IEEE Custom Integrated Circuits Conference, pages 113-120, Santa
Clara, CA, May 1-4 1995.
- [3225]
- H. Owhadi,
C. Scovel, and T. Sullivan.
On the brittleness of bayesian inference.
SIAM Review, 57(4):566-582, December 2015.
- [3226]
- D. Oyaro and
P. Triverio.
Turbomor-RC: an efficient model order reduction technique for RC networks
with many ports.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(10):1695-1706, October 2016.
- [3227]
- M. M. Ozdal,
S. Burns, and J. Hu.
Gate sizing and device technology selection algorithms for high performance
industrial designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 724-731, San Jose, CA, November 7-10 2011.
- [3228]
- S. Ozoguz and S. Ergun.
A non-autonomous IC chaotic oscillator and its application for random bit
generation.
In European Conference on Circuit Theory and Design (ECCTD), pages
II.165-II.168, Cork, Ireland, August 29 - September 2 2005.
- [3229]
- A. Pacelli.
A local circuit topology for inductive parasitics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 208-214, San Jose, CA, November 10-14 2002.
- [3230]
- C. Pacha, U. Auer,
C. Burwick, P. Glosekotter, A. Brennemann, W. Prost, F. J. Tegude, and K. F.
Goser.
Threshold logic circuit design of parallel adders using resonant tunneling
devices.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(5):558-572, October 2000.
- [3231]
- S. Padmanaban and S. Tragoudas.
Efficient identification of (critical) testable path delay faults using
decision diagrams.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):77-87, January 2005.
- [3232]
- U. Padmanabhan, J. M. Wang, and J. Hu.
Robust clock tree routing in the presence of process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(8):1385-1397, August 2008.
- [3233]
- S. Paek, S.-H. Moon,
W. Shin, J. Sim, and L.-S. Kim.
Powerfield: a transient temperature-to-power technique based on markov random
field theory.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
630-635, San Francisco, CA, June 3-7 2012.
- [3234]
- S. Paek, W. Shin,
J. Sim, and L.-S. Kim.
Powerfield: a probabilistic approach for temperature-to-power conversion based
on markov random field theory.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1509-1519, October 2013.
- [3235]
- S. Pagani, J. J.
Chen, and J. Henkel.
Energy and peak power efficiency analysis for the single voltage approximation
(SVA) scheme.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(9):1415-1428, September 2015.
- [3236]
- S. Paik and Y. Shin.
Multiobjective optimization of sleep vector for zigzag power-gated circuits in
standard cell elements.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
600-605, Anaheim, CA, June 8-13 2008.
- [3237]
- J. Pak, S.-K Lim, and
D. Z. Pan.
Electromigration-aware routing for 3d ics with stress-aware EM modeling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 325-332, San Jose, CA, November 5-8 2012.
- [3238]
- J. Pak, S.-K. Lim, and
D.-Z. Pan.
Electromigration study for multi-scale power/ground vias in TSV-based 3d ics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 379-386, San Jose, CA, November 18-21 2013.
- [3239]
- J. Pak, S. K. Lim, and
D. Z. Pan.
Electromigration study for multiscale power/ground vias in TSV-based 3-D
ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(12):1873-1885, December 2014.
- [3240]
- J. Pak, B. Yu, and
D.-Z. Pan.
Electromigration-aware redundant via insertion.
In 20th Asia and South Pacific Design Automation Conference, pages
544-549, Chiba/Tokyo, Japan, January 19-22 2015.
- [3241]
- E. Pakbaznia, F. Fallah, and M. Pedram.
Charge recycling in MTCMOS circuits: concept and analysis.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 97-102,
San Francisco, CA, July 24-28 2006.
- [3242]
- E. Pakbaznia, F. Fallah, and M. Pedram.
Sizing and placement of charge recycling transistor in MTCMOS circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 791-796, San Jose, CA, November 5-8 2007.
- [3243]
- E. Pakbaznia, F. Fallah, and M. Pedram.
Charge recylcing in power-gated CMOS circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1798-1811, October 2008.
- [3244]
- K. Palem and
A. Lingamneni.
What to do about the end of moore's law, probably!
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
924-929, San Francisco, CA, June 3-7 2012.
- [3245]
- G. A.
Paleologo, L. Benini, A. Bogliolo, and G. De Micheli.
Policy optimization for dynamic power management.
In IEEE/ACM 35th Design Automation Conference, pages 182-187, San
Francisco, CA, June 15-19 1998.
- [3246]
- I. Palit, Q. Lou,
N. Acampora, J. Nahas, M. Niemier, and X.-S. Hu.
Analytically modeling power and performance of a CNN system.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 186-193, Austin TX, November 2-6 2015.
- [3247]
- M. Palla,
J. Bargfrede, S. Eggersglus, W. Anheier, and R. Drechsler.
Timing arc based logic analysis for false noise reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 225-230, San Jose, CA, November 2-5 2009.
- [3248]
- G. Palumbo,
D. Pappalardo, and M. Gaibotti.
Charge-pump circuits: power consumption optimization.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(11):1535-1542, November 2002.
- [3249]
- G. Palumbo,
M. Pennisi, and M. Alioto.
A simple circuit approach to reduce delay variatons in domino logic gates.
IEEE Transactions on Circuits and Systems, 59(10):2292-2300, October
2012.
- [3250]
- G. Palumbo and M. Poli.
Propagation delay model of a current driven RC chain for an optimized design.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(4):572-575, April 2003.
- [3251]
- D. Pamunuwa, S. Elassaad, and H. Tenhunen.
Analytic modeling of interconnects for deep sub-micron circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 835-842, San Jose, CA, November 9-13 2003.
- [3252]
- D. Pamunuwa, L.-R. Zheng, and H. Tenhunen.
Maximizing throughput over parallel wire structures in the deep submicrometer
regime.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(2):224-243, April 2003.
- [3253]
- D. Pamunuwa,
S. Elassaad, and H. Tenhunen.
Modeling delay and noise in arbitrarily coupled RC trees.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(11):1725-1739, November 2005.
- [3254]
- Z. Pan, Y. Cai,
S. X.-D. Tan, Z. Luo, and X. Hong.
Transient analysis of on-chip power distribution networks using equivalent
circuit modeling.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 63-68, San Jose, CA, March 22-24 2004.
- [3255]
- D.-Z. Pan, B. Yu, and
J.-R. Gao.
Design for manufacturing with emerging nanolithography.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1453-1472, October 2013.
- [3256]
- D. Z. Pan and M. D.-F. Wong.
Manufacturability-aware physical layout optimizations.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 149-153, Austin, TX, May 9 - 11 2005.
- [3257]
- R. Panda,
A. Dharchoudhury, T. Edwards, J. Norton, and D. Blaauw.
Migration: A new technique to improve synthesized designs through incremental
customization.
In IEEE/ACM 35th Design Automation Conference, pages 388-391, San
Francisco, CA, June 15-19 1998.
- [3258]
- R. Panda,
D. Blaauw, R. Chaudhry, V. Zolotov, B. Young, and R. Ramaraju.
Model and analysis for combined package and on-chip power grid simulation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 179-184, Italy, July 26-27 2000.
- [3259]
- R. Panda,
S. Sundareswaran, and D. Blaauw.
On the interaction of power distribution network with substrate.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 388-393, Huntington Beach, California, August 6-7
2001.
- [3260]
- R. Panda,
S. Sundareswaran, and D. Blaauw.
Impact of low-impedance substrate on power supply integrity.
IEEE Design & Test of Computers, pages 16-22, May-June 2003.
- [3261]
- P. R. Panda and N. D. Dutt.
Low-power memory mapping through reducing address bus activity.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(3):309-320, September 1999.
- [3262]
- R. Panda and F. N. Najm.
Technology decomposition for low-power synthesis.
In IEEE Custom Integrated Circuits Conference, pages 627-630, Santa
Clara, CA, May 1-4 1995.
- [3263]
- R. Panda and F. N. Najm.
Technology-dependent transformations for low-power synthesis.
In 34th Design Automation Conference, pages 650-655, Anaheim, CA,
June 9-13 1997.
- [3264]
- P. P. Pande, R.-G.
Kim, W. Choi, Z. Chen, D. Marculescu, and R. Marculescu.
The (low) power of less wiring: enabling energy efficiency in many-core
platforms through wireless noc.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 165-169, Austin TX, November 2-6 2015.
- [3265]
- V. S. Pandit and W.-H.
Ryu.
Mutli-GHZ modeling and characterization of on-chip power delivery network.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 115-118, San Jose, CA, October 27-29 2008.
- [3266]
- Y. Pang and K. Radecka.
Optimizing imprecise fixed-point arithmetic circuits specified by taylor series
through arithmetic transform.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
397-402, Anaheim, CA, June 8-13 2008.
- [3267]
- J. Pangjun and
S. S. Sapatnekar.
Low-power clock distribution using multiple voltages and reduced swings.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):309-318, June 2002.
- [3268]
- B. M. Pangrle.
On the complexity of connectivity binding.
IEEE Transactions on Computer-Aided Design, 10(11):1460-1465,
November 1991.
- [3269]
- P. Pant, V. De, and
A. Chatterjee.
Device-circuit optimization for minimal energy and power consumption in CMOS
random logic networks.
In 34th Design Automation Conference, pages 403-408, Anaheim, CA,
June 9-13 1997.
- [3270]
- P. Pant, V. K. De,
and A. Chatterjee.
Simultaneous power supply, threshold voltage, and transistor size optimization
for low-power operation of CMOS circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(4):538-545, December 1998.
- [3271]
- P. Pant, R. K. Roy,
and A. Chatterjee.
Dual-threshold voltage assignment with transistor sizing for low power CMOS
circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(2):390-394, April 2001.
- [3272]
- M. D. Pant, P. Pant,
and D. S. Wills.
On-chip decoupling capacitor optimization using architectural level prediction.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):319-326, June 2002.
- [3273]
- S. Pant, D. Blaauw,
V. Zolotov, S. Sundareswaran, and R. Panda.
Vectorless analysis of supply noise induced delay variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 184-191, San Jose, CA, November 9-13 2003.
- [3274]
- S. Pant, D. Blaauw,
V. Zolotov, S. Sundareswaran, and R. Panda.
A stochastic approach to power grid analysis.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
171-176, San Diego, CA, June 7-11 2004.
- [3275]
- S. Pant and D. Blaauw.
Static timing anaylsis considering power supply variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 365-371, San Jose, CA, November 6-10 2005.
- [3276]
- S. Pant and E. Chiprout.
Power grid physics and implications for CAD.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
199-204, San Francisco, CA, July 24-28 2006.
- [3277]
- S. Panth,
K. Samadi, Y. Du, and S.-K. Lim.
Tier-partitioning for power delivery vs cooling tradeoff in 3d VLSI for
mobile applications.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [3278]
- H. Panzer,
T. Wolf, and B. Lohmann.
A strictly dissipative state space representation of second order systems.
Automatisierungstechnik, 60(12):392-396, July 2012.
- [3279]
- C. Papachristou, M. Spinning, and M. Nourani.
An effective power management scheme for RTL design.
In 33rd Design Automation Conference, pages 337-342, Las Vegas, NV,
June 3-7 1996.
- [3280]
- C. A. Papachristou, M. Nourani, and M. Spining.
A multiple clocking scheme for low-power RTL design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
7(2):266-276, June 1999.
- [3281]
- E. Papadopoulou.
Net-aware critical area extraction for opens in VLSI circuits via
higher-order voronoi diagrams.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(5):704-717, May 2011.
- [3282]
- M. C.
Papaefthymiou and K. H. Randall.
TIM: A timing package for two-phase, level-clocked circuitry.
In ACM/IEEE Design Automation Conference, pages 497-502, 1993.
- [3283]
- A. Papoulis and
S. U. Pillai.
Probability, Random Variables, and Stochastic Processes.
McGraw-Hill, Boston, MA, 4th edition, 2002.
- [3284]
- Athanasios Papoulis.
The Fourier Integral and its Applications.
McGraw-Hill Book Company, Inc., 1962.
- [3285]
- A. Papoulis.
Probability, Random Variables, and Stochastic Processes.
McGraw-Hill, Inc., New York, NY, 2nd edition, 1984.
- [3286]
- K. Parashar,
D. Menard, R. Rocher, O. Sentieys, D. Novo, and F. Catthoor.
Fast performance evaluation of fixed-point systems with un-smooth operators.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 9-16, San Jose, CA, November 7-11 2010.
- [3287]
- K. N.
Parashar, D. Menard, and O. Sentieys.
A polynomial time algorithm for solving the word-length optimization problem.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 638-645, San Jose, CA, November 18-21 2013.
- [3288]
- A. Pardo, R. I.
Bahar, S. Manne, P. Feldmann, G. D. Hachtel, and F. Somenzi.
CMOS dynamic power estimation based on collapsible current source transistor
modeling.
In ACM/IEEE International Symposium on Low Power Design, pages
111-116, Dana Point, CA, April 23-26 1995.
- [3289]
- S. Park,
A. Savvides, and M. Srivastava.
Battery capacity measurement and analysis using lithium coin cell battery.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 382-387, Huntington Beach, California, August 6-7
2001.
- [3290]
- J. Park,
K. Muhammad, and K. Roy.
Efficient modeling of 1/fa noise using multirate process.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1247-1256, July 2006.
- [3291]
- S. Park,
A. Shrivastava, N. Dutt, A. Nicolau, Y. Paek, and E. Earlie.
Register file power reducing using bypass sensitive compiler.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(6):1155-1159, June 2008.
- [3292]
- Y.-J. Park, P. Jain,
and S. Krishnan.
New electromigration validation: via node vector method.
In 2010 IEEE International Reliability Physics Symposium (IRPS), pages
698-704, Anaheim, CA, May 2-6 2010.
- [3293]
- S.-Y. Park and N.-I. Cho.
Fixed-point error analysis of CORDIC processor based on the variance
propagation formula.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(3):573-583, March 2004.
- [3294]
- K. P. Parker and
E. J. McCluskey.
Probabilistic treatment of general combinational networks.
IEEE Transactions on Computers, C-24:668-670, June 1975.
- [3295]
- D. Stott Parker, Jr.
Conditions for the optimality of the huffman algorithm.
SIAM Journal on Computing, 9(3):470-488, August 1980.
- [3296]
- J. Parkhurst, N. Sherwani, S. Maturi, D. Ahrams, and
E. Chiprout.
SRC physical design top ten problems.
In 1999 International Symposium on Physical Design, pages 55-58,
Monterey, CA, April 12-14 1999.
- [3297]
- J. Parkhurst, J. Darringer, and B. Grundmann.
From single core to multi-core: preparing for a new exponential.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 67-72, San Jose, CA, November 5-9 2006.
- [3298]
- S. Parter.
The use of linear graphs in gauss elimination.
SIAM Review, 3(2):119-130, April 1961.
- [3299]
- G. Parthasarathy, M. K. Iyer, K.-T. Cheng, and F. Brewer.
RTL SAT simplification by boolean and interval arithmetic reasoning.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 297-302, San Jose, CA, November 6-10 2005.
- [3300]
- E. Pastor and
J. Cortadella.
Polynomial algorithms for the synthesis of hazard-free circuits from signal
transition graphs.
In IEEE/ACM International Conference on Computer-Aided Design, pages
250-254, Santa Clara, CA, November 7-11 1993.
- [3301]
- K. Patel, W. Lee,
and M. Pedram.
Minimizing power dissipation during write operation to register files.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 183-188, Portland, Oregon, August 27-29 2007.
- [3302]
- K. N. Patel and I. L.
Markov.
Error-correction and crosstalk avoidance in DSM busses.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1076-1080, October 2004.
- [3303]
- M. Pathak,
J. Pak, D.-Z. Pan, and S.-K. Lim.
Electromigration modeling and full-chip reliability analysis for BEOL
interconnect in TSV-based 3dics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 555-562, San Jose, CA, November 7-10 2011.
- [3304]
- N. Patil, J. Deng,
H.-S. P. Wong, and S. Mitra.
Automated design of misaligned-carbon-nanotube-immune circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
958-961, San Diego, CA, June 4-8 2007.
- [3305]
- N. Patil, A. Lin,
J. Zhang, H.-S. P. Wong, and S. Mitra.
Digital VLSI logic technology using carbon nanotube fets: frequently asked
questions.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
304-309, San Francisco, CA, July 26-31 2009.
- [3306]
- P. Patra and
U. Narayanan.
Automated phase assignment for the synthesis of low power domino circuits.
In Design Automation Conference, pages 379-384, New Orleans, LA, June
21-25 1999.
- [3307]
- R. Patti.
3d integrated circuits: designing in a new dimension.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 274, San Jose, CA, November 5-8 2012.
- [3308]
- B. C. Paul, K. Kang,
H. Kufluoglu, M. A. Alam, and K. Roy.
Negative bias temperature instability: estimation and design for improved
reliability of nanoscale circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):743-751, April 2007.
- [3309]
- D. Paul, N. M.
Nakhla, R. Achar, and M. S. Nakhla.
Parallel algorithm for analysis of high-speed interconnects.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 191-194, San Jose, CA, October 27-29 2008.
- [3310]
- D. Paul, M. S.
Nakhla, R. Achar, and N. M. Nakhla.
Parallel circuit simulation via binary link formulations (pvb).
IEEE Transactions on Components, Packaging and Manufacturing
Technology, 3(5):768-782, May 2013.
- [3311]
- D. Paul, R. Achar,
M. S. Nakhla, and N. M. Nakhla.
Addressing partitioning issues in parallel circuit simulation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(12):2713-2723, December 2014.
- [3312]
- P. Pavan,
L. Larcher, M. Cuozzo, P. Zuliani, and A. Conte.
A complete model of e2prom memory cells for circuit simulations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(8):1072-1079, August 2003.
- [3313]
- A. Peano,
L. Ramini, M. Gavanelli, M. Nonato, and D. Bertozzi.
Design technology for fault-free and maximally-parallel wavelength-routed
optical networks-on-chip.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [3314]
- M. Pecht, F. R.
Nash, and J. H. Lory.
Understanding and solving the real reliability assurance problems.
In Annual Reliability and Maintainability Symposium, pages 159-161,
Washington, DC, January 16-19 1995.
- [3315]
- M. G. Pecht and F. R. Nash.
Predicting the reliability of electronic equipment.
In Proceedings of the IEEE, pages 990-1004, July 1994.
Published as Proceedings of the IEEE, volume 82, number 7.
- [3316]
- D. O. Pederson.
A historical review of circuit simulation.
IEEE Transactions on Circuits and Systems, CAS-31(1):103-111, January
1984.
- [3317]
- M. Pedram,
R. Bushroe, R. Camposano, G. De Micheli, A. Domic, C-P Hsu, and M. Jackson.
Panel: physical design and synthesis: merge or die!
In 34th Design Automation Conference, pages 238-239, Anaheim, CA,
June 9-13 1997.
- [3318]
- M. Pedram and B. T.
Preas.
Interconnection analysis for standard cell layouts.
IEEE Transactions on Computer-Aided Design, 18(10):1512-1519, October
1999.
- [3319]
- M. Pedram and Q. Wu.
Design considerations for battery-powered electronics.
In Design Automation Conference, pages 861-866, New Orleans, LA, June
21-25 1999.
- [3320]
- M. Pedram and Q. Wu.
Battery-powered digital CMOS design.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(5):601-607, October 2002.
- [3321]
- M. Pedram.
Power minimization in IC design: principles and applications.
ACM Transactions on Design Automation of Electronic Systems,
1(1):3-56, January 1996.
- [3322]
- M. Pedram.
Energy-efficient datacenters.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(10):1465-1484, October 2012.
- [3323]
- A. Peiravi and
M. Asyaei.
Current-comparison-based domino: new low-leakage high-speed domino circuit for
wide fan-in gates.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(5):934-943, May 2013.
- [3324]
- M. J. M.
Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers.
Matching properties of MOS transistors.
IEEE Journal of Solid-State Circuits, 24(5):1433-1440, October
1989.
- [3325]
- P. Penfield,
Jr. and J. Rubinstein.
Signal delay in RC tree networks.
In IEEE 18th Design Automation Conference, pages 613-617, 1981.
- [3326]
- H. Peng, K. Rouz,
M. Borah, and C.-K. Cheng.
Parallel full-chip transient simulation at transistor level.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 239-242, San Jose, CA, October 27-29 2008.
- [3327]
- H.-K. Peng, C. H.-P.
Wen, and J. Bhadra.
On soft error rate analysis of scaled CMOS designs - a statistical
perspective.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 157-163, San Jose, CA, November 2-5 2009.
- [3328]
- Y. Peng, B.-W. Ku,
Y. Park, K.-I. Park, S.-J. Jang, J.-S. Choi, and S.-K. Lim.
Design, packaging, and architectural policy co-optimization for DC power
integrity in 3d DRAM.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [3329]
- Y. Peng and X. Liu.
An efficient low-power repeater-insertion scheme.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2726-2736, December 2006.
- [3330]
- C. S. Petrie and
J. A. Connelly.
A noise-based IC random number generator for applications in cryptography.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 47(5):615-621, May 2000.
- [3331]
- P. Petrov and
A. Orailoglu.
Low-power insturction bus encoding for embedded processors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(8):812-826, August 2004.
- [3332]
- O. Peyran,
Z. Zeng, and W. Zhuang.
Area optimization of delay-optimized sturctures using intrinsic constraint
graphs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):888-906, June 2004.
- [3333]
- T. Pfingsten, D. J. L. Herrmann, and C. E. Rasmussen.
Model-based design analysis and yield optimization.
IEEE Transactions on Semiconductor Manufacturing, 19(4):475-486,
November 2006.
- [3334]
- J. Phillips,
L. Daniel, and L. Miguel Silveira.
Guaranteed passive balancing transformations for model order reduction.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages 52-57,
New Orleans, LA, June 10-14 2002.
- [3335]
- J. R.
Phillips, L. Daniel, and L. M. Silveira.
Guaranteed passive balancing transformations for model order reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(8):1027-1041, August 2003.
- [3336]
- J. R. Phillips
and L. M. Silveira.
Poor man's TBR: a simple model reduction scheme.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):43-55, January 2005.
- [3337]
- J. R. Phillips.
Variational interconnect analysis via PMTBR.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 872-879, San Jose, CA, November 7-11 2004.
- [3338]
- M. W. Phyu, K. Fu,
W.-L. Goh, and K.-S. Yeo.
Power-efficient explicit-pulsed dual-edge triggered sense-amplifier flip-flops.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(1):1-9, January 2011.
- [3339]
- C. Piguet, J.-M.
Masgonty, S. Cserveny, C. Arm, and P.-D. Pfister.
Low-power low-voltage library cells and memories.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 1521-1524, St. Julian, Malta, September 2-5 2001.
- [3340]
- C. Piguet,
C. Schuster, and J.-L. Nagel.
Optimizing architecture activity and logic depth for static and dynamic power
reduction.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 41-44, Montreal, Quebec, June 20-23 2004.
- [3341]
- L. Pileggi,
H. Schmit, A. J. Strojwas, P. Gopalakrishnan, V. Kheterpal, A. Koorapaty,
C. Patel, V. Rovner, and K. Y. Tong.
Exploring regular fabrics to optimize the performance cost trade-off.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
782-787, Anaheim, CA, June 2-6 2003.
- [3342]
- L. Pileggi.
Coping with RC(L) interconnect design headaches.
In IEEE/ACM International Conference on Computer-Aided Design, pages
246-253, San Jose, CA, November 5-9 1995.
- [3343]
- L. Pileggi.
Timing metrics for physical design of deep submicron technologies.
In ACM/IEEE International Symposium on Physical Design, pages 28-33,
Monterey, CA, April 6-8 1998.
- [3344]
- L. Pileggi.
Timing metrics for physical design of deep submicron technologies.
In International Symposium on Physical Design, pages 28-33, Monterey,
CA, 1998.
- [3345]
- L. Pileggi.
Achieving timing closure for giga-scale IC designs.
In ACM/IEEE 1999 International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU-99), pages 25-28,
Monterey, CA, March 8-9 1999.
- [3346]
- L. Pillage,
X. Huang, and R. Rohrer.
Asymptotic waveform evaluation for circuits containing floating nodes.
In IEEE International Symposium on Circuits and Systems, pages
613-616, 1990.
- [3347]
- L. T. Pillage and
R. A. Rohrer.
Asymptotic waveform evaluation for timing analysis.
IEEE Transactions on Computer-Aided Design, 9(4):352-366, April
1990.
- [3348]
- J. C. G.
Pimentel, E. Gad, and S. Roy.
High-order A-stable and L-stable state-space discrete modeling of
continuous systems.
IEEE Transactions on Circuits and Systems, 59(2):346-359, February
2012.
- [3349]
- A. Pinar and C. L. Liu.
Power invariant vector sequence compaction.
In IEEE/ACM International Conference on Computer-Aided Design, pages
473-476, San Jose, CA, November 8-12 1998.
- [3350]
- R. Pino, H. Li,
Y. Chen, M. Hu, and B. Liu.
Statistical memristor modeling and case study in neuromorphic computing.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
585-590, San Francisco, CA, June 3-7 2012.
- [3351]
- N. Pippenger.
Information theory and the complexity of boolean functions.
Mathematical Systems Theory, 10:129-167, 1977.
- [3352]
- Sergio Pissanetsky.
Sparse Matrix Technology.
Academic Press Inc., Orlando, FL, 1984.
- [3353]
- G. Poddar,
K. Chakrabarty, and S. Banerjee.
Control of chaos in DC-DC converters.
IEEE Transactions on Circuits and Systems - I: Fundamental Theory and
Applications, 45(6):672-676, June 1998.
- [3354]
- R. Pokala.
Thermal analysis in SPICE.
In IEEE International Conference on Computer-Aided Design, pages
256-259, 1989.
- [3355]
- F. J. Pollack.
New microarchitecture challenges in the coming generations of CMOS process
technologies.
In ACM/IEEE 32nd Annual International Symposium on Microarchitecture
(MICRO-32), page 2, Haifa, Israel, November 16-18 1999.
- [3356]
- I. Pomeranz and
S. M. Reddy.
Transparent scan: a new approach to test generation and test compaction for
scan circuits that incorporates limited scan operations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(12):1663-1670, December 2003.
- [3357]
- I. Pomeranz and
S. M. Reddy.
Transparent DFT: a design for testability and test generation approach for
synchronous sequential circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(6):1170-1175, June 2006.
- [3358]
- I. Pomeranz and
S. M. Reddy.
Double-single stuck-at faults: a delay fault model for synchronous sequential
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(3):426-432, March 2009.
- [3359]
- I. Pomeranz and
S. M. Reddy.
Random test generation with input cube avoidance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(1):45-54, January 2009.
- [3360]
- I. Pomeranz and
S. M. Reddy.
TOV: sequential test generation by ordering of test vectors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(3):454-465, March 2010.
- [3361]
- I. Pomeranz.
Invariant states and redundant logic in synchronous sequential circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(6):1171-1175, June 2007.
- [3362]
- I. Pomeranz.
Subsets of primary input vectors in sequential test generation for single
stuck-at faults.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(10):1579-1583, October 2011.
- [3363]
- T. Pompl,
C. Schlunder, M. Hommel, H. Nielen, and J. Schneider.
Practical aspects of reliability analysis for IC designs.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
193-198, San Francisco, CA, July 24-28 2006.
- [3364]
- D. Ponomarev, G. Kucuk, O. Ergin, and K. Ghose.
Power efficient comparators for long arguments in superscalar processors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 378-383, Seoul, Korea, August 25-27 2003.
- [3365]
- M. Popovich,
E. G. Friedman, R. M. Secareanu, and O. L. Hartin.
Efficient placement of distributed on-chip decoupling capacitors in nanoscale
ics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 811-816, San Jose, CA, November 5-8 2007.
- [3366]
- M. Popovich, E. G. Friedman, R. M. Secareanu, and O. L. Hartin.
Efficient distributed on-chip decoupling capacitors for nanoscale ics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(12):1717-1721, December 2008.
- [3367]
- M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny.
On-chip power distribution grids with multiple supply voltages for
high-performance integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(7):908-921, July 2008.
- [3368]
- M. Popovich, M. Sotman, A. Kolodny, and E. G. Friedman.
Effective radii of on-chip decoupling capacitors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(7):894-906, July 2008.
- [3369]
- M. Popovich and
E. G. Friedman.
Decoupling capacitors for multi-voltage power distribution systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(3):217-228, March 2006.
- [3370]
- S. Popovych,
H.-H. Lai, C.-M. Wang, Y.-L. Li, W.-H. Liu, and T.-C. Wang.
Density-aware detailed placement with instant legalization.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [3371]
- S. Posluszny, N. Aoki, D. Boerstler, P. Coulman, S. Dhong,
B. Flachs, P. Hofstee, N. Kojima, O. Kwon, K. Lee, D. Meltzer, K. Nowka,
J. Park, J. Peter, J. Silberman, O. Takahashi, and P. Villarrubia.
"timing closure by design," A high frequency microprocessor design
methodology.
In Design Automation Conference, pages 712-717, Los Angeles, CA, June
5-9 2000.
- [3372]
- G. Posser,
V. Mishra, P. Jain, R. Reis, and S. S. Sapatnekar.
A systematic approach for analyzing and optimizing cell-internal signal
electromigration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 486-491, San Jose, CA, November 2-6 2014.
- [3373]
- G. Posser,
V. MIshra, P. Jain, R. Reis, and S. S. Sapatnekar.
Cell-internal electromigration: analysis and pin placement based optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(2):220-231, February 2016.
- [3374]
- A. Pothen, H. D.
Simon, and K-P Liou.
Partitioning sparse matrices with eigenvectors of graphs.
SIAM J. Matrix Anal. Appl., 11(3):430-452, July 1990.
- [3375]
- M. Potkonjak, D. Chen, P. Kalla, and S. P. Levitan.
DA vision 2015: from here to eternity.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 271-277, Austin TX, November 2-6 2015.
- [3376]
- M. Potkonjak.
Synthesis of trustable ics using untrusted CAD tools.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
633-634, Anaheim, CA, June 13-18 2010.
- [3377]
- B. Potts,
R. Hokinson, W. Kang, J. Riley, D. Doman, F. Cano, N. S. Nagaraj, and
N. Durrant.
Enabling DIR (designing-in reliability) throught CAD capabilities.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 151-156, San Jose, CA, March 20-22 2000.
- [3378]
- M. Powell, S.-H.
Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar.
Gated-vdd: A circuit technique to reduce leakage in deep-submicron cache
memories.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 90-95, Italy, July 26-27 2000.
- [3379]
- M. Powell, S.-H.
Yang, B. Falsafi, K. Roy, and T. N. Vijaykumar.
Reducing leakage in a high-performance deep-submicron instruction cache.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(1):77-89, February 2001.
- [3380]
- S. R. Powell and P. M.
Chau.
Estimating power dissipation of VLSI signal processing chips: The PFA
technique.
In VLSI Signal Processing IV, pages 250-259. IEEE, 1991.
- [3381]
- D. K. Pradhan,
M. Chatterjee, M. V. Swarna, and W. Kunz.
Gate-level synthesis for low-power using new transformations.
In International Symposium on Low Power Electronics and Design, pages
297-300, Monterey, CA, August 12-14 1996.
- [3382]
- M. R. Prasad,
P. Chong, and K. Keutzer.
Why is ATPG easy?
In Design Automation Conference, pages 22-28, New Orleans, LA, June
21-25 1999.
- [3383]
- S. C. Prasad and K. Roy.
Circuit optimization for minimization of power consumption under delay
constraint.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
15-20, Napa, CA, April 24-27 1994.
- [3384]
- R. J. Pratap,
P. Sen, C. E. Davis, R. Mukhophdhyay, G. S. May, and J. Laskar.
Neurogenetic design centering.
IEEE Transactions on Semiconductor Manufacturing, 19(2):173-182, May
2006.
- [3385]
- Preparata and Yeh.
Introduction to Discrete Structures.
Addison-Wesley Publishing Company, 1973.
- [3386]
- E. J. Prinz.
The zen of nonvolatile memories.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
815-820, San Francisco, CA, July 24-28 2006.
- [3387]
- S. Priyadarshi, C. S. Saunders, N. M. Kriplani, H. Demircioglu,
W. R. Davis, P. D. Franzon, and M. B. Steer.
Parallel transient simulation of multiphysics circuits using delay-based
partitioning.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(10):1522-1535, October 2012.
- [3388]
- Y. Pu, J. P. de Gyvez,
H. Corporaal, and Y. Ha.
VT balancing and device sizing towards high yield of sub-threshold static
logic gates.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 355-358, Portland, Oregon, August 27-29 2007.
- [3389]
- Y. Pu, X. Zhang,
J. Huang, A. Muramatsu, M. Nomura, K. Hirairi, H. Takata, T. Sakurabayashi,
S. Miyano, M. Takamiya, and T. Sakurai.
Misleading energy and performance claims in sub/near threshold digital systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 625-631, San Jose, CA, November 7-11 2010.
- [3390]
- A. Puggelli,
T. Welp, A. Kuehlmann, and A. Sangiovanni-Vincentelli.
Are logic synthesis tools robust?
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
633-638, San Diego, CA, June 5-9 2011.
- [3391]
- R. Puri,
A. Bjorksten, and T. E. Rosser.
Logic optimization by output phase assignment in dynamic logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
2-8, San Jose, CA, November 10-14 1996.
- [3392]
- R. Puri, L. Stok,
J. Cohn, D. Kung, D. Pan, D. Sylvester, A. Srivastava, and S. Kulkarni.
Pushing ASIC performance in a power envelope.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
788-793, Anaheim, CA, June 2-6 2003.
- [3393]
- R. Puri, L. Stok,
and S. Bhattacharya.
Keeping hot chips cool.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
285-288, Anaheim, CA, June 13-17 2005.
- [3394]
- R. Puri and C. T. Chuang.
Hysteresis effect in floating-body partially-depleted SOI CMOS domino
circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 223-228, San Diego, CA, August 16-17 1999.
- [3395]
- R. Puri.
Minimizing power under performance constraint.
In International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 159-163, Austin, TX, May 17-20 2004.
- [3396]
- R. Puri.
Application driven high level design in the era of heterogeneous computing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
page 71, San Jose, CA, November 2-6 2014.
- [3397]
- Z. Qi, H. Yu, P. Liu,
S. X.-D. Tan, and L. He.
Wideband passive multiport model order reduction and realization of RLCM
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(8):1496-1509, August 2006.
- [3398]
- J. Qian, S. Pullela,
and L. Pillage.
Modeling the "effective capacitance" for the RC interconnect of CMOS gates.
IEEE Transactions on Computer-Aided Design, 13(12):1526-1535,
December 1994.
- [3399]
- H. Qian, S. R.
Nassif, and S. S. Sapatnekar.
Random walks in a supply network.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages 93-98,
Anaheim, CA, June 2-6 2003.
- [3400]
- H. Qian, J. N.
Kozhaya, S. R. Nassif, and S. S. Sapatnekar.
A chip-level electrostatic discharge simulation strategy.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 315-318, San Jose, CA, November 7-11 2004.
- [3401]
- H. Qian, S. R.
Nassif, and S. S. Sapatnekar.
Early-stage power grid analysis for uncertain working modes.
In ACM International Symposium on Physical Design (ISPD-04), pages
132-137, Phoenix, AZ, April 18-21 2004.
- [3402]
- H. Qian, S. R.
Nassif, and S. S. Sapatnekar.
Early-stage power grid analysis for uncertain working modes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(5):676-682, May 2005.
- [3403]
- H. Qian, S. R.
Nassif, and S. S. Sapatnekar.
Power grid analysis using random walks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(8):1204-1224, August 2005.
- [3404]
- W. Qian, M. D.
Riedel, H. Zhou, and J. Bruck.
Transforming probabilities with combinational logic.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(9):1279-1292, September 2011.
- [3405]
- W. Qian, C. Wang,
P. Li, D. J. Lilja, K. Bazargan, and M. D. Riede.
An efficient implementation of numerical integration using logical computation
on stochastic bit streams.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 156-162, San Jose, CA, November 5-8 2012.
- [3406]
- H. Qian and S. S.
Sapatnekar.
Hierarchical random-walk algorithms for power grid analysis.
In IEEE/ACM Asia and South Pacific Design Automation Conference
(ASP-DAC), pages 499-504, Yokohama, Japan, January 27-30 2004.
- [3407]
- H. Qian and S. S.
Sapatnekar.
A hybrid linear equation solver and its application in quadratic placement.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 905-909, San Jose, CA, November 6-10 2005.
- [3408]
- H. Qian and S. S.
Sapatnekar.
Fast poisson solvers for thermal analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 698-702, San Jose, CA, November 7-11 2010.
- [3409]
- Z. Qin and C.-K. Cheng.
Realizable parasitic reduction using generalized Y-delta transformation.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
220-225, Anaheim, CA, June 2-6 2003.
- [3410]
- Q. Qiu, Q. Wu,
M. Pedram, and C.-S. Ding.
Cycle-accurate macro-models for RT-level power analysis.
In 1997 International Symposium on Low Power Electronics and Design,
pages 125-130, Monterey, CA, August 18-20 1997.
- [3411]
- Q. Qiu, Q. Wu, and
M. Pedram.
Maximum power estimation using the limiting distributions of extreme order
statistics.
In IEEE/ACM 35th Design Automation Conference, pages 684-689, San
Francisco, CA, June 15-19 1998.
- [3412]
- Q. Qiu, Q. Wu, and
M. Pedram.
Stochastic modeling of a power-managed system: construction and optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 194-199, San Diego, CA, August 16-17 1999.
- [3413]
- Q. Qiu, Q. Wu, and
M Pedram.
Dynamic power management of complex systems using generalized stochastic petri
nets.
In Design Automation Conference, pages 352-356, Los Angeles, CA, June
5-9 2000.
- [3414]
- Q. Qiu, Y. Tan, and
Q. Wu.
Stochastic modeling and optimization for robust power management in a partially
observable system.
Design, Automation and Test in Europe (DATE-07), pages 779-784, April
16-20 2007.
- [3415]
- X. Qiu,
M. Marek-Sadowska, and W. P. Maly.
Characterizing vesfet-based ics with CMOS-oriented EDA infrastructure.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(4):495-506, April 2014.
- [3416]
- Q. Qiu and M. Pedram.
Dynamic power management based on continuous-time markov decision processes.
In Design Automation Conference, pages 555-561, New Orleans, LA, June
21-25 1999.
- [3417]
- G. Qu, N. Kawabe,
K. Usami, and M. Potkonjak.
Function-level power estimation methodology for microprocessors.
In Design Automation Conference, pages 810-813, Los Angeles, CA, June
5-9 2000.
- [3418]
- G. Qu and L. Yuan.
Design THINGS for the internet of things - an EDA perspective.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 411-416, San Jose, CA, November 2-6 2014.
- [3419]
- N. T. Quach,
N. Takagi, and M. J. Flynn.
Systematic IEEE rounding method for high-speed floating-point multipliers.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):511-521, May 2004.
- [3420]
- J. M. Rabaey,
C. Chu, P. Hoang, and M. Potkonjak.
Fast prototyping of datapath-intensive architectures.
IEEE Design & Test of Computers, 8(2):40-51, June 1991.
- [3421]
- J. M. Rabaey,
M. Potkonjak, F. Koushanfar, S.-F. Li, and T. Tuan.
Challenges and opportunities in broadband and wireless communication designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 76-82, San Jose, CA, November 5-9 2000.
- [3422]
- J. M. Rabaey.
Exploring the power dimension.
In IEEE 1996 Custom Integrated Circuits Conference, pages 215-220,
San Diego, CA, May 5-8 1996.
- [3423]
- J. M. Rabaey.
System-level power estimation and optimization - challenges and perspectives.
In 1997 International Symposium on Low Power Electronics and Design,
pages 158-160, Monterey, CA, August 18-20 1997.
- [3424]
- D. Rabe and W. Nebel.
Short circuit power consumption of glitches.
In International Symposium on Low Power Electronics and Design, pages
125-128, Monterey, CA, August 12-14 1996.
- [3425]
- M. O. Rabin.
Probabilistic algorithms.
In J. F. Traub, editor, Algorithms and Complexity, pages 21-39.
Academic Press, Inc., New York, NY, 1976.
- [3426]
- E. Rachlin and J. E.
Savage.
Nanowire addressing with randomized-contact decoders.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 735-742, San Jose, CA, November 5-9 2006.
- [3427]
- R. M. P. Rad and
M. Tehranipoor.
A new hybrid FPGA with nanoscale clusters and CMOS routing.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
727-730, San Francisco, CA, July 24-28 2006.
- [3428]
- V. Raghavan and
R. A. Rohrer.
AWE-right.
In Custom Integrated Circuit Conference (CICC-93), 1993.
- [3429]
- T. Ragheb and
Y. Massoud.
On the modeling of resistance in graphene nanoribbon (GNR) for future
interconnect applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 593-597, San Jose, CA, November 10-13 2008.
- [3430]
- A. Raghunathan, S. Dey, and N. K. Jha.
Glitch analysis and reduction in register transfer level power optimization.
In 33rd Design Automation Conference, pages 331-336, Las Vegas, NV,
June 3-7 1996.
- [3431]
- A. Raghunathan, S. Dey, and N. K. Jha.
Register-transfer level estimation techniques for switching activity and power
consumption.
In IEEE/ACM International Conference on Computer-Aided Design, pages
158-165, San Jose, CA, November 10-14 1996.
- [3432]
- A. Raghunathan, S. Dey, N. K. Jha, and K. Wakabayashi.
Controller re-specification to minimize switching activity in controller/data
path circuits.
In International Symposium on Low Power Electronics and Design, pages
301-304, Monterey, CA, August 12-14 1996.
- [3433]
- A. Raghunathan, S. Dey, N. K. Jha, and K. Wakabayashi.
Power management techniques for control-flow intensive designs.
In 34th Design Automation Conference, pages 429-434, Anaheim, CA,
June 9-13 1997.
- [3434]
- A. Raghunathan, S. Dey, and N. K. Jha.
Register transfer level power optimization with emphasis on glitch analysis and
reduction.
IEEE Transactions on Computer-Aided Design, 18(8):1114-1131, August
1999.
- [3435]
- V. Raghunathan, S. Ravi, A. Raghunathan, and G. Lakshminarayana.
Transient power management through high-level synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 545-552, San Jose, CA, November 4-8 2001.
- [3436]
- A. Raghunathan, S. Dey, and N. K. Jha.
High-level marco-modeling and estimation techniques for switching activity and
power consumption.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):538-557, August 2003.
- [3437]
- A. Raghunathan, S. Dey, and V. Kozhikkottu.
Recovery-based design for variation-tolerant socs.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
826-833, San Francisco, CA, June 3-7 2012.
- [3438]
- V. Raghunathan
and P.-H. Chou.
Design and power management of energy harvesting embedded systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 369-374, Tegernsee, Germany, October 4-6 2006.
- [3439]
- A. Rahman and
V. Polavarapuv.
Evaluation of low-leakage design techniques for field-programmable gate arrays.
In ACM/SIGDA International Symposium on Field Programmable Gate
Arrays, pages 23-30, Monterey, CA, February 22-24 2004.
- [3440]
- A.-M. Rahmani,
M.-H. Haghbayan, A. Kanduri, A. Y. Weldezion, P. Liljeberg, J. Plosila,
A. Jantsch, and H. Tenhunen.
Dynamic power management for many-core platforms in the dark silicon era: a
multi-objective control approach.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 219-224, Rome, Italy, July 22-24 2015.
- [3441]
- R. Raimi and J. Abraham.
Detecting false timing paths: experiments on powerpc microprocessors.
In Design Automation Conference, pages 737-741, New Orleans, LA, June
21-25 1999.
- [3442]
- Gordon Raisbeck.
Information Theory.
The MIT Press, Cambridge, MA, 1963.
- [3443]
- S. Raj, S. B. K.
Vrudhula, and J. Wang.
A methodology to improve timing yield in the presence of process variations.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
448-453, San Diego, CA, June 7-11 2004.
- [3444]
- S. Raja, F. Varadi,
M. Becer, and J. Geada.
Transistor level gate modeling for accurate and fast timing, noise, and power
analysis.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
456-461, Anaheim, CA, June 8-13 2008.
- [3445]
- T. Raja, V. D.
Agrawal, and M. L. Bushnell.
Variable input delay CMOS logic for low power design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(10):1534-1545, October 2009.
- [3446]
- A. Rajaram,
B. Lu, W. Guo, R. Mahapatra, and J. Hu.
Analytical bound for unwanted clock skew due to wire width variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 401-406, San Jose, CA, November 9-13 2003.
- [3447]
- A. Rajaram,
J. Hu, and R. Mahapatra.
Reducing clock skew variability via cross links.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 18-23,
San Diego, CA, June 7-11 2004.
- [3448]
- A. Rajaram,
J. Hu, and R. Mahapatra.
Reducing clock skew variability via crosslinks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(6):1176-1182, June 2006.
- [3449]
- A. Rajaram,
B. Lu, J. Hu, R. Mahapatra, and W. Guo.
Analytical bound for unwanted clock skew due to wire width variation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1869-1876, September 2006.
- [3450]
- R. Rajaraman and
D. F. Wong.
Optimum clustering for delay minimization.
IEEE Transactions on Computer-Aided Design, 14(12):1490-1495,
December 1995.
- [3451]
- S. Rajgopal and
G. Mehta.
Experiences with simulation-based schematic-level current estimation.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
9-14, Napa, CA, April 24-27 1994.
- [3452]
- R. Rajkumar,
I. Lee, L. Sha, and J. Stankovic.
Cyber-physical systems: the next computing revolution.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
731-736, Anaheim, CA, June 13-18 2010.
- [3453]
- J. Rajski and
J. Vasudevamurthy.
The testability-preserving concurrent decomposition and factorization of
boolean expressions.
IEEE Transactions on Computer-Aided Design, 11(6):778-793, June
1992.
- [3454]
- A. Rak and G. Cserey.
Macromodeling of the memristor in SPICE.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):632-641, April 2010.
- [3455]
- D. Rakhmatov
and S. B. K. Vrudhula.
Time-to-failure estimation for batteries in portable electronic systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 88-91, Huntington Beach, California, August 6-7 2001.
- [3456]
- D. Ramachandran, S. Irani, and R. K. Gupta.
An analysis of system level power management algorithms and their effects on
latency.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(3):291-305, March 2002.
- [3457]
- C. Ramachandran and F. J. Kurdahi.
Combined topological and functionality-based delay estimation using a
layout-driven approach for high-level applications.
IEEE Transactions on Computer-Aided Design, 13(12):1450-1460,
December 1994.
- [3458]
- V. Ramachandran.
Algorithmic aspects of MOS VLSI switch-level simulation with race
detection.
IEEE Transactions on Computers, C-35(5):462-475, May 1986.
- [3459]
- A. Ramalingam, A. K. Singh, S. R. Nassif, G.-J. Nam,
M. Orshansky, and D.-Z. Pan.
An accurate sparse matrix based framework for statistical static timing
analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 231-236, San Jose, CA, November 5-9 2006.
- [3460]
- A. Ramalingam, G. V. Devarayanadurg, and D. Z. Pan.
Accurate power grid analysis with behavioral transistor network modeling.
In ACM International Symposium on Physical Design (ISPD-07), pages
43-50, Austin, TX, March 18-21 2007.
- [3461]
- A. Ramalingam, A. K. Singh, S. R. Nassif, M. Orshansky, and
D. Z. Pan.
Accurate waveform modeling using singular value decomposition with applications
to timing analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 67-72, Austin, Texas,
February 26-27 2007.
- [3462]
- A. Ramalingam, A. K. Singh, S. R. Nassif, M. Orshansky, and
D. Z. Pan.
Accurate waveform modeling using singular value decomposition with applications
to timing analysis.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
148-153, San Diego, CA, June 4-8 2007.
- [3463]
- D. Ramanathan, S. Irani, and R. Gupta.
Latency effects of system level power management algorithms.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 350-355, San Jose, CA, November 5-9 2000.
- [3464]
- S. S. Ramani and
S. Bhanja.
Any-time probabilistic switching model using bayesian networks.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 86-89, Newport Beach, CA, August 9-11 2004.
- [3465]
- B. Ramkumar and
H. M. Kittur.
Low-power and area-efficient carry select adder.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(2):371-375, February 2012.
- [3466]
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj.
Achievable bounds on signal transition activity.
In IEEE/ACM International Conference on Computer-Aided Design, pages
126-129, San Jose, CA, November 9-13 1997.
- [3467]
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj.
Analytical estimation of signal transition activity from word-level statistics.
IEEE Transactions on Computer-Aided Design, 16(7):718-733, July
1997.
- [3468]
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj.
Analytical estimation of transition activity from word-level signal statistics.
In 34th Design Automation Conference, pages 582-587, Anaheim, CA,
June 9-13 1997.
- [3469]
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj.
Decorrelating (DECOR) transformations for low-power adaptive filters.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 250-255, Monterey, CA, August 10-12 1998.
- [3470]
- S. Ramprasad, I. N. Hajj, and F. N. Najm.
An optimization technique for dual-output domino logic.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 258-260, San Diego, CA, August 16-17 1999.
- [3471]
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj.
A coding framework for low-power address and data busses.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
7(2):212-221, June 1999.
- [3472]
- S. Ramprasad, N. R. Shanbhag, and I. N. Hajj.
Information-theoretic bounds on average signal transition activity.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(3):359-368, September 1999.
- [3473]
- S. Ramprasad, I. N. Hajj, and F. N. Najm.
A technique for improving dual-output domino logic.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(4):508-511, August 2002.
- [3474]
- S. Ramprasath and V. Vasudevan.
On the computation of criticality in statistical timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 172-179, San Jose, CA, November 5-8 2012.
- [3475]
- S. Ramprasath and V. Vasudevan.
Statistical criticality computation using the circuit delay.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(5):717-727, May 2014.
- [3476]
- S. Ramprasath and V. Vasudevan.
An efficient algorithm for statistical timing yield optimization.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [3477]
- Y. Ran, A. Kondratyev,
K.-T. Tseng, Y. Watanabe, and M. Marek-Sadowska.
Eliminating false positives in corsstalk noise analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(9):1406-1419, September 2005.
- [3478]
- Y. Ran and
M. Marek-Sadowska.
Via-configurable routing architectures and fast design mappability estimation
for regular fabrics.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 25-32, San Jose, CA, November 6-10 2005.
- [3479]
- V. Rao, J. Soreff,
T. Brodnax, and R. Mains.
Einstlt: Transistor level timing with einstimer.
In ACM/IEEE 1999 International Workshop on Timing Issues in the
Specification and Synthesis of Digital Systems (TAU-99), pages 1-6,
Monterey, CA, March 8-9 1999.
- [3480]
- R. Rao,
A. Srivastava, D. Blaauw, and D. Sylvester.
Statistical estimation of leakage current considering inter- and intra-die
process variation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 84-89, Seoul, Korea, August 25-27 2003.
- [3481]
- R. M. Rao, J. L.
Burns, A. Devgan, and R. B. Brown.
Efficient techniques for gate leakage estimation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 100-103, Seoul, Korea, August 25-27 2003.
- [3482]
- R. M. Rao, F. Liu,
J. L. Burns, and R. B. Brown.
A heuristic to determine low leakage sleep state vectors for CMOS
combinational circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 689-692, San Jose, CA, November 9-13 2003.
- [3483]
- R. Rao, A. Agarwal,
D. Sylvester, R. Brown, K. Nowka, and S. Nassif.
Approaches to run-time and standby mode leakage reduction in global buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 188-193, Newport Beach, CA, August 9-11 2004.
- [3484]
- R. Rao,
A. Srivastava, D. Blaauw, and D. Sylvester.
Statistical analysis of subthreshold leakage current for VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(2):131-139, February 2004.
- [3485]
- R. R. Rao,
A. Devgan, D. Blaauw, and D. Sylvester.
Parametric yield estimation considering leakage variability.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
442-447, San Diego, CA, June 7-11 2004.
- [3486]
- R. R. Rao, H. S.
Deogun, D. Blaauw, and D. Sylvester.
Bus encoding for total power reduction using a leakage-aware buffer
configuration.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(12):1376-1383, December 2005.
- [3487]
- R. R. Rao,
D. Blaauw, and D. Sylvester.
Soft error reduction in combinational logic using gate resizing and flipflop
selection.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 502-509, San Jose, CA, November 5-9 2006.
- [3488]
- R. R. Rao, A. Devgan,
D. Blaauw, and D. Sylvester.
Analytical yield prediction considering leakage/performance correlation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1685-1695, September 2006.
- [3489]
- W. Rao,
A. Orailoglu, and R. Karri.
Topology aware mapping of logic functions onto nanowire-based crossbar
architectures.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
723-726, San Francisco, CA, July 24-28 2006.
- [3490]
- R. R. Rao, K. Chopra,
D. T. Blaauw, and D. M. Sylvester.
Computing the soft error rate of a combinational logic circuit using
parameterized descriptors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(3):468-479, March 2007.
- [3491]
- V. Rao, D. Sinha,
N. Srimal, and P. K. Maurya.
Statistical path tracing in timing graphs.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [3492]
- R. Rao and S. Vrudhula.
Energy-optimal speed control of a generic device.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2737-2746, December 2006.
- [3493]
- N. Narayana Rao.
Elements of Engineering Electromagnetics.
Prentice Hall, Inc., Englewood Cliffs, NJ, 1986.
- [3494]
- V. B. Rao.
Delay analysis of the distributed RC line.
In 32nd Design Automation Conference, pages 370-375, San Francisco,
CA, June 12-16 1995.
- [3495]
- G. Rappitsch, E. Seebacher, M. Kocher, and E. Stadlober.
SPICE modeling of process variation using location depth corner models.
IEEE Transactions on Semiconductor Manufacturing, 17(2):201-213, May
2004.
- [3496]
- A. Rastogi,
W. Chen, and S. Kundu.
On estimating impact of loading effect on leakage current in sub-65nm scaled
CMOS circuits based on newton-raphson method.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
712-715, San Diego, CA, June 4-8 2007.
- [3497]
- C. L.
Ratzlaff, S. Pullela, and L. T. Pillage.
Modeling the RC-interconnect effects in a hierarchical timing analyzer.
In IEEE 1992 Custom Integrated Circuits Conference, pages
15.6.1-15.6.4, May 1992.
- [3498]
- K. Ravi and F. Somenzi.
High-density reachability analysis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
154-158, San Jose, CA, November 5-9 1995.
- [3499]
- C. Ravishankar, J. H. Anderson, and A. Kennings.
FPGA power reduction by guarded evaluation considering logic architecture.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(9):1305-1318, September 2012.
- [3500]
- A. Raychowdhury, S. Mukhopadhyay, and K. Roy.
A circuit-compatible model of ballistic carbon nanotube field-effect
transistors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(10):1411-1420, October 2004.
- [3501]
- A. Raychowdhury, B. C. Paul, S. Bhunia, and K. Roy.
Computing with subthreshold leakage: device/circuit/architecture co-design for
ultralow-power subthreshold operation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1213-1224, November 2005.
- [3502]
- A. Raychowdhury and K. Roy.
Modeling of metallic carbon-nanotube interconnects for circuit simulations and
a comparison with cu interconnects for scaled technologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):58-65, January 2006.
- [3503]
- A. Raychowdhury and K. Roy.
Carbon nanotube electronics: design of high-performance and low-power digital
circuits.
IEEE Transactions on Circuits and Systems, 54(11):2391-2401, November
2007.
- [3504]
- A. Raychowdhury.
Spin torque devices in embedded memory: model studies and design space
exploration.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 572-575, San Jose, CA, November 18-21 2013.
- [3505]
- A. Raychowhury, X. Fong, Q. Chen, and K. Roy.
Analysis of super cut-off transistors for ultralow power digital logic
circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 2-7, Tegernsee, Germany, October 4-6 2006.
- [3506]
- S. M. Reddy,
V. D. Agrawal, and S. K. Jain.
A gate level model for CMOS combinational logic circuits with application to
fault detection.
In IEEE 21st Design Automation Conference, pages 504-509,
Albuquerque, NM, June 25-27 1984.
- [3507]
- S. M. Reddy,
M. K. Reddy, and V. D. Agrawal.
Robust tests for stuck-open faults in CMOS combinational logic circuits.
In IEEE 14th International Symposium on Fault Tolerant Computing,
pages 44-49, Kissimee, FL, June 20-22 1984.
- [3508]
- M. K. Reddy, S. M.
Reddy, and P. Agrawal.
Transistor level test generation for MOS circuits.
In IEEE 22nd Design Automation Conference, pages 825-828, 1985.
- [3509]
- S. M. Reddy and M. K.
Reddy.
Testable realizations for FET stuck-open faults in CMOS combinational logic
circuits.
IEEE Transactions on Computers, C-35(8):742-754, August 1986.
- [3510]
- T. L. Reed.
Using the taguchi method of parameter design for improving product reliability.
In Tutorial Notes, Annual Reliability and Maintainability Symposium,
Washington, DC, January 16-19 1995.
- [3511]
- S. Rehman,
W. El-Harouni, M. Shafique, A. Kumar, and J. Henkel.
Architectural-space exploration of approximate multipliers.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [3512]
- A. Reimer,
A. Schulz, and W. Nebel.
Modelling macromodules for high-level dynamic power estimation of FPGA-based
digital designs.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 151-154, Tegernsee, Germany, October 4-6 2006.
- [3513]
- E. M.
Reingold, J. Nievergelt, and N. Deo.
Combinatorial algorithms, theory and practice.
Prentice-Hall, Inc., Englewood Cliffs, NJ, 1977.
- [3514]
- T. Reis and R. Stykel.
PABTEC: passivity-preserving balanced truncation for electrical circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(9):1354-1367, September 2010.
- [3515]
- T. Rejimon,
K. Lingasubramanian, and S. Bhanja.
Probabilistic error modeling for nano-domain logic circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(1):55-65, January 2009.
- [3516]
- T. Rejimon and
S. Bhanja.
A timing-aware probabilistic model for single-event-upset analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(10):1130-1139, October 2006.
- [3517]
- L. Ren, X. Chen,
Y. Wang, C. Zhang, and H. Yang.
Sparse LU factorization for parallel circuit simulation on GPU.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1125-1130, San Francisco, CA, June 3-7 2012.
- [3518]
- P. Ren, M. Lis, M.-H.
Cho, K.-S. Shim, C. W. Fletcher, O. Khan, N. Zheng, and S. Devadas.
Hornet: a cycle-level multicore simulator.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(6):890-903, June 2012.
- [3519]
- P. Rezvani,
A. H. Ajami, M. Pedram, and H. Savoj.
LEOPARD: A logical effort-based fanout optimizer for area and delay.
In IEEE/ACM International Conference on Computer-Aided Design, pages
516-519, San Jose, CA, November 7-11 1999.
- [3520]
- P. Rezvani and
M. Pedram.
A fanout optimization algorithm based on the effort delay model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(12):1671-1678, December 2003.
- [3521]
- J-K Rho, F. Somenzi,
and C. Pixley.
Minimum length synchronizing sequences of finite state machine.
In 30th ACM/IEEE Design Automation Conference, pages 463-468, Dallas,
Texas, June 14-18 1993.
- [3522]
- S. E. Rich, M. J.
Parker, and J. Schwartz.
Reducing the frequency gap between ASIC and custom designs: A custom
perspective.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
432-437, Las Vegas, NV, June 18-22 2001.
- [3523]
- R. Rithe, S. Chou,
J. Gu, A. Wang, S. Datla, G. Gammie, D. Buss, and A. Chandrakasan.
The effect of random dopant fluctuations on logic timing at low voltage.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(5):911-924, May 2012.
- [3524]
- J. Rius.
IR-drop in on-chip power distribution networks of ics with nonuniform power
consumption.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(3):512-522, March 2013.
- [3525]
- J. Rius.
Supply noise and impedance of on-chip power distribution networks in ics with
nonuniform power consumption and interblock decoupling capacitors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(6):993-1004, June 2015.
- [3526]
- J. Rizo-Morente, M. Casas-Sanchez, and C. J. Bleakley.
Dynamic current modeling at the instruction level.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 95-100, Tegernsee, Germany, October 4-6 2006.
- [3527]
- V. Rizzoli,
D. Masotti, F. Mastri, and E. Montanari.
System-oriented harmonic-balance algorithms for circuit-level simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(2):256-269, February 2011.
- [3528]
- E. Roa, W.-H. Chen,
and B. Jung.
Material implication in CMOS: a new kind of logic.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1254-1255, San Francisco, CA, June 3-7 2012.
- [3529]
- W. Robinett,
P. J. Kuekes, and R. S. Williams.
Defect tolerance based on coding and series replication in transistor-logic
demultiplexer circuits.
IEEE Transactions on Circuits and Systems, 54(11):2410-2421, November
2007.
- [3530]
- G. Robins,
J. Huang, and J. Lach.
A methodology for energy-quality tradeoff using imprecise hardware.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
504-509, San Francisco, CA, June 3-7 2012.
- [3531]
- S. H. Robinson and
J. P. Shen.
Towards a switch-level test pattern generation program.
In IEEE International Conference on Computer-Aided Design, pages
39-41, Santa Clara, CA, Nov. 18-21 1985.
- [3532]
- S. Rochel and N. S.
Nagaraj.
Full-chip signal interconnect analysis for electromigration reliability.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 337-340, San Jose, CA, March 20-22 2000.
- [3533]
- P. Rodman.
Forest vs trees: where's the slack.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
267-267, San Diego, CA, June 7-11 2004.
- [3534]
- R. Rodriguez, J. H. Stathis, and B. P. Linder.
Modeling and experimental verification of the effect of gate oxide breakdown on
CMOS inverters.
In International Reliability Physics Symposium (IRPS), pages 11-16,
Dallas, TX, March 30-April 4 2003.
- [3535]
- A. Rogachev,
L. Wan, and D. Chen.
Temperature aware statistical static timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 103-110, San Jose, CA, November 7-10 2011.
- [3536]
- B. Rohfleisch, A. Kolbl, and B. Wurth.
Reducing power dissipation after technology mapping by structural
transformations.
In 33rd Design Automation Conference, pages 789-794, Las Vegas, NV,
June 3-7 1996.
- [3537]
- R. Rohrer.
Fully automated network design by digital computer: preliminary considerations.
In Proceedings of the IEEE, pages 1929-1939, November 1967.
Published as Proceedings of the IEEE, volume 55, number 11.
- [3538]
- R. A. Rohrer.
Circuit partitioning simplified.
IEEE Transactions on Circuits and Systems, 35(1):2-5, January
1988.
- [3539]
- D. R. Rolston,
D. M. Gross, G. W. Roberts, and D. V. Plant.
A distributed synchronized clocking method.
IEEE Transactions on Circuits and Systems, 52(8):1597-1607, August
2005.
- [3540]
- J. Rommes and
W. H. A. Schilders.
Efficent methods for large resistor networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(1):28-39, January 2010.
- [3541]
- P. Rong and M. Pedram.
Battery-aware power management based on markovian decision processes.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 707-713, San Jose, CA, November 10-14 2002.
- [3542]
- P. Rong and M. Pedram.
An analytical model for predicting the remaining battery capacity of
lithium-ion batteries.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(5):441-451, May 2006.
- [3543]
- P. Rong and M. Pedram.
Battery-aware power management based on markovian decision processes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1337-1349, July 2006.
- [3544]
- G. S. Rose, M. M.
Ziegler, and M. R. Stan.
Large-signal two-terminal device model for nanoelectronic circuit analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(11):1201-1208, November 2004.
- [3545]
- J. Rosenfeld
and E. G. Friedman.
Design methodology for global resonant H-tree clock distribution networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(2):135-148, February 2007.
- [3546]
- J. Rosenfeld
and E. G. Friedman.
Quasi-resonant interconnects: a low power, low latency design methodology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(2):181-193, February 2009.
- [3547]
- A. Rosenthal.
Computing the reliability of complex networks.
SIAM Journal on Applied Mathematics, 32(2):384-393, March 1977.
- [3548]
- T. S. Rosing,
K. Mihic, and G. De Micheli.
Power and reliability management of socs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(4):391-403, April 2007.
- [3549]
- T. Roska.
Cellular wave computers and CNN technology - a soc architecture with xk
processors and sensor arrays.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 557-564, San Jose, CA, November 6-10 2005.
- [3550]
- Sheldon Ross.
Stochastic Processes.
John Wiley & Sons, New York, NY, 1983.
- [3551]
- J. L. Rossello and
J. Segura.
Power-delay modeling of dynamic CMOS gates for circuit optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 494-499, San Jose, CA, November 4-8 2001.
- [3552]
- J. L. Rossello and
J. Segura.
Charge-based analytical model for the evaluation of power consumption in
submicron CMOS buffers.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(4):433, April 2002.
- [3553]
- D. Rossi, A. K.
Nieuwland, S. V. E. S. van Dijk, R. P. Kleihorst, and C. Metra.
Power consumption of fault tolerant busses.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(5):542-553, May 2008.
- [3554]
- D. Rossi, J. M.
Cazeaux, M. Omana, C. Metra, and A. Chatterjee.
Accurate linear model for SET critical charge estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(8):1161-1166, August 2009.
- [3555]
- D. Rossi,
V. Tenentes, S. Yang, S. Khursheed, and B. M. Al-Hashimi.
Reliable power gating with NBTI aging benefits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(8):2735-2744, August 2016.
- [3556]
- J. P. Roth, W. G.
Bouricius, and P. R. Schneider.
Programmed algorithms to compute tests to detect and distinguish between
failures in logic circuits.
IEEE Transactions on Electronic Computers, EC-16(5):71-84, October
1967.
- [3557]
- J. P. Roth, V. G.
Oklobdzija, and J. F. Beetem.
Test generation for FET switching circuits.
In IEEE International Test Conference, pages 59-62, 1984.
- [3558]
- J. P. Roth.
Algebraic topological methods for the synthesis of switching systems I.
Transactions of the American Mathematical Society, 88(2):301-326,
July 1958.
- [3559]
- J. P. Roth.
Diagnosis of automata failure: a calculus and a method.
IBM Journal of Research and Development, 10(4):278-291, July 1966.
- [3560]
- John Paul Roth.
Computer Logic, Testing, and Verification.
Computer Science Press, Inc., Potomac, MD, 1980.
- [3561]
- P. W. K. Rothemund.
Design of DNA origami.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 471-478, San Jose, CA, November 6-10 2005.
- [3562]
- F. Rouatbi,
B. Haroun, and A. J. Al-Khalili.
Power estimation tool for sub-micron CMOS VLSI circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
204-209, Santa Clara, CA, November 8-12 1992.
- [3563]
- S. Roy, H. Arts, and
P. Banerjee.
Powerdrive: A fast, canonical power estimator for driving synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
601-606, San Jose, CA, November 8-12 1998.
- [3564]
- A. Roy, N. Mahmoud,
and M. H. Chowdhury.
Effects of coupling capacitance and inductance on delay uncertainty and clock
skew.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
184-187, San Diego, CA, June 4-8 2007.
- [3565]
- S. Roy, W. Chen,
C. C.-P. Chen, and Y. H. Hu.
Numerically convex forms and their application in gate sizing.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(9):1637-1647, September 2007.
- [3566]
- S. Roy, P. P.
Chakrabarti, and P. Dasgupta.
Satisfiability models for maximum transition power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(8):941-951, August 2008.
- [3567]
- K. Roy, J. P.
Kulkarni, and S. K. Gupta.
Device/circuit interactions at 22nm technology node.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 97-102,
San Francisco, CA, July 26-31 2009.
- [3568]
- A. Roy, J. Xu, and
M. H. Chowdhury.
Analysis of the impacts of signal slew and skew on the behavior of coupled
RLC interconnects for different switching patterns.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):338-342, February 2010.
- [3569]
- K. Roy, M. Sharad,
D. Fan, and K. Yogendra.
Exploring boolean and non-boolean computing with spin torque devices.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 576-580, San Jose, CA, November 18-21 2013.
- [3570]
- S. Roy, M. Choudhury,
R. Puri, and D.-Z. Pan.
Polynomial time algorithm for area and power efficient adder synthesis in
high-performance designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(5):820-831, May 2016.
- [3571]
- S. Roy and P. Banerjee.
An algorithm for converting floating-point computations to fixed-point in
MATLAB based FPGA design.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
484-487, San Diego, CA, June 7-11 2004.
- [3572]
- S. Roy and
K. Chakraborty.
Predicting timing violations through instruction-level path sensitization
analysis.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1074-1081, San Francisco, CA, June 3-7 2012.
- [3573]
- S. Roy and A. Dounavis.
Closed-form delay and crosstalk models for RLC on-chip interconnects using a
matrix rational approximation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(10):1481-1492, October 2009.
- [3574]
- S. Roy and A. Dounavis.
Efficient delay and crosstalk modeling of RLC interconnects using delay
algebraic equations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(2):342-346, February 2011.
- [3575]
- S. C. Dutta Roy and
S. Minocha.
On the evaluation of a matrix polynomial.
IEEE Transactions on Circuits and Systems - I, 39(7):567-570, July
1992.
- [3576]
- K. Roy and S. Prasad.
SYCLOP: Synthesis of CMOS logic for low power applications.
In IEEE International Conference on Computer Design, pages 464-467,
1992.
- [3577]
- K. Roy and S. C. Prasad.
Circuit activity based logic synthesis for low power reliable operations.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
1(4):503-513, December 1993.
- [3578]
- D. Roy.
Discrete rayleigh distribution.
IEEE Transactions on Reliability, 53(2):255-260, June 2004.
- [3579]
- P. Royannez,
H. Mair, F. Dahan, M. Wagner, M. Streeter, L. Bouetel, J. Blasquez,
H. Clasen, S. Semino, J. Dong, D. Scott, B. Pitts, C. Raibaut, and U. Ko.
A design platform for 90-nm leakage reduction techniques.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
549-550, Anaheim, CA, June 13-17 2005.
- [3580]
- J. S. Roychowdhury, A. R. Newton, and D. O. Pederson.
Simulating lossy interconnect with high frequency nonidealities in linear time.
In 29th ACM/IEEE Design Automation Conference, pages 75-80, Anaheim,
CA, June 8-12 1992.
- [3581]
- J. Roychowdhury and R. Melville.
Delivering global DC convergence for large mixed-signal circuits via
homotopy/continuation methods.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):66-78, January 2006.
- [3582]
- J. Roychowdhury.
Micro-photonic interconnects: characteristics, possibilities and limitations.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
574-575, San Diego, CA, June 4-8 2007.
- [3583]
- G. M. Royer.
A monte carlo procedure for potential theory problems.
IEEE Transactions on Microwave Theory and Techniques,
MTT-19(10):813-818, October 1971.
- [3584]
- N. Rubanov.
Subislands: The probabilistic match assignment algorithm for subcircuit
recgonition.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(1):26-38, January 2003.
- [3585]
- N. Rubanov.
High-performance subcircuit recognition method based on the nonlinear graph
optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2353-2363, November 2006.
- [3586]
- N. Rubanov.
A general framework to perform the MAX/MIN operations in parameterized
statistical timing analysis using information theoretic concepts.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(7):1011-1019, July 2011.
- [3587]
- J. Rubenstein, P. Penfield, Jr., and M. A. Horowitz.
Signal delay in RC tree networks.
IEEE Transactions on Computer-Aided Design, CAD-2(3):202-211, July
1983.
- [3588]
- A. Rubio,
N. Itazaki, X. Xu, and K. Kinoshita.
An approach to the analysis and detection of crosstalk faults in digital VLSI
circuits.
IEEE Transactions on Computer-Aided Design, 13(3):387-395, March
1994.
- [3589]
- Sergiu Rudeanu.
Boolean Functions and Equations.
North Holland Publishing Company, American Elsevier Publishing Co. Inc., New
York, NY, 1974.
- [3590]
- J. C. Rudell,
J-J Ou, R. S. Narayanaswami, G. Chien, J. A. Weldon, L. Lin, K-C Tsai,
L. Tee, K. Khoo, D. Au, T. Robinson, D. Gerna, M. Otsuka, and P. R. Gray.
Rcent developments in high integration multi-standard CMOS transceivers for
personal communication systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 149-154, Monterey, CA, August 10-12 1998.
- [3591]
- R. Rudell.
Dynamic variable ordering for ordered binary decision diagrams.
In IEEE/ACM International Conference on Computer-Aided Design, pages
42-47, Santa Clara, CA, November 7-11 1993.
- [3592]
- R. Rudell.
Tutorial: Design of a logic synthesis system.
In 33rd Design Automation Conference, pages 191-196, Las Vegas, NV,
June 3-7 1996.
- [3593]
- A. E. Ruehli,
N. Kulasza, and J. Pivnichny.
Inductance of nonstraight conductors close to a ground return plane.
IEEE Transactions on Microwave Theory and Techniques, pages 706-708,
August 1975.
- [3594]
- A. E. Ruehli,
C. Paul, and J. Garrett.
Inductance calculations using partial inductances and macromodels.
In IEEE International Symposium on Electromagnetic Compatibility
(EMC), pages 23-28, Atlanta, GA, August 1995.
- [3595]
- A. E. Ruehli and
J. Hayes.
Nonlinear circuit solver with linear interconnect load.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 195-198, San Jose, CA, October 27-29 2008.
- [3596]
- A. E. Ruehli.
Inductance calculations in a complex integrated circuit environment.
IBM Journal of Research and Development, 16(5):470-481, September
1972.
- [3597]
- A. E. Ruehli.
Survey of computer-aided electrical analysis of integrated circuit
interconnections.
IBM Journal of Research and Development, 23(6):626-639, November
1979.
- [3598]
- R. A. Rutenbar and
J. M. Cohn.
Layout tools for analog ics and mixed-signal socs: A survey.
In International Symposium on Physical Design, pages 76-83, San
Diego, CA, April 9-12 2000.
- [3599]
- R. A. Rutenbar.
Analog circuit and layout synthesis revisited.
In ACM International Symposium on Physical Design 2015, page 83,
Monterey, California, March 29 - April 1 2015.
- [3600]
- Y. Ryu and T. Kim.
Clock buffer polarity assignment combined with clock tree generation for
power/ground noise minimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 416-419, San Jose, CA, November 10-13 2008.
- [3601]
- N. Ryzhenko and
S. Burns.
Standard cell routing via boolean satisfiability.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
603-612, San Francisco, CA, June 3-7 2012.
- [3602]
- Y. Saad and M. H. Schultz.
GMRES: A generalized minimal residual algorithm for solving nonsymmetric
linear systems.
SIAM Journal on Scientific and Statistical Computing, 7:856-869, July
1986.
- [3603]
- Y. Saad.
Iterative Methods for Sparse Linear Systems.
SIAM, Philadelphia, PA, 2003.
- [3604]
- M. M. Sabry,
A. Sridhar, J. Meng, A. K. Coskun, and D. Atienza.
Greencool: an energy-efficient liquid cooling design technique for 3-D mpsocs
via channel width modulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(4):524-537, April 2013.
- [3605]
- D. Sacchetto, M. De Marchi, G. DeMicheli, and Y. Leblebici.
Alternative design methodologies for the next generation logic switch.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 231-234, San Jose, CA, November 7-10 2011.
- [3606]
- S. Safarpour, A. Veneris, G. Baeckler, and R. Yuan.
Efficient SAT-based boolean matching for FPGA technology mapping.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
466-471, San Francisco, CA, July 24-28 2006.
- [3607]
- S. Safarpour and
A. Veneris.
Automated design debugging with abstraction and refinement.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(10):1597-1608, October 2009.
- [3608]
- E. Safi,
A. Moshovos, and A. Veneris.
L-CBF: a low-power, fast counting bloom filter architecture.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 250-255, Tegernsee, Germany, October 4-6 2006.
- [3609]
- E. Safi, P. Akl,
A. Moshovos, and A. Veneris.
On the latency, energy and area of checkpointed, superscalar register alias
tables.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 379-382, Portland, Oregon, August 27-29 2007.
- [3610]
- E. Safi,
A. Moshovos, and A. Veneris.
L-CBF: a low-power, fast counting bloom filter architecture.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(6):628-638, June 2008.
- [3611]
- M. Saint-Laurent, V. G. Oklobdzija, S. S. Singh, and
M. Swaminathan.
Optimal sequencing energy allocation for CMOS integrated systems.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 194-199, San Jose, CA, March 18-21 2002.
- [3612]
- M. Saint-Laurent, B. Mohammad, and P. Bassett.
A 65-nm pulsed latch with a single clocked transistor.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 347-350, Portland, Oregon, August 27-29 2007.
- [3613]
- M. Saint-Laurent.
A model for interlevel coupling noise in multilevel interconnect structures.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(5):834-844, May 2007.
- [3614]
- Karem A.
Sakallah, Yao-Tsung Yen, and Steve S. Greenberg.
The meyer model revisited: explaining and correcting the charge
non-conservation problem.
In IEEE International Conference on Computer-Aided Design, pages
204-207, Santa Clara, CA, Nov. 9-12 1987.
- [3615]
- K. A.
Sakallah, T. N. Mudge, and O. A. Olukotun.
Analysis and design of latch-controlled synchronous digital circuits.
In 27th ACM/IEEE Design Automation Conference, pages 111-117,
Orlando, FL, June 24-28 1990.
- [3616]
- K. A.
Sakallah, T. N. Mudge, and O. A. Olukotun.
Analysis and design of latch-controlled synchronous digital circuits.
IEEE Transactions on Computer-Aided Design, 11(3):322-333, March
1992.
- [3617]
- T. Sakamoto,
T. Yamada, M. Mukuno, Y. Matsushita, Y. Harada, and H. Yasuura.
Power analysis techniques for soc with improved wiring models.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 259-262, Monterey, California, August 12-14 2002.
- [3618]
- K. Sakanushi, S. Nakatake, and Y. Kajitani.
The multi-BSG: stochastic approach to an optimum packing of
convex-rectilinear blocks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
267-274, San Jose, CA, November 8-12 1998.
- [3619]
- K. Sakanushi, Y. Kajitani, and D. P. Mehta.
The quarter-state-sequence floorplan representation.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(3):376-386, March 2003.
- [3620]
- C. M. Sakkas.
Potential distribution and multi-terminal dc resistance computations for LSI
technology.
IBM Journal of Research and Development, 23(6):640-651, November
1979.
- [3621]
- T. Sakurai,
S. Kobayashi, and M. Noda.
Simple expressions for interconnection delay, coupling and crosstalk in
VLSI's.
In 1991 IEEE International Symposium on Circuits and Systems, pages
2375-2378, June 1991.
- [3622]
- T. Sakurai,
B. Lin, and A. R. Newton.
Fast simulated diffusion: an optimization algorithm for multiminimum problems
and its application to MOSFET model parameter extraction.
IEEE Transactions on Computer-Aided Design, 11(2):228-234, February
1992.
- [3623]
- T. Sakurai,
H. Kawaguchi, and T. Kuroda.
Low-power CMOS design through vth control and low-swing circuits.
In 1997 International Symposium on Low Power Electronics and Design,
pages 1-6, Monterey, CA, August 18-20 1997.
- [3624]
- T. Sakurai and
A. Richard Newton.
Delay analysis of series-connected MOSFET circuits.
IEEE Journal of Solid-State Circuits, 26(2):122-131, February
1991.
- [3625]
- T. Sakurai.
Approximation of wiring delay in MOSFET LSI.
IEEE Journal of Solid-State Circuits, SC-18(4):418-426, August
1983.
- [3626]
- T. Sakurai.
Closed-form expressions for interconnection delay, coupling, and crosstalk in
VLSI's.
IEEE Transactions on Electron Devices, 40(1):118-124, January
1993.
- [3627]
- T. Sakurai.
Low-power and high-speed VLSI design with low supply voltage through
cooperation between levels.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 445-450, San Jose, CA, March 18-21 2002.
- [3628]
- T. Sakurai.
Minimizing power across multiple technology and design levels.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 24-27, San Jose, CA, November 10-14 2002.
- [3629]
- A. Saldanha.
Functional timing optimization.
In IEEE/ACM International Conference on Computer-Aided Design, pages
539-543, San Jose, CA, November 7-11 1999.
- [3630]
- R. A. Saleh,
B. A. A. Antao, and J. Singh.
Multilevel and mixed-domain simulation of analog circuits and systems.
IEEE Transactions on Computer-Aided Design, 15(1):68-82, January
1996.
- [3631]
- R. Saleh,
D. Overhauser, and S. Taylor.
Full-chip verification of UDSM designs.
In IEEE/ACM International Conference on Computer-Aided Design, pages
453-460, San Jose, CA, November 8-12 1998.
- [3632]
- R. Saleh, S. Z.
Hussain, S. Rochel, and D. Overhauser.
Clock skew verification in the presence of IR-drop in the power distribution
network.
IEEE Transactions on Computer-Aided Design, 19(6):635-644, June
2000.
- [3633]
- S. Salerno,
A. Bocca, E. Macii, and M. Poncino.
Limited intra-word transition codes: an energy-efficient bus encoding for LCD
display interfaces.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 206-211, Newport Beach, CA, August 9-11 2004.
- [3634]
- E. Salman,
A. Dasdan, F. Taraporevala, K. Kucukcakar, and E. G. Friedman.
Exploiting setup-hold interdependence in static timing analyis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(6):1114-1125, June 2007.
- [3635]
- E. Salman, E. G.
Friedman, R. M. Secareanu, and O. L. Hartin.
Worst case power/ground noise estimation using an equivalent transition time
for resonance.
IEEE Transactions on Circuits and Systems, 56(5):997-1004, May
2009.
- [3636]
- A. Salz and M. Horowitz.
IRSIM: An incremental MOS switch-level simulator.
In 26th ACM/IEEE Design Automation Conference, pages 173-178, Las
Vegas, NV, June 25-29 1989.
- [3637]
- A. Sama,
M Balakrishnan, and J. F. M. Theeuwen.
Speeding up power estimation of embedded software.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 191-196, Italy, July 26-27 2000.
- [3638]
- S. B. Samaan.
The impact of device parameter variations on the frequency and performance of
VLSI chips.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 343-346, San Jose, CA, November 7-11 2004.
- [3639]
- S. K. Samal,
S. Panth, K. Samadi, M. Saedi, Y. Du, and S.-K. Lim.
Fast and accurate thermal modeling and optimization for monolithic 3d ics.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [3640]
- S. K. Samal,
K. Samadi, P. Kamal, Y. Du, and S.-K. Lim.
Full chip impact study of power delivery network designs in monolithic 3d ics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 565-572, San Jose, CA, November 2-6 2014.
- [3641]
- R. Samanta,
G. Venkataraman, N. Shah, and J. Hu.
Elastic timing scheme for power-efficient and robust performance.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 92-97, Austin, Texas,
February 26-27 2007.
- [3642]
- R. Samanta,
G. Venkataraman, and J. Hu.
Clock buffer polarity assignment for power noise reduction.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
17(6):770-780, June 2009.
- [3643]
- M. Sami, D. Sciuto,
C. Silvano, and V. Zaccaria.
An instruction-level energy model for embedded VLIW architectures.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(9):998-1010, September 2002.
- [3644]
- C. Sanchez-Lopez, F. V. Fernandesz, E. Tlelo-Cuautle, and
S.-X.-D. Tan.
Pathological element-based active device models and their application to
symbolic analysis.
IEEE Transactions on Circuits and Systems, 58(6):1382-1395, June
2011.
- [3645]
- I. W. Sandberg.
Causality and the impulse response scandal.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(6):810-811, June 2003.
- [3646]
- M. Saneei,
A. Afzali-Kusha, and Z. Navabi.
Sign bit reduction encoding for low power applications.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
214-217, Anaheim, CA, June 13-17 2005.
- [3647]
- J. V.
Sanghavi, R. K Ranjan, R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
High performance BDD package by exploiting memory hierarchy.
In 33rd Design Automation Conference, pages 635-640, Las Vegas, NV,
June 3-7 1996.
- [3648]
- A. Sangiovanni-Vincentelli, L. Carloni, F. De Bernardinis, and
M. Sgroi.
Benefits and challenges for platform-based design.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
409-414, San Diego, CA, June 7-11 2004.
- [3649]
- A. L.
Sangiovanni-Vincentelli.
Circuit simulation.
In P. Antognetti, D. O. Pederson, and H. De Man, editors, Computer Design
Aids for VLSI Circuits, pages 19-112. Sijthoff & Noordhoff, Alphen aan
den Rijn, The Netherlands; Rockville, MD, USA, 1981.
- [3650]
- A. L.
Sangiovanni-Vincentelli, editor.
Advances in Computer-Aided Engineering Design.
JAI Press Inc., 1985.
- [3651]
- S. S.
Sapatnekar and W. Chuang.
Power vs. delay in gate sizing: conflicting objectives?
In IEEE/ACM International Conference on Computer-Aided Design, pages
463-466, San Jose, CA, November 5-9 1995.
- [3652]
- S. Sapatnekar and
H. Su.
Analysis and optimization of power grids.
IEEE Design & Test of Computers, pages 7-15, May-June 2003.
- [3653]
- S. S. Sapatnekar.
A timing model incorporating the effect of crosstalk on delay and its
application to optimal channel routing.
IEEE Transactions on Computer-Aided Design, 19(5):550-559, May
2000.
- [3654]
- N. Saraf and
K. Bazargan.
Sequential logic to transform probabilities.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 732-738, San Jose, CA, November 18-21 2013.
- [3655]
- D. Saraswat,
R. Achar, and M. Nakhla.
Circuit simulation of s-parameter based interconnects via passive macromodels.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 309-312, Montreal, Quebec, June 20-23 2004.
- [3656]
- D. Saraswat,
R. Achar, and M. S. Nakhla.
Global passivity enforcement algorithm for macromodels of interconnect
subnetowrks characterized by tabulated data.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(7):819-832, July 2005.
- [3657]
- O. Sarbishei, M. Tabandeh, B. Alizadeh, and M. Fujita.
A formal approach for debugging arithmetic circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(5):742-754, May 2009.
- [3658]
- H. K. Sarin and A. J.
McNelly.
A power modeling and characterization method for logic simulation.
In IEEE Custom Integrated Circuits Conference, pages 363-366, Santa
Clara, CA, May 1-4 1995.
- [3659]
- A. Sarkar,
S. Lin, and K. Wang.
A methodology for analysis and verification of power gated circuits with
correlated results.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 351-354, Portland, Oregon, August 27-29 2007.
- [3660]
- M. Sarrafzadeh, F. Dabiri, R. Jafari, T. Massey, and
A. Nahapetan.
Low power light-weight embedded systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 207-212, Tegernsee, Germany, October 4-6 2006.
- [3661]
- D. Sarta,
D. Trifone, and G. Ascia.
A data dependent approach to instruction level power estimation.
In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages
182-190, Como, Italy, March 4-5 1999.
- [3662]
- T. Sasao.
On the numbers of variables to represent sparse logic functions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 45-51, San Jose, CA, November 10-13 2008.
- [3663]
- T. Sassao and
M. Matsuura.
BDD representation for incompletely specified multiple-output logic functions
and its applications to functional decomposition.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
373-378, Anaheim, CA, June 13-17 2005.
- [3664]
- S. Sastry and J-I. Pi.
An investigation into statistical properties of partitioning and floorplanning
problems.
In 26th ACM/IEEE Design Automation Conference, pages 382-387, Las
Vegas, NV, June 25-29 1989.
- [3665]
- A. Sathanur, L. Benini, A. Macii, E. Macii, and M. Poncino.
Fast computation of discharge current upper bounds for clustered power gating.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(1):146-151, January 2011.
- [3666]
- A. Sathanur, L. Benini, A. Macii, E. Macii, and M. Poncino.
Row-based power-gating: a novel sleep transistor insertion methodology for
leakage power optimization in nanometer CMOS circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(3):469-482, March 2011.
- [3667]
- V. S. Sathe, M. C.
Papaefthymiou, and C. H. Ziesler.
A ghz-class charge recovery logic.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 91-94, San Diego, CA, August 8-10 2005.
- [3668]
- H. Sathyamurthy, S. S. Sapatnekar, and J. P. Fishburn.
Speeding up pipelined circuits through a combination of gate sizing and clock
skew optimization.
IEEE Transactions on Computer-Aided Design of Circuits and Systems,
17(2):173-182, February 1998.
- [3669]
- T. Sato, Y. Cao,
K. Agarwal, D. Sylvester, and C. Hu.
Bidirectional closed-form transformation between on-chip coupling noise
waveforms and interconnect delay-change curves.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(5):560-572, May 2003.
- [3670]
- J. H.
Satyanarayana and K. Parhi.
HEAT: Hierarchical energy analysis tool.
In 33rd Design Automation Conference, pages 9-14, Las Vegas, NV, June
3-7 1996.
- [3671]
- J. H.
Satyanarayana and K. K. Parhi.
Theoretical analysis of word-level switching activity in the presence of
glitching and correlation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(2):148-159, April 2000.
- [3672]
- S. Sauter,
D. Schmitt-Landsiedel, R. Thewes, and W. Weber.
Effect of parameter variations at chip and wafer level on clock skews.
IEEE Transactions on Semiconductor Manufacturing, 13(4):395-400,
November 2000.
- [3673]
- I. Savidis,
B. Vaisband, and E. G. Friedman.
Experimental analysis of thermal coupling in 3-D integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(10):2077-2089, October 2015.
- [3674]
- J. Savir, G. S.
Ditlow, and P. H. Bardell.
Random pattern testability.
IEEE Transactions on Computers, C-33(1):79-90, January 1984.
- [3675]
- J. Savir and W. H.
McAnney.
Random pattern testability of delay faults.
In IEEE International Test conference, pages 263-273, Sept. 8-11
1986.
- [3676]
- J. Savir and J. P. Roth.
Testing for, and distinguishing between failures.
In IEEE 12th International Symposium on Fault-Tolerant Computing,
pages 165-172, June 1982.
- [3677]
- P. Saxena and S. Gupta.
On integrating power and signal routing for shield count minimization in
congested regions.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(4):437-445, April 2003.
- [3678]
- B. C. Schafer and
T. Kim.
Hotspots elimination and temperature flattening in VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(11):1475-1487, November 2008.
- [3679]
- B. C. Schafer.
Probabilistic multiknob high-level synthesis design space exploration
acceleration.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(3):394-406, March 2016.
- [3680]
- M. Schaffner, F. K. Gurkaynak, A. Smolic, H. Kaeslin, and
L. Benini.
An aapproximate computing technique for reducing the complexity of a
direct-solver for sparse linear systems in real-time video processing.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [3681]
- L. Scheffer and
E. Nequist.
Why interconnect prediction doesn't work.
In International Workshop on System-Level Interconnect Prediction,
pages 139-144, San Diego, CA, April 8-9 2000.
- [3682]
- L. Scheffer.
The convergence of structured custom and ASIC designs.
In IEEE Custom Integrated Circuits Conference, pages 23-27, Santa
Clara, CA, May 1-4 1995.
- [3683]
- L. K. Scheffer.
CAD implications of new interconnect technologies.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
576-581, San Diego, CA, June 4-8 2007.
- [3684]
- L. K. Scheffer.
Design tools for artificial nervous systems.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
717-722, San Francisco, CA, June 3-7 2012.
- [3685]
- J. Scheible and
J. Lienig.
Automation of analog IC layout - challenges and solutions.
In ACM International Symposium on Physical Design 2015, pages 33-40,
Monterey, California, March 29 - April 1 2015.
- [3686]
- E. Schmidt,
G. von Colln, L. Kruse, F. Theeuwen, and W. Nebel.
Memory power models for multilevel power estimation and optimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(2):106-109, April 2002.
- [3687]
- M. Schmidt,
H. Kinzelbach, and U. Schichtmann.
Variational waveform propagation for accurate statistical timing analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 20-25, Monterey, CA,
February 25-26 2008.
- [3688]
- P. H.
Schneider, U. Schlichtmann, and B. Wurth.
Fast power estimation of large circuits.
IEEE Design & Test of Computers, 13(1):70-78, Spring 1996.
- [3689]
- E. Schneider, S. Holst, X. Wen, and H.-J. Wunderlich.
Data-parallel simulation for fast and accurate timing validation of CMOS
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 17-23, San Jose, CA, November 2-6 2014.
- [3690]
- P. H.
Schneider and S. Krishnamoorthy.
Effects of correlations on accuracy of power analysis - an experimental study.
In International Symposium on Low Power Electronics and Design, pages
113-116, Monterey, CA, August 12-14 1996.
- [3691]
- P. H.
Schneider and U. Schlichtmann.
Decomposition of boolean functions for low power based on a new power
estimation technique.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
123-128, Napa, CA, April 24-27 1994.
- [3692]
- P. R. Schneider.
On the necessity to examine D-chains in diagnostic test generation - an
example.
IBM Journal of Research and Development, 11:114, January 1967.
- [3693]
- A. Schottl.
A reliability model of a system with dependent components.
IEEE Transactions on Reliability, 45(2):267-273, June 1996.
- [3694]
- M. J. Schulte,
A. A. Sinkar, H. RezaGhasemi, and N.-S. Kim.
Cost-effective power delivery to support per-core voltage domains for
power-constrained processors.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
56-61, San Francisco, CA, June 3-7 2012.
- [3695]
- S. C. Schwartz and
Y. S. Yeh.
On the distribution function and moments of power sums with log-normal moments.
The Bell System Technical Journal, 61(7):1441-1462, September
1982.
- [3696]
- D. Scott, S. Tang,
S. Zhao, and M. Nandakumar.
Device physics impact on low leakage, high speed DSP design techniques.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 349-354, San Jose, CA, March 18-21 2002.
- [3697]
- R. M.
Secareanu, S. Warner, S. Seabridge, C. Burke, J. Becerra, T. E. Watrobski,
C. Morton, W. Staub, T. Tellier, I. S. Kourtev, and E. G. Friedman.
Substrate coupling in digital circuits in mixed-signal smart-power systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(1):67-78, January 2004.
- [3698]
- C-J. Seger.
A bounded delay race model.
In IEEE International Conference on Computer-Aided Design, pages
130-133, 1989.
- [3699]
- F. F. Sellers,
Jr., M. Y. Hsiao, and L. W. Bearnson.
Analyzing errors with the boolean difference.
IEEE Transactions on Computers, C-17(7):676-683, July 1968.
- [3700]
- S. Sen.
Channel-adaptive zero-margin & process-adaptive self-healing communication
circuits/systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 80-85, San Jose, CA, November 2-6 2014.
- [3701]
- E. Seneta.
Non-Negative Matrices and Markov Chains.
Springer-Verlag, New York, NY, 1981.
- [3702]
- M. Sengupta,
S. Saxena, L. Daldoss, G. Kramer, S. Minehane, and J. Cheng.
Application specific worst case corners using response surfaces and statistical
models.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 351-356, San Jose, CA, March 22-24 2004.
- [3703]
- M. Sengupta,
S. Szxena, L. Daldoss, G. Kramer, S. Minehane, and J. Cheng.
Application-specific worst case corners using response surfaces and statistical
models.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(9):1372-1380, September 2005.
- [3704]
- D. Sengupta and
R. Saleh.
Generalized power-delay metrics in deep submicron CMOS designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):183-189, January 2007.
- [3705]
- D. Sengupta and
R. Saleh.
Application-driven floorplan-aware voltage island design.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
155-160, Anaheim, CA, June 8-13 2008.
- [3706]
- D. Sengupta and
R. A. Saleh.
Application-driven voltage-island partitioning for low-power system-on-chip
design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(3):316-326, March 2009.
- [3707]
- D. Sengupta and
S. S. Sapatnekar.
Rescale: recalibrating sensor circuits for aging and lifetime estimation under
BTI.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 492-497, San Jose, CA, November 2-6 2014.
- [3708]
- R. Senthinathan, G. Tubbs, and M. Schuelein.
Negative feedback influence on simultaneously switching CMOS outputs.
In IEEE 1988 Custom Integrated Circuits Conference, pages
5.4.1-5.4.5, Rochester, NY, May 16-19 1988.
- [3709]
- J.-S. Seo,
D. Sylvester, D. Blaauw, H. Kaul, and R. Krishnamurthy.
A robust edge encoding technique for energy-efficient multi-cycle interconnect.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 68-73, Portland, Oregon, August 27-29 2007.
- [3710]
- Y.-H. Seo and D.-W. Kim.
A new VLSI architecture of parallel multiplier - accumulator based on radix-2
modified booth algorithm.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):201-208, February 2010.
- [3711]
- M. Seok, S. Hanson,
D. Sylvester, and D. Blaauw.
Analysis and optimization of sleep modes in subthreshold circuit design.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
694-699, San Diego, CA, June 4-8 2007.
- [3712]
- M. Seok.
Decoupling capacitor design strategy for minimizing supply noise of ultra low
voltage circuits.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
968-973, San Francisco, CA, June 3-7 2012.
- [3713]
- J. Seomun,
J. Kim, and Y. Shin.
Skewed flip-flop transformation for minimizing leakage in sequential circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
103-106, San Diego, CA, June 4-8 2007.
- [3714]
- J. Seomun, J.-H.
Kim, and Y. Shin.
Skewed flip-flop and mixed vt gates for minimizing leakage in sequential
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(11):1956-1968, November 2008.
- [3715]
- J. Seomun,
I. Shin, and Y. Shin.
Synthesis and implementation of active mode power gating circuits.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
487-492, Anaheim, CA, June 13-18 2010.
- [3716]
- G. Servel and
D. Deschacht.
On-chip crosstalk evaluation between adjacent interconnections.
In 7th IEEE International Conference on Electronics, Circuits and
Systems, pages 827-830, Beirut, Lebanon, December 17-19 2000.
- [3717]
- S. A. Seshia and
A. Rakhlin.
Game-theoretic timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 575-582, San Jose, CA, November 10-13 2008.
- [3718]
- S. C. Seth, L. Pan,
and V. D. Agrawal.
Predict - probabilistic estimation of digital circuit testability.
In IEEE 15th International Symposium on Fault-Tolerant Computing,
pages 220-225, Ann Arbor, MI, June 19-21 1985.
- [3719]
- S. C. Seth and V. D.
Agrawal.
Cutting chip-testing costs.
IEEE Spectrum, pages 38-45, April 1985.
- [3720]
- M. Severson,
K. Yuen, and Y. Du.
Not so fast my friend: Is near-threshold computing the answer for power
reduction of wireless devices?
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1160-1162, San Francisco, CA, June 3-7 2012.
- [3721]
- K. Sewell,
T. Mudge, D. Blaauw, D. Sylvester, N. Pinckney, R. Dreslinski, and D. Fick.
Assessing the performance limits of parallelized near-threshold computing.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1143-1148, San Francisco, CA, June 3-7 2012.
- [3722]
- A. Shacham,
K. Bergman, and L. P. Carloni.
The case for low-power photonic networks on chip.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
132-135, San Diego, CA, June 4-8 2007.
- [3723]
- O. Shacham,
M. Wachs, A. Danowitz, S. Galal, J. Brunhaver, W. Qadeer,
S. Sankaranarayanan, A. Vassilliev, S. Richardson, and M. Horowitz.
Avoiding game over: bringing design to the next level.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
623-629, San Francisco, CA, June 3-7 2012.
- [3724]
- M. Shafique,
S. Garg, J. Henkel, and D. Marculescu.
The EDA challenges in the dark silicon era.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [3725]
- M. Shafique and
J. Henkel.
Mitigating the power density and temperature problems in the nano-era.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 176-177, Austin TX, November 2-6 2015.
- [3726]
- S. Shah,
A. Srivastava, D. Sharma, D. Sylvester, D. Blaauw, and V. Zolotov.
Discrete vt assignment and gate sizing using a self-snapping continuous
formulation.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 705-712, San Jose, CA, November 6-10 2005.
- [3727]
- S. Shah, P. Gupta,
and A. Kahng.
Standard cell library optimization for leakage reduction.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
983-986, San Francisco, CA, July 24-28 2006.
- [3728]
- K. Shahookar
and P. Mazumder.
A genetic approach to standard cell placement using meta-genetic parameter
optimization.
IEEE Transactions on Computer-Aided Design, 9(5):500-512, May
1990.
- [3729]
- M. Shahriari and
F. Najm.
A gate-level timing model for SOI circuits.
In 8th IEEE International Conference on Electronics, Circuits and
Systems, pages 795-798, St. Julian, Malta, September 2-5 2001.
- [3730]
- N. Shanbhag,
K. Soumyanath, and S. Martin.
Reliable low-power design in the presence of deep submicron noise.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 295-302, Italy, July 26-27 2000.
- [3731]
- N. R.
Shanbhag, R. A. Abdallah, R. Kumar, and D. L. Jones.
Stochastic computation.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
859-864, Anaheim, CA, June 13-18 2010.
- [3732]
- N. R. Shanbhag.
Lower bounds on power-dissipation for DSP algorithms.
In International Symposium on Low Power Electronics and Design, pages
43-48, Monterey, CA, August 12-14 1996.
- [3733]
- N. Shanbhag.
Reliable and energy-efficient digital signal processing.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
830-835, New Orleans, LA, June 10-14 2002.
- [3734]
- N. R. Shanbhag.
A communication-theoretic design paradigm for reliable socs.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 76-76,
San Diego, CA, June 7-11 2004.
- [3735]
- L. Shang, L.-S.
Peh, and N. K. Jha.
Powerherd: a distributed scheme for dynamically satisfying peak-power
constraints in interconnection networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):92-110, January 2006.
- [3736]
- D. Shang,
A. Yakovlev, A. Koelmans, D. Sokolov, and A. Bystrov.
Registers for phase difference based logic.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(6):720-724, June 2007.
- [3737]
- L. Shannon and P. Chow.
SIMPPL: an adaptable soc framework using a programmable controller IP
interface to facilitate design reuse.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(4):377-390, April 2007.
- [3738]
- C. E. Shannon.
A symbolic analysis of relay and switching circuits.
AIEE Transactions, 57:713-723, 1938.
- [3739]
- M. Shao, D. F. Wong,
Y. Gao, L.-P. Yuan, and H. Cao.
Shaping interconnect for uniform current density.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 254-259, San Jose, CA, November 10-14 2002.
- [3740]
- M. J. Sharifi and
D. Baharepour.
A multiloop and full amplitude hysteresis model for molecular electronics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(2):187-196, February 2016.
- [3741]
- M. Sharifkhani and M. Sachdev.
A low power SRAM architecture based on segmented virtual grounding.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 256-261, Tegernsee, Germany, October 4-6 2006.
- [3742]
- M. Sharifkhani and M. Sachdev.
Segmented virtual ground architecture for low-power embedded SRAM.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(2):196-205, February 2007.
- [3743]
- S. Sharifsadeh, J. R. Koehler, A. B. Owen, and J. D. Shott.
Using simulators to model transmitted variability in IC manufacturing.
IEEE Transactions on Semiconductor Manufacturing, 2(3):82-93, August
1989.
- [3744]
- J. Sharkey,
A. Buyuktosunoglu, and P. Bose.
Evaluating design tradeoffs in on-chip power management for cmps.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 44-49, Portland, Oregon, August 27-29 2007.
- [3745]
- M. Shatzkes and
J. R. Lloyd.
A model for conductor failure considering diffusion concurrently with
electromigration resulting in a current exponent of 2.
Journal of Applied Physics, 59(11):3890-3893, June 1986.
- [3746]
- A. Shayan,
X. Hu, H. Peng, M. Popovich, W. Zhang, C.-K. Cheng, Lew C.-E., and X. Chen.
3d power distribution network co-design for nanoscale stacked silicon ics.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 11-14, San Jose, CA, October 27-29 2008.
- [3747]
- A. Shebaita,
C. Amin, F. Dartu, and Y. I. Ismail.
Expanding the frequency range of AWE via time shifting.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 935-938, San Jose, CA, November 6-10 2005.
- [3748]
- A. Shebaita,
D. Petranovic, and Y. I. Ismail.
Importance of volume discretization of single and coupled interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 119-126, San Jose, CA, November 5-9 2006.
- [3749]
- A. Shebaita,
D. Petranovic, and Y. I. Ismail.
Including inductance in static timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 686-691, San Jose, CA, November 5-8 2007.
- [3750]
- A. Shebaita,
D. Das, D. Petranovic, and Y. Ismail.
A noval moment based framework for accurate and efficient static timing
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(8):1258-1262, August 2011.
- [3751]
- B. N. Sheehan.
ENOR: Model order reduction of RLC circuits using nodal equations for
efficient factorization.
In Design Automation Conference, pages 17-21, New Orleans, LA, June
21-25 1999.
- [3752]
- B. N. Sheehan.
TICER: Realizable reduction of extracted RC circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
200-203, San Jose, CA, November 7-11 1999.
- [3753]
- B. N. Sheehan.
Osculating thevenin model for predicting delay and slew of capacitively
characterized cells.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
866-869, New Orleans, LA, June 10-14 2002.
- [3754]
- B. N. Sheehan.
Branch merge reduction of RLCM networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 658-664, San Jose, CA, November 9-13 2003.
- [3755]
- B. Sheehan.
Realizable reduction of RC networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(8):1393-1407, August 2007.
- [3756]
- R. S. Shelar,
S. S. Sapatnekar, P. Saxena, and X. Wang.
A predictive distributed congestion metric with application to technology
mapping.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(5):696-710, May 2005.
- [3757]
- R. S. Shelar and
M. Patyra.
Impact of local interconnects on timing and power in a high performace
microprocessor.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1623-1627, October 2013.
- [3758]
- J. H. Shelly and D. R.
Tryon.
Statistical techniques of timing verification.
In IEEE 20th Design Automation Conference, pages 396-402, 1983.
- [3759]
- J. P. Shen, W. Maly,
and F. J. Ferguson.
Inductive fault analysis of MOS integrated circuits.
Design and Test of Computers, pages 13-26, December 1985.
- [3760]
- A. Shen, A. Ghosh,
S. Devadas, and K. Keutzer.
On average power dissipation and random pattern testability of CMOS
combinational logic networks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
402-407, Santa Clara, CA, November 8-12 1992.
- [3761]
- A. Shen, S. Devadas,
and A. Ghosh.
Probabilistic manipulation of boolean functions using free boolean diagrams.
IEEE Transactions on Computer-Aided Design, 14(1):86-95, January
1995.
- [3762]
- R. Shen, S. X.-D.
Tan, J. Cui, W. Yu, Y. Cai, and G.-S. Chen.
Variational capacitance extraction and modeling based on orthogonal polynomial
method.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(11):1556-1566, November 2010.
- [3763]
- R. Shen, S. X.-D.
Tan, and J. Xiong.
A linear algorithm for full-chip statistical leakage power analysis considering
weak spatial correlation.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
481-486, Anaheim, CA, June 13-18 2010.
- [3764]
- W. Shen, Y. Cai,
X. Hong, and J. Hu.
An effective gated clock tree design based on activity and register aware
placement.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(12):1639-1648, December 2010.
- [3765]
- C. Shen, H. Choi,
S. Chakraborty, and M. Srivastava.
Towards a rich sensing stack for iot devices.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 424-427, San Jose, CA, November 2-6 2014.
- [3766]
- N. V. Shenoy and
W. Nicholls.
An efficient routing database.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
590-595, New Orleans, LA, June 10-14 2002.
- [3767]
- K. L. Shepard,
V. Narayanan, P. C. Elmendorf, and G. Zheng.
Global harmony: coupled noise analysis for full-chip RC interconnect
networks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
139-146, San Jose, CA, November 9-13 1997.
- [3768]
- K. L.
Shepard, V. Narayanan, and R. Rose.
Harmony: Static noise analysis of deep submicron digital integrated circuits.
IEEE Transactions on Computer-Aided Design, 18(8):1132-1150, August
1999.
- [3769]
- K. L. Shepard,
I. Meric, and P. Kim.
Characterization and modeling of graphene field-effect devices.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 406-411, San Jose, CA, November 10-13 2008.
- [3770]
- K. L. Shepard and D.-J.
Kim.
Body-voltage estimation in digital PD-SOI circuits and its application to
static timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
531-538, San Jose, CA, November 7-11 1999.
- [3771]
- K. L. Shepard and D.-J.
Kim.
Static noise analysis for digital integrated circuits in partially-depleted
silicon-on-insulator technology.
In Design Automation Conference, pages 239-242, Los Angeles, CA, June
5-9 2000.
- [3772]
- K. L. Shepard and D.-J.
Kim.
Body-voltage estimation in digital PD-SOI circuits and its application to
static timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(7):888-901, July 2001.
- [3773]
- K. L. Shepard and
D. N. Maynard.
Variability and yield improvement: rules, models and characterization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 834-835, San Jose, CA, November 5-9 2006.
- [3774]
- K. L. Shepard and
V. Narayanan.
Noise in deep submicron digital design.
In IEEE/ACM International Conference on Computer-Aided Design, pages
524-531, San Jose, CA, November 10-14 1996.
- [3775]
- K. L. Shepard.
Design methodologies for noise in digital integrated circuits.
In IEEE/ACM 35th Design Automation Conference, pages 94-99, San
Francisco, CA, June 15-19 1998.
- [3776]
- K. L. Shepard.
CAD issues for CMOS VLSI design in SOI.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 105-110, San Jose, CA, March 26-28 2001.
- [3777]
- K. Sheth,
E. Sarto, and J. McGrath.
The importance of adopting a package-aware chip design flow.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
853-856, San Francisco, CA, July 24-28 2006.
- [3778]
- G. Shi, B. Hu, and
C.-J. R. Shi.
On symbolic model order reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1257-1272, July 2006.
- [3779]
- J. Shi, S. X.-D. Tan,
and J. Fan.
Pattern-based iterative method for extreme large power/ground analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):680-692, April 2007.
- [3780]
- Y. Shi, J. Xiong,
C. Liu, and L. He.
Efficient decoupling capacitance budgeting considering operation and process
variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 803-810, San Jose, CA, November 5-8 2007.
- [3781]
- Y. Shi, J. Xiong,
C. Liu, and L. He.
Efficient decoupling capacitance budgeting considering operation and process
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(7):1253-1263, July 2008.
- [3782]
- J. Shi, Y. Cai,
W. Hou, L. Ma, S. X.-D. Tan, P.-H. Ho, and X. Wang.
GPU friendly fast poisson solver for structured power grid network analysis.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
178-183, San Francisco, CA, July 26-31 2009.
- [3783]
- B. Shi, Y. Zhang, and
A. Srivastava.
Dynamic thermal management under soft thermal constraints.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(11):2045-2054, November 2013.
- [3784]
- W. Shi, M. B.
Alawieh, X. Li, H. Yu, N. Arechiga, and N. Tomatsu.
Efficient statistical validation of machine learning systems for autonomous
driving.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 1-8, Austin TX, November 7-10 2016.
- [3785]
- C. Shi and R. W.
Brodersen.
Automated fixed-point data-type optimization tool for signal processing and
communication systems.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
478-483, San Diego, CA, June 7-11 2004.
- [3786]
- Y. Shi and L. He.
Modeling and design for beyond-the-die power integrity.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 411-416, San Jose, CA, November 7-11 2010.
- [3787]
- K. Shi and D. Howard.
Challenges in sleep transistor design and implementation in low-power designs.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
113-116, San Francisco, CA, July 24-28 2006.
- [3788]
- X. Shi and N. Nicolici.
On-chip generation of uniformly distributed constrained-random stimuli for
post-silicon validation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 808-815, Austin TX, November 2-6 2015.
- [3789]
- X. Shi and N. Nicolici.
On-chip cube-based constrained-random stimuli generation for post-silicon
validation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(7):1012-1025, July 2016.
- [3790]
- G. Shi and C.-J. R. Shi.
Model order reduction by dominant subspace projection: Error bound, subspace
computation, and circuit applications.
IEEE Transactions on Circuits and Systems I: Regular Papers,
52(5):975-993, May 2005.
- [3791]
- C. Shi and K. Zhang.
A robust approach for timing verification.
In IEEE International Conference on Computer-Aided Design, pages
56-59, Nov. 9-12 1987.
- [3792]
- C. Shi and K. Zhang.
Tree relaxation : a new iterative solution method for linear equations.
In IEEE International Conference on Circuits and Systems, pages
2355-2358, 1988.
- [3793]
- G. Shi.
A simple implementation of determinant decision diagram.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 70-76, San Jose, CA, November 7-11 2010.
- [3794]
- G. Shi.
Graph-pair decision diagram construction for topological symbolic circuit
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(2):275-288, February 2013.
- [3795]
- M-C. Shiau and C-Y. Wu.
The signal delay in interconnection lines considering the effect of
small-geometry CMOS inverters.
IEEE Transactions on Circuits and Systems, 37(3):420-425, March
1990.
- [3796]
- H.-C. Shih, P.-W.
Luo, J.-C. Yeh, S.-Y. Lin, D.-M. Kwai, S.-L. Lu, A. Schaefer, and C.-W. Wu.
Dart: a component-based DRAM area, power, and timing modeling tool.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(9):1356-1369, September 2014.
- [3797]
- H-C. Shih and J. A.
Abraham.
Transistor-level test generation for physical failures in CMOS circuits.
In IEEE 23rd Design Automation Conference, pages 243-249, 1986.
- [3798]
- B. Shim, S. R.
Sridhara, and N. R. Shanbhag.
Reliable low-power digital signal processing via reduced precision redundancy.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):497-510, May 2004.
- [3799]
- B. Shim and N. R.
Shanblag.
Energy-efficient soft error-tolerant digital signal processing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(4):336-348, April 2006.
- [3800]
- H. Shimada,
H. Ando, and T. Shimada.
Pipeline stage unification: a low-energy consumption, technique for future
mobile processors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 326-329, Seoul, Korea, August 25-27 2003.
- [3801]
- K. Shimazaki, S. Hirano, and H. Tsujikawa.
An EMI-noise analysis on LSI design with impedance estimation.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 169-174, San Jose, CA, March 18-21 2002.
- [3802]
- Y. Shimda and
K. Sakurai.
A new accurate yield prediction method for system-LSI embedded memories.
IEEE Transactions on Semiconductor Manufacturing, 16(3):436-445,
August 2003.
- [3803]
- T. Shimokawa and
M. Liao.
Goodness-of-fit tests for type-I extreme-value and 2-parameter weibull
distributions.
IEEE Transactions on Reliability, 48(1):79-86, March 1999.
- [3804]
- Y. Shin, S-I Chae,
and K. Choi.
Partial bus-invert coding for power optimization of system level bus.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 127-129, Monterey, CA, August 10-12 1998.
- [3805]
- Y. Shin, S.-I.
Chae, and K. Choi.
Partial bus-invert coding for power optimization of application-specific
systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(2):377-383, April 2001.
- [3806]
- Y. Shin, K. Choi,
and Y.-H. Chang.
Narrow bus encoding for low-power DSP systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(5):656-660, October 2001.
- [3807]
- Y. Shin, S. Paik,
and H.-O. Kim.
Semicustom design of zigzag power-gated circuits in standard cell elements.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(3):327-339, March 2009.
- [3808]
- S. Shin, K. Kim, and
S.-M. Kang.
Compact models for memristors based on charge-flux constitutive relationships.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):590-598, April 2010.
- [3809]
- S. Shin, K. Kim, and
S.-M. Kang.
Resistive computing: memristors-enabled signal multiplication.
IEEE Transactions on Circuits and Systems, 60(5):1241-1249, May
2013.
- [3810]
- I. Shin, J.-J. Kim,
Y.-S. Lin, and Y. Shin.
One-cycle correction of timing errors in pipelines with standard clocked
elements.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(2):600-612, February 2016.
- [3811]
- D. Shin and K. Choi.
Low power high level synthesis by increasing data correlation.
In 1997 International Symposium on Low Power Electronics and Design,
pages 62-67, Monterey, CA, August 18-20 1997.
- [3812]
- Y. Shin and T. Sakurai.
Coupling-driven bus design for low-power application specific systems.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
750-753, Las Vegas, NV, June 18-22 2001.
- [3813]
- Y. Shin and T. Sakurai.
Estimation of power distribution in VLSI interconnects.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 370-375, Huntington Beach, California, August 6-7
2001.
- [3814]
- Y. Shin and T. Sakurai.
Power distribution analysis of VLSI interconnects using model order
reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(6):739-745, June 2002.
- [3815]
- K. Shinkai,
M. Hashimoto, A. Kurokawa, and T. Onoye.
A gate delay model focusing on current fluctuation over wide-range of process
and environmental variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 47-53, San Jose, CA, November 5-9 2006.
- [3816]
- C. G. Shirley.
A defect model of reliability.
In International Reliability Physics Symposium, pages 3.1-3.56, Las
Vegas, NV, April 1995.
- [3817]
- P. P.
Shirvani, N. Saxena, and E. J. McCluskey.
Common-mode failures in redundant VLSI systems: A survey.
IEEE Transactions on Reliability, 49(3):377-387, September 2000.
- [3818]
- W.-T. Shiue and
C. Chakrabarti.
Memory exploration for low power, embedded systems.
In Design Automation Conference, pages 140-145, New Orleans, LA, June
21-25 1999.
- [3819]
- H. Shojaei and
A. Davoodi.
Trace signal selection to enhance timing and logic visibility in post-silicon
validation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 168-172, San Jose, CA, November 7-11 2010.
- [3820]
- M. Shoji.
CMOS Digital Circuit Technology.
Prentice-Hall, Englewood Cliffs, NJ, 1987.
- [3821]
- G. Shomalnasab
and L. Zhang.
New analytic model of coupling and substrate capacitance in nanometer
technologies.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(7):1268-1280, July 2015.
- [3822]
- IU. A. Shreider and
N. P. Buslenko et al.
The Monte Carlo Method.
Pergamon Press, New York, NY, 1966.
- [3823]
- Y.-T. Shyu, J.-M.
Lin, C.-P. Huang, C.-W. Lin, Y.-Z. Lin, and S.-J. Chang.
Effective and efficient approach for power reduction by using multi-bit
flip-flops.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(4):624-635, April 2013.
- [3824]
- Y.-T. Shyu, J.-M.
Lin, C.-C. Lin, C.-P. Huang, and S.-I. Chang.
An efficient and effective methodology to control turn-on sequence of power
switches for power-gating designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(10):1730-1743, October 2016.
- [3825]
- J. Siebert,
J. Collier, and R. Amirtharajah.
Self-timed circuits for energy harvesting AC power supplies.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 315-318, San Diego, CA, August 8-10 2005.
- [3826]
- B. K. Sikdar,
N. Ganguly, and P. P. Chaudhuri.
Generation of test patterns without prohibited pattern set.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(12):1650-1660, December 2004.
- [3827]
- L. G. De Silva,
J. R. Philips, and L. M. Silveira.
Efficient computation of the exact worst-delay corner.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 7-12, Austin, Texas,
February 26-27 2007.
- [3828]
- J. M. S. Silva,
J. R. Phillips, and L. M. Silveira.
Efficient simulation of power grids.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(10):1523-1532, October 2010.
- [3829]
- J. P. M. Silva and
K. Sakallah.
GRASP - A new search algorithm for satisfiability.
In IEEE/ACM International Conference on Computer-Aided Design, pages
220-227, San Jose, CA, November 10-14 1996.
- [3830]
- L. M.
Silveira, J. K. White, H. Neto, and L. Vidigal.
On exponential fitting for circuit simulation.
IEEE Transactions on Computer-Aided Design, 11(5):566-574, May
1992.
- [3831]
- L. M.
Silveira, M. Kamon, and J. White.
Efficient reduced-order modeling of frequency-dependent coupling inductances
associated with 3-D interconnect structures.
In 32nd ACM/IEEE Design Automation Conference, pages 376-380, June
1995.
- [3832]
- L. M.
Silveira, M. Kamon, I. Elfadel, and J. White.
A coordinate-transformed arnoldi algorithm for generating guaranteed stable
reduced-order models of RLC circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
288-294, San Jose, CA, November 10-14 1996.
- [3833]
- L. M. Silveira
and J. R. Phillips.
Exploiting input information in a model reduction algorithm for massively
coupled parasitic networks.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
385-388, San Diego, CA, June 7-11 2004.
- [3834]
- P. Silver, J. C.
Anderson, and R. Murray.
Joint DAC/IWBDA special session engineering biology: fundamentals and
applications.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
220-221, Anaheim, CA, June 13-18 2010.
- [3835]
- V. Simoncini.
Computational methods for linear matrix equations.
Siam Review, 58(3):377-441, September 2016.
- [3836]
- H. Simonis,
N. Nguyen, and M. Dincbas.
Verification of digital circuits using CHIP.
In G. J. Milne, editor, The Fusion of Hardware Design and
Verification, pages 421-442. Elsevier Science Publishers B.V.
(North-Holland), 1988.
- [3837]
- T. Simunic,
L. Benini, and G. De Micheli.
Cycle-accurate simulation of energy consumption in embedded systems.
In Design Automation Conference, pages 867-873, New Orleans, LA, June
21-25 1999.
- [3838]
- T. Simunic,
S. P. Boyd, and P. Glynn.
Managing power consumption in netowrks on chips.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(1):96-107, January 2004.
- [3839]
- E. Singerman, Y. Abarbanel, and S. Baartmans.
Transaction based pre-to-post silicon validation.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
564-568, San Diego, CA, June 5-9 2011.
- [3840]
- D. Singh, J. M.
Rabaey, M. Pedram, F. Catthoor, S. Rajgopal, N. Sehgal, and T. J. Mozdzen.
Power conscious CAD tools and methodologies: A perspective.
In Proceedings of the IEEE, pages 570-593, April 1995.
Published as Proceedings of the IEEE, volume 83, number 4.
- [3841]
- A. Singh,
J. Tharian, and J. Plusquellic.
Path delay estimation using power supply transient signals: a comparative study
using fourier and wavelet analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 748-753, San Jose, CA, November 9-13 2003.
- [3842]
- A. K. Singh,
M. Mani, and M. Orshansky.
Statistical technology mapping for parametric yield.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 511-518, San Jose, CA, November 6-10 2005.
- [3843]
- D. P. Singh,
V. Manohararajah, and S. D. Brown.
Incremental retiming for FPGA physical synthesis.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
433-438, Anaheim, CA, June 13-17 2005.
- [3844]
- J. Singh,
V. Nookala, Z.-Q. Luo, and S. Sapatnekar.
Robust gate sizing by geometric programming.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
315-320, Anaheim, CA, June 13-17 2005.
- [3845]
- H. Singh,
K. Agarwal, D. Sylvester, and K. J. Nowka.
Enhanced leakage reduction techniques using intermediate strength power gating.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(11):1215-1224, November 2007.
- [3846]
- J. Singh, Z.-Q.
Luo, and S. S. Sapatnekar.
A geometric programming-based worst case gate sizing method incorporating
spatial correlation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):295-308, February 2008.
- [3847]
- A. K. Singh,
M. Lok, K. Ragab, C. Caramanis, and M. Orshansky.
An algorithm for exploiting modeling error statistics to enable robust analog
optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 62-69, San Jose, CA, November 7-11 2010.
- [3848]
- A. K. Singh,
K. Ragab, M. Lok, C. Caramanis, and M. Orshansky.
Predictable equation-based analog optimization based on eplicit capture of
modeling error statistics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(10):1485-1498, October 2012.
- [3849]
- R. Singh and N. Bhat.
An offset compensation techniques for latch type sense amplifiers in high-speed
low-power srams.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(6):652-657, June 2004.
- [3850]
- A. Singh and P. Li.
On behavioral model equivalence checking for large analog/mixed signal systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 55-61, San Jose, CA, November 7-11 2010.
- [3851]
- M. Singh and S. M.
Nowick.
Synthesis for logical initializability of synchronous finite-state machines.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(5):542-557, October 2000.
- [3852]
- J. Singh and S. S.
Sapatnekar.
Congestion-aware topology optimization of structured power/ground networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(5):683-695, May 2005.
- [3853]
- J. Singh and
S. Sapatnekar.
Statistical timing analysis with correlated non-gaussian parameters using
independent component analysis.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
155-160, San Francisco, CA, July 24-28 2006.
- [3854]
- J. Singh and S. S.
Sapatnekar.
Partition-based algorithm for power grid design using locality.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(4):664-677, April 2006.
- [3855]
- J. Singh and S. S.
Sapatnekar.
A scalable statistical static timing analyzer incorporating correlated
non-gaussian and gaussian parameter variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(1):160-173, January 2008.
- [3856]
- K. J. Singh and
P. A. Subrahmanyam.
Extracting RTL models from transistor netlists.
In IEEE/ACM International Conference on Computer-Aided Design, pages
11-17, San Jose, CA, November 5-9 1995.
- [3857]
- V. Singh.
Lithography at 14nm and beyond: choices and challenges.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), page 459,
San Diego, CA, June 5-9 2011.
- [3858]
- V. Singhal,
C. Pixley, A. Aziz, and R. K. Brayton.
Theory of safe replacements for sequential circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(2):249-265, February 2001.
- [3859]
- R. Singhal,
G. Choi, and R. Mahapatra.
Information theoretic approach to address delay and reliability in long on-chip
interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 310-314, San Jose, CA, November 5-9 2006.
- [3860]
- R. Singhal,
G. Choi, and R. N. Mahapatra.
Data handling limits of on-chip interconnects.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(6):707-713, June 2008.
- [3861]
- K. Singhal and
V. Visvanathan.
Statistical device models for worst case files and electrical test data.
IEEE Transactions on Semiconductor Manufacturing, 12(4):470-484,
November 1999.
- [3862]
- A. Singhee,
C.-F. Fang, J.-D. Ma, and R. A. Rutenbar.
Probabilistic interval-valued computation: toward a practical surrogate for
statistics inside CAD tools.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
167-172, San Francisco, CA, July 24-28 2006.
- [3863]
- A. Singhee,
C.-F. Fang, J.-D. Ma, and R. A. Rutenbar.
Probabilistic interval-valued computation: toward a practical surrogate for
statistics inside CAD tools.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(12):2317-2330, December 2008.
- [3864]
- A. Singhee,
S. Singhal, and R. A. Rutenbar.
Practical, fast monte carlo statistical static timing analysis: why and how.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 190-195, San Jose, CA, November 10-13 2008.
- [3865]
- A. Singhee and
P. Castalino.
Pareto sampling: choosing the right weights by derivative pursuit.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
913-916, Anaheim, CA, June 13-18 2010.
- [3866]
- A. Singhee and
R. A. Rutenbar.
Beyond low-order statistical response surfaces: latent variable regression for
efficient, highly nonlinear fitting.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
256-261, San Diego, CA, June 4-8 2007.
- [3867]
- A. Singhee and
R. A. Rutenbar.
From finance to flip-flops: a study of fast quasi-monte carlo methods from
computational finance applied to statistical circuit analysis.
In IEEE International Symposium on Quality Electronic Design (ISQED),
San Jose, CA, March 26-28 2007.
- [3868]
- A. Singhee and
R. A. Rutenbar.
Why quasi-monte carlo is better than monte carlo or latin hypercube sampling
for statistical circuit analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(11):1763-1776, November 2010.
- [3869]
- A. Sinha, A. Wang,
and A. P. Chandrakasan.
Algorithmic transforms for efficient energy scalable computation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 31-36, Italy, July 26-27 2000.
- [3870]
- S. Sinha,
A. Mishchenko, and R. K. Brayton.
Topologically constrained logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 679-686, San Jose, CA, November 10-14 2002.
- [3871]
- A. Sinha,
N. Ickes, and A. P. Chandrakasan.
Instruction level and operating system profiling for energy exposed software.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(6):1044-1057, December 2003.
- [3872]
- D. Sinha, N. V.
Shenoy, and H. Zhou.
Statistical gate sizing for timing yield optimization.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 1037-1041, San Jose, CA, November 6-10 2005.
- [3873]
- D. Sinha,
D. Khalil, Y. I. Ismail, and H. Zhou.
A timing dependent power estimation framework considering coupling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 401-407, San Jose, CA, November 5-9 2006.
- [3874]
- D. Sinha, N. V.
Shenoy, and H. Zhou.
Statistical timing yield optimization by gate sizing.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(10):1140-1146, October 2006.
- [3875]
- D. Sinha, H. Zhou,
and N. V. Shenoy.
Advances in computation of the maximum of a set of gaussian random variables.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(8):1522-1533, August 2007.
- [3876]
- D. Sinha,
A. Rubin, C. Visweswariah, F. Borkam, G. Schaeffer, and S. Abbaspour.
Feasible aggressor-set identification under constraints for maximum coupling
noise.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(7):1096-1100, July 2009.
- [3877]
- D. Sinha,
C. Visweswariah, N. Venkateswaran, J. Xiong, and V. Zolotov.
Reversible statistical max/min operation: concept and applications to timing.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1067-1073, San Francisco, CA, June 3-7 2012.
- [3878]
- D. Sinha,
V. Zolotov, J. Hu, S. K. Raghunathan, A. Bhanji, and C. M. Casey.
Generation and use of statistical timing macro-models considering slew and load
variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [3879]
- D. Sinha,
V. Zolotov, S. K. Raghunathan, M. H. Wood, and K. Kalafala.
Practical statistical static timing analysis with current source models.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [3880]
- A. Sinha and A. P.
Chandrakasan.
Jouletrack - A web based tool for software energy profiling.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
220-225, Las Vegas, NV, June 18-22 2001.
- [3881]
- D. Sinha and H. Zhou.
Gate sizimg for crosstalk reduction under timing constraints by lagrangian
relaxation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 14-19, San Jose, CA, November 7-11 2004.
- [3882]
- D. Sinha and H. Zhou.
A unified framework for statistical timing analysis with coupling and multiple
input switching.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 837-843, San Jose, CA, November 6-10 2005.
- [3883]
- D. Sinha and H. Zhou.
Statistical timing analysis with coupling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2965-2975, December 2006.
- [3884]
- A. Sinkar,
T. Park, and N.-S. Kim.
Clamping virtual supply voltage of power-gated circuits for active leakage
reduction and gate-oxide reliability improvement.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(3):580-588, March 2013.
- [3885]
- S. Sirichotiyakul, T. Edwards, C. Oh, J. Zuo, A. Dharchoudhury,
R. Panda, and D. Blaauw.
Stand-by power minimization through simultaneous threshold voltage selection
and circuit sizing.
In Design Automation Conference, pages 436-441, New Orleans, LA, June
21-25 1999.
- [3886]
- S. Sirichotiyakul, D. Blaauw, C. Oh, R. Levy, V. Zolotov, and
J. Zuo.
Driver modeling and alignment for worst-case delay noise.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
720-725, Las Vegas, NV, June 18-22 2001.
- [3887]
- S. Sirichotiyakul, T. Edwards, C. Oh, R. Panda, and D. Blaauw.
Duet: An accurate leakage estimation and optimization tool for dual-vt
circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
10(2):79-90, April 2002.
- [3888]
- D. Sitaram,
Y. Zheng, and K. L. Shepard.
Full-chip, three-dimensional, shapes-based RLC extraction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):711-727, May 2004.
- [3889]
- M. Sivaraman
and A. J. Strojwas.
Timing analysis based on primitive path delay fault identification.
In IEEE/ACM International Conference on Computer-Aided Design, pages
182-189, San Jose, CA, November 9-13 1997.
- [3890]
- M. Sivaraman
and A. J. Strojwas.
Primitive path delay faults: identification and their use in timing analysis.
IEEE Transactions on Computer-Aided Design, 19(11):1347-1362,
November 2000.
- [3891]
- D. Skias, Th.
Haniotakis, Y. Tsiatouhas, and A. Arapoyanni.
A state assignment algorithm for finite state machines.
In 7th IEEE International Conference on Electronics, Circuits and
Systems, pages 823-825, Beirut, Lebanon, December 17-19 2000.
- [3892]
- I. Skliarova and
A. B. Ferrari.
A software/reconfigurable hardware SAT solver.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):408-419, April 2004.
- [3893]
- N. J. A. Sloane.
On finding the paths though a network.
The Bell System Technical Journal, 51(2):371-390, February 1972.
- [3894]
- A. Smith,
A. Veneris, M. Fahim Ali, and A. Viglas.
Fault diagnosis and logic debugging using boolean satisfiability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(10):1606-1621, October 2005.
- [3895]
- D. Smith.
Delving into deep submicron.
Integrated System Design, pages 15-22, February 1995.
- [3896]
- G. Smith.
Platform based design: does it answer the entire soc challenge.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
407-407, San Diego, CA, June 7-11 2004.
- [3897]
- R. Smunyahirun
and E.-L. Tan.
Derivation of the most energy-efficient source functions by using calculus of
variations.
IEEE Transactions on Circuits and Systems, 63(4):494-502, April
2016.
- [3898]
- T. Smy and P. Gunupudi.
Robust simulation of opto-electronic systems by alternating complex envelope
representations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(7):1139-1143, July 2012.
- [3899]
- E. S. Snyder,
A. Kapoor, and C. Anderson.
The impact of statistics on hot-carrier lifetime estimates of n-channel
MOSFETS.
In B. Vasquez, A. Sabnis, K. P. MacWilliams, and J. C. S. Woo, editors,
Microelectronics Manufacturing and Reliability, Proc. SPIE 1802,
pages 180-187. SPIE - The International Society for Optical Engineering,
Bellingham, WA, 1992/93.
- [3900]
- I. M. Sobol.
A Primer for the Monte Carlo Method.
CRC Press, Boca Raton, FL, 1994.
- [3901]
- H. Soeleman,
K. Roy, and B. C. Paul.
Robust subthreshold logic for ultra-low power operation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
9(1):90-99, February 2001.
- [3902]
- H. Soleimani, A. Abmadi, and M. Bavandpour.
Biologically inspired spiking neurons: piecewise linear models and digital
implementation.
IEEE Transactions on Circuits and Systems, 59(12):2991-3004, December
2012.
- [3903]
- A. Solomatnikov, D. Somasekhar, N. Sirisantana, and K. Roy.
Skewed CMOS: noise-tolerant high-performance low-power static circuit family.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(4):469-476, August 2002.
- [3904]
- P. M. Solomon.
A comparison of semiconductor devices for high-speed logic.
In Proceedings of the IEEE, pages 489-510, May 1982.
Published as Proceedings of the IEEE, volume 70, number 5.
- [3905]
- A. K. Somani,
U. R. Sandadi, D. W. Twigg, and T. C. Sharma.
An efficient decomposition technique for markov-chain analysis.
In Annual Reliability and Maintainability Symposium, pages 465-469,
Washington, DC, January 16-19 1995.
- [3906]
- K. Son and M. Soma.
Dynamic life-estimation of CMOS ics in real operating environment: precise
electrical method and MLE.
IEEE Transactions on Reliability, 46(1):31-37, March 1997.
- [3907]
- H.-Y. Song,
K. Nepal, R. I. Bahar, and J. Grodstein.
Timing analysis for full-custom circuits using symbolic DC formulations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1815-1830, September 2006.
- [3908]
- Q. Song, F. Liu,
J. Cao, and W. Yu.
Pinning-controllability analysis of complex networks: an m-matrix approach.
IEEE Transactions on Circuits and Systems, 59(11):2692-2701, November
2012.
- [3909]
- Y. Song, H. Yu, and
S. M. Pudukotai DinakarRao.
Reachability-based robustness verification and optimization of SRAM dynamic
stability under process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(4):585-598, April 2014.
- [3910]
- W. S. Song and L. A.
Glasser.
Power distribution techniques for VLSI circuits.
IEEE Journal of Solid-State Circuits, SC-21(1):150-156, February
1986.
- [3911]
- G. Sorkin.
Asymptotically perfect trivial global routing: a stochastic analysis.
IEEE Transactions on Computer-Aided Design, 6(5):820-827, September
1987.
- [3912]
- P. P.
Sotiriadis, T. Konstantakopoulos, and A. Chandrakasan.
Analysis and implementation of charge recycling for deep sub-micron buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 364-369, Huntington Beach, California, August 6-7
2001.
- [3913]
- P. P.
Sotiriadis and A. Chandrakasan.
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron
technologies.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 322-327, San Jose, CA, November 5-9 2000.
- [3914]
- P. P.
Sotiriadis and A. P. Chandrakasan.
A bus energy model for deep submicron technology.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):341-350, June 2002.
- [3915]
- P. P.
Sotiriadis and A. P. Chandrakasan.
Bus energy reduction by transition pattern coding using a detailed deep
submicrometer bus model.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 50(10):1280-1295, October 2003.
- [3916]
- K.-C. Sou,
A. Megretski, and L. Daniel.
A quasi-convex optimization approach to parameterized model order reduction.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
933-938, Anaheim, CA, June 13-17 2005.
- [3917]
- K.-C. Sou,
A. Megretski, and L. Daniel.
Bounding l2 gain system error generated by approximations of the nonlinear
vector field.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 879-886, San Jose, CA, November 5-8 2007.
- [3918]
- K. C. Sou,
A. Megretski, and L. Daniel.
A quasi-convex optimization approach to parameterized model order reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(3):456-469, March 2008.
- [3919]
- A. Sridhar,
A. Vincenzi, M. Ruggiero, and D. Atienza.
Neural network-based thermal simulation of integrated circuits on gpus.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(1):23-36, January 2012.
- [3920]
- A. Sridhar,
Y. Madhour, D. Atienza, T. Brunschwiler, and J. Thome.
STEAM: a fast compact thermal model for two-phase cooling of integrated
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 256-263, San Jose, CA, November 18-21 2013.
- [3921]
- S. R.
Sridhara, G. Balamurugan, and N. R. Shanbhag.
Joint equalization and coding for on-chip bus communication.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(3):314-318, March 2008.
- [3922]
- S. R. Sridhara
and N. R. Shanbhag.
Coding for system-on-chip networks: a unified framework.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
103-106, San Diego, CA, June 7-11 2004.
- [3923]
- S. Sridhara and
N. R. Shanbhag.
Coding for system-on-chip networks: a unified framework.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):655-667, June 2005.
- [3924]
- S. R. Sridhara
and N. R. Shanbhag.
A low-power bus design using joint repeater insertion and coding.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 99-102, San Diego, CA, August 8-10 2005.
- [3925]
- S. R. Sridhara
and N. R. Shanbhag.
Coding for reliable on-chip buses: a class of fundamental bounds and practical
codes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(5):977-982, May 2007.
- [3926]
- H. C.
Srinivasaiah and N. Bhat.
Mixed-mode simulation approach to characterize the circuit delay sensitivity to
implant dose variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(6):742-747, June 2003.
- [3927]
- A. Srinivasan, G. D. Huber, and D. P. LaPotin.
Accurate area and delay estimation from RTL descriptions.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(1):168-172, March 1998.
- [3928]
- S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir,
Y. Xie, and M. J. Irwin.
Improving soft-error tolerance of FPGA configuration bits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 107-110, San Jose, CA, November 7-11 2004.
- [3929]
- S. Srinivasan and K. Sarpatwari.
Flaw: FPGA lifetime awareness.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
630-635, San Francisco, CA, July 24-28 2006.
- [3930]
- T. Sripramong
and C. Toumazou.
The invention of CMOS amplifiers using genetic programming and current-flow
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(11):1237-1252, November 2002.
- [3931]
- M. B.
Srivastava, A. P. Chandrakasan, and R. W. Brodersen.
Predictive system shutdown and other architectural techniques for energy
efficient programmable computation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
4(1):42-55, March 1996.
- [3932]
- A. Srivastava, R. Bai, D. Blaauw, and D. Sylvester.
Modeling and analysis of leakage power considering within-die process
variations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 64-67, Monterey, California, August 12-14 2002.
- [3933]
- A. Srivastava, R. Kastner, C. Chen, and M. Sarrafzadeh.
Timing driven gate duplication.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(1):42-51, January 2004.
- [3934]
- A. Srivastava, D. Sylvester, and D. Blaauw.
Power minimization using simultaneous gate sizing, dual-vdd and dual-vth
assignment.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
783-787, San Diego, CA, June 7-11 2004.
- [3935]
- A. Srivastava, D. Sylvester, and D. Blaauw.
Statistical optimization of leakage power considering process variations using
dual-vth and sizing.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
773-778, San Diego, CA, June 7-11 2004.
- [3936]
- A. Srivastava, S. Shah, K. Agarwal, D. Sylvester, D. Blaauw, and
S. Director.
Accurate and efficient gate-level parametric yield estimation considering
correlated variations in leakage power and performance.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
535-540, Anaheim, CA, June 13-17 2005.
- [3937]
- A. Srivastava, T. Kachru, and D. Sylvester.
Low-power-design space exploration considering process variation using robust
optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):67-79, January 2007.
- [3938]
- A. Srivastava, K. Chopra, S. Shah, D. Sylvester, and D. Blaauw.
A novel approach to perform gate-level yield analysis and optimization
considering correlated variations in power and performance.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):272-285, February 2008.
- [3939]
- N. Srivastava and K. Banerjee.
Performance analysis of carbon nanotube interconnects for VLSI applications.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 383-390, San Jose, CA, November 6-10 2005.
- [3940]
- M. Srivastava and M. Potkonjak.
Power optimization in programmable processors and ASIC implementations of
linear systems: transformation-based approach.
In 33rd Design Automation Conference, pages 343-348, Las Vegas, NV,
June 3-7 1996.
- [3941]
- S. Srivastava and J. Roychowdhury.
Interdependent latch setup/hold time characterization via euler-newton curve
tracing on state-transition equations.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
136-141, San Diego, CA, June 4-8 2007.
- [3942]
- S. Srivastava and J. Roychowdhury.
Rapid and accurate latch characterization via direct newton solution of
setup/hold times.
Design, Automation and Test in Europe (DATE-07), pages 1006-1011,
April 16-20 2007.
- [3943]
- S. Srivastava and J. Roychowdhury.
Independent and interdependent latch setup/hold time characterization via
newton-raphson solution and euler curve tracking of state-transition
equations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(5):817-830, May 2008.
- [3944]
- A. Srivastava and M. Sarrafzadeh.
Predictabilitly: definition, analysis, and optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 118-121, San Jose, CA, November 10-14 2002.
- [3945]
- A. Srivastava and D. Sylvester.
A general framework for probabilistic low-power design space exploration
considering process variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 808-813, San Jose, CA, November 7-11 2004.
- [3946]
- A. Srivastava and D. Sylvester.
Minimizing total power by simultaneous vdd/vth assignment.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(5):665-677, May 2004.
- [3947]
- A. Srivastava.
Simultaneous vt selection and assignment for leakage optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 146-151, Seoul, Korea, August 25-27 2003.
- [3948]
- G. I. Stamoulis.
A monte-carlo approach for the accurate and efficient estimation of average
transition probabilities in sequential logic circuits.
In IEEE 1996 Custom Integrated Circuits Conference, pages 221-224,
San Diego, CA, May 5-8 1996.
- [3949]
- M. R. Stan and W. P.
Burleson.
Limited-weight codes for low-power I/O.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
209-214, Napa, CA, April 24-27 1994.
- [3950]
- M. R. Stan and W. P.
Burleson.
Bus-invert coding for low power I/O.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
3(1):49-58, March 1995.
- [3951]
- M. R. Stan and W. P.
Burleson.
Two-dimensional codes for low power.
In International Symposium on Low Power Electronics and Design, pages
335-340, Monterey, CA, August 12-14 1996.
- [3952]
- M. R. Stan and W. P.
Burleson.
Low-power encodings for global communication in CMOS VLSI.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
5(4):444-455, December 1997.
- [3953]
- T. Stanion and
C. Sechen.
Maximum projections of don't care conditions in a boolean network.
In IEEE International Conference on Computer-Aided Design, pages
674-679, Santa Clara, CA, 1993.
- [3954]
- P. Stanley-Marbell and M. S. Hsiao.
Fast, flexible cycle-accurate energy estimation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 141-146, Huntington Beach, California, August 6-7
2001.
- [3955]
- C. H. Stapper.
Modeling of integrated circuit defect sensitivities.
IBM Journal of Research and Development, 27(6):549-557, November
1983.
- [3956]
- D. Stark and
M. Horowitz.
Analyzing CMOS power supply networks using ariel.
In 25th ACM/IEEE Design Automation Conference, pages 460-464,
Anaheim, CA, June 12-15 1988.
- [3957]
- D. Stark and
M. Horowitz.
Techniques for calculating currents and voltages in VLSI power supply
networks.
IEEE Transactions on Computer-Aided Design, 9(2):126-132, February
1990.
- [3958]
- G. Steele,
D. Overhauser, S. Rochel, and S. Z. Hussain.
Full-chip verification methods for DSM power distribution systems.
In IEEE/ACM 35th Design Automation Conference, pages 744-749, San
Francisco, CA, June 15-19 1998.
- [3959]
- S. Steinhorst
and L. Hedrich.
Trajectory-directed discrete state space modeling for formal verification of
nonlinear analog circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 202-209, San Jose, CA, November 5-8 2012.
- [3960]
- P. Stephan,
R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
Combinational test generation using satisfiability.
IEEE Transactions on Computer-Aided Design, 15(9):1167-1176,
September 1996.
- [3961]
- I. Stevanovic and C. C. McAndrew.
Corrections to "quadratic backward propagation of variance for nonlinear
statistical circuit modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(12):1896-1896, December 2009.
- [3962]
- I. Stevanovic and C. C. McAndrew.
Quadratic backward propagation of variance for nonlinear statistical circuit
modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(9):1428-1432, September 2009.
- [3963]
- K. S. Stevens and
F. Dartu.
Algorithms for MIS vector generation and pruning.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 408-414, San Jose, CA, November 5-9 2006.
- [3964]
- T. Stohr, M. Alt,
A. Hetzel, and J. Koehl.
Analysis, reduction and avoidance of crosstalk on VLSI chips.
In ACM/IEEE International Symposium on Physical Design, pages
211-218, Monterey, CA, April 6-8 1998.
- [3965]
- V. Stojanovic, V. G. Oklobdzija, and R. Bajwa.
A unified approach in the analysis of latches and flip-flops for low-power
systems.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 227-232, Monterey, CA, August 10-12 1998.
- [3966]
- T. Stojanovski and L. Kocarev.
Chaos-based random number generators - part I: Analysis.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(3):281-289, March 2001.
- [3967]
- T. Stojanovski and L. Kocarev.
Chaos-based random number generators - part II: Practical realizations.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 48(3):382-385, March 2001.
- [3968]
- V. Stopjakova, P. Malosek, M. Matej, V. Nagy, and M. Margala.
Defect detection in analog and mixed circuits by neural networks using wavelet
analysis.
IEEE Transactions on Reliability, 54(3):441-448, September 2005.
- [3969]
- M. Storace and O. De
Feo.
Piecewise-linear approximation of nonlinear dynamical systems.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(4):830-842, April 2004.
- [3970]
- H.-G.
Stratigopoulos and S. Mir.
Analog test metrics estimates with PPM accuracy.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 241-247, San Jose, CA, November 7-11 2010.
- [3971]
- Ben G. Streetman.
Solid State Electronic Devices.
Prentice Hall, Inc., Englewood Cliffs, NJ, 1995.
- [3972]
- A. Strojwas,
T. Jhaveri, V. Rovner, and L. T. Pileggi.
Creating an affordable 22nm node using design-lithography co-optimization.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 95-96,
San Francisco, CA, July 26-31 2009.
- [3973]
- A. G. M.
Strollo, E. Napoli, and C. Cimino.
Analysis of power dissipation in double edge-triggered flip-flops.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(5):624-629, October 2000.
- [3974]
- A. G. M.
Strollo, D. De Caro, E. Napoli, and N. Petra.
A novel high-speed sense-amplifier-based flip-flop.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1266-1274, November 2005.
- [3975]
- D. Stroobandt
and F. J. Kurdahi.
On the characterization of multi-point nets in electronic design.
In IEEE Eighth Great Lakes Symposium on VLSI, pages 344-350,
Lafayette, LA, February 19-21 1998.
- [3976]
- M. A. Styblinski
and M. Huang.
Drift reliability optimization in IC design: generalized formulation and
practical examples.
IEEE Transactions on Computer-Aided Design, 12(8):1242-1252, August
1993.
- [3977]
- S-L. Su, V. B. Rao, and
T. N. Trick.
A simple and accurate node reduction technique for interconnect modeling in
circuit extraction.
In IEEE International Conference on Computer-Aided Design, pages
270-273, 1986.
- [3978]
- H.-P. Su, A. C.-H. Wu,
and Y.-L. Lin.
A timing-driven soft-macro placement and resynthesis method in interaction with
chip floorplanning.
IEEE Transactions on Computer-Aided Design, 18(4):475-483, April
1999.
- [3979]
- H. Su, K. H. Gala, and
S. S. Sapatnekar.
Fast analysis and optimization of power/ground networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 477-480, San Jose, CA, November 5-9 2000.
- [3980]
- P. Su, S. K. H. Fung,
W. Liu, and C. Hu.
Studying the impact of gate tunneling on dynamic behaviors of
partially-depleted SOI CMOS using BSIMPD.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 487-491, San Jose, CA, March 18-21 2002.
- [3981]
- Q. Su, A V.
Balakrishnan, and C.-K. Koh.
A factorization-based framework for passivity-preserving model order reduction
of RLC systems.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages 40-45,
New Orleans, LA, June 10-14 2002.
- [3982]
- H. Su, E. Acar, and
S. R. Nassif.
Power grid reduction based on algebraic multigrid principles.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
109-112, Anaheim, CA, June 2-6 2003.
- [3983]
- H. Su, K. H. Gala, and
S. S. Sapatnekar.
Analysis and optimization of structured power/ground networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(11):1533-1544, November 2003.
- [3984]
- H. Su, F. Liu,
A. Devgan, E. Acar, and S. Nassif.
Full chip leakage estimation considering power supply and temperature
variations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 78-83, Seoul, Korea, August 25-27 2003.
- [3985]
- H. Su, S. S.
Sapatnekar, and S. R. Nassif.
Optimal decoupling capacitor sizing and placement for standard-cell layout
designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(4):428-436, April 2003.
- [3986]
- H. Su, J. Hu, S. S.
Sapatnekar, and S. R. Nassif.
A methodology for the simultaneous design of supply and signal networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(12):1614-1624, December 2004.
- [3987]
- Y. Su, J. Wang,
X. Zeng, Z. Bai, C. Chiang, and D. Zhou.
SAPOR: second-order arnoldi method for passive order reduction of RCS
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 74-79, San Jose, CA, November 7-11 2004.
- [3988]
- H. Su, D. Widiger,
C. Kashyap, F. Liu, and B. Krauter.
A noise-driven effective capacitance method with fast embedded noise rule
calculation for functional noise analysis.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
186-189, Anaheim, CA, June 13-17 2005.
- [3989]
- F. Su, K. Chakrabarty,
and R. B. Fair.
Microfluidics-based biochips: technology issues, implementation platforms, and
design-automation challenges.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(2):211-223, February 2006.
- [3990]
- J. Su, T. Tu, and L. He.
A quantum annealing approach for boolean satisfiability problem.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [3991]
- B.-Y. Su and Y.-W. Chang.
An exact jumper insertion algorithm for antenna effect avoidance/fixing.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
325-328, Anaheim, CA, June 13-17 2005.
- [3992]
- Y. Su and W. Rao.
Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping
and morphing simultaneously.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 456-462, San Jose, CA, November 7-10 2011.
- [3993]
- J. S. Suehle and H. A.
Schafft.
Current density dependence of electromigration t50 enhancement due to pulsed
operation.
In IEEE 28th International Reliability Physics Symposium, pages
106-110, New Orleans, LA, March 27-29 1990.
- [3994]
- D. S.
Sugiharto, C. Y. Yang, H. Le, and J. E. Chung.
Beating the heat.
IEEE Circuits and Devices Magazine, 14(5):43-51, September 1998.
- [3995]
- A. Suissa,
O. Romain, J. Denoulet, K. Hachicha, and P. Garda.
Empirical method based on neural networks for analog power modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(5):839-844, May 2010.
- [3996]
- V. Sukharev,
X. Huang, H.-B. Chen, and S.-X.-D. Tan.
IR-drop based electromigration assessment: parametric failure chip-scale
analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 428-433, San Jose, CA, November 2-6 2014.
- [3997]
- V. Sukharev,
X. Huang, and X.-D. Tan.
Electromigration induced stress evolution under alternate current and pulse
current loads.
Journal of Applied Physics, 118(3), July 21 2015.
- [3998]
- V. Sukharev,
A. Kteyan, J.-H. Choy, S. Chatterjee, and F. N. Najm.
Theoretical predictions of EM-induced degradation in test-structures and
on-chip power grids with analytical and numerical analysis.
In IEEE International Reliability Physics Symposium (IRPS), page 6B.5,
Monterey, CA, April 2-6 2017.
- [3999]
- V. Sukharev.
Physically based simulation of electromigration-induced degradation mechanisms
in dual-inlaid copper interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(9):1326-1335, September 2005.
- [4000]
- A. K.
Sultania, D. Sylvester, and S. S. Sapatnekar.
Tradeoffs between gate oxide leakage and delay for dual tox circuits.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
761-766, San Diego, CA, June 7-11 2004.
- [4001]
- A. K.
Sultania, D. Sylvester, and S. S. Sapatnekar.
Gate oxide leakage and delay tradeoffs for dual-tox circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(12):1362-1375, December 2005.
- [4002]
- M. Sumita,
S. Sakiyama, M. Kinoshita, Y. Araki, Y. Ikeda, and K. Fukuoka.
Mixed body-bias technologies with fixed vt and ids generation circuits.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 233-234, Austin, TX, May 9 - 11 2005.
- [4003]
- M. Sumita.
High resolution body bias techniques for reducing the impacts of leakage
current and parasitic bipolar.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 203-208, San Diego, CA, August 8-10 2005.
- [4004]
- S.-Z. Sun, D. H. C.
Du, and H.-C. Chen.
Efficient timing analysis for CMOS circuits considering data dependent
delays.
IEEE Transactions on Computer-Aided Design, 17(6):546-552, June
1998.
- [4005]
- K. Sun, Q. Zhou,
K. Mohanram, and D. C. Sorensen.
Parallel domain decomposition for simulation of large-scale power grids.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 54-59, San Jose, CA, November 5-8 2007.
- [4006]
- J. Sun, J. Li, D. Ma,
and J. M. Wang.
Chebyshev affine-arithmetic-based parametric yield prediction under limited
descriptions of uncertainty.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1852-1865, October 2008.
- [4007]
- X. Sun, P. Nuzzo,
C.-C. Wu, and A. Sangiovanni-Vincentelli.
Contract-based system-level composition for analog circuits.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
605-610, San Francisco, CA, July 26-31 2009.
- [4008]
- P. Sun, X. Li, and
M.-Y. Ting.
Efficient incremental analysis of on-chip power grid via sparse approximation.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
676-681, San Diego, CA, June 5-9 2011.
- [4009]
- J. Sun, P. Gupta,
and J. Roveda.
A new uncertainty budgeting based method for robust analog/mixed-signal design.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
529-535, San Francisco, CA, June 3-7 2012.
- [4010]
- S. Sun, M. Monga,
P. H. Jones, and J. Zambreno.
An I/O bandwidth-sensitive sparse matrix-vector multiplication engine on
fpgas.
IEEE Transactions on Circuits and Systems, 59(1):113-123, January
2012.
- [4011]
- S. Sun, X. Li, H. Liu,
K. Luo, and B. Gu.
Fast statistical analysis of rate circuit failure events via scaled-sigma
sampling for high-dimensional variation space.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(7):1096-1109, July 2015.
- [4012]
- Z. Sun, E. Demircan,
M. D. Shroff, T. Kim, X. Huang, and S.-X.-D. Tan.
Voltage-based electromigration immortality check for general multi-branch
interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [4013]
- S. Sun and X. Li.
Fast statistical analysis of rare circuit failure events via subset simulation
in high-dimensional variation space.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 324-331, San Jose, CA, November 2-6 2014.
- [4014]
- S. Sun and X. Li.
Fast statistical analysis of rare failure events for memory circuits in
high-dimensional variation space.
In 20th Asia and South Pacific Design Automation Conference, pages
302-307, Chiba/Tokyo, Japan, January 19-22 2015.
- [4015]
- V. Sundararajan, S. S. Sapatnekar, and K. K. Parhi.
Fast and exact transistor sizing based on iterative relaxation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(5):568-581, May 2002.
- [4016]
- V. Sundararajan and K. K. Parhi.
Low power synthesis of dual threshold voltage CMOS VLSI circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 139-144, San Diego, CA, August 16-17 1999.
- [4017]
- K. Sundaresan and N. R. Mohapatra.
An analysis of timing violations due to spatially distributed thermal effects
in global wires.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
515-520, San Diego, CA, June 4-8 2007.
- [4018]
- R. Sundblad and
C. Svensson.
Fully dynamic switch-level simulation of CMOS circuits.
IEEE Transactions on Computer-Aided Design, CAD-6(2):282-289, March
1987.
- [4019]
- D. C. Suresh,
B. Agrawal, and W. Najjar.
A tunable bus encoder for off-chip data buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 319-322, San Diego, CA, August 8-10 2005.
- [4020]
- O. Suvak and A. Demir.
Computing quadratic approximations for the isochrons of oscillators: a general
theory and advanced numerical methods.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 397-402, San Jose, CA, November 2-5 2009.
- [4021]
- C. Svensson and
A. Alvandpour.
Low power and low voltage CMOS digital circuit techniques.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 7-10, Monterey, CA, August 10-12 1998.
- [4022]
- C. Svensson and
D. Liu.
A power estimation tool and prospects of power savings in CMOS VLSI chips.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
171-176, Napa, CA, April 24-27 1994.
- [4023]
- V. Swaminathan and K. Chakrabarty.
Generalized network flow techniques for dynamic voltage scaling in hard
real-time systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 21-25, San Jose, CA, November 9-13 2003.
- [4024]
- V. Swaminathan and K. Chakrabarty.
Network flow techniques for dynamic voltage scaling in hard real-time systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(10):1385-1398, October 2004.
- [4025]
- D. Sylvester and
K. Keutzer.
Getting to the bottom of deep sub-micron.
In IEEE/ACM International Conference on Computer-Aided Design, pages
203-211, San Jose, CA, November 8-12 1998.
- [4026]
- D. Sylvester and
K. Keutzer.
Getting to the bottom of deep submicron II: A global wiring paradigm.
In 1999 International Symposium on Physical Design, pages 193-200,
Monterey, CA, April 12-14 1999.
- [4027]
- D. Sylvester and
K. Keutzer.
A global wiring paradigm for deep submicron design.
IEEE Transactions on Computer-Aided Design, 19(2):242-252, February
2000.
- [4028]
- S. M. Sze.
VLSI Technology.
McGraw-Hill Book Company, New York, NY, 1983.
- [4029]
- J. Sztipanovits, T. Bapty, S. Neema, X. Koutsoukos, and
E. Jackson.
Design tool chain for cyber-physical systems: lessons learned.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4030]
- H. Szu and R. Hartley.
Fast simulated annealing.
Physics Letters A, 122(3,4):157-162, June 8 1987.
- [4031]
- T. H.
Szymanski, H. Wu, and A. Gourgy.
Power complexity of multiplexer-based optoelectronic crossbar switches.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(5):604-617, May 2005.
- [4032]
- T. G. Szymanski.
Leadout: a static timing analyzer for MOS circuits.
In IEEE International Conference on Computer-Aided Design, pages
130-133, Santa Clara, CA, Nov. 11-13 1986.
- [4033]
- A. Tabbara,
R. K. Brayton, and A. R. Newton.
Retiming for DSM with area-delay trade-offs and delay constraints.
In Design Automation Conference, pages 725-730, New Orleans, LA, June
21-25 1999.
- [4034]
- M. Tachibana, S. Kurosawa, R. Nojima, N. Kojima, M. Yamada,
T. Mitsushashi, and N. Goto.
Power and area optimization by reorganizing CMOS complex gate circuits.
In ACM/IEEE International Symposium on Low Power Design, pages
155-160, Dana Point, CA, April 23-26 1995.
- [4035]
- D. Tadesse,
D. Sheffield, E. Lenge, R. I. Bahar, and J. Grodstein.
Accurate timing analysis using SAT and pattern-dependent delay models.
Design, Automation and Test in Europe (DATE-07), pages 1018-1023,
April 16-20 2007.
- [4036]
- M. Tadeusiewicz.
A method for finding bounds on all the dc solutions of transistor circuits.
IEEE Transactions on Circuits and Systems - I, 39(7):557-564, July
1992.
- [4037]
- P. Tafertshofer, A. Ganz, and K. J. Antreich.
IGRAINE - an implication graph-based engine for fast implication,
justification, and propagation.
IEEE Transactions on Computer-Aided Design, 19(8):907-927, August
2000.
- [4038]
- M. B. Tahoori.
A mapping algorithm for defect-tolerance of reconfigurable nano-architectures.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 668-672, San Jose, CA, November 6-10 2005.
- [4039]
- M. B. Tahoori.
Application-independent defect-tolerant crossbar nano-archiectures.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 730-734, San Jose, CA, November 5-9 2006.
- [4040]
- A. Tajalli and
Y. Leblebici.
Design trade-offs in ultra-low-power digital nanoscale CMOS.
IEEE Transactions on Circuits and Systems, 58(9):2189-2200, September
2011.
- [4041]
- H. Takahashi, K. J. Keller, K. T. Le, K. K. Saluja, and
Y. Takamatsu.
A method for reducing the target fault list of crosstalk faults in synchronous
sequential circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(2):252-263, February 2005.
- [4042]
- S. Takahashi, Y. Yoshida, and S. Tsukiyama.
A gaussian mixture model for statistical timing analysis.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
110-115, San Francisco, CA, July 26-31 2009.
- [4043]
- Y. Takashima.
Analytical placement for rectilinear blocks.
In 20th Asia and South Pacific Design Automation Conference, pages
220-225, Chiba/Tokyo, Japan, January 19-22 2015.
- [4044]
- K. Takeuchi,
K. Yanagisawa, T. Sato, K. Sakamoto, and S. Hojo.
Probabilistic crosstalk delay estimation for asics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1377-1383, September 2004.
- [4045]
- K. Takeuchi,
M. Shimada, T. Sato, Y. Katsuki, H. Yoshikawa, and H. Matsushita.
Spatial distribution measurement of dynamic voltage drop caused by pulse and
periodic injection of spot noise.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(1):164-168, January 2013.
- [4046]
- E. Talpes and
D. Marculescu.
Toward a multiple clock/voltage island design style for power-aware processors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(5):591-603, May 2005.
- [4047]
- K. H. Tam, Y. Yu,
L. He, T. T. Jing, and X. Zhang.
Dual-vdd buffer insertion for power reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(8):1498-1502, August 2008.
- [4048]
- W.-C. Tam and S. Blanton.
To DFM or not to DFM?
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
65-70, San Diego, CA, June 5-9 2011.
- [4049]
- R. Tamhankar, S. Murali, S. Stergiou, A. Pullini, F. Angiolini,
L. Benini, and G. De Micheli.
Timing-error-tolerant network-on-chip design methodology.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(7):1297-1310, July 2007.
- [4050]
- Y. Tamiya,
Y. Matsunaga, and M. Fujita.
LP based cell selection with constraints of timing, area and power
consumption.
In IEEE/ACM International Conference on Computer-Aided Design, pages
378-381, San Jose, CA, November 6-10 1994.
- [4051]
- X.-D. Tan, C.-J. R.
Shi, D. Lungeanu, J.-C. Lee, and L.-P. Yuan.
Reliability-constrained area optimization of VLSI power/ground networks via
sequence of linear programmings.
In Design Automation Conference, pages 78-83, New Orleans, LA, June
21-25 1999.
- [4052]
- T. K. Tan,
A. Raghunathan, G. Lakshminarayana, and N. K. Jha.
High-level software energy macro-modeling.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
605-610, Las Vegas, NV, June 18-22 2001.
- [4053]
- T. K. Tan,
A. Raghunathan, G. Lakshminarayana, and N. K. Jha.
High-level energy macromodeling of embedded software.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(9):1037-1050, September 2002.
- [4054]
- S. X.-D. Tan,
C.-J. R. Shi, and J.-C. Lee.
Reliability-constrained area optimization of VLSI power/ground networks via
sequence of linear programmings.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(12):1678-1684, December 2003.
- [4055]
- X.-D. Tan and C.-J. R. Shi.
Fast power/ground network optimization based on equivalent circuit modeling.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
550-554, Las Vegas, NV, June 18-22 2001.
- [4056]
- S. X.-D. Tan and C.-J. R. Shi.
Efficient very large scale integration power/ground network sizing based on
equivalent circuit modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(3):277-284, March 2003.
- [4057]
- S. X.-D. Tan and C.-J. R. Shi.
Efficient approximation of symbolic expressions for analog behavioral modeling
and analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):907-918, June 2004.
- [4058]
- S. X.-D. Tan.
A general s-domain hierarchical network reduction algorithm.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 650-657, San Jose, CA, November 9-13 2003.
- [4059]
- S. X.-D. Tan.
A general hierarchical circuit modeling and simulation algorithm.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):418-434, March 2005.
- [4060]
- H.-A. Tanaka,
A. Hasegawa, H. Mizuno, and T. Endo.
Synchronizability of distributed clock oscillators.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(9):1271-1278, September 2002.
- [4061]
- X. Tang, V. K. De,
and J. D. Meindl.
Effects of random MOSFET parameter fluctuations on total power consumption.
In International Symposium on Low Power Electronics and Design, pages
233-236, Monterey, CA, August 12-14 1996.
- [4062]
- L. C. Tang, Y. Lu,
and E. P. Chew.
Mean residual life of lifetime distributions.
IEEE Transactions on Reliability, 48(1):73-78, March 1999.
- [4063]
- Z. Tang, N. Chang,
S. Lin, W. Xie, O. S. Nakagawa, and L. He.
Instruction prediction for step power reduction.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 211-216, San Jose, CA, March 26-28 2001.
- [4064]
- S. Tang,
S. Narendra, and V. De.
Temperature and process invariant MOS-based reference current generation
circuits for sub-1v operation.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 199-204, Seoul, Korea, August 25-27 2003.
- [4065]
- X. Tang, H. Zhou,
and P. Banerjee.
Leakage power optimization with dual-vth library in high-level synthesis.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
202-207, Anaheim, CA, June 13-17 2005.
- [4066]
- X. Tang, R. Tian,
and M.-D.-F. Wong.
Minimizing wire length in floorplanning.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1744-1783, September 2006.
- [4067]
- X. Tang, X. Yuan,
and M. S. Gray.
Practical method for obtaining a feasible integer solution in hierarchical
layout optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 99-104, San Jose, CA, November 5-8 2007.
- [4068]
- Q. Tang, A. Zjajo,
M. Berkelaar, and N. van der Meijs.
RDE-based transistor-level gate simulation for statistical static timing
analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
787-792, Anaheim, CA, June 13-18 2010.
- [4069]
- Q. Tang,
J. Rodriguez, A. Zjajo, M. Berkelaar, and N. van der Meijs.
Statistical transistor-level timing analysis using direct random differential
equation solver.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(2):210-223, February 2014.
- [4070]
- Q. Tang, A. Zjajo,
M. Berkelaar, and N. van der Meijs.
Considering crosstalk effects in statistical timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(2):318-322, February 2014.
- [4071]
- K. T. Tang and E. G.
Friedman.
Simultaneous switching noise in on-chip CMOS power distribution networks.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(4):487-493, August 2002.
- [4072]
- A. Tang and N. K. Jha.
Genfin: genetic algorithm-based multiobjective statistical logic circuit
optimization using incremental statistical analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(3):1126-1139, March 2016.
- [4073]
- T. K. Tang and M. S.
Nakhla.
Analysis of high-speed VLSI interconnects using the asymptotic waveform
evaluation technique.
IEEE Transactions on Computer-Aided Design, 11(3):341-352, March
1992.
- [4074]
- W. C. Tang.
Overview of microelectromechanical systems and design processes.
In 34th Design Automation Conference, pages 670-673, Anaheim, CA,
June 9-13 1997.
- [4075]
- Y. Tanji and H. Asai.
Closed-form expressions of distributed RLC interconnects for analysis of
on-chip inductance effects.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
810-813, San Diego, CA, June 7-11 2004.
- [4076]
- D. Tannir.
Direct sensitivity analysis of nonlinear distortation in RF circuits using
multidimensional moments.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(3):321-331, March 2015.
- [4077]
- A. Taparia,
B. Banerjee, and T. R. Viswanathan.
Power-supply noise reduction using active inductors in mixed-signal systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(11):1960-1968, November 2011.
- [4078]
- S. Tarafdar,
M. Leeser, and Z. Yin.
Integrating floorplanning in data-transfer based high-level synthesis.
In IEEE/ACM International Conference on Computer-Aided Design, pages
412-417, San Jose, CA, November 8-12 1998.
- [4079]
- R. Tarjan.
Depth-first search and linear graph algorithms.
SIAM Journal On Computing, 1(2):146-160, June 1972.
- [4080]
- R. E. Tarjan.
A unified approach to path problems.
Journal of the Association for Computing Machinery, 28(3):577-593,
July 1981.
- [4081]
- Robert Tarjan.
Data Structures and Network Algorithms.
Society for Industrial and Applied Mathematics (SIAM), 1983.
- [4082]
- S. Tasiran and
A. Demir.
Smart monte carlo for yield estimation.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-06), San Jose, CA, February 27-28
2006.
- [4083]
- B. Taskin and I. S.
Kourtev.
Linearization of the timing analysis and optimization of level-sensitive
digital synchronous circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(1):12-27, January 2004.
- [4084]
- Y. Taur.
CMOS design near the limit of scaling.
IBM J. Res. & Dev., 46(2/3):213-222, March-May 2002.
- [4085]
- B. F. Tawadros and
R. S. Guindi.
State assignment for low-leakage finite state machines.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 115-118, Quebec City, Quebec, June 19-22 2005.
- [4086]
- S. A. Tawfik and
V. Kursun.
Dual supply voltages and dual clock frequencies for lower clock power and
suppressed temperature-gradient-induced clock skew.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(3):347-355, March 2010.
- [4087]
- C. N. Taylor,
S. Dey, and Y. Zhao.
Modeling and minimization of interconnect energy dissipation in nanometer
technologies.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
754-757, Las Vegas, NV, June 18-22 2001.
- [4088]
- R. R. Taylor and
H. Schmit.
Creating a power-aware structured ASIC.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 74-77, Newport Beach, CA, August 9-11 2004.
- [4089]
- M. Taylor.
Is dark silicon useful?
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1131-1136, San Francisco, CA, June 3-7 2012.
- [4090]
- C.-K. Teh, M. Hamada,
T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki.
Conditional data mapping flip-flops for low-power and high-performance systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(12):1379-1383, December 2006.
- [4091]
- R. Telichevesky, K. Kundert, I. Elfadel, and J. White.
Fast simulation algorithms for RF circuits.
In IEEE 1996 Custom Integrated Circuits Conference, pages 437-444,
San Diego, CA, May 5-8 1996.
- [4092]
- G. E. Tellez,
A. Farrahi, and M. Sarrafzadeh.
Activity-driven clock design for low power circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
62-65, San Jose, CA, November 5-9 1995.
- [4093]
- C-C. Teng, A. M.
Hill, and S-M. Kang.
Estimation of maximum transition counts at internal nodes in CMOS VLSI
circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
366-370, San Jose, CA, November 5-9 1995.
- [4094]
- C-C. Teng, Y-K.
Cheng, E. Rosenbaum, and S-M. Kang.
Hierarchical electromigration reliability diagnosis.
In 33rd Design Automation Conference, pages 752-757, Las Vegas, NV,
June 3-7 1996.
- [4095]
- C.-C. Teng, Y.-K.
Cheng, E. Rosenbaum, and S.-M. Kang.
item: A temperature-dependent electromigration reliability diagnosis tool.
IEEE Transactions on Computer-Aided Design, 16(8):882-893, August
1997.
- [4096]
- Y.-C. Teng, S. C.
Chin, and J. C. S. Woo.
The impact of SOI mosfets on low power digital circuits.
In 1997 International Symposium on Low Power Electronics and Design,
pages 243-246, Monterey, CA, August 18-20 1997.
- [4097]
- B. Teng and J. H.
Anderson.
Latch-based performance optimization for field-programmable gate arrays.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(5):667-680, May 2013.
- [4098]
- Y. Teng and B. Taskin.
Frequency-centric resonant rotary clock distribution network design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 742-749, San Jose, CA, November 2-6 2014.
- [4099]
- H. Tennakoon and
C. Sechen.
Gate sizing using lagrangian relaxation combined with a fast gradient-based
pre-processing step.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 395-402, San Jose, CA, November 10-14 2002.
- [4100]
- H. Tennakoon and
C. Sechen.
Nonconvex gate delay modeling and delay optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(9):1583-1594, September 2008.
- [4101]
- R. A. Thakker,
C. Santhe, M. S. Baghini, and M. B. Patil.
A table-based approach to study the impact of process variations on finfet
circuit performance.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(4):627-631, April 2010.
- [4102]
- A. Thayse and M. Davio.
Boolean differential calculus and its application to switching theory.
IEEE Transactions on Computers, C-22(4):409-420, April 1973.
- [4103]
- A. Thayse.
Transient analysis of logical networks applied to hazard detection.
Philips Research Reports, 25(5):261-336, October 1970.
- [4104]
- A. Thayse.
Boolean differential calculus.
Philips Research Reports, 26:229-246, June 1971.
- [4105]
- A. Thayse.
A fast algorithm for the proper decomposition of boolean functions.
Philips Research Reports, 27:140-150, April 1972.
- [4106]
- A. Thayse.
A variational diagnosis method for stuck-faults in combinatorial networks.
Philips Research Reports, 27:82-98, February 1972.
- [4107]
- D. B. Thomlas and
W. Luk.
The LUT-SR family of uniform random number generators for FPGA
architectures.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(4):761-770, April 2013.
- [4108]
- S. Thompson,
P. Packan, and M. Bohr.
MOS scaling: transistor challenges for the 21st century.
Intel Technology Journal, pages 1-19, Q3 1998.
- [4109]
- S. K. Thompson.
Sampling.
John Wiley & Sons, Inc., New York, NY, 2nd edition, 2002.
- [4110]
- J. Thong and
N. Nicolici.
A novel optimal single constant multiplication algorithm.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
613-616, Anaheim, CA, June 13-18 2010.
- [4111]
- J. Thong and
N. Nicolici.
FPGA acceleration of enhanced boolean constraint propagation for SAT
solvers.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 234-241, San Jose, CA, November 18-21 2013.
- [4112]
- J. Thong and
N. Nicolici.
SAT solving using FPGA-based heterogeneous computing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 232-239, Austin TX, November 2-6 2015.
- [4113]
- H. K.
Thornquist, E. R. Keiter, R. J. Hoekstra, D. M. Day, and E. G. Boman.
A parallel preconditioning strategy for efficient transistor-level circuit
simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 410-417, San Jose, CA, November 2-5 2009.
- [4114]
- M. A. Thornton and
V. S. S. Nair.
Efficient calculation of spectral coefficients and their applications.
IEEE Transactions on Computer-Aided Design, 14(11):1328-1341,
November 1995.
- [4115]
- T. Thorp, G. Yee,
and C. Sechen.
Domino logic synthesis using complex static gates.
In IEEE/ACM International Conference on Computer-Aided Design, pages
242-247, San Jose, CA, November 8-12 1998.
- [4116]
- T. J. Thorp, G. S.
Yee, and C. M. Sechen.
Design and synthesis of dynamic circuits.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
11(1):141-149, February 2003.
- [4117]
- B. Thudi and D. Blaauw.
Non-iterative switching window computation for delay-noise.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
390-395, Anaheim, CA, June 2-6 2003.
- [4118]
- M. W. Tian and C.-J. R. Shi.
Worst case tolerance analysis of linear analog circuits using sensitivity
bands.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 47(8):1138-1145, August 2000.
- [4119]
- T.-K. Tien, S.-C.
Chang, and T.-K. Tsai.
Crosstalk alleviation for dynamic PLA.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(12):1416-1424, December 2002.
- [4120]
- T.-K. Tien, C.-S.
Tsai, S.-C. Chang, and C. Yeh.
Power minimization for dynamic plas.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(6):616-624, June 2006.
- [4121]
- L. Ting, J. S. May,
W. R. Hunter, and J. W. McPherson.
AC electromigration characterization and modeling of multilayered
interconnections.
In International Reliability Physics Symposium (IRPS), pages 311-316,
1993.
- [4122]
- V. Tiwari,
P. Ashar, and S. Malik.
Technology mapping for low power.
In 30th ACM/IEEE Design Automation Conference, pages 74-79, Dallas,
TX, June 14-18 1993.
- [4123]
- V. Tiwari,
S. Malik, and A. Wolfe.
Power analysis of embedded software: a first step towards software power
minimization.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2(4):437-445, December 1994.
- [4124]
- V. Tiwari,
S. Malik, and A. Wolfe.
Power analysis of embedded software: a first step towards software power
minimization.
In IEEE/ACM International Conference on Computer-Aided Design, pages
384-390, San Jose, CA, November 6-10 1994.
- [4125]
- V. Tiwari,
S. Malik, and P. Ashar.
Guarded evaluation: pushing power management to logic synthesis/design.
In ACM/IEEE International Symposium on Low Power Design, pages
221-226, Dana Point, CA, April 23-26 1995.
- [4126]
- V. Tiwari,
S. Malik, and P. Ashar.
Guarded evaluation: pushing power management to logic synthesis/design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 17(10):1051-1060, October 1998.
- [4127]
- V. Tiwari,
D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez.
Reducing power in high performance microprocessors.
In IEEE/ACM 35th Design Automation Conference, pages 732-737, San
Francisco, CA, June 15-19 1998.
- [4128]
- S. K. Tiwary,
A. Gupta, J. R. Phillips, C. Pinello, and R. Zlatanovici.
First steps towards SAT-based formal analog verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 1-8, San Jose, CA, November 2-5 2009.
- [4129]
- S. K. Tiwary and
J. R. Phillips.
WAVSTAN: waveform based variational static timing analysis.
Design, Automation and Test in Europe (DATE-07), pages 1000-1005,
April 16-20 2007.
- [4130]
- S. K. Tiwary and
R. A. Rutenbar.
Faster, parametric trajectory-based macromodels via localized linear
reductions.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 876-883, San Jose, CA, November 5-9 2006.
- [4131]
- A. Todri, S.-C.
Chang, and M. Marek-Sadowska.
Electromigration and voltage drop aware power grid optimization for power gated
ics.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 391-394, Portland, Oregon, August 27-29 2007.
- [4132]
- A. Todri,
M. Marek-Sadowska, and S.-C. Chang.
Analysis and optimization of power-gated ics with multiple power gating
configurations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 783-790, San Jose, CA, November 5-8 2007.
- [4133]
- A. Todri,
M. Marek-Sadowska, and J. Kozhaya.
Power supply noise aware workload assignment for multi-core systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 330-337, San Jose, CA, November 10-13 2008.
- [4134]
- A. Todri and
M. Marek-Sadowska.
Power delivery for multicore systems.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(12):2243-2255, December 2011.
- [4135]
- A. Todri and
M. Marek-Sadowska.
Reliability analysis and optimization of power-gated ics.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(3):457-468, March 2011.
- [4136]
- A. Todri-Sanial, S. Kundu, P. Girard, A. Bosio, L. Dilillo, and
A. Virazel.
Globally constrained locally optimized 3-D power delivery networks.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(10):2131-2144, October 2014.
- [4137]
- A. Todri-Sanial and Y. Cheng.
A study of 3-D power delivery networks with multiple clock domains.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(11):3218-3231, November 2016.
- [4138]
- J. R. Tolbert,
X. Zhao, S. K. Lim, and S. Mukhopadhyay.
Analysis and design of energy and slew aware subthreshold clock systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(9):1349-1358, September 2011.
- [4139]
- Y. Tomita,
N. Iwanishi, R. Yamaguchi, and H. Edamatsu.
Dual threshold delay model for nonlinear device characterization.
In IEEE Custom Integrated Circuits Conference, pages 371-374, Santa
Clara, CA, May 1-4 1995.
- [4140]
- X. Tong, F. F. Wu,
and L. Qi.
Available transfer capability calculation using a smoothing pointwise maximum
function.
IEEE Transactions on Circuits and Systems, 55(2):450-462, February
2008.
- [4141]
- R. O. Topaloglu.
Design with finfets: design rules, patterns, and variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 569-571, San Jose, CA, November 18-21 2013.
- [4142]
- E. A.
Trachtenberg and D. Varma.
A design automation tool for fast, efficient decomposition of logical
functions.
In IEEE International Conference on Computer-Aided Design, pages
70-73, Santa Clara, CA, Nov. 9-12 1987.
- [4143]
- L. N. Trefethen
and J. A. C. Weideman.
The exponentially convergent trapezoidal rule.
SIAM Review, 56(3):385-458, 2014.
- [4144]
- R. Trihy.
Addressing library creation challenges from recent liberty extensions.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
474-479, Anaheim, CA, June 8-13 2008.
- [4145]
- R. Trinchero, P. Manfredi, T. Ding, and I. S. Stievano.
Combined parametric and worst case circuit analysis via taylor models.
IEEE Transactions on Circuits and Systems, 63(7):1067-1078, July
2016.
- [4146]
- D. R. Tryon, F. M.
Armstrong, and M. R. Reiter.
Statistical failure analysis of system timing.
IBM Journal of Research and Development, 28(4):340-355, July 1984.
- [4147]
- Y-F. Tsai,
D. Duarte, N. Vijaykrishnan, and M. J. Irwin.
Implications of technology scaling on leakage reduction techniques.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
187-190, Anaheim, CA, June 2-6 2003.
- [4148]
- J.-L. Tsai,
D. Baik, C. C.-P. Chen, and K. K. Saluja.
A yield improvement methodology using pre- and post-silicon statistical clock
scheduling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 611-618, San Jose, CA, November 7-11 2004.
- [4149]
- Y.-F. Tsai,
D. Duarte, N. Vijaykrishnan, and M. J. Irwin.
Impact of process scaling on the efficacy of leakage reduction schemes.
In International Conference on Integrated Circuit Design and Technology
(ICICDT), pages 3-11, Austin, TX, May 17-20 2004.
- [4150]
- Y.-F. Tsai, D. E.
Duarte, N. Vijaykrishnan, and M. J. Irwin.
Characterization and modeling of run-time techniques for leakage power
reduction.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(11):1221-1233, November 2004.
- [4151]
- J.-L. Tsai,
L. Zhang, and C. C.-P. Chen.
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 575-581, San Jose, CA, November 6-10 2005.
- [4152]
- K.-L. Tsai, S.-J.
Ruan, L.-W. Chen, F. Lai, and E. Naroska.
Low power dynamic bus encoding for deep sub micron design.
In The 3rd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-05), pages 159-162, Quebec City, Quebec, June 19-22 2005.
- [4153]
- M.-C. Tsai,
D. Zhang, and Z. Tang.
Modeling litho-constrained design layout.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
354-357, San Diego, CA, June 4-8 2007.
- [4154]
- M.-H. Tsai, W.-S.
Ding, H.-Y. Hsieh, and J.-C.-M. Li.
Transient IR-drop anaylsis for at-speed testing using representative random
walk.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(9):1980-1989, September 2014.
- [4155]
- S. Tsai and C.-Y. (Ric)
Huang.
A false-path aware formal static timing analyzer considering simultaneous input
transitions.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 25-30,
San Francisco, CA, July 26-31 2009.
- [4156]
- C.-H. Tsai and S.-M. Kang.
Fast temperature calculation for transient electrothermal simulation by mixed
frequency/time domain thermal power model reduction.
In Design Automation Conference, pages 750-755, Los Angeles, CA, June
5-9 2000.
- [4157]
- C.-H. Tsai and W.-K. Mak.
A fast parallel approach for common path pessimism removal.
In 20th Asia and South Pacific Design Automation Conference, pages
372-377, Chiba/Tokyo, Japan, January 19-22 2015.
- [4158]
- R-S Tsay.
An exact zero-skew clock routing algorithm.
IEEE Transactions on Computer-Aided Design, 12(2):242-249, February
1993.
- [4159]
- J. Tschanz,
S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De.
Comparative delay and energy of single edge-triggered & dual edge-triggered
pulsed flip-flops for high-performance microprocessors.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 147-152, Huntington Beach, California, August 6-7
2001.
- [4160]
- J. Tschanz,
K. Bowman, and V. Le.
Variation-tolerant circuits: circuit solutions and techniques.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
762-763, Anaheim, CA, June 13-17 2005.
- [4161]
- J. Tschanz,
K. Bowman, C. Wilkerson, S.-L. Lu, and T. Karnik.
Resilient circuits - enabling energy-efficient performance and reliability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 71-73, San Jose, CA, November 2-5 2009.
- [4162]
- K. Tseng and
M. Horowitz.
False coupling exploration in timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(11):1795-1805, November 2005.
- [4163]
- K. Tseng and V. Kariat.
Static noise analysis with noise windows.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
864-868, Anaheim, CA, June 2-6 2003.
- [4164]
- Y. P. Tsividis.
Operation and Modeling of the MOS Transistor.
McGraw-Hill, 1987.
- [4165]
- C-Y Tsui,
M. Pedram, and A. M. Despain.
Efficient estimation of dynamic power consumption under a real delay model.
In IEEE International Conference on Computer-Aided Design, pages
224-228, Santa Clara, CA, November 7-11 1993.
- [4166]
- C-Y Tsui,
M. Pedram, and A. M. Despain.
Technology decomposition and mapping targeting low power dissipation.
In 30th ACM/IEEE Design Automation Conference, pages 68-73, Dallas,
TX, June 14-18 1993.
- [4167]
- C-Y. Tsui,
M. Pedram, C-A. Chen, and A. M. Despain.
Low power state assignment targeting two- and multi-level logic
implementations.
In IEEE/ACM International Conference on Computer-Aided Design, pages
82-87, San Jose, CA, November 6-10 1994.
- [4168]
- C-Y Tsui,
M. Pedram, and A. M. Despain.
Exact and approximate methods for calculating signal and transition
probabilities in fsms.
In 31st ACM/IEEE Design Automation Conference, pages 18-23, San
Diego, CA, June 6-10 1994.
- [4169]
- C-Y. Tsui,
M. Pedram, and A. M. Despain.
Power efficient technology decomposition and mapping under an extended power
consumption model.
IEEE Transactions on Computer-Aided Design, 13(9):1110-1122,
September 1994.
- [4170]
- C-Y Tsui,
J. Monteiro, M. Pedram, S. Devadas, A. M. Despain, and B. Lin.
Power estimation methods for sequential logic circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
3(3):404-416, September 1995.
- [4171]
- C-Y. Tsui,
R. Marculescu, D. Marculescu, and M. Pedram.
Improving the efficiency of power simulators by input vector compaction.
In 33rd Design Automation Conference, pages 165-168, Las Vegas, NV,
June 3-7 1996.
- [4172]
- C-Y Tsui, K-K Chan,
Q. Wu, C-S Ding, and M. Pedram.
A power estimation framework for designing low power portable video
applications.
In 34th Design Automation Conference, pages 421-424, Anaheim, CA,
June 9-13 1997.
- [4173]
- C.-Y. Tsui,
M. Pedram, and A. M. Despain.
Low-power state assignment targeting two- and multilevel logic implementations.
IEEE Transactions on Computer-Aided Design, 17(12):1281-1291,
December 1998.
- [4174]
- Y. Tsukamoto, K. Nii, S. Imaoka, Y. Oda, S. Ohbayashi,
T. Yoshizawa, H. Makino, K. Ishibashi, and H. Shinohara.
Worst-case analysis to obtain stable read/write DC margin of high density
6t-SRAM-array with local vth variability.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 398-405, San Jose, CA, November 6-10 2005.
- [4175]
- R. H. Tu, E. Rosenbaum,
W. Y. Chan, C. C. Li, E. Minami, K. Quader, P. K. Ko, and C. Hu.
Berkeley reliability tools - BERT.
IEEE Transactions on Computer-Aided Design, 12(10):1524-1534, October
1993.
- [4176]
- S.-W. Tu, Y.-W. Chang,
and J.-Y. Jou.
RLC coupling-aware simulation and on-chip bus encoding for delay reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2258-2275, October 2006.
- [4177]
- W.-P Tu, C.-H Chou,
S.-H. Huang, S.-C. Chang, Y.-T. Nieh, and C.-Y. Chou.
Low-power timing closure methodology for ultra-low voltage designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 697-704, San Jose, CA, November 18-21 2013.
- [4178]
- T. Tuan, A. Rahman,
S. Das, S. Trimberger, and S. Kao.
A 90-nm low-power FPGA for battery-powered applications.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(2):296-300, February 2007.
- [4179]
- E. Tuncer,
J. Cortadella, and L. Lavagno.
Enabling adaptability through elastic clocks.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 8-10,
San Francisco, CA, July 26-31 2009.
- [4180]
- S. Turgis,
N. Azemard, and D. Auvergne.
Explicit evaluation of short circuit power dissipation for CMOS logic
structures.
In ACM/IEEE International Symposium on Low Power Design, pages
129-134, Dana Point, CA, April 23-26 1995.
- [4181]
- S. Turgis and
D. Auvergne.
A novel macromodel for power estimation in CMOS structures.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 17(11):1090-1098, November 1998.
- [4182]
- B. Tutuianu,
F. Dartu, and L. Pileggi.
An explicit RC-circuit delay approximation based on the first three moments
of the impulse response.
In 33rd Design Automation Conference, pages 611-616, Las Vegas, NV,
June 3-7 1996.
- [4183]
- B. Tutuianu,
R. Baldick, and M. S. Johnstone.
Nonlinear driver models for timing and noise analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(11):1510-1521, November 2004.
- [4184]
- S. Tuuna,
J. Isoaho, and H. Tenhunen.
Analytical model for crosstalk and intersymbol interference in point-to-point
buses.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1400-1411, July 2006.
- [4185]
- S. Tuuna, L.-R.
Zheng, J. Isoaho, and H. Tenhunen.
Modeling of on-chip bus switching current and its impact on noise in power
supply grid.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(6):766-774, June 2008.
- [4186]
- S. Tuuna,
E. Nigussie, J. Isoaho, and H. Tenhunen.
Modelling of energy dissipation in RLC current-model signaling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(6):1146-1155, June 2012.
- [4187]
- A. Tyagi.
Hercules: a power analyzer for MOS VLSI circuits.
In IEEE International Conference on Computer-Aided Design, pages
530-533, Nov. 9-12 1987.
- [4188]
- A. Tyagi.
VLSI design parsing.
In IEEE/ACM International Conference on Computer-Aided Design, pages
30-34, Santa Clara, CA, November 8-12 1992.
- [4189]
- A. Tyagi.
Entropic bounds on FSM switching.
In International Symposium on Low Power Electronics and Design, pages
323-328, Monterey, CA, August 12-14 1996.
- [4190]
- A. Tyagi.
Entropic bounds on FSM switching.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
5(4):456-464, December 1997.
- [4191]
- K. Uchida.
Single-electron devices for ubiquitous and secure computing applications.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
301-303, San Francisco, CA, July 26-31 2009.
- [4192]
- T. Uchino,
F. Minami, T. Mitsuhashi, and N. Goto.
Switching activity analysis using boolean approximation method.
In IEEE/ACM International Conference on Computer-Aided Design, pages
20-25, San Jose, CA, November 5-9 1995.
- [4193]
- T. Uchino,
F. Minami, M. Murakata, and T. Mitsuhashi.
Switching activity analysis for sequential circuits using boolean approximation
method.
In International Symposium on Low Power Electronics and Design, pages
79-84, Monterey, CA, August 12-14 1996.
- [4194]
- T. Uchino and J. Cong.
An interconnect energy model considering coupling effects.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
555-558, Las Vegas, NV, June 18-22 2001.
- [4195]
- T. Uchino and J. Cong.
An interconnect energy model considering coupling effects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(7):763-776, July 2002.
- [4196]
- I. Ukhov, Z. Peng,
M. Bao, and P. Eles.
Steady-state dynamic temperature analysis and reliability optimization for
embedded multiprocessor systems.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
197-204, San Francisco, CA, June 3-7 2012.
- [4197]
- I. Ukhov, P. Eles,
and Z. Peng.
Probabilistic analysis of power and temperature under process variation for
electronic system design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(6):931-944, June 2014.
- [4198]
- I. Ukhov, P. Eles,
and Z. Peng.
Temperature-centric reliability analysis and optimization of electronic systems
under process variation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(11):2417-2430, November 2015.
- [4199]
- F. Fatz ul Hassan, W. Vanderbanwhede, and F. Rodriguez-Salazar.
Impact of random dopant flucatuations on the timing characteristics of
flip-flops.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(1):157-161, January 2012.
- [4200]
- J. Um and T. Kim.
Synthesis of arithmetic circuits considering layout effects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(11):1487-1503, November 2003.
- [4201]
- C. Umans,
T. Villa, and A. L. Sangiovanni-Vincentelli.
Complexity of two-level logic minimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1230-1246, July 2006.
- [4202]
- P. Urard,
A. Maalej, R. Guizzetti, and N. Chawla.
Leveraging sequential equivalence checking to enable system-level to RTL
flows.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
816-821, Anaheim, CA, June 8-13 2008.
- [4203]
- K. Usami,
K. Nogami, M. Igarashi, F. Minami, Y. Kawasaki, T. Ishikawa, M. Kanazawa,
T. Aoki, M. Takano, C. Mizuno, M. Ichida, S. Sonoda, M. Takahashi, and
N. Hatanaka.
Automated low-power technique exploiting multiple supply voltages applied to a
media processor.
In IEEE 1997 Custom Integrated Circuits Conference, pages 131-134,
Santa Clara, CA, May 5-8 1997.
- [4204]
- K. Usami,
N. Kawabe, M. Koizumi, K. Seta, and T. Furusawa.
Automated selected multi-threshold design for ultra-low standby applications.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 202-206, Monterey, California, August 12-14 2002.
- [4205]
- K. Usami and
M. Horowitz.
Clustered voltage scaling technique for low-power design.
In ACM/IEEE International Symposium on Low Power Design, pages 3-8,
Dana Point, CA, April 23-26 1995.
- [4206]
- M. Vadizadeh, M. Fathipour, and A. Amid.
A novel nanoscale tunnel FET structure for increasing on/off current ratio.
In IEEE 20th International Conference on Microelectronics (ICM), pages
344-347, Sharjah, UAE, December 14-17 2008.
- [4207]
- K. Vaidyanathan, L. Liebmann, A. Strojwas, and L. Pileggi.
Sub-20 nm design technology co-optimization for standard cell logic.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 124-131, San Jose, CA, November 2-6 2014.
- [4208]
- A. Valentian, O. Thomas, A. Vladimirescu, and A. Amara.
Modeling subthreshold SOI logic for static timing analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(6):662-670, June 2004.
- [4209]
- L. G. Valiant.
The complexity of enumeration and reliability problems.
SIAM Journal on Computing, 8(3):410-421, August 1979.
- [4210]
- J. P. A. van der Wagt.
Tunneling-based SRAM.
In Proceedings of the IEEE, pages 571-595, April 1999.
Published as Proceedings of the IEEE, volume 87, number 4.
- [4211]
- A. J.
van Genderen and N. P. van der Meijs.
Extracting simple but accurate RC models for VLSI interconnect.
In IEEE International Conference on Circuits and Systems, pages
2351-2354, 1988.
- [4212]
- M. van Heijningen, M. Badaroglu, S. Donnay, M. Engels, and
I. Bolsens.
High-level simulation of substrate noise generation including power supply
noise coupling.
In Design Automation Conference, pages 446-451, Los Angeles, CA, June
5-9 2000.
- [4213]
- V. M. van
Santen, H. Amrouch, J. Martin-Martinez, M. Nafria, and J. Henkel.
Designing guardbands for instantaneous aging effects.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [4214]
- A. Vandecappelle, M Miranda, E. Brockmeyer, F. Catthoor, and
D. Verkest.
Global multimedia system design exploration using accurate memory organization
feedback.
In Design Automation Conference, pages 327-332, New Orleans, LA, June
21-25 1999.
- [4215]
- L. Vandenberghe, S. Boyd, and A. El Gamal.
Optimizing dominant time constant in RC circuits.
IEEE Transactions on Computer-Aided Design of Circuits and Systems,
17(2):110-125, February 1998.
- [4216]
- J. R.
Vanderhaegen and R. W. Brodersen.
Automated design of operational transconductance amplifiers using reversed
geometric programming.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
133-138, San Diego, CA, June 7-11 2004.
- [4217]
- P. Vanoostende, P. Six, and H. J. DeMan.
DARSI: RC data reduction.
IEEE Transactions on Computer-Aided Design, 10(4):493-500, April
1991.
- [4218]
- P. Vanoostende, P. Six, and H. J. De Man.
PRITI: Estimation of maximal currents and current derivatives in complex
CMOS circuits using activity waveforms.
In European Design Automation Conference (EDAC), pages 347-353,
1993.
- [4219]
- B. K. S.
V. L. Varaprasad, L. M. Patnaik, H. S. Jamadagni, and V. K. Agrawal.
A new ATPG technique (expotan) for testing analog circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(1):189-196, January 2007.
- [4220]
- G. V.
Varatkar, S. Narayanan, N. R. Shanbhag, and D. L. Jones.
Stochastic networked computation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(10):1421-1432, October 2010.
- [4221]
- G. V. Varatkar
and N. R. Shanbhag.
Energy-efficient motion estimation using error-tolerance.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 113-118, Tegernsee, Germany, October 4-6 2006.
- [4222]
- Richard S. Varga.
Matrix Iterative Analysis.
Prentice-Hall, Englewood Cliffs, NJ, 1962.
- [4223]
- A. Varma,
B. Bowhill, J. Crop, C. Gough, B. Griffith, D. Kingsley, and K. Sistla.
Power management in the intel xeon e5 v3.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 371-376, Rome, Italy, July 22-24 2015.
- [4224]
- D. Vasilyev and
J. White.
A more reliable reduction algorithm for behavioral model extraction.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 813-820, San Jose, CA, November 6-10 2005.
- [4225]
- A. Vassighi,
A. Kashavarzi, S. Narendra, G. Schrom, Y. Ye, S. Lee, G. Chrysler,
M. Sachdev, and V. De.
Design optimizations for microprocessors at low temperature.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages 2-5,
San Diego, CA, June 7-11 2004.
- [4226]
- H. J. M. Veendrick.
Short-circuit dissipation of static CMOS circuitry and its impact on the
design of buffer circuits.
IEEE Journal of Solid-State Circuits, SC-19(4):468-473, August
1984.
- [4227]
- V. Veeramachaneni, A. Tyagi, and S. Rajgopal.
Re-encoding for low power state assignment of fsms.
In ACM/IEEE International Symposium on Low Power Design, pages
173-178, Dana Point, CA, April 23-26 1995.
- [4228]
- V. Veetil,
D. Sylvester, and D. Blaauw.
Critically aware latin hypercube sampling for efficient statistical timing
analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 24-30, Austin, Texas,
February 26-27 2007.
- [4229]
- V. Veetil,
D. Sylvester, and D. Blaauw.
Fast and accurate waveform analysis with current source models.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 73-79, Austin, Texas,
February 26-27 2007.
- [4230]
- V. Veetil,
D. Sylvester, and D. Blaauw.
Efficient monte carlo based incremental statistical timing analysis.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 7-13, Monterey, CA,
February 25-26 2008.
- [4231]
- V. Veetil,
D. Sylvester, and D. Blaauw.
Efficient monte carlo based incremental statistical timing analysis.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
676-681, Anaheim, CA, June 8-13 2008.
- [4232]
- V. Veetil,
D. Sylvester, D. Blaauw, S. Shah, and S. Rochel.
Efficient smart sampling based full-chip leakage analysis for intra-die
variation considering state dependence.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
154-159, San Francisco, CA, July 26-31 2009.
- [4233]
- V. Veetil,
Y.-H. Chang, D. Sylvester, and D. Blaauw.
Efficient smart monte carlo based SSTA on graphics processing units with
improved resource utilization.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
793-798, Anaheim, CA, June 13-18 2010.
- [4234]
- V. Veetil,
D. Sylvester, and D. Blaauw.
A lower bound computation method for evaluation of statistical design
techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 562-569, San Jose, CA, November 7-11 2010.
- [4235]
- J. B.
Velamala, V. Ravi, and Y. Cao.
Failure diagnosis of asymmetric aging under NBTI.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 428-433, San Jose, CA, November 7-10 2011.
- [4236]
- J. B.
Velamala, K. Sutaria, T. Sato, and Y. Cao.
Physics matters: statistical aging prediction under trapping/detrapping.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
139-144, San Francisco, CA, June 3-7 2012.
- [4237]
- S. R. Vemuru and
N. Scheinberg.
Short-circuit power dissipation estimation for CMOS logic gates.
IEEE Transactions on Circuits and Systems - I, 41(11):762-765,
November 1994.
- [4238]
- J. D. Venables and
R. G. Lye.
A statistical model for electromigration induced failure in thin film
conductors.
In Proc. 10th Annual IEEE Reliability Physics Symposium, pages
159-164, Las Vegas, Nevada, April 5-7 1972.
- [4239]
- A. Veneris and M. S.
Abadir.
Design rewiring using ATPG.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(12):1469-1479, December 2002.
- [4240]
- A. Veneris and I. N.
Hajj.
Design error diagnosis and correction via test vector generation.
IEEE Transactions on Computer-Aided Design, 18(12):1803-1816,
December 1999.
- [4241]
- A. Veneris and
S. Safarpour.
The day sherlock holmes decided to do EDA.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
631-634, San Francisco, CA, July 26-31 2009.
- [4242]
- G. Venkataraman, K. Jayakumar, J. Hu, P. Li, S. Khatri,
A. Rajaram, P. McGuinness, and C. Alpert.
Practical techniques to reduce skew and its variations in buffered clock
networks.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 592-596, San Jose, CA, November 6-10 2005.
- [4243]
- R. Venkatesan, J. A. Davis, and J. D. Meindl.
A physical model for the transient response of capactively loaded distributed
rlc interconnects.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
763-766, New Orleans, LA, June 10-14 2002.
- [4244]
- R. Venkatesan, A. Agarwal, K. Roy, and A. Raghunathan.
Implementation of pulsed-latch and pulsed-register circuits to minimize
clocking power.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 667-673, San Jose, CA, November 7-10 2011.
- [4245]
- N. K.
Verghese, D. J. Allstot, and M. A. Wolfe.
Fast parasitic extraction for substrate coupling in mixed-signal ics.
In IEEE Custom Integrated Circuits Conference, pages 121-124, Santa
Clara, CA, May 1-4 1995.
- [4246]
- B. Victor and
K. Keutzer.
Bus encoding to prevent crosstalk delay.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 57-63, San Jose, CA, November 4-8 2001.
- [4247]
- T. Villa, T. Kam,
R. K. Brayton, and A. L. Sangiovanni-Vincentelli.
Explicit and implicit algorithms for binate covering problem.
IEEE Transactions on Computer-Aided Design, 16(7):677-691, July
1997.
- [4248]
- C. De
Villemagne and R. E. Skelton.
Model reductions using a projection formulation.
International Journal of Control, 46(6):2141-2169, 1987.
- [4249]
- J. F. Villena and
L. M. Silveira.
3por - parallel projection based parameterized order reduction for
multi-dimensional linear models.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 536-542, San Jose, CA, November 7-11 2010.
- [4250]
- J. F. Villena and
L. M. Silveira.
SPARE - a scalable algorithm for passive, structure preserving,
parameter-aware model order reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(6):925-938, June 2010.
- [4251]
- J. F. Villena and
L. M. Silveira.
Multi-dimensinoal automatic sampling schemes for multi-point modeling
methodologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(8):1141-1151, August 2011.
- [4252]
- J. F. Villena and
L. M. Silveira.
Exploiting parallelism for improved automation of multidimensional model order
reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(1):37-49, January 2012.
- [4253]
- J. Viraraghavan, S. J. Pandharpure, and J. Watts.
Statistical compact model extraction: a neural network approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(12):1920-1929, December 2012.
- [4254]
- C. Visweswariah, R. A. Haring, and A. R. Conn.
Noise considerations in circuit optimization.
IEEE Transactions on Computer-Aided Design, 19(6):679-690, June
2000.
- [4255]
- C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Waler, and
S. Narayan.
First-order incremental block-based statistical timing analysis.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
331-336, San Diego, CA, June 7-11 2004.
- [4256]
- C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker,
S. Narayan, D. K. Beece, J. Piaget, N. Venkateswaran, and J. G. Hemmett.
First-order incremental block-based statistical timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2170-2180, October 2006.
- [4257]
- C. Visweswariah and A. R. Conn.
Formulation of static circuit optimization with reduced size, degeneracy, and
redundancy by timing graph manipulation.
In IEEE/ACM International Conference on Computer-Aided Design, pages
244-251, San Jose, CA, November 7-11 1999.
- [4258]
- C. Visweswariah and R. Rohrer.
Piecewise approximate circuit simulation.
In IEEE International Conference on Computer-Aided Design, pages
248-251, 1989.
- [4259]
- C. Visweswariah.
Optimization techniques for high-performance digital circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
198-205, San Jose, CA, November 9-13 1997.
- [4260]
- C. Visweswariah.
Death, taxes and failing chips.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
343-347, Anaheim, CA, June 2-6 2003.
- [4261]
- A. Vittal, L. H.
Chen, M. Marek-Sadowska, K.-P. Wang, and S. Yang.
Crosstalk in VLSI interconnections.
IEEE Transactions on Computer-Aided Design, 18(12):1817-1824,
December 1999.
- [4262]
- A. Vittal and
M. Marek-Sadowska.
Crosstalk reduction for VLSI.
IEEE Transactions on Computer-Aided Design, 16(3):290-298, March
1997.
- [4263]
- A. Vittal and
M. Marek-Sadowska.
Low-power buffered clock tree design.
IEEE Transactions on Computer-Aided Design, 16(9):965-975, September
1997.
- [4264]
- J. Vlach, J. A.
Barby, A. Vannelli, T. Talkhan, and C.-J. R. Shi.
Group delay as an estimate of delay in logic.
IEEE Transactions on Computer-Aided Design, 10(7):949-953, July
1991.
- [4265]
- A. Vladimirescu, Y. Cao, O. Thomas, H. Qin, D. Markovic,
A. Valentian, R. Ionita, J. Rabaey, and A. Amara.
Ultra-low-voltage robust design issues in deep-submicron CMOS.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 49-52, Montreal, Quebec, June 20-23 2004.
- [4266]
- D. Vo.
Automated SPICE characterization of gate array and standard cell libraries.
In IEEE Custom Integrated Circuits Conference (CICC), pages 363-366,
1987.
- [4267]
- C. Voigt.
Gene and cellular circuit design.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
115-115, San Diego, CA, June 5-9 2011.
- [4268]
- L. von Ahn.
Human computation.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
418-419, San Francisco, CA, July 26-31 2009.
- [4269]
- S. B. K.
Vrudhula, D. Blaauw, and S. Sirichotiyakul.
Estimation of the likelihood of capacitive coupling noise.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
653-658, New Orleans, LA, June 10-14 2002.
- [4270]
- S. Vrudhula,
D. T. Blaauw, and S. Sirichotiyakul.
Probabilistic analysis of interconnect coupling noise.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(9):1188-1203, September 2003.
- [4271]
- S. Vrudhula,
J.-M. Wang, and P. Ghanta.
Hermite polynomial based interconnect analysis in the presence of process
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2001-2011, October 2006.
- [4272]
- S. B. K. Vrudhula and
H-Y. Xie.
Techniques for CMOS power estimation and logic synthesis for low power.
In ACM/IEEE 1994 International Workshop on Low Power Design, pages
21-26, Napa, CA, April 24-27 1994.
- [4273]
- L. Vu-Quoc,
Y. Zhai, and K.-D.-T. Ngo.
Efficient simulation of coupled circuit-field problems: generalized falk
method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(8):1209-1219, August 2004.
- [4274]
- P. Vuillod,
L. Benini, A. Bogliolo, and G. De Micheli.
Clock-skew optimization for peak current reduction.
In International Symposium on Low Power Electronics and Design, pages
265-270, Monterey, CA, August 12-14 1996.
- [4275]
- P. Vuillod,
L. Benini, and G. De Micheli.
Re-mapping for low power under tight timing constraints.
In 1997 International Symposium on Low Power Electronics and Design,
pages 287-292, Monterey, CA, August 18-20 1997.
- [4276]
- M. Vujkovic,
D. Wadkins, B. Swartz, and C. Sechen.
Efficient timing closure without timing driven placement and routing.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
268-273, San Diego, CA, June 7-11 2004.
- [4277]
- M. Vujkovic and
C. Sechen.
Optimized power-delay curve generation for standard cell ics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 387-394, San Jose, CA, November 10-14 2002.
- [4278]
- J. Vygen.
Slack in static timing analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1876-1885, September 2006.
- [4279]
- I. Vytyaz, P. K.
Hanumolu, U.-K. Moon, and K. Mayaram.
Design-oriented analysis of circuits with equality constraints.
IEEE Transactions on Circuits and Systems, 58(5):1089-1098, May
2011.
- [4280]
- S. A. Wadekar and
A. C. Parker.
Interconnect-based system-level energy and power prediction to guide
architecture exploration.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(4):373-380, April 2004.
- [4281]
- R. L. Wadsack.
Fault coverage in digital integrated circuits.
The Bell System Technical Journal, 57(5):1475-1488, May-June 1978.
- [4282]
- R. L. Wadsack.
Fault modeling and logic simulation of CMOS and MOS integrated circuits.
The Bell System Technical Journal, 57(5):1449-1474, May-June 1978.
- [4283]
- I. Wagner,
V. Bertacco, and T. Austin.
Shielding against design flaws with field repairable control logic.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
344-347, San Francisco, CA, July 24-28 2006.
- [4284]
- I. Wagner,
V. Bertacco, and T. Austin.
Using field-programmable control logic to correct design errors in
microprocessors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(2):380-393, February 2008.
- [4285]
- K. D. Wagner.
Clock system design.
IEEE Design & Test of Computers, 5(5):9-27, October 1988.
- [4286]
- M. Wainberg and
V. Betz.
Robust optimization of multiple timing constraints.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(12):1942-1953, December 2015.
- [4287]
- K. Wakabayashi and T. Okamoto.
C-based SOC design flow and EDA tools: An ASIC and system vendor
perspective.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 19(12):1507-1522, December 2000.
- [4288]
- D. E. Wallace
and M. S. Chandrasekhar.
High-level delay estimation for technology-independent logic equations.
In IEEE International Conference on Computer-Aided Design, pages
188-191, Santa Clara, CA, November 11-15 1990.
- [4289]
- D. E. Wallace and
C. H. Sequin.
Plug-in timing models for an abstract timing verifier.
In 23rd ACM/IEEE Design Automation Conference, pages 683-689, Las
Vegas, NV, June 29 - July 2 1986.
- [4290]
- R. E. Walpole,
R. H. Myers, and S. L. Myers.
Probability and Statistics for Engineers and Scientists.
Prentice Hall International, Inc., Upper Saddle River, NJ, 6th edition,
1998.
- [4291]
- L. Wan and D. Chen.
Analysis of circuit dynamic behavior with timed ternary decision diagram.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 516-523, San Jose, CA, November 7-11 2010.
- [4292]
- L. Wan and D. Chen.
Analysis of digital circuit dynamic behavior with timed ternary decision
diagrams for better-than-worst-case design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(5):662-675, May 2012.
- [4293]
- S. Wane and A.-Y. Kuo.
Chip-package co-design methodology for global co-simulation of re-distribution
layers (RDL).
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 59-62, San Jose, CA, October 27-29 2008.
- [4294]
- H. Wang, H. De, and
R. Lahri.
Improving hot-electron reliability through circuit analysis and design.
In IEEE 29th Annual International Reliability Physics Symposium, pages
107-111, Las Vegas, NV, April 9-11 1991.
- [4295]
- C-Y. Wang, K. Roy,
and T-L. Chou.
Maximum power estimation for sequential circuits using a test generation based
technique.
In IEEE 1996 Custom Integrated Circuits Conference, pages 229-232,
San Diego, CA, May 5-8 1996.
- [4296]
- Q. Wang, S. B. K.
Vrudhula, and S. Ganguly.
An investigation of power delay trade-offs on powerpc circuits.
In 34th Design Automation Conference, pages 425-428, Anaheim, CA,
June 9-13 1997.
- [4297]
- J. M. Wang, E. S.
Kuh, and Q. Yu.
The chebyshev expansion based passive model for distributed interconnect
networks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
370-375, San Jose, CA, November 7-11 1999.
- [4298]
- M. Wang, X. Yang,
and M. Sarrafzadeh.
Dragon2000: Standard-cell placement tool for large industry circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 260-263, San Jose, CA, November 5-9 2000.
- [4299]
- W. Wang,
A. Raghunathan, G. Lakshminarayana, and N. K. Jha.
Input space adaptive design: A high-level methodology for energy and
performance optimization.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
738-743, Las Vegas, NV, June 18-22 2001.
- [4300]
- C.-Y. Wang, S.-W.
Tung, and J.-Y. Jou.
An automorphic approach to verification pattern generation for soc design
verification using port-order fault model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(10):1225-1232, October 2002.
- [4301]
- J. M. Wang,
C. Chu, Q. Yu, and E. S. Kuh.
On projection-based algorithms for model-order reduction of interconnects.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 49(11):1563-1585, November 2002.
- [4302]
- C.-C. Wang, Y.-H.
Hsueh, and Y.-P. Chen.
An area-saving decoder structure for roms.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):581-589, August 2003.
- [4303]
- J. Wang,
P. Ghanta, and S. Vrudhula.
Stochastic analysis of interconnect performance in the presence of process
variations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 880-886, San Jose, CA, November 7-11 2004.
- [4304]
- J. Wang, K. K.
Muchheria, and J. G. Kumar.
A clustering based area I/O planning for flip-chip technology.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 196-204, San Jose, CA, March 22-24 2004.
- [4305]
- J.-M. Wang, O. A.
Hafiz, and J. Li.
A linear fractional transform (LFT) based model for interconnect parametric
uncertainty.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
375-380, San Diego, CA, June 7-11 2004.
- [4306]
- P. Wang, G. Pei,
and E. C.-C. Kan.
Pulsed wave interconnect.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):453-463, May 2004.
- [4307]
- W. Wang,
A. Raghunathan, G. Lakshminarayana, and N. K. Jha.
Input space adaptive design: a high-level methodology for optimizing energy and
performance.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(6):590-602, June 2004.
- [4308]
- C.-C. Wang, Y.-L.
Tseng, and C.-C. Chiu.
A temperature-insensitive self-recharging circuitry used in drams.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):405-409, March 2005.
- [4309]
- H. Wang,
M. Miranda, A. Papanikolaou, F. Catthoor, and W. Dehaene.
Variable tapered pareto buffer design and implementation allowing run-time
configuration for low-power embedded srams.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(10):1127-1135, October 2005.
- [4310]
- J.-M. Wang,
B. Srinivas, D. Ma, C. C.-P. Chen, and J. Li.
System-level power and thermal modeling and analysis by orthogonal polynomial
based response surface approach (OPRS).
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 728-735, San Jose, CA, November 6-10 2005.
- [4311]
- X. Wang,
M. Ottavi, F. J. Meyer, and F. Lombardi.
Estimating the manufacturing yield of compiler-based embedded srams.
IEEE Transactions on Semiconductor Manufacturing, 18(3):412-421,
August 2005.
- [4312]
- Z. Wang, R. Murgai,
and J. Roychowdhury.
ADAMIN: automated, accurate macromodeing of digital aggressors for power and
ground supply noise prediction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):56-64, January 2005.
- [4313]
- G. Wang, W. Gong,
and R. Kastner.
On the use of bloom filters for defect maps in nanocomputing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 743-746, San Jose, CA, November 5-9 2006.
- [4314]
- G. Wang,
S. Sivaswamy, C. Ababei, K. Bazargan, R. Kastner, and E. Bozorgzadeh.
Statistical analysis and design of HARP fpgas.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2088-2102, October 2006.
- [4315]
- H.-G. Wang, C.-H.
Chan, L. Tsang, and V. Jandhyala.
On sampling algorithms in multilevel QR factorization method for
magnetoquasistatic analysis of integrated circuits over multilayered lossy
substrates.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1777-1792, September 2006.
- [4316]
- J.-M. Wang, J. Li,
S. Yanamanamanda, L. K. Vakati, and K. K. Muchherla.
Modeling the driver load in the presence of process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2264-2275, October 2006.
- [4317]
- W.-S. Wang,
V. Kreinovich, and M. Orshansky.
Statistical timing based on incomplete probabilistic descriptions of parameter
uncertainty.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
161-166, San Francisco, CA, July 24-28 2006.
- [4318]
- X. Wang,
J. Kanapka, W. Ye, N. R. Aluru, and J. White.
Algorithms in faststokes and its application to micromachined device
simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(2):248-257, February 2006.
- [4319]
- F. Wang, Y. Xie,
and H. Yu.
A novel criticality computation method in statistical timing analysis.
Design, Automation and Test in Europe (DATE-07), pages 1611-1616,
April 16-20 2007.
- [4320]
- J. Wang, D. Das,
and H. Zhou.
Gate sizing by lagrangian relaxation revisited.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 111-118, San Jose, CA, November 5-8 2007.
- [4321]
- L.-C. Wang,
P. Bastani, and M. S. Abadir.
Design-silicon timing correlation - a data mining perspective.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
384-389, San Diego, CA, June 4-8 2007.
- [4322]
- W. Wang, Z. Wei,
S. Yang, and Y. Cao.
An efficient method to identify critical gates under circuit aging.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 735-740, San Jose, CA, November 5-8 2007.
- [4323]
- W. Wang, S. Yang,
S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, and Y. Cao.
The impact of NBTI on the performance of combinational and sequential
circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
364-369, San Diego, CA, June 4-8 2007.
- [4324]
- Y. Wang, H. Luo,
K. He, R. Luo, H. Yang, and Y. Xie.
Temperature-aware NBTI modeling and the impact of input vector control on
performance degradation.
Design, Automation and Test in Europe (DATE-07), pages 546-551, April
16-20 2007.
- [4325]
- X. Wang,
M. Tehranipoor, and R. Datta.
Path-RO: a novel on-chip critical path delay measurement under process.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 640-646, San Jose, CA, November 10-13 2008.
- [4326]
- Y. Wang, W.-S.
Luk, X. Zeng, J. Tao, C. Yan, J. Tong, W. Cai, and J. Ni.
Timing yield driven clock skew scheduling considering non-gaussian
distributions of critical path delays.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
223-226, Anaheim, CA, June 8-13 2008.
- [4327]
- J. Wang, D. Das,
and H. Zhou.
Gate sizing by lagrangian relaxation revisited.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(7):1071-1084, July 2009.
- [4328]
- J. Wang,
S. Yaldiz, X. Li, and L. T. Pileggi.
SRAM parametric failure analysis.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
496-501, San Francisco, CA, July 26-31 2009.
- [4329]
- X. Wang, Y. Cai,
Q. Zhou, S. X.-D. Tan, and T. Eguia.
Decoupling capacitance efficient placement for reducing transient power supply
noise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 745-751, San Jose, CA, November 2-5 2009.
- [4330]
- W. Wang, S. Yang,
S. Bhardwaj, S. Vrudhula, F. Liu, and Y. Cao.
The impact of NBTI effect on combinational circuit: modeling, simulation, and
analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(2):173-183, February 2010.
- [4331]
- Y. Wang, Z. Zhang,
C.-K. Koh, G.-K.-H. Pang, and N. Wong.
PEDS: passivity enforcement for descriptor systems via hamiltonian-symplectic
matrix pencil perturbation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 800-807, San Jose, CA, November 7-11 2010.
- [4332]
- H. Wang, S.-X.-D.
Tan, G. Liao, R. Quintanilla, and A. Gupta.
Full-chip runtime error-tolerant thermal estimation and prediction for
practical thermal management.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 716-723, San Jose, CA, November 7-10 2011.
- [4333]
- J. Wang, X. Chen,
C. Liao, and S. Hu.
The approximation scheme for peak power driven voltage partitioning.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 736-741, San Jose, CA, November 7-10 2011.
- [4334]
- L. Wang,
M. Olbrich, E. Barke, T. Buchner, M. Buhler, and P. Panitz.
A theoretical probabilistic simulation framework for dynamic power estimation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 708-715, San Jose, CA, November 7-10 2011.
- [4335]
- J. Wang, X. Chen,
L. Liu, and S. Hu.
Fast approximation for peak power driven voltage partitioning in almost linear
time.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 698-704, San Jose, CA, November 5-8 2012.
- [4336]
- S. Wang, J. Chen,
and M. Tehranipoor.
Representative critical reliability paths for low-cost and accurate on-chip
aging evaluation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 736-741, San Jose, CA, November 5-8 2012.
- [4337]
- Y. Wang, X. Hu,
C.-K. Cheng, G.-K.-H. Pang, and N. Wong.
Corrigendum to "A realistic early-stage power grid verification algorithm
based on hierarchical constraints".
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(3):452-452, March 2012.
- [4338]
- Y. Wang, X. Hu,
C.-K. Cheng, G.-K.-H. Pang, and N. Wong.
A realistic early-stage power grid verification algorithm based on hierarchical
constraints.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(1):109-120, January 2012.
- [4339]
- Y. Wang, Z. Zhang,
C.-K. Koh, G. Shi, G.-K.-H. Pang, and N. Wong.
Passivity enforcement for descriptor systems via matrix pencil perturbation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):532-545, April 2012.
- [4340]
- X. Wang, W. Yueh,
D. B. Roy, S. Narasimhan, Y. Zheng, S. Mukhopadhyay, D. Mukhopadhyay, and
S. Bhunia.
Role of power grid in side channel attack and power-grid-aware secure design.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [4341]
- K. Wang, B. H.
Meyer, R. Zhang, M. Stan, and K. Skadron.
Walking pads: managing c4 placement for transient voltage noise minimization.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [4342]
- S. Wang,
F. Firouzi, F. Oboril, and M. B. Tahoori.
Stress-aware P/G TSV planning in 3d-ics.
In 20th Asia and South Pacific Design Automation Conference, pages
94-99, Chiba/Tokyo, Japan, January 19-22 2015.
- [4343]
- T. Wang, J. Liu,
C. Zhuo, and Y. Shi.
1-bit compressed sensing based framework for built-in resonance frequency
prediction using on-chip noise sensors.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 721-728, Austin TX, November 2-6 2015.
- [4344]
- X. Wang, T. Wang,
T. Mak, M. Yang, Y. Jiang, and M. Daneshtalab.
Fine-grained runtime power budgeting for networks-on-chip.
In 20th Asia and South Pacific Design Automation Conference, pages
160-165, Chiba/Tokyo, Japan, January 19-22 2015.
- [4345]
- X. Wang, J. Xu,
Z. Wang, K. J. Chen, X. Wu, Z. Wang, P. Yang, and L. H. K. Duong.
An analytical study of power delivery systems for many-core processors using
on-chip and off-chip voltage regulators.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(9):1401-1414, September 2015.
- [4346]
- Y. Wang, M. Li,
X. Yi, Z. Song, M. Orshansky, and C. Caramanis.
Novel power grid reduction method based on l1 regularization.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4347]
- Y. Wang, S. Yao,
S. Tao, X. Chen, Y. Ma, Y. Shi, and H. Yang.
Hs3-DPG: hierarchical simulation for 3-D P/G network.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(10):2307-2311, October 2015.
- [4348]
- Y.-C. Wang,
S. Yin, M. Jun, X. Li, L. T. Pileggi, T. Mukherjee, and R. Negi.
Accurate passivity-enforced macromodeling for RF circuits via iterative
zero/pole update based on measurement data.
In 20th Asia and South Pacific Design Automation Conference, pages
441-446, Chiba/Tokyo, Japan, January 19-22 2015.
- [4349]
- J. Wang, N. Gong,
and E. G. Friedman.
PNS-FCR: flexible charge recycling dymanic circuit technique for low-power
microprocessors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(2):613-624, February 2016.
- [4350]
- Z. Wang, J. Xu,
P. Yang, L.-H.-K Duong, Z. Wang, X. Wang, Z. Wang, H. Li, and R. K. V. Maeda.
A holistic modeling and analysis of optical-electrical interfaces for
inter/intra-chip interconnects.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
24(7):2462-2474, July 2016.
- [4351]
- L.-C. Wang and M. S.
Abadir.
Data mining in EDA - basic principles, promises, and constraints.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [4352]
- T.-Y. Wang and C. C.-P.
Chen.
3-D thermal-ADI: A linear time chip level transient thermal simulator.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(12):1434-1445, December 2002.
- [4353]
- T.-Y. Wang and C. C.-P.
Chen.
Optimization of the power/ground network wire-sizing and spacing based on
sequential network simplex algorithm.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 157-162, San Jose, CA, March 18-21 2002.
- [4354]
- S. Wang and S. K. Gupta.
An automatic test pattern generator for minimizing switching activity during
scan testing activity.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(8):954-968, August 2002.
- [4355]
- J. Wang and O. Hafiz.
Predicting interconnect uncertainty with a new robust model order reduction
method.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 363-370, San Jose, CA, March 22-24 2004.
- [4356]
- Z. Wang and
A. Herkersdorf.
An efficient approach for system-level timing simulation of compiler-optimized
embedded software.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
220-225, San Francisco, CA, July 26-31 2009.
- [4357]
- R. Wang and C.-K. Koh.
A frequency-domain technique for statistical timing analysis of clock meshes.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 334-339, San Jose, CA, November 5-8 2007.
- [4358]
- F. Wang and X. Li.
Correlated bayesian model fusion: efficient performance modeling of large-scale
tunable analog/RF integrated circuits.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [4359]
- K. Wang and
M. Marek-Sadowska.
On-chip power supply network optimization using multigrid-based technique.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
113-118, Anaheim, CA, June 2-6 2003.
- [4360]
- K. Wang and
M. Marek-Sadowska.
Buffer sizing for clock power minimization subject to general skew constraints.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
159-164, San Diego, CA, June 7-11 2004.
- [4361]
- K. Wang and
M. Marek-Sadowska.
On-chip power-supply network optimization using multigrid-based technique.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(3):407-417, March 2005.
- [4362]
- V. Wang and D. Markovic.
Linear analysis of random process variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 292-296, San Jose, CA, November 10-13 2008.
- [4363]
- B. Wang and P. Mazumder.
Accelerated chip-level thermal analysis using multilayer green's function.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(2):325-344, February 2007.
- [4364]
- Y. Wang and C. McCrosky.
Negation trees: a unified approach to boolean function complementation.
IEEE Transactions on Computers, 45(5):626-630, May 1996.
- [4365]
- J. M. Wang and T. V.
Nguyen.
Extended krylov subspace method for reduced order analysis of linear circuits
with multiple sources.
In Design Automation Conference, pages 247-252, Los Angeles, CA, June
5-9 2000.
- [4366]
- W.-S. Wang and
M. Orshansky.
Path-based statistical timing analysis handling arbitrary delay correlations:
theory and implementation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(12):2976-2988, December 2006.
- [4367]
- W.-S. Wang and
M. Orshansky.
Robust estimation of parametric yield under limited descriptions of
uncertainty.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 884-890, San Jose, CA, November 5-9 2006.
- [4368]
- L. Wang and N. Patel.
Improving error tolerance for multithreaded register files.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(8):1009-1020, August 2008.
- [4369]
- C-Y. Wang and K. Roy.
Control unit synthesis targeting low-power processors.
In International Conference on Computer Design, pages 454-459,
1995.
- [4370]
- C-Y Wang and K. Roy.
COSMOS: A continuous optimization approach for maximum power estimation of
CMOS circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
52-55, San Jose, CA, November 9-13 1997.
- [4371]
- C.-Y. Wang and K. Roy.
Maximum power estimation for CMOS circuits using deterministic and
statistical approaches.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(1):134-140, March 1998.
- [4372]
- C-Y Wang and K. Roy.
Maximization of power dissipation in large CMOS circuits considering spurious
transitions.
IEEE Transactions on Circuits and Systems, 47(4):483-490, April
2000.
- [4373]
- T. Wang and
J. Roychowdhury.
Design tools for oscillator-based computing systems.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4374]
- L. Wang and N. R.
Shanbhag.
Low-power AEC-based MIMO signal processing for gigabit ethernet
1000base-T transceivers.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 334-339, Huntington Beach, California, August 6-7
2001.
- [4375]
- L. Wang and N. R.
Shanbhag.
Low-power MIMO signal processing.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(3):434-445, June 2003.
- [4376]
- S. Wang and
M. Tehranipoor.
Light-weight on-chip structure for measuring timing uncertainty induced by
noise in integrated circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(5):1030-1041, May 2014.
- [4377]
- Q. Wang and S. B. K.
Vrudhula.
Static power optimization of deep submicron CMOS circuits for dual VT
technology.
In IEEE/ACM International Conference on Computer-Aided Design, pages
490-496, San Jose, CA, November 8-12 1998.
- [4378]
- Q. Wang and S. B. K.
Vrudhula.
A new short circuit power model for complex CMOS gates.
In IEEE Alessandro Volta Memorial Workshop on Low-Power Design, pages
98-106, Como, Italy, March 4-5 1999.
- [4379]
- Q. Wang and S. B. K.
Vrudhula.
Algorithms for minimizing standby power in deep submicrometer, dual-vt CMOS
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(3):306-318, March 2002.
- [4380]
- J. Wang and X. Xiong.
Scalable power grid transient analysis via MOR-assisted time-domain
simulations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 548-552, San Jose, CA, November 18-21 2013.
- [4381]
- S. Wang.
General constructive representations for continuous piecewise-linear functions.
IEEE Transactions on Circuits and Systems, 51(9):1889-1896, September
2004.
- [4382]
- J. Wang.
Deterministic random walk preconditioning for power grid analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 392-398, San Jose, CA, November 5-8 2012.
- [4383]
- F.-Z. Wang.
A triangular periodic table of elementary circuit elements.
IEEE Transactions on Circuits and Systems, 60(3):616-623, March
2013.
- [4384]
- J. Warnock.
Circuit design challenges at the 14nm technology node.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
464-467, San Diego, CA, June 5-9 2011.
- [4385]
- V. Wason and
K. Banerjee.
A probabilistic framework for power-optimal repeater insertion in global
interconnects under parameter variations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 131-136, San Diego, CA, August 8-10 2005.
- [4386]
- S. Weber,
T. Ressurricao, and C. Duarte.
Yield prediction with a new generalized process capability index applicable to
non-normal data.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(6):931-942, June 2016.
- [4387]
- L. Wei, Z. Chen, and
K. Roy.
Mixed-vth (MVT) CMOS circuit design methodology.
In Design Automation Conference, pages 430-435, New Orleans, LA, June
21-25 1999.
- [4388]
- L. Wei, Z. Chen,
K. Roy, M. C. Johnson, Y. Ye, and V. K. De.
Design and optimization of dual-threshold circuits for low-voltage low-power
applications.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
7(1):16-24, March 1999.
- [4389]
- S. Wei,
S. Meguerdichian, and M. Potkonjak.
Gate-level characterization: foundations and hardware security applications.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
222-227, Anaheim, CA, June 13-18 2010.
- [4390]
- H. Wei, J. Zhang,
L. Wei, N. Patil, A. Lin, M. M. Shulaker, H.-Y. Chen, H.-S.-P. Wong, and
S. Mitra.
Carbon nanotube imperfection-immune digital VLSI: frequently asked questions
updated.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 227-230, San Jose, CA, November 7-10 2011.
- [4391]
- C.-J. Wei, H. Chen,
and S.-J. Chen.
Design and implementation of block-based partitioning for parallel flip-chip
power-grid analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(3):370-379, March 2012.
- [4392]
- J. Wei and C. Rowen.
Implementing low-power configurable processors - practical options and
tradeoffs.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
706-711, Anaheim, CA, June 13-17 2005.
- [4393]
- E. Wein.
Core integration: overview and challenges.
In IEEE/ACM International Conference on Computer-Aided Design, pages
450-452, San Jose, CA, November 8-12 1998.
- [4394]
- R. Weiss.
Synthetic biology: from bacteria to stem cells.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
634-635, San Diego, CA, June 4-8 2007.
- [4395]
- J. Welser.
The semiconductor industrys nanoelectronics research initiative: motivation and
challenges.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
298-300, San Francisco, CA, July 26-31 2009.
- [4396]
- C.-H.-P. Wen, L.-C.
Wang, and J. Bhadra.
An incremental learning framework for estimating signal controllability in
unit-level verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 250-257, San Jose, CA, November 5-8 2007.
- [4397]
- W. Wen, Y. Zhang,
Y. Chen, Y. Wang, and Y. Xie.
Ps3-RAM: a fast portable and scalable statistical STT-RAM reliability
analysis method.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1187-1192, San Francisco, CA, June 3-7 2012.
- [4398]
- W. Wen, C.-R. Wu,
X. Hu, B. Liu, T.-Y. Ho, X. Li, and Y. Chen.
An EDA framework for large scale hybrid neuromorphic computing systems.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4399]
- H. Wen and L. B. Kish.
Noise based logic: why noise?
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 152-155, San Jose, CA, November 5-8 2012.
- [4400]
- C. Wen and X. Ma.
A basis-function canonical piecewise-linear approximation.
IEEE Transactions on Circuits and Systems, 55(5):1328-1334, June
2008.
- [4401]
- S.-H. Weng,
Q. Chen, and C.-K. Cheng.
Time-domain analysis of large-scale circuits by matrix exponential method with
adaptive control.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(8):1180-1193, August 2012.
- [4402]
- S.-H. Weng,
Q. Chen, N. Wong, and C.-K. Cheng.
Circuit simulation via matrix exponential method for stiffness handling and
parallel processing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 407-414, San Jose, CA, November 5-8 2012.
- [4403]
- I.-C. Wey, Y.-G. Chen,
C.-H. Yu, A.-Y. A. Wu, and J. Chen.
Design and implementation of cost-effective probabilistic-based noise-tolerant
VLSI circuits.
IEEE Transactions on Circuits and Systems, 56(11):2411-2424, November
2009.
- [4404]
- J. White.
CAD challenges in biomems design.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
629-632, San Diego, CA, June 7-11 2004.
- [4405]
- R. Wille, B. Li,
U. Schlichtmann, and R. Drechsler.
From biochips to quantum circuits: computer-aided design for emerging
technologies.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [4406]
- S. Williams,
L. Oliker, R. Vuduc, J. Shalf, K. Yelick, and J. Demmel.
Optimization of sparse matrix-vector multiplication on emerging multicore
platforms.
In ACM/IEEE International Conference for High Performance Computing,
Networking, Storage, and Analysis (SC-07), Reno, NV, November 10-16
2007.
- [4407]
- J. Williamson, Q. Liu, F. Lu, W. Mohrman, K. Li, R. Dick, and
L. Shang.
Data sensing and analysis: challenges for wearables.
In 20th Asia and South Pacific Design Automation Conference, pages
136-141, Chiba/Tokyo, Japan, January 19-22 2015.
- [4408]
- C. J. Willits,
D. C. Dietz, and A. H. Moore.
Series-system reliability estimation using very small binomial samples.
IEEE Transactions on Reliability, 46(2):296-302, June 1997.
- [4409]
- S. Wimer and L. Koren.
The optimal fan-out of clock network for power minimization by adaptive gating.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(10):1772-1780, October 2012.
- [4410]
- E. Winfree and S.-W.
Shin.
Compiling and verifying DNA-based chemical reaction network implementations.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
115-115, San Diego, CA, June 5-9 2011.
- [4411]
- A. Witvrouw.
CMOS-MEMS integration: why, how and what.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 826-827, San Jose, CA, November 5-9 2006.
- [4412]
- J. M. Wojciechowski, L. J. Opalski, and K. Zamlynski.
Design centering using an approximation to the constraint region.
IEEE Transactions on Circuits and Systems I: Regular Papers,
51(3):598-607, March 2004.
- [4413]
- M. Wolf and E. Feron.
What don't we know about CPS architectures?
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4414]
- A. Wolfe.
Opportunities and obstacles in low-power system-level CAD.
In 33rd Design Automation Conference, pages 15-20, Las Vegas, NV,
June 3-7 1996.
- [4415]
- H.-S. Won, K.-S. Kim,
K.-O. Jeong, K.-T. Park, K.-M. Choi, and J.-T. Kong.
An MTCMOS design methodology and its application to mobile computing.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 110-115, Seoul, Korea, August 25-27 2003.
- [4416]
- J. L. Wong,
F. Koushanfar, S. Meguerdichian, and M. Potkonjak.
A probabilistic constructive approach to optimization problems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 453-456, San Jose, CA, November 4-8 2001.
- [4417]
- J.-L. Wong,
F. Koushanfar, S. Megerian, and M. Potkonjak.
Probabilistic constructive optimization techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(6):859-868, June 2004.
- [4418]
- N. Wong,
V. Balakrishnan, and C.-K. Koh.
Passivity-preserving model reduction via a computationally efficient
project-and-balance scheme.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
369-374, San Diego, CA, June 7-11 2004.
- [4419]
- H.-Y. Wong,
L. Cheng, Y. Lin, and L. He.
FPGA device and architecture evaluation considering process variations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 19-24, San Jose, CA, November 6-10 2005.
- [4420]
- J.-L. Wong,
F. Kourshanfar, and M. Potkonjak.
Flexible ASIC: shared masking for multiple media processors.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
909-914, Anaheim, CA, June 13-17 2005.
- [4421]
- E. Wong, J. Minz,
and S.-K. Lim.
Decoupling capacitor planning and sizing for noise and leakage reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 395-400, San Jose, CA, November 5-9 2006.
- [4422]
- H.-S.-P. Wong,
J. Deng, A. Hazeghi, T. Krishnamohan, and G.-C. Wan.
Carbon nanotube transistor circuits - models and tools for design and
performance optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 651-654, San Jose, CA, November 5-9 2006.
- [4423]
- J.-L. Wong,
A. Davoodi, V. Khandelwal, A. Srivastava, and M. Potkonjak.
A statistical methodology for wire-length prediction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1327-1336, July 2006.
- [4424]
- N. Wong,
V. Balakrishnan, C.-K. Koh, and T.-S. Ng.
Two algorithms for fast and accurate passivity-preserving model order
reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2062-2075, October 2006.
- [4425]
- E. Wong, J. R.
Minz, and S. K. Lim.
Decoupling-capacitor planning and sizing for noise and leakage reduction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(11):2023-2034, November 2007.
- [4426]
- H. Wong, V. Betz,
and J. Rose.
Quantifying the gap between FPGA and custom CMOS to aid microarchitectural
design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(10):2067-2080, October 2014.
- [4427]
- H.-S.-P. Wong,
H. Yi, M. Tung, and K. Okabe.
Physical layout design of directed self-assembly guiding alphabet for IC
contact hole/via patterning.
In ACM International Symposium on Physical Design 2015, pages 65-66,
Monterey, California, March 29 - April 1 2015.
- [4428]
- N. Wong and
V. Balakrishnan.
Fast balanced stochastic truncation via a quadratic extension of the
alternating direction implicit iteration.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 801-805, San Jose, CA, November 6-10 2005.
- [4429]
- N. Wong and
V. Balakrishnan.
Multi-shift quadratic alternating direction implicit iteration for high-speed
positive-real balanced truncation.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
257-260, San Francisco, CA, July 24-28 2006.
- [4430]
- N. Wong and
V. Balakrishnan.
Fast positive-real balanced truncation via quadratic alternating direction
implicit iteration.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(9):1725-1731, September 2007.
- [4431]
- J. S. J. Wong and P. Y. K.
Cheung.
Timing measurement platform for arbitrary black-box circuits based on
transition probability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(12):2307-2320, December 2013.
- [4432]
- N. Wong.
Fast positive-real balanced truncation of symmetric systems using cross riccati
equations.
Design, Automation and Test in Europe (DATE-07), pages 1496-1501,
April 16-20 2007.
- [4433]
- N. Wong.
Efficient positive-real balanced truncation of symmetric systems via
cross-riccati equations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(3):470-480, March 2008.
- [4434]
- N. Wong.
An efficient passivity test for descriptor systems via canonical projector
techniques.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
957-962, San Francisco, CA, July 26-31 2009.
- [4435]
- S. Woods and
G. Casinovi.
Efficient solution of systems of boolean equations.
In IEEE/ACM International Conference on Computer-Aided Design, pages
542-546, San Jose, CA, November 10-14 1996.
- [4436]
- M. H. Woods.
MOS VLSI reliability and yield trends.
In Proceedings of the IEEE, pages 1715-1729, December 1986.
Published as Proceedings of the IEEE, volume 74, number 12.
- [4437]
- W. Wu, M. Pedram, and
X. Wu.
Clock-gating and its application to low power design of sequential circuits.
In IEEE 1997 Custom Integrated Circuits Conference, pages 479-482,
Santa Clara, CA, May 5-8 1997.
- [4438]
- Q. Wu, Q. Qiu,
M. Pedram, and C.-S. Ding.
Cycle-accurate macro-models for RT-level power analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(4):520-528, December 1998.
- [4439]
- L. Wu, J. Fang,
H. Yonezawa, Y. Kawakami, N. Iwanishi, H. Yan, P. Chen, A. I-H Chen,
N. Koike, Y. Okamoto, C-S Yeh, and Z. Liu.
GLACIER: A hot carrier gate level circuit characterization and simulation
system for VLSI design.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 73-79, San Jose, CA, March 20-22 2000.
- [4440]
- Q. Wu, M. Pedram, and
X. Wu.
Clock-gating and its application to low power design of sequential circuits.
IEEE Transactions on Circuits and Systems, 47(3):415-420, March
2000.
- [4441]
- W.-L. Wu, C.-N. Sze,
C.-C. Cheung, and H. Fan.
On improved graph-based alternative wiring scheme for multi-level logic
optimization.
In 7th IEEE International Conference on Electronics, Circuits and
Systems, pages 654-657, Beirut, Lebanon, December 17-19 2000.
- [4442]
- Q. Wu, Q. Qiu, and
M. Pedram.
Estimation of peak power dissipation in VLSI circuits using the limiting
distributions of extreme order statistics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(8):942-956, August 2001.
- [4443]
- X. Wu, X. Hong, Y. Cai,
C. K. Cheng, J. Gu, and W. Dai.
Area minimization of power distribution network using efficient nonlinear
programming techniques.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 153-157, San Jose, CA, November 4-8 2001.
- [4444]
- B. Wu, J. Zhu, and
F. N. Najm.
An analytical approach for dynamic range estimation.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
472-477, San Diego, CA, June 7-11 2004.
- [4445]
- B. Wu, J. Zhu, and
F. N. Najm.
Dynamic range estimation for nonlinear systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 660-667, San Jose, CA, November 7-11 2004.
- [4446]
- X. Wu, X. Hong,
Y. Cai, Z. Luo, C.-K. Cheng, J. Gu, and W. Dai.
Area minimization of power distribution network using efficient nonlinear
programming techniques.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(7):1086-1094, July 2004.
- [4447]
- B. Wu, J. Zhu, and
F. N. Najm.
A non-parametric approach for dynamic range estimation of nonlinear systems.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
841-844, Anaheim, CA, June 13-17 2005.
- [4448]
- D. Wu,
G. Venkataraman, J. Hu, Q. Li, and R. Mahapatra.
Dicer: distributed and cost-effective redundancy for variation tolerance.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 393-397, San Jose, CA, November 6-10 2005.
- [4449]
- Y.-W. Wu, C.-L. Yang,
P.-H. Yuh, and Y.-W. Chang.
Joint exploration of architectural and physical design spaces with thermal
consideration.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 123-126, San Diego, CA, August 8-10 2005.
- [4450]
- B. Wu, J. Zhu, and
F. N. Najm.
Dynamic-range estimation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(9):1618-1636, September 2006.
- [4451]
- H. Wu, M. D.-F. Wong,
and I-M. Liu.
Timing-constrained and voltage-island-aware voltage assignment.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
429-432, San Francisco, CA, July 24-28 2006.
- [4452]
- W. Wu, L. Jin,
J. Yang, P. Liu, and S. X.-D. Tan.
A systematic method for functional unit power estimation in microprocessors.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
554-557, San Francisco, CA, July 24-28 2006.
- [4453]
- G. Wu, T. Lin, H.-H.
Huang, C. Chu, and P. A. Beerel.
Asynchronous circuit placement by lagrangian relaxation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 641-646, San Jose, CA, November 2-6 2014.
- [4454]
- J. Wu, J. Xiong,
P. Shil, and Y. Shi.
Real time anomaly detection in wide area monitoring of smart grids.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 197-204, San Jose, CA, November 2-6 2014.
- [4455]
- K. C. Wu, I.-C. Lin,
Y.-T. Wang, and S.-S. Yang.
BTI-aware sleep transistor sizing algorithm for reliable power gating
designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(10):1591-1595, October 2014.
- [4456]
- W. Wu, W. Xu,
R. Krishnan, Y.-L. Chen, and L. He.
Rescope: high-dimensional statistical circuit simulation towards full failure
region coverage.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [4457]
- R. Wu, C.-H. Chen,
C. Li, T.-C. Huang, F. Lan, C. Zhang, Y. Pan, J. E. Bowers, R. G. Beausoleil,
and K.-T. Cheng.
Variation-aware adaptive tuning for nanophotonic interconnects.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 487-493, Austin TX, November 2-6 2015.
- [4458]
- Y. Wu, S. Thomson,
H. Sun, D. Krause, S. Yu, and G. Kurio.
Free razor: a novel voltage scaling low-power technique for large soc designs.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(11):2431-2437, November 2015.
- [4459]
- S.-W. Wu and Y.-W. Chang.
Efficient power/ground network analysis for power integrity-driven design
methodology.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
177-180, San Diego, CA, June 7-11 2004.
- [4460]
- Q. Wu and M.-S. Hsiao.
State variable extraction and partitioning to reduce problem complexity for
ATPG and design validation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2275-2282, October 2006.
- [4461]
- B.-H. Wu and C.-Y. (Ric) Huang.
A robust general constrained random pattern generator for constraints with
variable ordering.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 109-114, San Jose, CA, November 5-8 2012.
- [4462]
- K.-C. Wu and D. Marculescu.
A low-cost, systematic methodology for soft error robustness of logic circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(2):367-379, February 2013.
- [4463]
- X. Wu and M. Pedram.
Low power sequential circuit design by using priority encoding and clock
gating.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 143-148, Italy, July 26-27 2000.
- [4464]
- H-J. Wunderlich.
Protest: a tool for probabilistic testability analysis.
In ACM/IEEE 22nd Design Automation Conference, pages 204-211,
1985.
- [4465]
- J. L. Wyatt, Jr.
Monotone sensitivity of nonlinear nonuniform RC transmission lines, with
application to timing analysis of digital MOS integrated circuits.
IEEE Transactions on Circuits and Systems, CAS-32(1):28-33, January
1985.
- [4466]
- J. L. Wyatt, Jr.
Signal delay in RC mesh networks.
IEEE Transactions on Circuits and Systems, CAS-32(5):507-510, May
1985.
- [4467]
- M. Xakellis and
F. Najm.
Statistical estimation of the switching activity in digital circuits.
In 31st ACM/IEEE Design Automation Conference, pages 728-733, San
Diego, CA, June 6-10 1994.
- [4468]
- H. Xiang, H. Qian,
C. Zhou, Y.-S. Lin, F. Yee, A. Sullivan, and P.-F. Lu.
Row based dual-VDD island generation and placement.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [4469]
- X-M. Xiao and R. Spence.
A fast constrained optimization algorithm for IC design.
In IEEE International Symposium on Circuits and Systems (ISCAS), pages
2252-2255, 1990.
- [4470]
- L. Xie, A. Davoodi,
J. Zhang, and T.-H. Wu.
Adjustment-based modeling for statistical static timing analysis with high
dimension of variability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 181-184, San Jose, CA, November 10-13 2008.
- [4471]
- S. Xie, Z. Yang, and
Y. Fu.
Nonnegative matrix factorization applied to nonlinear speech and image
cryptosystems.
IEEE Transactions on Circuits and Systems, 55(8):2356-2367, September
2008.
- [4472]
- L. Xie, Z. Davoodi,
J. Zhang, and T.-H. Wu.
Adjustment-based modeling for timing analysis under variability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(7):1085-1095, July 2009.
- [4473]
- L. Xie, A. Davoodi,
and K. K. Saluja.
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing
variations.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
274-279, Anaheim, CA, June 13-18 2010.
- [4474]
- Y. Xie, M. Nikdast,
J. Xu, W. Zhang, Q. Li, X. Wu, Y. Ye, X. Wang, and W. Liu.
Crosstalk noise and bit error rate analysis for optical network-on-chip.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
657-660, Anaheim, CA, June 13-18 2010.
- [4475]
- Y. Xie, M. Nikdast,
J. Xu, X. Wu, W. Zhang, Y. Ye, X. Wang, Z. Wang, and W. Liu.
Formal worst-case analysis of crosstalk noise in mesh-based optical
networks-on-chip.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(10):1823-1836, October 2013.
- [4476]
- L. Xie and A. Davoodi.
Robust estimation of timing yield with partial statistical information on
process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(12):2264-2276, December 2008.
- [4477]
- L. Xie and A. Davoodi.
Representative path selection for post-silicon timing prediction under
variability.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
386-391, Anaheim, CA, June 13-18 2010.
- [4478]
- L. Xie and A. Davoodi.
Bound-based statistically-critical path extraction under process variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(1):59-71, January 2011.
- [4479]
- L. Xie and A. Davoodi.
Post-silicon failing-path isolation incorporating the effects of process
variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(7):1008-1018, July 2012.
- [4480]
- J. Xie and
M. Swaminathan.
3d transient thermal solver using non-conformal domain decomposition approach.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 333-340, San Jose, CA, November 5-8 2012.
- [4481]
- J. Xiong, J. Chen,
J. Ma, and L. He.
Post global routing RLC crosstalk budgeting.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 504-509, San Jose, CA, November 10-14 2002.
- [4482]
- J. Xiong,
V. Zolotov, and L. He.
Robust extraction of spatial correlation.
In ACM/IEEE International Symposium on Physical Design, pages 2-9,
San Jose, CA, April 9-12 2006.
- [4483]
- J. Xiong,
V. Zolotov, N. Venkateswaran, and C. Visweswariah.
Criticality computation in parameterized statistical timing.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 63-68,
San Francisco, CA, July 24-28 2006.
- [4484]
- J. Xiong,
V. Zolotov, and L. He.
Robust extraction of spatial correlation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(4):619-631, April 2007.
- [4485]
- J. Xiong,
C. Visweswariah, and V. Zolotov.
Statistical ordering of correlated timing quantities and its application for
path ranking.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
122-125, San Francisco, CA, July 26-31 2009.
- [4486]
- X. Xiong and J. Wang.
An efficient dual algorithm for vectorless power grid verification under linear
current constraints.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
837-842, Anaheim, CA, June 13-18 2010.
- [4487]
- X. Xiong and J. Wang.
A hierarchical matrix inversion algorithm for vectorless power grid
verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 543-550, San Jose, CA, November 7-11 2010.
- [4488]
- X. Xiong and J. Wang.
Dual algorithms for vectorless power grid verification under linear current
constraints.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(10):1469-1482, October 2011.
- [4489]
- X. Xiong and J. Wang.
Vectorless verification of RLC power grids with transient current
constraints.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 548-554, San Jose, CA, November 7-10 2011.
- [4490]
- X. Xiong and J. Wang.
Parallel forward and back substitution for efficient power grid simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 660-663, San Jose, CA, November 5-8 2012.
- [4491]
- X. Xiong and J. Wang.
Constraint abstraction for vectorless power grid verification.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [4492]
- X. Xiong and J. Wang.
Verifying RLC power grids with transient current contraints.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(7):1059-1071, July 2013.
- [4493]
- Z. Xiu and R. A. Rutenbar.
Timing-driven placement by grid-warping.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
585-590, Anaheim, CA, June 13-17 2005.
- [4494]
- L. Xiu.
Clock technology: the next frontier.
IEEE Circuits and Systems Magazine, 17(2):27-46, Second Quarter
2017.
- [4495]
- C. Xu, T. S. Fiez, and
K. Mayaram.
An error control method for application of the discrete cosine transform to
extraction of substrate parasitics in ics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(5):932-938, May 2006.
- [4496]
- H. Xu, W.-B. Jone, and
R. Vemuri.
Accurate energy breakeven time estimation for run-time power gating.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 161-168, San Jose, CA, November 10-13 2008.
- [4497]
- T. Xu, K. Chakrabarty,
and V. K. Pamula.
Design and optimization of a digital microfluidic biochip for protein
crystallization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 297-301, San Jose, CA, November 10-13 2008.
- [4498]
- W. Xu, Y. Chen, X. Wang,
and T. Zhang.
Improving STT MRAM storage density through smaller-than-worst-case
transistor sizing.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 87-90,
San Francisco, CA, July 26-31 2009.
- [4499]
- T. Xu, P. Li, and
B. Yan.
Decoupling for power gating: sources of power noise and design strategies.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
1002-1007, San Diego, CA, June 5-9 2011.
- [4500]
- C. Xu, S. K. Kolluri,
K. Endo, and K. Banerjee.
Analytical thermal model for self-heating in advanced finfet devices with
implications for design and reliability.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(7):1045-1058, July 2013.
- [4501]
- H. Xu, V. F. Pavlidis,
X. Tang, W. Burleson, and G. DeMicheli.
Timing uncertainty in 3-D clock trees due to process variations and power
supply noise.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(12):2226-2239, December 2013.
- [4502]
- T. Xu and B. Brim.
A resonance-free power delivery system design methodology applying 3d optimized
extended adaptive voltage positioning.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 107-110, San Jose, CA, October 27-29 2008.
- [4503]
- M. Xu and F. J. Kurdahi.
Accurate prediction of quality metrics for logic level designs targeted toward
lookup-table-based FPGA's.
IEEE Transactions on Very Large Scale Integration Systems (VLSI),
7(4):411-418, December 1999.
- [4504]
- Q. Xu and P. Mazumder.
Equivalent-circuit interconnect modeling based on fifth-order differential
quadrature methods.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(6):1068-1079, December 2003.
- [4505]
- Q. Xu and N. Nicolici.
Wrapper design for multifrequency IP cores.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(6):678-685, June 2005.
- [4506]
- X. Xuan, A. D.
Singh, and A. Chatterjee.
Reliability evaluation for integrated circuit with defective interconnect under
electromigration.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 29-34, San Jose, CA, March 24-26 2003.
- [4507]
- G. Y. Yacoub and W. H. Ku.
An accurate simulation technique for short-circuit power dissipation based on
current component isolation.
In IEEE International Conference on Circuits and Systems, pages
1157-1161, 1989.
- [4508]
- G. Yahalom,
O. Vikinski, and G. Sizikov.
Architecture constraints over dynamic current consumption.
In IEEE Conference on Electrical Performance of Electronic Packaging
(EPEP), pages 3-6, San Jose, CA, October 27-29 2008.
- [4509]
- C. Yakopcic,
T. M. Taha, G. Subramanyan, and R. E. Pino.
Generalized memristive device SPICE model and its application in circuit
design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(8):1201-1214, August 2013.
- [4510]
- H. Yalcin, J. P.
Hayes, and K. A. Sakallah.
An approximate timing analysis method for datapath circuits.
In IEEE/ACM International Conference on Computer-Aided Design, pages
114-118, San Jose, CA, November 10-14 1996.
- [4511]
- H. Yalcin,
M. Mortazavi, R. Palermo, C. Bamji, and K. Sakallah.
Functional timing analysis for IP characterization.
In Design Automation Conference, pages 731-736, New Orleans, LA, June
21-25 1999.
- [4512]
- H. Yalcin,
M. Mortazavi, R. Palermo, C. Bamji, K. A. Sakallah, and J. P. Hayes.
Fast and accurate timing characterization using functional information.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(2):315-331, February 2001.
- [4513]
- H. Yalcin,
R. Palermo, M. Mortazavi, C. Bamji, K. Sakallah, and J. Hayes.
An advanced timing characterization method using mode dependency.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
657-660, Las Vegas, NV, June 18-22 2001.
- [4514]
- M. E. Yalcin,
J. A. K. Suykens, and J. Vandewalle.
True random bit generation from a double-scroll attractor.
IEEE Transactions on Circuits and Systems, 51(7):1395-1404, July
2004.
- [4515]
- H. Yalcin and J. P.
Hayes.
Hierarchical timing analysis using conditional delays.
In IEEE/ACM International Conference on Computer-Aided Design, pages
371-377, San Jose, CA, November 5-9 1995.
- [4516]
- T. J.
Yamaguchi, M. Soma, J. P. Nissen, D. E. Halter, R. Raina, and M. Ishida.
Skew measurements in clock distribution circuits using an analytic signal
method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(7):997-1009, July 2004.
- [4517]
- H. Yamamoto and
J. A. Davis.
Decreased effectiveness of on-chip dcoupling capacitance in high-frequency
operation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(6):649-659, June 2007.
- [4518]
- K. Yamamura and
K. Horiuchi.
A globally and quadratically convergent algorithm for solving nonlinear
resistive networks.
IEEE Transactions on Computer-Aided Design, 9(5):487-499, May
1990.
- [4519]
- K. Yamamura.
An algorithm for representing functions of many variables by superpositions of
functions of one variable and addition.
IEEE Transactions on Circuits and Systems, Part I, 43(4):338-340,
April 1996.
- [4520]
- T. Yamashita, T. Fujimoto, and K. Ishibashi.
A dynamic clock skew compensation circuit technique for low power clock
distribution.
In IEEE 2005 International Conference on Integrated Circuit Design and
Technology (ICICDT), pages 7-10, Austin, TX, May 9 - 11 2005.
- [4521]
- L. Yan, J. Luo, and
N. K. Jha.
Combined dynamic voltage scaling and adaptive body biasing for heterogeneous
distributed real-time embedded systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 30-37, San Jose, CA, November 9-13 2003.
- [4522]
- L. Yan, J. Luo, and
N. K. Jha.
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous
distributed real-time embedded systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):1030-1041, July 2005.
- [4523]
- B. Yan, S. X.-D. Tan,
P. Liu, and B. McGaughy.
SBPOR: second-order balanced truncation for passive order reduction of RLC
circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
158-161, San Diego, CA, June 4-8 2007.
- [4524]
- B. Yan, S. X.-D.Tan,
G. Chen, and L. Wu.
Modeling and simulation for on-chip power grid networks by locally dominant
krylov subspace method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 744-749, San Jose, CA, November 10-13 2008.
- [4525]
- B. Yan, L. Zhou,
S. X.-D. Tan, J. Chen, and B. McGaughy.
Demor: decentralized model order reduction of linear networks with massive
ports.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
409-414, Anaheim, CA, June 8-13 2008.
- [4526]
- C. Yan, S.-G. Wang,
and X. Zeng.
A new method for multiparameter robust stability distribution analysis of
linear analog circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 420-427, San Jose, CA, November 7-10 2011.
- [4527]
- B. Yan, S.-X.-D. Tan,
L. Zhou, J. Chen, and R. Shen.
Decentralized and passive model order reduction of linear networks with massive
ports.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(5):865-877, May 2012.
- [4528]
- L. Yan and J. R. English.
Economic cost modeling of environmental-stress-screening and burn-in.
IEEE Transactions on Reliability, 46(2):275-282, June 1997.
- [4529]
- L. Yan.
A PCA-based PCM data anlayzing method for diagnosing process failures.
IEEE Transactions on Semiconductor Manufacturing, 19(4):404-410,
November 2006.
- [4530]
- X. Yang, B. Krauter,
and L. T. Pileggi.
Combined ac and transient power distribution analysis.
In IEEE 1996 Custom Integrated Circuits Conference, pages 233-236,
San Diego, CA, May 5-8 1996.
- [4531]
- X. Yang, W. H. Ku,
and C.-K. Cheng.
RLS interconnect delay estimation via moments of amplitude and phase
response.
In IEEE/ACM International Conference on Computer-Aided Design, pages
208-213, San Jose, CA, November 7-11 1999.
- [4532]
- J.-S. Yang, J.-Y.
Kim, J.-H. Choi, M.-H. Yoo, and J.-T. Kong.
Elimination of false aggressors using the functional relationship for full-chip
crosstalk analysis.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 344-347, San Jose, CA, March 24-26 2003.
- [4533]
- G. Yang, Z. Wang,
and S.-M. Kang.
Low power and high performance circuit techniques for high fan-in dynamic
gates.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 421-424, San Jose, CA, March 22-24 2004.
- [4534]
- J. Yang,
L. Capodieci, and D. Sylvester.
Advanced timing analysis based on post-OPC extraction of critical dimensions.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages
359-364, Anaheim, CA, June 13-17 2005.
- [4535]
- C. Yang,
S. Chakraborty, D. Gope, and V. Jandhyala.
A parallel low-rank multilevel matrix compression algorithm for parasitic
extraction of electrically large structures.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
1053-1056, San Francisco, CA, July 24-28 2006.
- [4536]
- J. Yang, E. Cohen,
C. Tabery, N. Rodriguez, and M. Craig.
An up-stream design auto-fix flow for manufacturability enhancement.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages 73-76,
San Francisco, CA, July 24-28 2006.
- [4537]
- Y. Yang, C. Zhu,
Z.-P. Gu, L. Shang, and R. P. Dick.
Adaptive multi-domain thermal modeling and analysis for integrated circuit
synthesis and design.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 575-582, San Jose, CA, November 5-9 2006.
- [4538]
- S. Yang, W. Wang,
T. Lu, W. Wolf, N. Vijaykrishnan, and Y. Xie.
Case study of reliability-aware and lower-power design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(7):861-873, July 2008.
- [4539]
- J. Yang, Y. Cai,
Q. Zhou, and J. Shi.
Fast poisson solver preconditioned method for robust power grid analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 531-536, San Jose, CA, November 7-10 2011.
- [4540]
- J. Yang, Z. Li,
Y. Cai, and Q. Zhou.
Powerrush: a linear simulator for power grid.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 482-487, San Jose, CA, November 7-10 2011.
- [4541]
- Y.-S. Yang,
S. Sinha, A. Veneris, and R. K. Brayton.
Automating logic transformations with approximate spfds.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(5):651-664, May 2011.
- [4542]
- F. Yang, X. Zeng,
and Y.-F. Su.
AMOR: an efficient aggregating based model order reduction method for
many-terminal interconnect circuits.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
295-300, San Francisco, CA, June 3-7 2012.
- [4543]
- J. Yang, Z. Li,
Y. Cai, and Q. Zhou.
Powerrush: efficient transient simulation for power grid analysisy.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 653-659, San Jose, CA, November 5-8 2012.
- [4544]
- W. Yang, L. Wang,
and A. Mishchenko.
Lazy man's logic synthesis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 597-604, San Jose, CA, November 5-8 2012.
- [4545]
- Y.-S. Yang,
A. Veneris, and N. Nicolici.
Automating data analysis and acquisition setup in a silicon debug environment.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(6):1118-1131, June 2012.
- [4546]
- J. Yang, Y. Cai,
Q. Zhou, and J. Shi.
Friendly fast poisson solver preconditioning technique for power grid analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(4):899-912, April 2014.
- [4547]
- J. Yang, Z. Li,
Y. Cai, and Q. Zhou.
Powerrush: an efficient simulator for static power grid analysis.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(10):2103-2116, October 2014.
- [4548]
- Y.-M. Yang, Y.-W.
Chang, and I.-H.-R. Jiang.
itimerc: common path pessimism removal using effective reduction methods.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 600-605, San Jose, CA, November 2-6 2014.
- [4549]
- Y.-M. Yang,
I.-H.-R. Jiang, and S.-T. Ho.
Pushpull: short-path padding for timing error resilient circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(4):558-570, April 2014.
- [4550]
- J. Yang, L. Ma,
K. Zhao, Y. Cai, and T.-F. Ngai.
Early stage real-time soc power estimation using RTL instrumentation.
In 20th Asia and South Pacific Design Automation Conference, pages
779-784, Chiba/Tokyo, Japan, January 19-22 2015.
- [4551]
- K. Yang and K.-T. Cheng.
Silicon debug for timing errors.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(11):2084-2088, November 2007.
- [4552]
- C. Yang and
M. Ciesielski.
BDS: A BDD-based logic optimization system.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(7):866-876, July 2002.
- [4553]
- S. Yang and
M. Greenstreet.
Noise margin analysis for dynamic logic circuits.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 406-412, San Jose, CA, November 6-10 2005.
- [4554]
- S. Yang and M. R.
Greenstreet.
Simulating improbable events.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
154-157, San Diego, CA, June 4-8 2007.
- [4555]
- J. Yang and R. Gupta.
FV encoding for low-power data I/O.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 84-87, Huntington Beach, California, August 6-7 2001.
- [4556]
- B.-D. Yang and L.-S. Kim.
A low-power charge-recycling ROM architcture.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(4):590-600, August 2003.
- [4557]
- W. Yao, S. Pan,
B. Achkir, J. Fan, and L. He.
Modeling and application of multi-port TSV networks in 3-D IC.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(4):487-496, April 2013.
- [4558]
- J. Yao, Z. Ye, and
Y. Wang.
Scalable compact modeling for on-chip passive elements with correlated
parameter extraction and adaptive boundary compression.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(9):1424-1428, September 2014.
- [4559]
- A.-A. Yassine and F. N.
Najm.
A fast layer elimination approach for power grid reduction.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [4560]
- S. S. Yau and Y-S. Tang.
An efficient algorithm for generating complete test sets for combinational
logic circuits.
IEEE Transactions on Computers, C-20(11):1245-1251, November 1971.
- [4561]
- W. Ye, N. Vijaykrishnan,
M. Kandemir, and M. J. Irwin.
The design and use of simplepower: A cycle-accurate energy estimation tool.
In Design Automation Conference, pages 340-345, Los Angeles, CA, June
5-9 2000.
- [4562]
- X. Ye, P. Li, and
F. Liu.
Practical variation-aware interconnect delay and slew analysis for statistical
timing verification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 54-59, San Jose, CA, November 5-9 2006.
- [4563]
- X. Ye, P. Li, M. Zhao,
R. Panda, and J. Hu.
Analysis of large clock meshes via harmonic-weighted model order reduction and
port sliding.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 627-631, San Jose, CA, November 5-8 2007.
- [4564]
- X. Ye, F. Y. Liu, and
P. Li.
Fast variational interconnect delay and slew computation using quadratic
models.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
15(8):913-926, August 2007.
- [4565]
- X. Ye, Y. Zhan, and
P. Li.
Statistical leakage power minimization using fast equi-slack shell based
optimization.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-07), pages 37-42, Austin, Texas,
February 26-27 2007.
- [4566]
- X. Ye, Y. Zhan, and
P. Li.
Statistical leakage power minimization using fast equi-slack shell based
optimization.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
853-858, San Diego, CA, June 4-8 2007.
- [4567]
- X. Ye, W. Dong, P. Li,
and S. Nassif.
MAPS: multi-algorithm parallel circuit simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 73-78, San Jose, CA, November 10-13 2008.
- [4568]
- X. Ye, D. Wei, and
P. Li.
A multi-algorithm approach to parallel circuit simulation.
In ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems (TAU-08), pages 110-115, Monterey, CA,
February 25-26 2008.
- [4569]
- Y. Ye, F. Liu,
S. Nassif, and Y. Cao.
Statistical modeling and simulation of threshold variation under dopant
fluctuations and line-edge roughness.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
900-905, Anaheim, CA, June 8-13 2008.
- [4570]
- Z. Ye, D. Vasilyev,
Z. Zhu, and J. R. Phillips.
Sparse implicit projection (SIP) for reduction of general many-terminal
networks.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 746-743, San Jose, CA, November 10-13 2008.
- [4571]
- Z. Ye, Z. Zhu, and
J. R. Phillips.
Generalized krylov recycling methods for solution of multiple related linear
equation systems in electromagnetic analysis.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
682-687, Anaheim, CA, June 8-13 2008.
- [4572]
- Y. Ye, F. Liu, M. Chen,
and Y. Cao.
Variability analysis under layout pattern-dependent rapid-thermal annealing
process.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
551-556, San Francisco, CA, July 26-31 2009.
- [4573]
- X. Ye, P. Li, M. Zhao,
R. Panda, and J. Hu.
Scalable analysis of mesh-based clock distribution networks using
application-specific reduced order modeling.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(9):1342-1353, September 2010.
- [4574]
- R. Ye, F. Yuan, and
Q. Xu.
Online clock skew tuning for timing speculation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 442-447, San Jose, CA, November 7-10 2011.
- [4575]
- X. Ye, W. Dong, P. Li,
and S. Nassif.
Hierarchical multialgorithm parallel circuit simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(1):45-58, January 2011.
- [4576]
- Y. Ye, F. Liu,
M. Chen, S. Nassif, and Y. Cao.
Statistical modeling and simulation of threshold variation under random dopant
fluctuations and line-edge roughness.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(6):987-996, June 2011.
- [4577]
- Z. Ye, Y. Li, M. Gao,
and Z. Yu.
A novel framework for passive macro-modeling.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
546-551, San Diego, CA, June 5-9 2011.
- [4578]
- R. Ye, T. Wang,
F. Yuan, R. Kumar, and Q. Xu.
On reconfiguration-oriented approximate adder design and its application.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 48-54, San Jose, CA, November 18-21 2013.
- [4579]
- R. Ye, F. Yuan,
Z. Sun, W.-B. Jone, and Q. Xu.
Post-placement voltage island generation for timing-speculative circuits.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [4580]
- Y. Ye, J. Xu, B. Huang,
X. Wu, W. Zhang, Y. Wang, M. Nikdast, Z. Wang, W. Liu, and Z. Wang.
3-D mesh-based optical network-on-chip for multiprocessor system-on-chip.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(4):584-596, April 2013.
- [4581]
- F. Ye, F. Firouzi,
Y. Yang, K. Chakrabarty, and M. B. Tahoori.
On-chip droop-induced circuit delay prediction based on support-vector
machines.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(4):665-678, April 2016.
- [4582]
- F. Ye and K. Chakrabarty.
TSV open defects in 3-D integrated circuits: characterization, test, and
optimal spare allocation.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1024-1030, San Francisco, CA, June 3-7 2012.
- [4583]
- X. Ye and P. Li.
On-the-fly runtime adaptation for efficient execution of parallel
multi-algorithm circuit simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 298-304, San Jose, CA, November 7-11 2010.
- [4584]
- X. Ye and P. Li.
Parallel program performance modeling for runtime optimization of
multi-algorithm circuit simulation.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
561-566, Anaheim, CA, June 13-18 2010.
- [4585]
- A. Ye and J. Rose.
Using bus-based connections to improve field-programmable gate-array density
for implementing datapath circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(5):462-473, May 2006.
- [4586]
- Y. Ye and K. Roy.
Energy recovery circuits using reversible and partially reversible logic.
IEEE Transactions on Circuits and Systems, Part I: Fundamental Theory and
Applications, 43(9):769-778, September 1996.
- [4587]
- Y. Ye and K. Roy.
A graph-based synthesis algorithm for AND/XOR networks.
In 34th Design Automation Conference, pages 107-112, Anaheim, CA,
June 9-13 1997.
- [4588]
- Z. Ye and Z. Yu.
An efficient algorithm for modeling spatially-correlated process variation in
statistical full-chip leakage analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 239-244, San Jose, CA, November 2-5 2009.
- [4589]
- H. R. Yeager and R. W.
Dutton.
Improvement in norm-reducing newton methods for circuit simulation.
IEEE Transactions on Computer-Aided Design, 8(5):538-546, May
1989.
- [4590]
- G. Yeap.
CPU controller optimization in HDL logic synthesis.
In IEEE 1997 Custom Integrated Circuits Conference, pages 127-130,
Santa Clara, CA, May 5-8 1997.
- [4591]
- G. S. Yee,
R. Christopherson, T. Thorp, B. P. Wong, and C. Sechen.
An automated shielding algorithm and tool for dynamic circuits.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 369-374, San Jose, CA, March 20-22 2000.
- [4592]
- G. Yee and C. Sechen.
Clock-delayed domino for dynamic circuit design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(4):425-430, August 2000.
- [4593]
- Y.-J. Yeh, S.-Y. Kuo,
and J.-Y. Jou.
Converter-free multiple-voltage scaling techniques for low-power CMOS digital
design.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 20(1):172-178, January 2001.
- [4594]
- H.-H. Yeh, C.-Y. Wu,
and C.-Y. Huang.
MACACO: modeling and analysis of circuits for approximate computing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 674-678, San Jose, CA, November 7-10 2011.
- [4595]
- C. Yeh and Y.-S. Kang.
Cell-based layout techniques supporting gate-level voltage scaling for low
power.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(5):629-633, October 2000.
- [4596]
- C.-Y. Yeh and
M. Marek-Sadowska.
Sequential delay budgeting with interconnect prediction.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(10):1028-1037, October 2004.
- [4597]
- C.-Y. Yeh and
M. Marek-Sadowska.
Timing-aware power noise reduction in layout.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 627-634, San Jose, CA, November 6-10 2005.
- [4598]
- T.-H. Yeh and S-J. Wang.
Power-aware high-level synthesis with clock skew management.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(1):167-171, January 2012.
- [4599]
- J.-T. Yen and Q. R. Yin.
Multiprocessor design verification methodology for motorola mpc74xx powerpc
microprocessor.
In Design Automation Conference, pages 718-723, Los Angeles, CA, June
5-9 2000.
- [4600]
- S. Yesil, M. M.
Ozdal, T. Kim, A. Ayupov, S. Burns, and O. Ozturk.
Hardware accelerator design for data centers.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 770-775, Austin TX, November 2-6 2015.
- [4601]
- H. Yi, T. Yoneda,
M. Inoue, Y. Sato, S. Kajihara, and H. Fujiwara.
A failure prediction strategy for transistor aging.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
20(11):1951-1959, November 2012.
- [4602]
- J.-S. Yim, S.-O. Bae,
and C.-M. Kyung.
A floorplan based planning methodology for power and clock distribution in
asics.
In Design Automation Conference, pages 766-771, New Orleans, LA, June
21-25 1999.
- [4603]
- L. Yin, Y. Deng, and
P. Li.
Simulation-assisted formal verification of nonlinear mixed-signal circuits with
bayesian inference guidance.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(7):977-990, July 2013.
- [4604]
- T. Yioultsis, A. Woo, and A. C. Cangellaris.
Passive synthesis of compact frequency-dependent interconnect models via
quadrature spectral rules.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 827-834, San Jose, CA, November 9-13 2003.
- [4605]
- M. Yoeli and S. Rinon.
Application of ternary algebra to the study of static hazards.
Journal of the Association for Computing Machinery, 11(1):84-97,
January 1964.
- [4606]
- G. Yoh and F. N. Najm.
A statistical model for electromigration failures.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 45-50, San Jose, CA, March 20-22 2000.
- [4607]
- M. Yoon.
Sequence-switch coding for low-power data transmission.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
12(12):1381-1385, December 2004.
- [4608]
- H. Yoshida,
K. De, and V. Boppana.
Accurate pre-layout estimation of standard cell characteristics.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
208-211, San Diego, CA, June 7-11 2004.
- [4609]
- S. Youn and J. Kim.
Preventing global convergence failure in mixed-signal systems via indeterminate
state ("X") elimination.
IEEE Transactions on Circuits and Systems, 60(10):2561-2571, October
2013.
- [4610]
- D. Young and
A. Christou.
Failure-mechanism models for electromigration.
IEEE Transactions on Reliability, 43(2):186-192, June 1994.
- [4611]
- D. H. Younger.
Minimum feedback arc sets for a directed graph.
IEEE Transactions on Circuit Theory, CT-10(2):238-245, June 1963.
- [4612]
- A. Youssef,
M. Anis, and M. Elmasry.
POMR: a power-aware interconnect optimization methodology.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(3):297-307, March 2005.
- [4613]
- A. Youssef,
Z. Yang, M. Anis, S. Areibi, A. Vannelli, and M. Elmasry.
A power-efficient multipin ILP-based routing technique.
IEEE Transactions on Circuits and Systems, 57(1):225-235, January
2010.
- [4614]
- Q. Yu, J. M. Wang, and
E. S. Kuh.
Multipoint moment matching model for multiport distributed interconnect
networks.
In IEEE/ACM International Conference on Computer-Aided Design, pages
85-91, San Jose, CA, November 8-12 1998.
- [4615]
- Z. Yu, D. Yergeau, and
R. W. Dutton.
Full chip thermal simulation.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 145-149, San Jose, CA, March 20-22 2000.
- [4616]
- S. Yu, D. M. Petranovic,
S. Krishnan, K. Lee, and C. Y. Yang.
Resistance matrix in crosstalk modeling for multiconductor systems.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 122-125, San Jose, CA, March 22-24 2004.
- [4617]
- H. Yu, L. He, and
S. X.-D. Tan.
Block structure preserving model order reduction.
In IEEE Behavioral Modeling and Simulation Workshop, pages 1-6,
September 22-23 2005.
- [4618]
- H. Yu, Y. Shi, and
L. He.
Fast analysis of structured power grid by triangularization based structure
preserving model order reduction.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
205-210, San Francisco, CA, July 24-28 2006.
- [4619]
- H. Yu, Y. Shi, L. He,
and D. Smart.
A fast block structure preserving model order reduction for inverse inductance
circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 7-12, San Jose, CA, November 5-9 2006.
- [4620]
- G. Yu, W. Dong,
Z. Feng, and P. Li.
A framework for accounting for process model uncertainty in statistical static
timing analysis.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
829-834, San Diego, CA, June 4-8 2007.
- [4621]
- H. Yu, C. Chu, and
L. He.
Off-chip decoupling capacitor allocation for chip package co-design.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
618-621, San Diego, CA, June 4-8 2007.
- [4622]
- G. Yu, W. Dong,
Z. Feng, and P. Li.
Statistical static timing analysis considering process variation model
uncertainty.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(10):1880-1890, October 2008.
- [4623]
- X. Yu, , and
R. D. (Shawn) Blanton.
Multiple defect diagnosis using no assumptions on failing pattern
characteristics.
In ACM/IEEE 45th Design Automation Conference (DAC-08), pages
361-366, Anaheim, CA, June 8-13 2008.
- [4624]
- H. Yu, C. Chu, Y. Shi,
D. Smart, L. He, and S. X.-D. Tan.
Fast analysis of a large-scale inductive interconnect by
block-structure-preserved macromodeling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
18(10):1399-1411, October 2010.
- [4625]
- B. Yu, J.-R. Gao,
D. Ding, Y. Ban, J.-S. Yang, K. Yuan, M. Cho, and D. Z. Pan.
Dealing with IC manufacturability in extreme scaling.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 240-242, San Jose, CA, November 5-8 2012.
- [4626]
- C.-C. Yu, A. Alaghi,
and J. P. Hayes.
Scalable sampling methodology for logic simulation: reduced-ordered monte
carlo.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 195-201, San Jose, CA, November 5-8 2012.
- [4627]
- T. Yu, Z. Xiao, and
M. D. F. Wong.
Efficient parallel power grid analysis via additive schwarz method.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 399-406, San Jose, CA, November 5-8 2012.
- [4628]
- W. Yu, T. Zhang,
X. Yuan, and H. Qian.
Fast 3-D thermal simulation for integrated circuits with domain decomposition
method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(12):2014-2018, December 2013.
- [4629]
- B. Yu, D.-Z. Pan,
T. Matsunawa, and X. Zeng.
Machine learning and pattern matching in physical design.
In 20th Asia and South Pacific Design Automation Conference, pages
286-293, Chiba/Tokyo, Japan, January 19-22 2015.
- [4630]
- X. Yu and M. Abramovici.
Sequential circuit ATPG using combinational algorithms.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(8):1294-1310, August 2005.
- [4631]
- B. Yu and M. L. Bushnell.
A novel dynamic power cutoff technique (DPCT) for active leakage reduction in
deep submicron CMOS circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 214-219, Tegernsee, Germany, October 4-6 2006.
- [4632]
- H. Yu and L. He.
A provably passive and cost-efficient model for inductive interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(8):1283-1294, August 2005.
- [4633]
- Q. Yu and E. S. Kuh.
New efficient and accurate moment matching based model for crosstalk estimation
in coupled RC trees.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 151-157, San Jose, CA, March 26-28 2001.
- [4634]
- G. Yu and P. Li.
Yield-aware hierarchical optimization of large analog integrated circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 79-84, San Jose, CA, November 10-13 2008.
- [4635]
- G. Yu and P. Li.
Hierarchical analog/mixed-signal circuit optimization under process variations
and tuning.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(2):313-317, February 2011.
- [4636]
- Z. Yu and X. Liu.
Design of rotary clock based circuits.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages 43-48,
San Diego, CA, June 4-8 2007.
- [4637]
- T. Yu and M. D. F. Wong.
PGT SOLVER: an efficient solver for power grid transient analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 647-652, San Jose, CA, November 5-8 2012.
- [4638]
- L-P. Yuan, C-C.
Teng, and S-M. Kang.
Nonparametric estimation of average power dissipation in CMOS VLSI
circuits.
In IEEE 1996 Custom Integrated Circuits Conference, pages 225-228,
San Diego, CA, May 5-8 1996.
- [4639]
- L-P Yuan, C-C
Teng, and S-M Kang.
Statistical estimation of average power dissipation in CMOS VLSI circuits
using nonparametric techniques.
In International Symposium on Low Power Electronics and Design, pages
73-78, Monterey, CA, August 12-14 1996.
- [4640]
- L-P Yuan, C-C Teng,
and S-M Kang.
Statistical estimation of average power dissipation in sequential circuits.
In 34th Design Automation Conference, pages 377-382, Anaheim, CA,
June 9-13 1997.
- [4641]
- L.-P. Yuan, C.-C.
Teng, and S.-M. Kang.
Statistical estimation of average power dissipation using nonparametric
techniques.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
6(1):65-73, March 1998.
- [4642]
- J. Yuan, K. Albin,
A. Aziz, and C. Pixley.
Simplifying boolean constraint solving for random simulation-vector generation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 123-127, San Jose, CA, November 10-14 2002.
- [4643]
- J. Yuan, A. Aziz,
C. Pixley, and K. Albin.
Simplifying boolean constraint solving for random simulation-vector generation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(3):412-420, March 2004.
- [4644]
- L. Yuan,
S. Leventhal, and G. Qu.
Temperature-aware leakage minimization technique for real-time systems.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 761-764, San Jose, CA, November 5-9 2006.
- [4645]
- Y. Yuan and T. Chen.
The dynamic testing of combinational logic networks.
In IEEE 12th International Symposium on Fault Tolerant Computing,
pages 173-180, June 1982.
- [4646]
- L.-P. Yuan and S.-M. Kang.
A sequential procedure for average power analysis of sequential circuits.
In 1997 International Symposium on Low Power Electronics and Design,
pages 231-234, Monterey, CA, August 18-20 1997.
- [4647]
- F. Yuan and A. Opal.
An efficient transient analysis algorithm for mildly nonlinear circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(6):662-673, June 2002.
- [4648]
- L. Yuan and G. Qu.
Analysis of energy reduction on dynamic voltage scaling-enabled systems.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(12):1827-1837, December 2005.
- [4649]
- L. Yuan and G. Qu.
Enhanced leakage reduction technique by gate replacement.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 47-50,
Anaheim, CA, June 13-17 2005.
- [4650]
- L. Yuan and G. Qu.
A combined gate replacement and input vector control approach for leakage
current reduction.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(2):173-182, February 2006.
- [4651]
- L. Yuan and G. Qu.
Simultaneous input vector selection and dual threshold voltage assignment for
static leakage minimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 548-551, San Jose, CA, November 5-8 2007.
- [4652]
- F. Yuan and Q. Xu.
On timing-independent false path identification.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 532-535, San Jose, CA, November 7-11 2010.
- [4653]
- R. Zafalon,
C. Guardiani, M. C. Rossi, and R. Rambaldi.
Forward power annotation on physical layout floor-plan.
In IEEE 1996 Custom Integrated Circuits Conference, pages 389-392,
San Diego, CA, May 5-8 1996.
- [4654]
- R. Zafalon,
M. Rossello, E. Macii, and M. Poncino.
Power macromodeling for a high quality RT-level power estimation.
In 2000 IEEE 1st International Conference on Quality Electronic Design
(ISQED), pages 59-63, San Jose, CA, March 20-22 2000.
- [4655]
- M. Zaheer,
X. Li, and C. Gu.
MPME-DP: multi-population moment estimation via dirichlet process for
efficient validation of analog/mixed-signal circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 316-323, San Jose, CA, November 2-6 2014.
- [4656]
- V. Zakian.
Simplification of linear time-invariant systems by moment approximants.
International Journal of Control, 18(3):455-460, 1973.
- [4657]
- S. Zanella,
A. Nardi, A. Neviani, M. Quarantelli, S. Saxena, and C. Guardiani.
Analysis of the impact of process variations on clock skew.
IEEE Transactions on Semiconductor Manufacturing, 13(4):401-407,
November 2000.
- [4658]
- G. Zardalidis and I. G. Karafyllidis.
SECA: a new single-electron-circuit simulator.
IEEE Transactions on Circuits and Systems, 55(9):2774-2784, October
2008.
- [4659]
- P. Zarkesh-Ha, J. A. Davis, W. Loh, and J. D. Meindl.
On a pin versus gate relationship for heterogeneous systems: heterogeneous
rent's rule.
In IEEE Custom Integrated Circuits Conference, pages 93-96, Santa
Clara, CA, May 11-14 1998.
- [4660]
- P. Zarkesh-Ha, J. A. Davis, W. Loh, and J. D. Meindl.
Prediction of interconnect fan-out distribution using rent's rule.
In International Workshop on System-Level Interconnect Prediction,
pages 107-112, San Diego, CA, April 8-9 2000.
- [4661]
- E. Zeheb.
On solving the equation ax=b with more variables than unknowns.
IEEE Transactions on Circuits and Systems, 39(10):833-834, October
1992.
- [4662]
- J. Zeida and P. Frain.
General framework for removal of clock network pessimism.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 632-639, San Jose, CA, November 10-14 2002.
- [4663]
- A. Zemanian.
Delay-time bounds for on-chip and off-chip interconnection networks.
In IEEE International Symposium on Circuits and Systems (ISCAS), pages
2634-2637, 1990.
- [4664]
- J. Zeng, M. Abadir,
and J. Abraham.
False timing path identification using ATPG techniques and delay-based
estimation.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
562-565, New Orleans, LA, June 10-14 2002.
- [4665]
- Z. Zeng, X. Ye,
Z. Feng, and P. Li.
Tradeoff analysis and optimization of power delivery networks with on-chip
voltage regulation.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
831-836, Anaheim, CA, June 13-18 2010.
- [4666]
- Z. Zeng, T. Xu,
Z. Feng, and P. Li.
Fast static analysis of power grids: algorithms and implementations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 488-493, San Jose, CA, November 7-10 2011.
- [4667]
- Z. Zeng and P. Li.
Locality-driven parallel power grid optimization.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(8):1190-1200, August 2009.
- [4668]
- J. Zeng.
Modeling and simulation of electrified droplets and its application to
computer-aided design of digital microfluidics.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(2):224-233, February 2006.
- [4669]
- N.-E.
Zergainoh, L. Tambour, and A. Jerraya.
Automatic delay correction method for IP block-based design of VLSI
dedicated digital signal processing systems: theoretical foundations and
implementation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(4):349-360, April 2006.
- [4670]
- B. Zhai, D. Blaauw,
D. Sylvester, and K. Flautner.
Theoretical and practical limits of dynamic voltage scaling.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
868-873, San Diego, CA, June 7-11 2004.
- [4671]
- B. Zhai,
D. Blaauw, D. Sylvester, and K. Flautner.
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
13(11):1239-1252, November 2005.
- [4672]
- B. Zhai, S. Hanson,
D. Blaauw, and D. Sylvester.
Analysis and mitigation of variability in subthreshold design.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 20-25, San Diego, CA, August 8-10 2005.
- [4673]
- B. Zhai, R. G.
Dreslinski, D. Blaauw, T. Mudge, and D. Sylvester.
Energy efficient near-threshold chip multi-processing.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 32-37, Portland, Oregon, August 27-29 2007.
- [4674]
- R. Y. Zhan, H. G.
Feng, Q. Wu, G. Chen, X. K. Guan, and A. Z. Wang.
A technology-independent CAD tool for ESD protection device extraction -
esdextractor.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 510-513, San Jose, CA, November 10-14 2002.
- [4675]
- R. Zhan, H. Feng,
Q. Wu, H. Xie, X. Guan, G. Chen, and A. Z. H. Wang.
Esdextractor: a new technology-independent CAD tool for arbitrary ESD
protection device extraction.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(10):1362-1370, October 2003.
- [4676]
- Y. Zhan, A. J.
Strojwas, X. Li, L. T. Pileggi, D. Newmark, and M. Sharma.
Correlation-aware statistical timing analysis with non-gaussian delay
distributions.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 77-82,
Anaheim, CA, June 13-17 2005.
- [4677]
- Y. Zhan, A. J.
Strojwas, M. Sharma, and D. Newmark.
Statistical critical path analysis considering correlations.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 699-704, San Jose, CA, November 6-10 2005.
- [4678]
- Y. Zhan, T. Zhang,
and S. S. Sapatnekar.
Module assignment for pin-limited designs under the stacked-vdd paradigm.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 656-659, San Jose, CA, November 5-8 2007.
- [4679]
- X. Zhan, P. Li, and
E. Sanchez-Sinencio.
Distributed on-chip regulation: theoretical stability foundation, over-design
reduction and performance optimization.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [4680]
- Y. Zhan and S. S.
Sapatnekar.
A high efficiency full-chip thermal simulation algorithm.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 635-638, San Jose, CA, November 6-10 2005.
- [4681]
- Y. Zhan and S. S.
Sapatnekar.
High-efficiency green function-based thermal simulation algorithms.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(9):1661-1675, September 2007.
- [4682]
- H. Zhang,
V. George, and J. M. Rabaey.
Low-swing on-chip signaling techniques: effectiveness and robustness.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
8(3):264-272, June 2000.
- [4683]
- R. Zhang,
K. Roy, C.-K. Koh, and D. B. Janes.
Stochastic wire-length and delay distributions of 3-dimensional circuits.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 208-213, San Jose, CA, November 5-9 2000.
- [4684]
- X. Zhang,
W. Shan, and K. Roy.
Low-power weighted random pattern testing.
IEEE Transactions on Computer-Aided Design, 19(11):1389-1398,
November 2000.
- [4685]
- Y. Zhang, J. Lach,
K. Skadron, and M. R. Stan.
Odd/even bus invert with two-phase transfer for buses with coupling.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 80-83, Monterey, California, August 12-14 2002.
- [4686]
- L. Zhang, Y. Hu,
and C.-C. Chen.
Statistical timing analysis in sequential circuit for on-chip global
interconnect pipelining.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
904-907, San Diego, CA, June 7-11 2004.
- [4687]
- S. Zhang,
V. Wason, and K. Banerjee.
A probabilistic framework to estimate full-chip subthreshold leakage power
distribution considering within-die and die-to-die P-T-V variations.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 156-161, Newport Beach, CA, August 9-11 2004.
- [4688]
- L. Zhang,
W. Chen, Y. Hu, J. A. Gubner, and C. C.-P. Chen.
Correction-preserved non-gaussian statistical timing analysis with quadratic
timing model.
In ACM/IEEE 42nd Design Automation Conference (DAC-05), pages 83-88,
Anaheim, CA, June 13-17 2005.
- [4689]
- L. Zhang,
J. Wilson, R. Bashirullah, L. Luo, J. Xu, and P. Franzon.
Driver pre-emphasis techniques for on-chip global buses.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 186-191, San Diego, CA, August 8-10 2005.
- [4690]
- R. Zhang,
P. Gupta, L. Zhong, and N. K. Jha.
Threshold network synthesis and optimization and its application to
nanotechnologies.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(1):107-118, January 2005.
- [4691]
- B. Zhang,
A. Arapostathis, S. Nassif, and M. Orshansky.
Analytical modeling of SRAM dynamic stability.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 315-322, San Jose, CA, November 5-9 2006.
- [4692]
- L. Zhang,
W. Chen, Y. Hu, and C. C.-P. Chen.
Statistical static timing analysis with conditional linear MAX/MIN
approximation and extended canonical timing model.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(6):1183-1191, June 2006.
- [4693]
- L. Zhang,
W. Chen, Y. Hu, J. A. Gubner, and C.-C.-P. Chen.
Correlation-preserved statistical timing with a quadratic form of gaussian
variables.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(11):2437-2449, November 2006.
- [4694]
- M. Zhang,
S. Mitra, T.-M. Mak, N. Seifert, N.-J. Wang, Q. Shi, K.-S. Kim, N. R.
Shanbhag, and R. J. Patel.
Sequential element design with built-in soft error resilience.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
14(12):1368-1378, December 2006.
- [4695]
- W. Zhang, N. K.
Jha, and L. Shang.
Nature: a hybrid nanotube/CMOS dynamically reconfigurable architecture.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
711-716, San Francisco, CA, July 24-28 2006.
- [4696]
- W. Zhang,
L. Shang, and N. K. Jha.
Nanomap: an integrated design optimization flow for a hybrid nanotube/CMOS
dynamically reconfigurable architecture.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
300-305, San Diego, CA, June 4-8 2007.
- [4697]
- L. Zhang,
A. Carpenter, B. Ciftcioglu, A. Garg, M. Huang, and H. Wu.
Injection-locked clocking: a low power clock distribution scheme for
high-performance microprocessors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(9):1251-1256, September 2008.
- [4698]
- H. Zhang, T.-H.
Chen, M.-Y. Ting, and X. Li.
Efficient design-specific worst-case corner extraction for integrated circuits.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages
386-389, San Francisco, CA, July 26-31 2009.
- [4699]
- J. Zhang,
N. Patil, A. Hazeghi, and S. Mitra.
Carbon nanotube circuits in the presence of carbon nanotube density variations.
In ACM/IEEE 46th Design Automation Conference (DAC-09), pages 71-76,
San Francisco, CA, July 26-31 2009.
- [4700]
- J. Zhang, N. P.
Patil, and S. Mitra.
Probabilistic analysis and design of metallic-carbon-nanotube-tolerant digital
logic circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(9):1307-1320, September 2009.
- [4701]
- W. Zhang, W. Yu,
X. Hu, L. Zhang, R. Shi, H. Peng, Z. Zhu, C.-E. Lew, R. Murgai, T. Shibuya,
N. Ito, and C.-K. Cheng.
Efficient power network analysis considering multidomain clock gating.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 28(9):1348-1358, September 2009.
- [4702]
- W. Zhang, T.-H.
Chen, M.-Y. Ting, and X. Li.
Toward efficient large-scale performance modeling of integrated circuits via
multi-mode/multi-corner sparse regression.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
897-902, Anaheim, CA, June 13-18 2010.
- [4703]
- W. Zhang, X. Li,
and R. A. Rutenbar.
Bayesian virtual probe: minimizing variation characterization cost for
nanoscale IC technologies via bayesian inference.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
262-267, Anaheim, CA, June 13-18 2010.
- [4704]
- Y. Zhang, P. Li,
and G. M. Huang.
Separatrices in high-dimensional state space: system-theoretical tangent
computation and application to SRAM dynamic stability analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
567-572, Anaheim, CA, June 13-18 2010.
- [4705]
- J. Zhang, N. P.
Patil, A. Hazeghi, H.-S.-P. Wong, and S. Mitra.
Characterization and design of logic circuits in the presence of carbon
nanotube density variations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(8):1103-1113, August 2011.
- [4706]
- W. Zhang,
K. Balakrishnan, X. Li, D. Boning, and R. Rutenbar.
Toward efficient spatial variation decomposition via sparse regression.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 162-169, San Jose, CA, November 7-10 2011.
- [4707]
- W. Zhang, X. Li,
F. Liu, E. Acar, R. A. Rutenbar, and R. D. Blanton.
Virtual probe: a statistical framework for low-cost silicon characterization of
nanoscale integrated circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(12):1814-1827, December 2011.
- [4708]
- Y. Zhang,
X. Wang, and Y. Chen.
STT-RAM cell design optimization for persistent and non-persistent error
rate reduction: a statistical design view.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 471-477, San Jose, CA, November 7-10 2011.
- [4709]
- Z. Zhang, I. M.
Elfadel, and L. Daniel.
Model order reduction of fully parameterized systems by recursive least square
optimization.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 523-530, San Jose, CA, November 7-10 2011.
- [4710]
- J. Zhang, A. Lin,
N. Patil, H. Wei, L. Wei, H.-S.-P. Wong, and S. Mitra.
Robust digital VLSI using carbon nanotubes.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(4):453-471, April 2012.
- [4711]
- W. Zhang,
A. Singhee, J. Xiong, P. Habitz, A. Joshi, C. Visweswariah, and J. Sundquist.
A dynamic method for efficient random mismatch characterization of standard
cells.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 180-186, San Jose, CA, November 5-8 2012.
- [4712]
- J. Zhang,
F. Yuan, R. Ye, and Q. Xu.
Forter: a forward error correction scheme for timing error resilience.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 55-60, San Jose, CA, November 18-21 2013.
- [4713]
- W. Zhang,
K. Balakrishnan, X. Li, D. S. Boning, S. Saxena, A. Strojwas, and R. A.
Rutenbar.
Efficient spatial pattern analysis for variation decomposition via robust
sparse regression.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(7):1072-1085, July 2013.
- [4714]
- W. Zhang, X. Li,
S. Saxena, A. Strojwas, and R. Rutenbar.
Automatic clustering of wafer spatial signatures.
In ACM/IEEE 50th Design Automation Conference (DAC-2013), San
Francisco, CA, June 2-6 2013.
- [4715]
- Y. Zhang,
I. Bayram, Y. Wang, H. Li, and Y. Chen.
ADAMS: asymmetric differential STT-RAM cell structure for reliable and
high-performance applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 9-16, San Jose, CA, November 18-21 2013.
- [4716]
- Z. Zhang, T. A.
El-Moselhy, I. M. Elkfadel, and L. Daniel.
Stochastic testing method for transistor-level uncertainty quantification based
on generalized polynomial chaos.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(10):1533-1545, October 2013.
- [4717]
- Z. Zhang, I. M.
Elfadel, and L. Daniel.
Uncertainty quantification for integrated circuits: stochastic spectral
methods.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 803-810, San Jose, CA, November 18-21 2013.
- [4718]
- Z. Zhang, T. A.
El-Moselhy, I. M. Elfadel, and L. Daniel.
Calculation of generalized polynomial-chaos basis functions and gauss
quadrature rules in hierarchical uncertainty quantification.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 33(5):728-740, May 2014.
- [4719]
- Q. Zhang,
Y. Tian, T. Wang, F. Yuan, and Q. Xu.
Approxeigen: an approximate computing technique for large-scale
eigen-decomposition.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 824-830, Austin TX, November 2-6 2015.
- [4720]
- R. Zhang,
K. Mazumdar, B. H. Meyer, K. Wang, K. Skadron, and M. R. Stan.
Transient voltage noise in charge-recycled power delivery networks for
many-layer 3d-IC.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 152-158, Rome, Italy, July 22-24 2015.
- [4721]
- G.-L. Zhang,
B. Li, and U. Schlichtmann.
Piecetimer: a holistic timing analysis framework considering setup/hold time
interdependency using a piecewise model.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
Austin TX, November 7-10 2016.
- [4722]
- Y. Zhang and C. Chu.
Fast and effective placement refinement for routability.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
21(9):1751-1756, September 2013.
- [4723]
- X. Zhang and A. Louri.
A multilayer nanophotonic interconnection network for on-chip many-core
communications.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
156-161, Anaheim, CA, June 13-18 2010.
- [4724]
- H. Zhang and J. Rabaey.
Low-swing interconnect interface circuits.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 161-166, Monterey, CA, August 10-12 1998.
- [4725]
- M. Zhang and N. R.
Shanbhag.
A soft error rate analysis (SERA) methodology.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 111-118, San Jose, CA, November 7-11 2004.
- [4726]
- M. Zhang and N. R.
Shanbhag.
Soft-error-rate-analysis (SERA) methodology.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2140-2155, October 2006.
- [4727]
- Z-Y Zhao, Q-M Zhang,
G-L Tan, and J. M. Xu.
A new preconditioner for CGS iteration in solving large sparse nonsymmetric
linear equations in semiconductor device simulation.
IEEE Transactions on Computer-Aided Design, 10(11):1432-1440,
November 1991.
- [4728]
- M. Zhao, R. V.
Panda, S. S. Sapatnekar, T. Edwards, R. Chaudhry, and D. Blaauw.
Hierarchical analysis of power distribution networks.
In Design Automation Conference, pages 150-155, Los Angeles, CA, June
5-9 2000.
- [4729]
- S. Zhao, K. Roy,
and C.-K. Koh.
Frequency domain analysis of switching noise on power supply network.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 487-492, San Jose, CA, November 5-9 2000.
- [4730]
- M. Zhao, R. V.
Panda, S. S. Sapatnekar, and D. Blaauw.
Hierarchical analysis of power distribution networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(2):159-168, February 2002.
- [4731]
- S. Zhao, K. Roy,
and C.-K. Koh.
Decoupling capacitance allocation and its application to power-supply
noise-aware floorplanning.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 21(1):81-92, January 2002.
- [4732]
- M. Zhao, Y. Fu,
V. Zolotov, S. Sundarewsaran, and R. Panda.
Optimal placement of power supply pads and pins.
In ACM/IEEE 41st Design Automation Conference (DAC-04), pages
165-170, San Diego, CA, June 7-11 2004.
- [4733]
- P. Zhao, T. K.
Darwish, and M. A. Bayoumi.
High-performance and low-power conditional discharge flip-flop.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
12(5):477-484, May 2004.
- [4734]
- S. Zhao, B. Yao,
H. Chen, Y. Zhu, C.-K. Cheng, M. Hutton, T. Collins, S. Srinivasan, N. Chou,
and P. Suaris.
Improving the efficiency of static timing analysis with false paths.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 527-531, San Jose, CA, November 6-10 2005.
- [4735]
- D. Zhao,
S. Upadhyaya, and M. Margala.
Design of a wireless test control network with radio-on-chip technology for
nanometer system-on-a-chip.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(7):1411-1418, July 2006.
- [4736]
- M. Zhao, Y. Fu,
V. Zolotov, S. Sundareswaran, and R. Panda.
Optimal placement of power-supply pads and pins.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):144-154, January 2006.
- [4737]
- M. Zhao, R. Panda,
S. Sundareswaran, S. Yan, and Y. Fu.
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling
and linear programming.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
217-222, San Francisco, CA, July 24-28 2006.
- [4738]
- M. Zhao, R. Panda,
B. Reschke, Y. Fu, T. Mewett, S. Chandrasekaran, S. Sundareswaran, and
S. Yan.
On-chip decoupling capacitance and PIG wire co-optimization for dynamic
noise.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
162-167, San Diego, CA, June 4-8 2007.
- [4739]
- C. Zhao, Y. Zhao,
and S. Dey.
Intelligent robustness insertion for optimal transient error tolerance
improvement in VLSI circuits.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
16(6):714-724, June 2008.
- [4740]
- J. Zhao,
S. Madduri, R. Vadlamani, W. Burleson, and R. Tessier.
A dedicated monitoring infrastructure for multicore processors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
19(6):1011-1022, June 2011.
- [4741]
- X. Zhao, J. Wang,
Z. Feng, and S. Hu.
Power grid analysis with hierarchical support graphs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 543-547, San Jose, CA, November 7-10 2011.
- [4742]
- X. Zhao, J. R.
Tolbert, S. Mukhopadhyay, and S.-K. Lim.
Variation-aware clock network design methodology for ultralow voltage (ULV)
circuits.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(8):1222-1234, August 2012.
- [4743]
- X. Zhao, Y. Wan,
M. Scheuermann, and S.-K. Lim.
Transient modeling of TSV-wire electromigration and lifetime analysis of
power distribution network for 3d ics.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 363-370, San Jose, CA, November 18-21 2013.
- [4744]
- X. Zhao, Z. Feng,
and C. Zhuo.
An efficient spectral graph sparsification approach to scalable reduction of
large flip-chip power grids.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 218-223, San Jose, CA, November 2-6 2014.
- [4745]
- X. Zhao, L. Han, and
Z. Feng.
A performance-guided graph sparsification approach to scalable and robust
SPICE-accurate integrated circuit simulations.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(10):1639-1651, October 2015.
- [4746]
- Y. Zhao and S. Dey.
Fault-coverage analysis techniques of crosstalk in chip interconnects.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(6):770-782, June 2003.
- [4747]
- X. Zhao and Z. Feng.
GPSCP: A general-purpose support-circuit preconditioning approach to
large-scale SPICE-accurate nonlinear circuit simulations.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 429-435, San Jose, CA, November 5-8 2012.
- [4748]
- X. Zhao and Z. Feng.
Towards efficient SPICE-accurate nonlinear circuit simulation with on-the-fly
support-circuit preconditioners.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1119-1124, San Francisco, CA, June 3-7 2012.
- [4749]
- M. Zhao and S. S.
Sapatnekar.
Technology mapping for domino logic.
In IEEE/ACM International Conference on Computer-Aided Design, pages
248-251, San Jose, CA, November 8-12 1998.
- [4750]
- M. Zhao and S. S.
Sapatnekar.
Timing-driven partitioning and timing optimization of mixed static-domino
implementations.
IEEE Transactions on Computer-Aided Design, 19(11):1322-1336,
November 2000.
- [4751]
- H. Zheng,
B. Krauter, and L. Pileggi.
Electrical modeling of integrated-package power and ground distributions.
IEEE Design & Test of Computers, pages 24-31, May-June 2003.
- [4752]
- R. Zheng, J. Suh,
C. Xu, N. Hakim, B. Bakkaloglu, and Y. Cao.
Programmable analog device array (PANDA): a platform for transistor-level
analog reconfigurability.
In ACM/IEEE 48th Design Automation Conference (DAC-2011), pages
322-327, San Diego, CA, June 5-9 2011.
- [4753]
- L. Zheng, S. Shin,
and S.-M.-S. Kang.
Modular structure of compact model for memristive devices.
IEEE Transactions on Circuits and Systems, 61(5):1390-1399, May
2014.
- [4754]
- H. Zheng and L. T.
Pileggi.
Modeling and analysis of regular symmetrically structured power/ground
distribution networks.
In ACM/IEEE 39th Design Automation Conference (DAC-02), pages
395-398, New Orleans, LA, June 10-14 2002.
- [4755]
- H. Zheng and L. T.
Pileggi.
Robust and passive model order reduction for circuits containing susceptance
elements.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 761-766, San Jose, CA, November 10-14 2002.
- [4756]
- G. Zhong, C.-K.
Yoh, and K. Roy.
A twisted-bundle layout structure for minimizing inductive coupling noise.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 406-411, San Jose, CA, November 5-9 2000.
- [4757]
- G. Zhong, C.-K.
Koh, and K. Roy.
On-chip interconnect modeling by wire duplication.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 341-346, San Jose, CA, November 10-14 2002.
- [4758]
- G. Zhong, C.-K.
Koh, and K. Roy.
On-chip interconnect modeling by wire duplication.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(11):1521-1532, November 2003.
- [4759]
- L. Zhong, S. Ravi,
A. Raghunathan, and N. K. Jha.
Power estimation for cycle-accurate functional descriptions of hardware.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 668-675, San Jose, CA, November 7-11 2004.
- [4760]
- L. Zhong, S. Ravi,
A. Raghunathan, and N. K. Jha.
RTL-aware cycle-accurate functional power estimation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(10):2103-2117, October 2006.
- [4761]
- L. Zhong and N. K. Jha.
Interconnect-aware high-level synthesis for low power.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 110-117, San Jose, CA, November 10-14 2002.
- [4762]
- Y. Zhong and M. D.-F. Wong.
Fast algorithms for IR drop analysis in large power grid.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 351-357, San Jose, CA, November 6-10 2005.
- [4763]
- D. Zhou, N. Chen,
and W. Cai.
A fast wavelet collocation method for high-speed VLSI circuit.
In IEEE/ACM International Conference on Computer-Aided Design, pages
115-122, San Jose, CA, November 5-9 1995.
- [4764]
- H. Zhou, N. Shenoy,
and W. Nicholls.
Timing analysis with crosstalk as fixpoints on complete lattice.
In ACM/IEEE 38th Design Automation Conference (DAC-01), pages
714-719, Las Vegas, NV, June 18-22 2001.
- [4765]
- S. Zhou, Y. Zhu,
Y. Hu, R. Graham, M. Hutton, and C.-K. Cheng.
Timing model reduction for hierarchical timing analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 415-422, San Jose, CA, November 5-9 2006.
- [4766]
- Q. Zhou, L. Zhong,
and K. Mohanram.
Power signal processing: a new perspective for power analysis and optimization.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 165-170, Portland, Oregon, August 27-29 2007.
- [4767]
- S. Zhou, B. Yao,
H. Chen, Y. Zhu, M. Hutton, T. Collins, S. Srinivasan, N.-C. Chou, P. Suaris,
and C.-K. Cheng.
Efficient timing analysis with known false paths using biclique covering.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(5):959-969, May 2007.
- [4768]
- Y. Zhou,
S. Thekkei, and S. Bhunia.
Low power FPGA design using hybrid CMOS-NEMS approach.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 14-19, Portland, Oregon, August 27-29 2007.
- [4769]
- T.-Y. Zhou, H. Liu,
D. Zhou, and T. Tarim.
A fast analog circuit analysis algorithm for design modification and
verification.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(2):308-313, February 2011.
- [4770]
- Y. Zhou, E. Gad,
M. S. Nakhla, and R. Achar.
Structural characterization and efficient implementation techniques for
A-stable high-order integration methods.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 31(1):101-108, January 2012.
- [4771]
- H. Zhou and C. Lin.
Retiming for wire pipelining in system-on-chip.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(9):1338-1345, September 2004.
- [4772]
- Q. Zhou and K. Mohanram.
Cost-effective radiation hardening technique for combinational logic.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 100-106, San Jose, CA, November 7-11 2004.
- [4773]
- Q. Zhou and
K. Mohanram.
Elmore model for energy estimation in RC trees.
In ACM/IEEE 43rd Design Automation Conference (DAC-06), pages
965-970, San Francisco, CA, July 24-28 2006.
- [4774]
- Z. Zhou and K. Mohanram.
Gate sizing to radiation harden combinational logic.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 25(1):155-166, January 2006.
- [4775]
- T.-Y. Zhou and G. Wan.
A practical SOC simulation verification solution: robust design and automatic
modeling.
In The 2nd Annual Northeast Workshop on Circuits and Systems
(NEWCAS-04), pages 89-92, Montreal, Quebec, June 20-23 2004.
- [4776]
- H. Zhou and D. F. Wong.
An exact gate decomposition algorithm for low-power technology mapping.
In IEEE/ACM International Conference on Computer-Aided Design, pages
575-580, San Jose, CA, November 9-13 1997.
- [4777]
- H. Zhou.
Timing analysis with crosstalk is a fixpoint on a complete lattice.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 22(9):1261-1269, September 2003.
- [4778]
- Z. Zhu, B. Yao, and
C.-K. Cheng.
Power network analysis using an adaptive algebraic multigrid approach.
In ACM/IEEE 40th Design Automation Conference (DAC-03), pages
105-108, Anaheim, CA, June 2-6 2003.
- [4779]
- Z. Zhu, B. Song, and
J. K. White.
Algorithms in fastimp: a fast and wide band impedance extraction program for
complicated 3-D geometries.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(7):981-998, July 2005.
- [4780]
- X.-L. Zhu, X.-D.
Zhang, Z.-Z. Ding, and Y. Jia.
Adaptive nonlinear PCA algorithms for blind source separation without
prewhitening.
IEEE Transactions on Circuits and Systems, 53(3):745-753, March
2006.
- [4781]
- C. Zhu, Z. (Peter)
Gu, L. Shang, R. P. Dick, and R. G. Knobel.
Towards an ultra-low-power architecture using single-electron tunneling
transistors.
In ACM/IEEE 44th Design Automation Conference (DAC-07), pages
312-317, San Diego, CA, June 4-8 2007.
- [4782]
- Z. Zhu, H. Peng,
C.-K. Cheng, K. Rouz, M. Borah, and E.-S. Kuh.
Two-stage newton-raphson method for transistor-level simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 26(5):881-895, May 2007.
- [4783]
- H. Zhu, Y. Wang,
F. Liu, X. Li, X. Zeng, and P. Feldmann.
Efficient transient analysis of power delivery network with clock/power gating
by sparse approximation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 34(3):409-421, March 2015.
- [4784]
- D. Zhu, S. Yu RA N.
Chang, and M. Pedram.
Toward a profitable grid-connected hybrid electrical energy storage system for
residential use.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(7):1151-1164, July 2016.
- [4785]
- J. Zhu and S. Calman.
Context sensitive symbolic pointer analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 24(4):516-531, April 2005.
- [4786]
- J. Zhu and D. D. Gajski.
An ultra-fast instruction set simulator.
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems,
10(3):363-373, June 2002.
- [4787]
- N. Zhu and H.-Y. Koh.
Power grid modeling techniques for hierarchical power network analysis.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 313-318, San Jose, CA, March 26-28 2001.
- [4788]
- Z. Zhu and J. Phillips.
Random sampling of moment graph: a stochastic krylov-reduction algorithm.
Design, Automation and Test in Europe (DATE-07), pages 1502-1507,
April 16-20 2007.
- [4789]
- Y. Zhu and S.-X.-D. Tan.
GPU-accelerated parallel monte carlo analysis of analog circuits by
hierarchical graph-based solver.
In 20th Asia and South Pacific Design Automation Conference, pages
719-724, Chiba/Tokyo, Japan, January 19-22 2015.
- [4790]
- Z. Zhu and J. White.
Fastsies: a fast stochastic integral equation solver for modeling the rough
surface effect.
In IEEE/ACM International Conference on Computer-Aided Design
(ICCAD-05), pages 675-682, San Jose, CA, November 6-10 2005.
- [4791]
- Y. Zhu and J. Xiong.
Modern big data analytics for old-fashioned semiconductor industry
applications.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 776-780, Austin TX, November 2-6 2015.
- [4792]
- J. Zhu.
Symbolic pointer analysis.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 150-157, San Jose, CA, November 10-14 2002.
- [4793]
- H. Zhuang, S.-H.
Weng, J.-H. Lin, and C.-K. Cheng.
MATEX: a distributed framework for transient simulation of power distribution
networks.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [4794]
- H. Zhuang,
W. Yu, I. Kang, X. Wang, and C.-K. Cheng.
An algorithmic framework for efficient large-scale circuit simulation using
exponential integrators.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4795]
- H. Zhuang,
W. Yu, S.-H. Weng, I. Kang, J.-H. Lin, X. Zhang, R. Coutts, and C.-K. Cheng.
Simulation algorithms with exponential integration for time-domain analysis of
large-scale power delivery networks.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 35(10):1681-1693, October 2016.
- [4796]
- C. Zhuo, J. Hu,
M. Zhao, and K. Chen.
Fast decap allocation based on algebraic multigrid.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 107-111, San Jose, CA, November 5-9 2006.
- [4797]
- C. Zhuo, J. Hu,
M. Zhao, and K. Chen.
Power grid analysis and optimization using algebraic multigrid.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 27(4):738-751, April 2008.
- [4798]
- C. Zhuo, D. Blaauw,
and D. Sylvester.
Post-fabrication measurement-driven oxide breakdown reliability prediction and
management.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 441-448, San Jose, CA, November 2-5 2009.
- [4799]
- C. Zhuo, K. Chopra,
D. Sylvester, and D. Blaauw.
Process variation and temperature-aware full chip oxide breakdown reliability
analysis.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 30(9):1321-1334, September 2011.
- [4800]
- C. Zhuo, G. Wilke,
R. Chakraborty, A. Aydiner, S. Chakravarty, and W.-K. Shih.
A silicon-validated methodology for power delivery modeling and simulation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 255-262, San Jose, CA, November 5-8 2012.
- [4801]
- C. Zhuo,
D. Sylvester, and D. Blaauw.
A statistical framework for post-fabrication oxide breakdown reliability
prediction and management.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 32(4):630-643, April 2013.
- [4802]
- C. Zhuo, H. Gan, and
W.-K. Shih.
Early-stage power grid design: extraction, modeling and optimization.
In ACM/IEEE 50th Design Automation Conference (DAC-2014), San
Francisco, CA, June 1-5 2014.
- [4803]
- C. Zhuo, G. Wilke,
R. Chatraborty, A. A. Aydiner, S. Chakravarty, and W.-K. Shih.
Silicon-validated power delivery modeling and analysis on a 32-nm DDR I/O
interface.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
23(9):1760-1771, September 2015.
- [4804]
- C. Zhuo, K. Unda,
Y. Shi, and W.-K. Shih.
A novel cross-layer framework for early-stage power delivery and architecture
co-exploration.
In ACM/IEEE 53rd Design Automation Conference (DAC-2016), Austin,
Texas, June 5-9 2016.
- [4805]
- A. Ziabari,
J.-H. Park, E. K. Ardestani, J. Renau, S.-M. Kang, and A. Shakouri.
Power blurring: fast static and transient thermal analysis method for packaged
integrated circuits and power devices.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
22(11):2366-2379, November 2014.
- [4806]
- C. H. Ziesler,
J. Kim, V. S. Sathe, and M. C. Papaefthymiou.
A 225 mhz resonant clocked ASIC chip.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 48-53, Seoul, Korea, August 25-27 2003.
- [4807]
- A. Zjajo, Q. Tang,
M. Berkelaar, J. P. de Gyvez, A. Di Bucchianico, and N. van der Meijs.
Stochastic analysis of deep-submicrometer CMOS process for reliable circuits
designs.
IEEE Transactions on Circuits and Systems, 58(1):164-175, January
2011.
- [4808]
- J. G. Zola.
Simple model of metal oxide varistor for pspice simulation.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 23(10):1491-1494, October 2004.
- [4809]
- V. Zolotov,
D. Blaauw, R. Panda, and C. Oh.
Noise injection and propagation in high performance designs.
In IEEE International Symposium on Quality Electronic Design (ISQED),
pages 425-430, San Jose, CA, March 18-21 2002.
- [4810]
- V. Zolotov,
D. Blaauw, S. Sirichotiyakul, M. Becer, C. Oh, R. Panda, A. Grinshpon, and
R. Levy.
Noise propagation and failure criteria for VLSI designs.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 587-594, San Jose, CA, November 10-14 2002.
- [4811]
- V. Zolotov,
J. Xiong, S. Abbaspour, D. J. Hathaway, and C. Visweswariah.
Compact modeling of variational waveforms.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 705-712, San Jose, CA, November 5-8 2007.
- [4812]
- V. Zolotov,
J. Xiong, H. Fatemi, and C. Visweswariah.
Statistical path selection for at-speed test.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 624-631, San Jose, CA, November 10-13 2008.
- [4813]
- V. Zolotov,
C. Visweswariah, and J. Xiong.
Voltage binning under process variation.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 425-432, San Jose, CA, November 2-5 2009.
- [4814]
- V. Zolotov,
J. Xiong, H. Fatemi, and C. Visweswariah.
Statistical path selection for at-speed test.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems, 29(5):749-759, May 2010.
- [4815]
- V. Zolotov,
D. Sinha, J. Hemmett, E. Foreman, C. Visweswariah, J. Xiong, J. Leitzen, and
N. Venkateswaran.
Timing analysis with nonseparable statistical and deterministic variations.
In ACM/IEEE 49th Design Automation Conference (DAC-2012), pages
1061-1066, San Francisco, CA, June 3-7 2012.
- [4816]
- V. Zolotov and
P. Feldmann.
Variation aware cross-talk aggressor alignment by mixed integer linear
programming.
In ACM/IEEE 52nd Design Automation Conference (DAC-2015), San
Francisco, CA, June 7-11 2015.
- [4817]
- V. Zolotov and
J. Xiong.
Optimal statistical chip disposition.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 95-102, San Jose, CA, November 7-10 2011.
- [4818]
- Y. Zorian,
S. Dey, and M. J. Rodgers.
Test of future system-on-chips.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 392-398, San Jose, CA, November 5-9 2000.
- [4819]
- P. Zuber,
P. Dobrovolny, and M. Miranda.
A holistic approach for statistical SRAM analysis.
In ACM/IEEE 47th Design Automation Conference (DAC-2010), pages
717-722, Anaheim, CA, June 13-18 2010.
- [4820]
- P. S.
Zuchowski, C. B. Reynolds, R. J. Grupp, S. G. Davis, B. Cremen, and
B. Troxel.
A hybrid ASIC and FPGA architecture.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 187-194, San Jose, CA, November 10-14 2002.
- [4821]
- P. S.
Zuchowski, P. A. Habitz, J. D. Hayes, and J. H. Oppold.
Process and environmental variation impacts on ASIC timing.
In IEEE/ACM International Conference on Computer-Aided Design (ICCAD),
pages 336-342, San Jose, CA, November 7-11 2004.
- [4822]
- C. A. Zukowski.
Relaxing bounds for linear RC mesh circuits.
IEEE Transactions on Computer-Aided Design, CAD-5(2):305-312, April
1986.
- [4823]
- V. Zyuban and P. Kogge.
The energy complexity of register files.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 305-310, Monterey, CA, August 10-12 1998.
- [4824]
- V. Zyuban and P. Kogge.
Application of STD to latch-power estimation.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
7(1):111-115, March 1999.
- [4825]
- V. Zyuban and P. Kogge.
Optimization of high-performance superscalar architectures for energy
efficiency.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 84-89, Italy, July 26-27 2000.
- [4826]
- V. Zyuban and
D. Meltzer.
Clocking strategies and scannable latches for low power applications.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 346-351, Huntington Beach, California, August 6-7
2001.
- [4827]
- V. Zyuban and
P. Strenski.
Unified methodology for resolving power-performance tradeoffs at the
microarchitectural and circuit levels.
In ACM/IEEE International Symposium on Low Power Electronics and
Design, pages 166-171, Monterey, California, August 12-14 2002.
- [4828]
- V. Zyuban.
Optimization of scannable latches for low energy.
IEEE Transactions on Very Large Scale Intergration (VLSI) Systems,
11(5):778-788, October 2003.