As FPGAs grow ever larger and include more diverse and high-speed blocks like high-speed memory interfaces and processor subsystems, the task of connecting all the modules in a design with traditional low-level FPGA interconnect is becoming ever more time-consuming and difficult.
Furthermore, to expand FPGA use to new domains like the data center, faster design times and easy integration of components, including at run time with partial reconfiguration, are highly desirable. This talk will discuss how Networks-on-Chips can be incorporated into FPGAs as a new type of hard block, and can shorten design time, improve hardware efficiency, and simplify advanced CAD flows like partial reconfiguration. We will show how different design styles and applications can be mapped to and benefit from this new interconnect. We will outline progress to date on an automated CAD flow to simplify use of such structures, and some of the remaining challenges. Finally, we'll look at how recent trends in FPGA architecture and end markets - the interest in embedded FPGA fabrics in systems-on-chips, the increasing use of silicon interposers to build FPGA systems, registered interconnect, and the prospect of FPGAs in the data center - impact the case for making this disruptive architecture change.
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