LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY seg7 IS
	PORT(
		Input		: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
		Output		: OUT	STD_LOGIC_VECTOR(1 TO 8));
END seg7;

ARCHITECTURE Concurrent OF seg7 IS
	SIGNAL Flip : STD_LOGIC_VECTOR(1 TO 8);
BEGIN
	WITH Input SELECT
		--			 abcdefg.
		Flip	<=	"11111100" WHEN "0000",		--0
					"01100000" WHEN "0001",		--1
					"11011010" WHEN "0010",		--2
					"11110010" WHEN "0011",
					"01100110" WHEN "0100",
					"10110110" WHEN "0101",		--5
					"00111110" WHEN "0110",
					"11100000" WHEN "0111",		--7
					"11111110" WHEN "1000",		--8
					"11100110" WHEN "1001",		--9
					"11101110" WHEN "1010",		--A
					"00111110" WHEN "1011",		--b
					"10011100" WHEN "1100",		--C
					"01111010" WHEN "1101",		--d
					"10011110" WHEN "1110",		--E
					"10001110" WHEN OTHERS;		--F
	Output <= NOT (Flip);
END Concurrent;

LIBRARY ieee;
USE ieee.std_logic_1164.all;

PACKAGE seg7_package IS
	COMPONENT seg7	PORT (
		Input		: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
		Output		: OUT	STD_LOGIC_VECTOR(1 TO 8));
	END COMPONENT;
END seg7_package;