module wrapper (address, data,codata,srama,sramdl,sramdh,codsync,
		codread,codwrite,sram1en,sram2en,sram1oe,sram2oe,
		sram1we,sram2we,sram1ud,sram2ud,sram1ld,sram2ld,
		br_sfpga,bg_sfpga,bgack_sfpga,clk,fc,berr,as,halt,reset,
		dtack,lds,uds,rw,irqsf,iacksf,hex0,hex1,hex2,hex3,
		sfpga_digital, sfpga_con40,sfpga_logic,sfpga_con60,
		led);
	//change any pins being using as outputs to have type "output" 
	//leave unused as "input"
	input [23:1] address;
	input [15:0] data;
	input [31:0] codata;
	input [17:0] srama;
	input [15:0] sramdl;
	input [15:0] sramdh;
	input codsync;
	input codread;
	input codwrite;
	input sram1en;
	input sram2en;
	input sram1oe;
	input sram2oe;
	input sram1we;
	input sram2we;
	input sram1ud;
	input sram2ud;
	input sram1ld;
	input sram2ld;
	input br_sfpga;
	input bg_sfpga;
	input bgack_sfpga;
	input clk;
	input [2:0] fc;
	input berr;
	input as;
	input halt;
	input reset;
	input dtack;
	input lds;
	input uds;
	input rw;
	input irqsf;
	input iacksf;
	input [7:0] hex0;
	input [7:0] hex1;
	input [7:0] hex2;
	input [7:0] hex3;
	input [33:0] sfpga_digital;
	input [31:0] sfpga_con40;
	input [17:0] sfpga_logic;
	input [51:0] sfpga_con60;
	input [15:0] led;

//Declarations
//all of the above signals are "wires" by default.  If needed, declare
//them as "reg" or "integer" or "tri" ... etc., here, along with any
//other signals you need


//Code
//your code starts here

	
endmodule