Adaptive FPGAs: High-Level Architecture and a Synthesis Method
Abstract
This paper presents preliminary work exploring adaptive field
programmable gate arrays (AFPGAs). An AFPGA is adaptative in the sense
that the functionality of subcircuits placed on the chip can change in
response to changes observed on certain control signals. We describe
the high-level architecture which adds additional control logic and
SRAM bits to a traditional FPGA to produce an AFPGA. We also describe a
synthesis method that identifies and resynthesizes mutually exclusive
pieces of logic so that they may share the resources available in an
AFPGA. The architectural feature and its associated synthesis method
helps reduce circuit size by 28% on average and up to 40% on select
circuits.
Reference
Valavan Manohararajah, Stephen D. Brown, and Zvonko G. Vranesic, "Adaptive FPGAs: High-Level Architecture and a Synthesis Method", In Proceedings of the Conference on Field Programmable Logic and Applications, Madrid, Spain, August 2006, pp. 267-274.
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