FPGA PLB Evaluation using Quantified Boolean Satisfiability
Abstract
This paper describes a novel Field Programmable Gate Array (FPGA)
logic synthesis technique which determines if a logic function can
be implemented in a given programmable circuit and describes how
this problem can be formalized and solved using Quantified Boolean
Satisfiability. This technique is general enough to be applied to any
type of logic function and programmable circuit; thus, it has many
applications to FPGAs. The application demonstrated in this paper
is FPGA PLB evaluation where the results show that this tool allows
radical new features of FPGA logic blocks to be evaluated in a rigorous
scientific way.
Reference
Andrew C. Ling, Deshanand P. Singh and Stephen D. Brown, "FPGA PLB Evaluation using Quantified Boolean Satisfiability," in IEE Proceedings on Computers and Digital Techniques, Volume 153, Number 3, May 2006, pp. 165-172. ISSN 1350-2387 Invited Journal Paper
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