Variable Implementations for Vector Architectural and
A comprehensive software simulation package that is used for exploring
innovative architectural configurations and compiler algorithms for vector
processing. The package consists of:
VSUIF was the first component to be completed (see below).
pieces were built during the summer of 1997.
Corinna Lee defined the
VMIPS instruction set and worked out how the initial
structure for vmable.
retargetted both VSUIF and the publicly available
gas to VMIPS.
For the simulators, we started with mable and cello,
simulators developed by Todd Mowry.
Parham Aarabi modified these to include vector capabilities
resulting in vmable and vcello.
Kristin Hofstee wrote various TCL scripts to facilitate using VIVACE; and
Corinna Lee wrote TCL and awk scripts to analyze performanace data
produced by vcello. Since then,
Mark Stoodley has been
adding features to VIVACE,
primarily in vcello.
a collection of programs from image processing, speech processing,
and encryption that serve as the workload for our studies
an extension of the MIPS instruction set architecture to include
vector instructions for computational and memory operations.
- VSUIF: an experimental vectorizing compiler
- vgas: an assembler for VMIPS
- vmable: a functional simulator that emulates a fully
linked MIPS executable containing VMIPS instructions
- vcello: a parameterizable timing simulator that
simulates the behavior of a wide variety of vector processors
- a variety of awk and TCL scripts that facilitate tool usage
and analyze performance data
an experimental vectorizing compiler
augmented the SUIF
compiler with a vectorize pass and modified mgen
into vmgen to
generate stripmined, vectorized code for the
Torrent T0 vector microprocessor.
Implementation details and performance
evaluation data are available in Derek's
later modified vmgen to
target the VMIPS vector instruction set.
SVX_SUIF: an extension to VSUIF to target
short vector extensions (SVX)
Paul Hellyar is replacing
the code generation pass vmgen with
another pass that produces stripmined C source code with the
in-line assembly macros for a short vector extension. The generated
C code is then passed to the native C compiler that performs
instruction scheduling and register allocation for the SVX
The pass is being written such that it can be
"easily" retargetted to any of the SVX architectures.
The first target is the VIS instruction set.
Last Updated: 14 Aug 1998
Corinna G. Lee