Computing in Memory Bibliography

With processor clock rates outstripping memory access times, and each new hierarchy of caching contributing more overhead, it makes sense to put some of the processing internal to the memory where there already exists thousands of times more bandwidth then at the CPU.

Here's my bibliography of multiple processors in memory. The PIM and C-RAM were specifically designed to be useful as main memory. I've made the sometimes subjective distinction between "multiple processors integrated into structure of memory array" and "multiple processors and memory macros integrated onto a chip".

Please send suggestions and additions. Hypertext references like those below would be particularly helpful.

Multiple processors integrated into structure of memory array


Duncan G. Elliott, W. Martin Snelgrove, and Michael Stumm. Computational RAM: A Memory-SIMD Hybrid and its Application to DSP. In Custom Integrated Circuits Conference, pages 30.6.1--30.6.4, Boston, MA, May 1992.

Duncan G. Elliott, W. Martin Snelgrove, Christian Cojocaru, and Michael Stumm. A PetaOp/s is Currently Feasible by Computing in RAM. In PetaFLOPS Frontier Workshop, Washington DC, February 1995.

D. G. Elliott and W. M. Snelgrove. C-RAM: Memory with a Fast SIMD Processor. In Proceedings of the Canadian Conference on VLSI, pages 3.3.1--3.3.6, Ottawa, October 1990.


Jim Childers, Peter Reinecke, and Hiroshi Miyaguchi. SVP: A Serial Video Processor. IEEE 1990 Custom Integrated Circuits Conference, pages 17.3.1--17.3.4, May 1990.

Hiroshi Miyaguchi, Hujime Krasawa, and Xhinichi Watanabe. Digital TV with Serial Video Processor. IEEE Transactions on Consumer Electronics, 36(3):318--326, August 1990.


Per-Erik Danielsson, Par Emanuelsson, Keping Chen, and Per Ingelhag. Single-Chip High-Speed Computation of Optical Flow. In IAPR International Workshop on Machine Vision Applications, pages 331--335, November 1990.

Pixel Planes

Henry Fuchs, John Poulton, John Eyles, Trey Greer, Jack Goldfeather, David Ellsworth, Steve Molnar, Greg Turk, Brice Trebbs, and Laura Israel. Pixel-Planes 5: A Heterogeneous Multiprocessor Graphics System Using Processor-Enhanced Memories. In SIGGRAPH'89, pages 79--88, Boston, July 1989.

Henry Fuchs, Jack Goldfeather, Jeff P. Hultquist, Susan Spach, John D. Austin, Jr. Frederick P. Brooks, John G. Eyles, and John Poulton. Fast Spheres, Shadows, Textures, Transparencies, and Image Enhancemts in Pixel-Planes. In SIGGRAPH'85, pages 111--120, San Francisco, July 1985.

Multiple processors and memory macros integrated onto a chip


Maya Gokhale, Bill Holmes, and Ken Iobst. Processing in Memory: the Terasys Massively Parallel PIM Array. Computer, 28(3):23--31, April 1995.

Loring Wirbel. NSA taps Cray Computer, National. Electronic Engineering Times, 1(816):39--40, September 26 1994.

Maya Gokhale, Bill Holmes, Ken Iobst, Alan Murray, and Tom Turnbull. A Massively Parallel Processor-in-Memory Array and its Programming Environment. Technical Report SRC-TR-92-076, Supercomputer Research Centre - Institute for Defence Analyses, 17100 Science Drive, Bowie, Maryland, November 1992.


Peter M. Kogge. EXECUBE - A New Architecture for Scalable MPPs. In 1994 International Conference on Parallel Processing, pages I77--I84, August 1994.

Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, and Eric Retter. Combined DRAM and Logic for Massively Parallel Systems. In Conference on Advanced Research in VLSI, pages 4--16, Chapel Hill, NC, March 1995.


J. M. Jennings, E. W. Davis, and R. A. Heaton. Comparative Performance Evaluation of a New SIMD Machine. In Proceedings of the 3nd Symposium on the Frontiers of Massively Parallel Computation, pages 255--258, College Park MD, October 1990.

R. A. Heaton and D. W. Blevins. BLITZEN: a VLSI Array Processing Chip. In Custom Integrated Circuits Conference, pages 12.1.1--12.1.5, San Diego, CA, May 1989.

D. W. Blevins, E. W. Davis, R. A. Heaton, and J. H. Reif. BLITZEN: a Highly Integrated Massively Parallel Machine. In Proceedings of the 2nd Symposium on the Frontiers of Massively Parallel Computation, pages 399--406, Fairfax VA, October 1988.


Nobuyuki Yamashita, Tohru Kimura, Yoshihiro Fujita, Yoshiharu Aimoto, Takashi Manaba, Shin'ichiro Okazaki, Kazuyuki Nakamura, and Masakazu Yamashina. A 3.84GIPS Integrated Memory Array Processor LSI with 64 Processing Elements and 2Mb SRAM. In International Solid-State Circuits Conference, pages 260--261, San Francisco, February 1994. NEC.


Peter Schiefer. Picture Processing RAMs (PPRAMs) for Motion Estimation. ce, 38(3):570--575, August 1992.

Geometric Array Parallel Processor

Eugene L. Cloud. The Geometric Arithmetic Parallel Processor. In The 2nd Symposium on the Frontiers of Massively Parallel Computation, pages 373--381, Fairfax Virginia, October 1988. Martin Marietta Electronic Systems.

Single processor and significant memory integrated onto a chip

Analog Devices SHARC
more to come

Designs without hardware implementations

Microprocessor Report. Personal Views on the Future of Microprocessors. Microprocessor Report, pages 11--14, November 7 1990. [ David A. Patterson's comments on IRAM.]

Harold S. Stone. A Logic-in-Memory Computer. IEEE Transactions on Computers, C-19(1):73--78, January 1970.

Duncan's home page