ECE 1767: Class Information

Spring 2002

Staff

Professor: Andreas Veneris
Office: 2001 Sandford Fleming Building
Phone Number 946-3062
Email: veneris@eecg.toronto.edu
Office Hours: Monday 3:00-5:00pm or by appointment.



Lecture Schedule

Class meets every Monday 3:00-5:00pm, Room 506, 203 College Str.

Textbook

Any of the following two texts are very good references:

Michael L. Bushwell and Vishwani D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits Kluwer Academic Publishers 2000 (ISBN:0792379918 ).

Miron Abramovici, Melvin A. Breuer, and Arthur D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1994 (ISBN:0780310624).



Lecture notes are available on the WWW and on reserve at Copywell store on College Street.

Prerequisites

You are presumed to have good knowledge of undergraduate-level VLSI/logic design and computer architecture. You will also need to have some experience in programming using C or C++.

Course Contents

The following schedule is tentative but we expect to discuss most of the following topics:

Newsgroup and the Webpage

All official announcements will be posted through the ut.ecf.ece1767 newsgroup. Questions on the material (i.e. lectures, exam, project etc) will also be welcome through the newsgroup. No solutions should be posted by students on the newsgroup. Please do not use this newsgroup for any posts other than those relating to the course.

The WWW page for the class is www.eecg.toronto.edu/~ece1767 . In this site you will be able to find all available course information, lecture notes and project related handouts. Make sure to check the class homepage regularly, and to reload it to ensure you are seeing the most recent version. Virtually every handout will be distributed electronically, and important announcements will be also posted in the main WWW page

Course Requirements and Grading Policy

Course requirements include a machine project, a writing assignment and a final exam.

There will be 4 phases of a machine project, each of major scope. This project will serve as an application of the theory presented in the lectures on a real machine. In particular, you will build a parser that reads Verilog-like coded combinational and sequential circuits, a logic simulator, a parallel fault simulator and an automated test pattern generator. For the project you will need to code in C or C++. You will also need to include documentation for the different routines/pieces of your code. If you want to use some other programming language, you will need to arrange it with the instructor. There is no particular deadline to submit the different phases of this project. Nevertheless, you will need to complete the work of each phase before you proceed to the next one. At the end of the semester, the instructor will meet briefly with each student to discuss different aspects of the project. You will also need to submit a project report. A brief project description can be found here

For the writing assignment, you will be given a collection of research papers and you will be asked to select a few of them, read them and write a brief summary along with your comments on the work contained.

Finally, there will be a comprehensive 2:00hrs final exam at the end of the semester (Place/Time: TBA). The exam will be based on material covered in the lectures, i.e. all reading assignments. The final exam will be closed book.

The weighting scheme for the final grade is as follows:

Machine Project 50%
Writing Assignment and Project Report 15%
Final Exam 35%

Cheating Policy

Cheating is against ``fair--play'' and will not be tolerated under any circumstances. The University holds among its highest principles the notion of academic freedom and integrity. If you are caught cheating it may lower your grade or it can even give you a fail grade for the class. If you think that there is an issue that influences your performance then talk to the instructor.
Last Updated: Jan 10, 2000