2.0 Placement

A. Sangiovanni-Vincentelli, "Automatic Layout of Integrated Circuits", in Design systems for VLSI Circuits: Logic Synthesis and Silicon Compilation, G. De Micheli, A. Sangiovanni-Vincentelli and P. Antognetti, Eds., Martinus Nijhoff Publishers, pp. 113-196, 1987.

2. M. Hanan, J.M. Kurtzberg, "Placement Techniques", in Design Automation of Digital Systems, Vol. 1, M. Breuer, Ed., Englewood Cliffs, NJ: Prentice Hall, Chapter 5, 1972.

3. M.A. Breuer, "Min-Cut Placement", Design Automation & Fault-Tolerant Computing, vol. 1, no. 4, pp. 343-362, Oct. 1977.

4. A. E. Dunlop and B. W. Kernighan, "A Placement Procedure for Layout of VLSI Circuits", IEEE Trans. CAD of ICs and Systems, vol. CAD-4, no. 1, pp. 92-98, Jan. 1985.

5. J. P. Blanks, "Near-Optimal Quadratic-Based Placement for a Class of IC Layout Problems", IEEE Circuits and Devices Magazine, pp. 31-37, Sept. 1985.

6. L. Sha, R. Dutton, "An Analytical Algorithm for Placement of Arbitrarily Sized Rectangular Blocks," Proc. 1985 Design Automation Conference, pp. 602-607.

7. D.W. Jepsen and C.D. Gelatt, Jr., "Macro Placement by Monte Carlo Annealing", Proc. 1983 IEEE Int'l Conf. on Computer Design, pp 495-498, Nov. 1983.

8. D. Wong and C. Liu, "A New Algorithm for Floor-plan Design", Proc. 23rd ACM/IEEE Design Automation Conference, pp. 101-107, June 1986.

9. N. Togawa, M. Sato, T. Ohtsuki, "Maple: A simulataneous Technology Mapping, Placement and Global Routing Algorithm for Field-Programmable Gate Arrays," Proc. ICCAD '94, pp. 156-163.

10. C. Cheng, "RISA: Accurate and Efficient Placement and Routability Modeling," Proc. ICCAD '94, pp 690-696.