3.0 Routing

J. Soukup, "Circuit Layout", Proceedings of the IEEE, vol. 69, no. 10, pp. 1281-1304, Oct. 1981.

2. T. Ohtsuki, "Maze-Running and Line Search Algorithms", in Layout Design and Verification, Advances in CAD, Vol. 4, T. Ohtsuki, Ed., Elsevier Science Publishing Co., pp. 99-132, 1986.

3. D. Hightower, "The Lee Router Revisited", Proc. IEEE Int'l Conf on Computer Design, pp. 136-139, Oct 1983.

4. E. S. Kuh and M. Marek-Sadowska, "Global Routing", in Layout Design and Verification, Advances in CAD, Vol. 4, T. Ohtsuki, Ed., Elsevier Science Publishing Co., pp. 169-198, 1986.

5. J. Soukup and J.C. Royle, "On Hierarchical Routing", Journal of Digital Systems, vol. V, no. 3, pp. 265-289, 1981.

6. S. Brown, J.S. Rose, Z. Vranesic, "A Detailed Router for Field Programmable Gate Arrays" IEEE Transactions on Computer-Aided Design of Circuits and Systems, Vol. 11, No. 5, May 1992, pp. 620-628.

7. M. Burstein, "Channel Routing", in Layout Design and Verification, Advances in CAD, Vol. 4, T. Ohtsuki, Ed., Elsevier Science Publishing Co., pp. 133-168, 1986.

8. A. Hashimoto and J. Stevens, "Wire Routing by Optimizing Channel Assignment within Large Apertures", Proc. 8th SHARE/ACM/IEEE Design Automation Workshop, pp. 155-179, 1971.

9. D. Deutch, "A Dogleg Channel Router", Proc. 13th ACM/IEEE Design Automation Conference, pp. 425-433, 1976.

10. T. Yoshimura and E. Kuh, "Efficient Algorithms for Channel Routing", IEEE Trans, CAD of ICS and Systems, vol. CAD-1, pp. 25-34, Jan. 1982.

11. R. Rivest and C. Fiduccia, "A Greedy Channel Router", Proc. 19th ACM/IEEE Design Automation Conference, pp. 418-424, 1982.

12. M. Burstein and R. Pelavin, "Hierarchical Wire Routing", IEEE Trans, CAD of ICS and Systems, vol. CAD-2, pp. 223-234, Oct. 1983.