4.0 Wirability Theory

W.R. Heller, C. George Hsi, W.F. Mikhail, "Wirability - Designing Wiring Space for Chips and Chip Packages," IEEE Design & Test of Computers, vol. 1, no. 3, pp. 43-51, Aug. 1984.

2. Heller, W.R., W.F. Mikhail, W.E. Donath, "Prediction of Wiring Space Requirements for LSI", Jour. Design Automation and Fault Tolerant Computing, vol. 2, no. 2, pp. 117-144, May 1978.

3. W.E. Donath, "Placement and Average Interconnection Lengths of Computer Logic", IEEE Trans. Circuits and Systems, vol CAS-26, pp. 272-277, April 1979.

4. M. Feuer, "Connectivity of Random Logic", IEEE Trans Computers, vol. C-31, no. 1, pp. 29-33, Jan. 1982.

5. A. El Gamal, ''Two-Dimensional Stochastic Model for Interconnections in Master Slice Integrated Circuits,'' IEEE Transactions on Circuits and Systems Vol. CAS-28, No. 2, February 1981, pp. 127-138.

6. S. Sastry, A. Parker, "Stochastic Models for Wireability Analysis of Gate Arrays," IEEE Trans. Computer-Aided Design, Vol. CAD-5 No. 1, January 1986, pp. 52-65.