2.0 Preparation

Do Tutorial #1 and as much of Tutorial #2 as possible before the lab.

2. Design, enter and simulate a circuit, using VHDL as the primary entry method, that implements the following logic function:

You are to design two functions, f1 and f2, with four inputs named x1, x0, y1, and y0. Consider X = x1 x0 to be a number. The four possible patterns of x1 x0, namely 00, 01, 10, and 11 represent the four numbers 0, 1, 2, and 3, respectively (we will learn about representing numbers in this way later). Similarly, consider Y = y1 y0 to be another number with the same four possible values. The function f1 should be 1 when the two numbers represented by X and Y are equal (i.e., X = Y). Otherwise, f1 should be 0. The function f2 should be 1 when the number represented by X is greater than the number represented by Y (i.e., X > Y).

Show truth tables for functions f1 and f2. Derive a Boolean expression in canonical form for each function. Use algebraic manipulation to simplify the Boolean expressions. Enter the simplified Boolean expressions into maxplus2 in two different ways:

Draw a schematic that includes the logic gates for both f1 and f2.

ii. Write VHDL code that represents both f1 and f2 with Boolean equations.

Your preparation, to be marked, should consist of the VHDL code, the schematic and the simulator output all circuits, including that from Tutorial #1.

3. Be sure to place all your design files on your home directory on the ECE ugsparcs. Your login name and password for ECE ugsparcs is the same as your ECF account. If you don't have either an ECF account or an ECE account, request one from ECF (in GB 154) and then send a request to tim@eecg to make sure one is created on ECE ugsparcs. The ECE ugsparc machines are named ugsparc1.eecg.toronto.edu up to ugsparc48.eecg.toronto.edu, and are located at the south-west corner of the Galbraith building, second floor, roob GB 251. You can also bring files from home on a floppy disk, and use them directly on the PCs in the lab.