3.0 Preparation

Design and simulate (using timing simulation) the following circuits, using the graphic editor of maxplus2 (DO NOT USE VHDL, except for part 5). You should design all of these circuits with gates from the "prim" library. Make a separate directory for each of the circuits you design. Parts 1, 2, and 3 concern the basic operation of circuits that have memory, and so we have you design these from basic gates. Part 3 also demonstrates the use of hierarchical design in maxplus2.

A set-reset latch, using cross-coupled 2-input NOR gates.

2. A level-sensitive clocked D latch, based on the set-reset latch you designed above.

3. Turn the D-latch into a symbol (using File | Create Default Symbol method as described in Tutorial 1) and use it to design a positive edge-triggered master-slave D flip-flop. By doing this, you are creating hierarchy, which is the essential method of all large scale design.

4. Create a four-bit shift register (as illustrated above in Figure 1) from D flip-flops, and turn it into a symbol as you did for the D-latch in part 3. Instead of using the flip-flop you designed in part 3, use the D flip-flops available in the "prim" library (as the symbol "DFF"). Make sure that the four outputs Q₃, Q₂,Q₁, and Q₀, are available as outputs from your shift register. Recall that there are D flip-flops inside the basic macrocell of the MAX 7128, and you need not build them from scratch.

Design, enter and simulate a circuit that connects the outputs of the shift register (Q₃Q₂Q₁Q₀) to the inputs X₃X₂X₁X₀ of your circuit from Part 1 of Lab #3. The inputs to your circuit should be a single D_in signal and the clock. The point here is to generate the inputs to your circuit from Lab #3, serially, one bit at a time, rather than in parallel, four bits at a time. You will again need define a symbol for your circuit of Lab #3, and use hierarchy in the graphic editor to build this circuit.

5. Build and simulate an edge-triggered D-type flip flop as described in the VHDL Reference guide, Section A.10.2 on page 16. Build and simulate a 3-bit D register the same way, with an asynchronous reset signal as described in Section A.10.4.