3.0 Preparation

Note: all preparation schematics, VHDL code and simulation output MUST BE PRINTED on paper for marking, before the lab begins.

You are to design a sequence recognizer, like the one described in class, that outputs a "1" when the bit sequence 011 has occurred. The output of 1 should be in the cycle following the last 1 of the pattern 011. Here is an example input/output sequence:

Input	1	0	1	1	1	0	0	1	1	0	1	0	1	1	0
Output	0	0	0	0	1	0	0	0	0	1	0	0	0	0	1

Design this circuit using the graphic editor and basic gates only. DO NOT use VHDL. The purpose here is to be sure that you understand basic circuit of a state machine. Your preparation should consist of:

The state diagram (draw by hand).

ii. The state transition table, with encoding.

iii. Your schematic.

iv. The simulation output.

Design a sequence recognizer that recognizes the four-bit pattern 0101. Use VHDL and the CASE/IF statements as described in class and the VHDL reference manual. Below is a sample sequence of inputs and outputs:

Input	1	0	1	0	1	0	1	1	1	0	1	0	1	1	0
Output	0	0	0	0	0	1	0	1	0	0	0	0	0	1	0

Your preparation should consist of:

The state diagram.

ii. The VHDL code.

iii. The simulation output.