The Task

The purpose of the project is to:

Gain experience dealing with the design of a larger digital system, and to deal with the issues in going from a soft simple specification (“make a digital toaster controller”) to an actual complete design. There is no substitute for experience!
Express your creativity by applying what you have learned in this course to a project of your own choosing.

You are to design and implement a 3-week project of your own choosing that uses digital logic in some creative way. You may use any of the parts available in the lab, but are restricted to using just one of the Altera boards. If you wish, you may use the Altera Flex 10K70 on the board, as well as the Max 7128. An important part of this lab is the creativity required to think up an interesting project, and then negotiate with a TA or instructor as to the final form of the project.

Originality Approval

The first step in your project is to come up with an original idea. You must submit your idea, in a 1-3 line description, via email to your instructor for "originality" approval. The instructor will quickly respond to tell you if the idea has already been proposed more than once or twice. If it has, you'll have to come up with something different. Please note that this approval is only the first step and only deals with the basic idea, and not the scope/effort required for the project; that comes next:

Before the First Project lab

You will submit a two-page project proposal of what your project is about. See the course web page for the course to find project proposal form. This should be a short description that gives:

· The basic idea of the project, and the basic function of your circuit.

· Describe the inputs and outputs, and give a simple block diagrams describing how the various parts of your circuit interact.

· Your plan of action for each of the three lab periods - "milestones"

Present this to a TA or instructor to get their opinion on whether the project is viable. Once approved, you should get their signature. This is just a check to make sure that you do not try something overly ambitious.

At the first project lab, you must be prepared to begin implementing your project. Your marks for the first lab period will be based on the level of preparation you have done -- you must have circuits and schematics ready to be built and tested.

Written Report

You will be required to hand in a written report describing your project, which is due Wednesday December 3rd, at 5pm in Room Galbraith 204D. The report should have a maximum of 1500 words and contain the following sections:

o Introduction/Motivation - what you're doing and why.

o A description of the design, in both illustrations (block diagram) and words. This should be a well-written easy-to-read document!

o A description of the working/not working status of the project. If it did not work, indicate the reasons why you think it didn't work.

o Indicate what you would do differently if you were to start the project over again. What did you learn?

INCLUDE as Appendices: your design files (graphic design files and Verilog files) as well as any simulation output files that illustrate the working of your project.

The project accounts for 10% of your overall grade. This will be a total of 30 marks broken down in the following way:

1st Lab Prep: in the first lab project period, a mark out of 5. The mark will be based on the quality of the preparation - you must come with one period's worth of work to do in the lab, using the lab facilities. You shouldn't be doing design work here, but implementation.

Technical Quality: A grade out of 20 on how good your design is. Did you choose a reasonable implementation or did you come up with a complicated solution? Have you taken a good design approach, considering partitioning and hierarchy? How well does it work? This mark is based both on the report and the observations of your supervising TA in all of the labs.

Report Writing Quality: A grade out of 5 on the quality of the written document. In industry, good technical work usually goes un-noticed unless it is documented well.