ECE 241 F - Digital Systems Fall 2003
		Lecture and Lab Schedule
Lect #	Date (Sect 2/ Sect 1)	Contents	Text Chapter/Section	Lab (Monday or Tuesday 3-6pm)
1	Thur/Fri Sept 4/5	Motivation & course outline Handouts: basic, lab schedule, lab, software, project	2.1-2.2	No Lab
2	Mon/Tue Sept 8/9	light switches as logic functions, truth tables; gates; basic AND/OR Gates	2.3-2.4	No Lab
3	Wed        Sept 10	Variables & Functions, inversion simple boolean expressions simple synthesis of logic - from truth tables;  time-varying signals	2.5 (not including 2.5.1) 2.7
4	Thur/Fri Sept 11/12	Lab 1 Discussion; including good practice in labs - bottom up design, careful testing Voltage, Transistor switch, 7400 series ->Logic Analyzer; Boolean Algebgra, axioms,laws;	pp. 68-69.
5	Mon/Tue Sept 15/16	Sum of products representation, minterms simple algebraic minimization; example; Karnaugh Maps	2.6, 4.1	Lab 1 - Combinational Logic, TTL, Protoboard and Logic Analyzer
6	Wed       Sept 17	How programmable logic is built	3.5-7, 10
7	Thur/Fri Sept 18/19	Intro to CAD; Intro to Verilog HDL language Quartus demo; Lab 2 Discussion	2.9-2.10
8	Mon/Tue Sept 22/23	Optimization 1, 3 & 4 variable K-maps	4.1	Lab 2 - Introduction to CAD and Quartus - Tutorial
9	Wed       Sept 24	Optimization 2 don’t cares & 7 segment example	4.2-4.3
10	Thur/Fri Sept 25/26	Optimization 3 multi-level logic, factoring - LAB #3 discussion	4.6-4.7
11	Mon/Tue Sept 29/30	Sequential Logic; defn of comb. vs seq cross-coupled NOR latch Transparency, RS Latch, D Latch, timing diagram; desire for edge trig;	7.1-7.3	Lab 3 - 7 Segment Decoder
12	Wed         Oct 1	master-slave D-type flip flop, timing diagram, set up & hold time of FF; clock-to-Q;	7.4
13	Thur/Fri Oct 2/3	Serial Transmission of Data - shift registers, parallel to serial conversion;  Discuss LAB #4	7.8
14	Mon/Tue Oct 6/7	Coding Registers in Verilog - issues;	7.8	Lab 4 - Sequential Logic
15	Wed        Oct 8	Registers/Counters Ripple Counters Synchronous Counter; BCD Counter	7.9-7.11
16	Thur/Fri Oct 9/10	NMOS transistor,NMOS &CMOS gates - build using transistors	3.3
17	Wed/Tue  Oct 15/14	Numbers/Arithmetic Representation Adder - using basic logic, Full Adder, ripple carry adder - Lab 5 Discussion	5.1-5.2	Midterm!  No Lab
18	Wed        Oct 15	for Section 01 ONLY - Slop
19	Thur/Fri Oct 16/17	State Machine 1 intro; simple recognizer, steps-state diagram method #1 - 1 one encoding direct method	8.1
20	Mon/Tue Oct 20/21	State Machine 2 method #2 - full encoding, State Trans Table, K-map etc.	8.2-8.3	Lab 5 - Adders and Registers
21	Wed         Oct 22	State Machine 3 Lab 6 discussion - handshaking!	8.4-8.5
22	Thur/Fri Oct 23/24	Verilog coding of state machines, Project Headsup	8.4
23	Mon/Tue Oct 27/28	General form of Moore Machine, [Mealy machine  taught very briefly]  Example State Machine design for transmission system,	8.5	Lab 6 Small finite state machine - sequence recognizer handshaking state machine at high speed
24	Wed        Oct 29	State Machine Minimization - Brown method Project Headsup, handout approval form	8.6
25	Thur/Fri Oct 30/31	Lab 7 discussion - Entire lecture, concerns LPMs, handshaking big FSMs, FSM review
26	Mon/Tue Nov 3/4	RAM - SRAM; LPMs for SRAM Altera 10K RAM; How to use RAM	10.1.3	Lab 7 big finite statemachine, modules and handshaking PROJECT PROPOSALS DUE
27	Wed        Nov 5	Internal working of SRAM - bit, row, column deocder (for address bus) tristate gate (for data bus)	10.1.4
28	Thur/Fri Nov 6/7	Debouncing switches different methods - Debouncing switches	10.3.4
29	Mon/Tue Nov 10/11	transistor operation at process level real propagation delay, waveform fanout dependency	3.8-3.9	Project 1
30	Wed        Nov 12	Gate Delay; critical path, maximum clock frequency; hold time violations Flip flop timing - setup and hold, clock to Q, Demo Quartus Timing Analyzer
31	Thur/Fri Nov 13/14	Reading delays from data sheets Ring Oscillator
32	Mon/Tue Nov 17/18	Number Representation and Signed Number Representation	5.1-5.2	Project 2
33	Wed     Nov 19	2’s complement addition and Subtraction	5.2-5.3
34	Thur/Fri Nov 20/21	Carry-Lookahead Adders	5.4
35	Mon/Tue Nov 24/25	Hierarchical Carry Lookahead Bit Serial Adder	5.4	Project 3
36	Wed     Nov 26	Multipliers - unsigned & signed	5.6
37	Thur/Fri Nov 27/28	Multiplexors, Multiplexors as Logic Demultiplexors, Decoders	6.2-6.4
38	Mon/Tue Dec 1/2	FPGAs, LUT Mapping Multiplexors, Shannon's Expansion Theorem	6.1
39	Wed        Dec 3	Arithmetic Comparison Circuit (Not covered in class, but Read Section 6.5);  Course Summary, Exam Discussion	6.5	Project Reports Due