ECE241F - Digital Systems - Lab 3
More Complex Logic Design:
7-Segment Displays and Hierarchical Design
The purpose of this lab is to build several more complex logic circuits and to gain increased familiarity with the Quartus CAD software. It is also to learn how to create more complex circuits using a hierarchical design approach – groups of groups of circuits.
You are to create two logic circuits to drive one of the seven-segment displays on the Altera programmable logic board. Please see Section 5.0 for details of how to use the 7-segment display on the DE2 Educational board. (In particular, note that to turn a light-segment on, you must drive the corresponding pin to a logical “0”).
1. Design a circuit that takes a four bit (X3, X2, X1, X0) input from the digital switch board, and drives the 7 segment display HEX0 on the DE2 board as described in the table below. Note that for the letters, some are capitalized and some are not. (The reason is that a capital B, for example, would come out the same as an 8 on a 7- segment display, so we will display a lower-case b instead).
X3 X2 X1X0 |
Display (note the capitalization) |
0000 |
0 |
0001 |
1 |
0010 |
2 |
0011 |
3 |
0100 |
4 |
0101 |
5 |
0110 |
6 |
0111 |
7 |
1000 |
8 |
1001 |
9 |
1010 |
A |
1011 |
b |
1100 |
C |
1101 |
d |
1110 |
E |
1111 |
F |
Table 1
Determine the equations for the 7-segment display segments, and minimize them using the Karnaugh-map method described in class. Write Verilog code to represent the logic function for each segment as a Boolean equation (using just the AND (&), OR (|), NOT (~) operators). Simulate and test your equations using the Quartus functional simulator, or with the timing simulator with the Cyclone II device set.
1. Power up the DE2 Educational Board to verify that the 7-segment displays are functioning properly.
2. Download and test the circuit from Part 1 and Part 3 of the preparation. Show each working circuit to the TA.
The DE2 Educational Board has 8 Hex (7-segment) displays. These displays, as with almost everything on the DE2, are connected directly to the pins of the chip. The figure below shows the indexing of each segment.
Figure 2
The table below shows how the segments in Figure 2 correspond to the pin names from the DE2_pin_assignments.csv file.
Display Segment |
Wires for HEX0 |
Wires for HEX1 |
0 |
HEX0[0] |
HEX1[0] |
1 |
HEX0[1] |
HEX1[1] |
2 |
HEX0[2] |
HEX1[2] |
3 |
HEX0[3] |
HEX1[3] |
4 |
HEX0[4] |
HEX1[4] |
5 |
HEX0[5] |
HEX1[5] |
6 |
HEX0[6] |
HEX1[6] |
The same naming convention is used for all of the Hex displays on the DE2 board.