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5724276 : Logic block structure optimized for sum generation INVENTORS: Rose; Jonathan S., Palo Alto, CA Bauer; Trevor J., Campbell, CA ASSIGNEES: Xilinx, Inc., San Jose, CA ISSUED: Mar. 3 , 1998   FILED: June 17, 1996 SERIAL NUMBER: 664628   MAINT. STATUS: INTL. CLASS (Ed. 6): G06F 007/50; U.S. CLASS: 364/716.06; 364/784.01; FIELD OF SEARCH: 364-716,768,784,786,785 ; 326-38,39 ; ABSTRACT:   The present invention is part of a Field Programmable Gate Array logic block which performs arithmetic functions as well as logic functions. The novel structure includes a small amount of extra hardware which can implement the XOR function as well as several other useful functions. With the invention, one-bit adders can be generated using only a single lookup table, a carry multiplexer, and the extra hardware. N-bit adders can be implemented with N lookup tables. Multipliers, adders, counters, loadable synchronous set-reset counters and many other common functions are all more efficiently implemented with the invention. U.S. REFERENCES:   (No patents reference this one) Patent Inventor   Issued    Title 5267187 Hsieh et al. 11 /1993 Logic structure and circuit for fast carry 5436574 Veenstra 7 /1995 Universal logic module with arithmetic capabilities 5481206 New et al. 1 /1996 Circuit for fast carry and logic 5481486 Cliff et al. 1 /1996 Look up table implementation of fast carry arithmetic and exclusive-OR operations EXEMPLARY CLAIM(s): Show all 3 claims We claim:     1. A field programmable gate array (FPGA) logic block structure comprising: a first multiplexer having at least two data inputs and at least one control input; a second multiplexer having at least two data inputs and at least one control input, said second multiplexer providing a first data input to said first multiplexer; a first lookup table having a plurality of inputs, said first lookup table providing true and complement output signals, one as a second data input to said first multiplexer and one as a first data input to said second multiplexer; a second lookup table having a plurality of inputs, said second lookup table providing a second data input to said second multiplexer; and a plurality of lines accessible from a general interconnect structure of an FPGA, one of said lines providing a control input to said first multiplexer, and other of said lines providing said inputs to said first and second lookup tables. RELATED U.S. APPLICATIONS: none FOREIGN APPLICATION PRIORITY DATA: none FOREIGN REFERENCES: none OTHER REFERENCES: "The Programmable Logic Data Book", 1994, pp. 2-9 through 2-13, available from Xilinx Inc., 2100 Logic Drive, San Jose, CA 95124. ATTORNEY, AGENT, or FIRM: Young; Edel M.; PRIMARY/ASSISTANT EXAMINERS: Ngo; Chuong Dinh;

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