EVE: A CAD Tool Providing Placement and Pipelining Assistance for High-Speed FPGA Circuit Designs

Extracting Logic Delays

•Enumerate all delay paths in a slice, for each path:

–Construct a circuit with the path using XDL

–Query Xilinx Timing Analyzer (TRACE)

–Record delay in delay-matching table

G1->FFY_D : 0.815ns

F1->FFX_D : 0.815ns

Logic Slice