References

1

J. Rose and S. Brown, ``Flexibility of interconnection structures for field-programmable gate arrays,'' IEEE Journal of Solid-State Circuits, vol. 26, pp. 277-282, March 1991.

2

Altera Corporation, Datasheet: FLEX 10K Embedded Programmable Logic Family, July 1995.

3

Actel Corporation, Datasheet: 3200DX Field-Programmable Gate Arrays, 1995.

4

Xilinx, Inc., The Programmable Logic Data Book, 1994.

5

AT&T Microelectronics, Product Brief: AT&T Optimized Reconfigurable Cell Array (ORCA) Series Field-Programmable Gate Arrays (FPGAs), April 1993.

6

S. J. E. Wilton, J. Rose, and Z. G. Vranesic, ``Architecture of centralized field-configurable memory,'' in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 97-103, 1995.

7

T. Ngai, J. Rose, and S. J. E. Wilton, ``An SRAM-Programmable field-configurable memory,'' in IEEE Custom Integrated Circuits Conference, pp. 499-502, May 1995.

8

J. L. Kouloheris and A. E. Gamal, ``PLA-based FPGA area versus cell granularity,'' in 1992 Custom Integrated Circuits Conference, pp. 4.3.1-4.3.4, 1992.

9

E. Sentovich, ``SIS: A system for sequential circuit analysis,'' tech. rep., Electronics Research Laboratory, University of California, Berkeley, May 1992.

10

J. Cong and Y. Ding, ``An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs,'' in IEEE/ACM International Conference on Computer-Aided Design, pp. 48-53, November 1992.

11

S. J. E. Wilton, Architecture of Field-Configurable Memory. PhD thesis, University of Toronto, in preparation.

12

S. J. E. Wilton and N. P. Jouppi, ``CACTI: an enhanced cache access and cycle time model,'' IEEE Journal of Solid-State Circuits, vol. 31, pp. 677-688, May 1996.