A key challenge in hardware design is creating interconnect -- all the circuitry responsible for delivering data between functional (computation, storage, and control) elements, in a timely manner, while keeping resource usage to a minimum.
The GENIE project aims to make designers' lives easier by automating the generation of application-specific interconnect, primarily for targeting FPGAs. Applications vary in their communication requirements, and thus in the complexity and parameterization of their interconnect. Sometimes point-to-point wires are enough, and sometimes a routed on-chip network is required, with a topology customized to the communication traces present in the application. We envision a tool which automatically optimizes these architectural choices, and generates synthesizable RTL as output, enabling designers to rapidly experiment with different interconnect implementations.
GENIE aims to borrow aspects of existing tools and research and integrate them into a cohesive, easily-usable tool:
Currently, GENIE is in an early alpha version and does not contain the features marked with *, and many others likely need further testing and enhancement.
GENIE takes a specification of functional modules, their interfaces, and the logical/desired links between them, and generates synthesizable Verilog for the entire system. The generated system contains instances of the functional modules and an interconnect fabric that realizes the logical connectivity. The interconnect architecture is composed of Split and Merge primitives cascaded to form an arbitrary topology. Topologies may be pre-selected from a built-in set, or can be customized by writing additional code.
Downloads and source code can be found at the project's Github repository here.