Your goal is to design two high speed fully-differential
comparators and compare the performance between the two
designs. Both designs are intended for the front end
of an 8-bit flash A/D and therefore have limited power
dissipation.
Main Specs for one comparator:
Fully-differential input.
0.2mW total power dissipation from a 3V supply
2 volt peak-to-peak input differential swing
10uA reference current available
2mV resolution
Determine the maximum clock-rate.
Design 1: Continuous-time front-end (i.e. not capacitively coupled)
Design 2: A switched-capacitor front-end with offset compensation
always clocked. Assume input capacitors are 100fF each and
that the bottom plate parasitica capacitance is 33fF while
the top plate parasitic capacitance is 10fF.