| SIS script.algebraic | FBDD 1.0 | |||||
| Circuit | Runtime | S.C. Area |
FPGA Area |
Runtime | S.C. Area |
FPGA Area |
| b01.blif | 0 | 67744 | 13 | 49 | 50576 | 13 |
| b02.blif | 0 | 41296 | 4 | 25 | 26448 | 4 |
| b03.blif | 100 | 266336 | 52 | 108 | 136416 | 52 |
| b04.blif | 800 | 885312 | 174 | 935 | 619904 | 162 |
| b05.blif | 1200 | 861648 | 220 | 1249 | 806432 | 222 |
| b06.blif | 100 | 82592 | 10 | 40 | 65888 | 10 |
| b07.blif | 400 | 636144 | 140 | 312 | 437552 | 132 |
| b08.blif | 200 | 266800 | 48 | 269 | 219008 | 56 |
| b09.blif | 100 | 264944 | 48 | 119 | 163328 | 49 |
| b10.blif | 200 | 283968 | 78 | 243 | 228288 | 67 |
| b11.blif | 800 | 740544 | 174 | 944 | 762816 | 169 |
| b12.blif | 2700 | 1659728 | 402 | 4984 | 1201760 | 383 |
| b13.blif | 400 | 540096 | 97 | 252 | 353104 | 88 |
| b14.blif | 77900 | 6895504 | 1931 | 37014 | 5959616 | 1816 |
| b14_1.blif | 50800 | 6057520 | 1626 | 18294 | 5189840 | 1622 |
| b15.blif | 11553500 | 10691488 | 3185 | 43882 | 9205760 | 2901 |
| b15_1.blif | 261200 | 10607040 | 3094 | 44739 | 8549664 | 2779 |
| b17.blif | - | - | - | 161595 | 28667776 | 9222 |
| b17_1.blif | - | - | - | 122957 | 26631744 | 8529 |
| b20.blif | 502600 | 13910720 | 3887 | 69114 | 12431024 | 3695 |
| b20_1.blif | 351300 | 12562800 | 3295 | 52185 | 11405120 | 3298 |
| b21.blif | 542200 | 14544544 | 4159 | 81417 | 13083872 | 3946 |
| b21_1.blif | 379100 | 12728448 | 3364 | 53043 | 11097488 | 3334 |
| b22.blif | 1739700 | 21203408 | 5890 | 66777 | 18879232 | 5694 |
| b22_1.blif | 1234600 | 19035136 | 5029 | 51099 | 17011168 | 4897 |
| Total | 811645 | 173183824 | 53140 | |||
| SIS Total | 16699900 | 134833760 | 36920 | 527093 | 117884304 | 35389 |
| Norm | 31.7X | 114.4% | 104.3% | 1.0X | 100.0% | 100.0% |
| For SIS, b17 and b17_1 could not complete in under 4 hours. | ||||||
| Praetor was used for technology mapping to FPGA | ||||||
| SIS mapper and lib2.genlib were used for technology mapping to Standard Cell | ||||||