| Xilinx | Altera | FBDD 1.0 | ||||
| Circuit | Runtime | FPGA Ar |
Runtime | FPGA Are |
Runtime (with Praetor) |
FPGA Area |
| b01.blif | 12722 | 12 | 8889 | 9 | 49 | 13 |
| b02.blif | 12344 | 4 | 8889 | 4 | 25 | 4 |
| b03.blif | 13767 | 29 | 8889 | 49 | 208 | 52 |
| b04.blif | 21444 | 189 | 15556 | 165 | 1135 | 162 |
| b05.blif | 29133 | 216 | 30000 | 186 | 1549 | 222 |
| b06.blif | 12567 | 9 | 7778 | 9 | 40 | 10 |
| b07.blif | 20933 | 146 | 14444 | 133 | 512 | 132 |
| b08.blif | 14311 | 52 | 11111 | 43 | 369 | 56 |
| b09.blif | 15400 | 63 | 8889 | 46 | 219 | 49 |
| b10.blif | 15467 | 64 | 11111 | 62 | 343 | 67 |
| b11.blif | 27011 | 205 | 20000 | 156 | 1244 | 169 |
| b12.blif | 32756 | 399 | 26667 | 354 | 5484 | 383 |
| b13.blif | 16233 | 93 | 10000 | 84 | 452 | 88 |
| b14.blif | 409100 | 1912 | 157778 | 1830 | 41114 | 1816 |
| b14_1.blif | 229689 | 1509 | 115556 | 1465 | 22094 | 1622 |
| b15.blif | 431733 | 3274 | 235556 | 2995 | 54182 | 2901 |
| b15_1.blif | 586844 | 3030 | 221111 | 2709 | 51939 | 2779 |
| b17.blif | 36963422 | 9635 | 925556 | 9374 | 211195 | 9222 |
| b17_1.blif | 4634011 | 9330 | 901111 | 8297 | 157157 | 8529 |
| b20.blif | 1396422 | 3803 | 400000 | 3677 | 94414 | 3695 |
| b20_1.blif | 860333 | 3189 | 266667 | 3052 | 70085 | 3298 |
| b21.blif | 1463033 | 3941 | 413333 | 3837 | 101517 | 3946 |
| b21_1.blif | 834822 | 3112 | 270000 | 3134 | 69843 | 3334 |
| b22.blif | 2886644 | 5682 | 642222 | 5606 | 90177 | 5694 |
| b22_1.blif | 1698111 | 4741 | 465556 | 4613 | 74599 | 4897 |
| Total | 52638256 | 54639 | 5196667 | 51889 | 1049945 | 53140 |
| Norm | 50.1X | 102.8% | 4.9X | 1.0X | 1.0X | 100.0% |
| For SIS, b17 and b17_1 could not complete in under 4 hours. | ||||||
| Praetor was used for technology mapping to FPGA | ||||||
| SIS mapper and lib2.genlib were used for technology mapping to Standard Cell | ||||||