Comparison with commercial tools on MCNC benchmarks

	Xilinx		Quartus		FBDD 1.0
Circuit	Runtime	FPGA Area	Runtime	FPGA Area	Runtime (with Praetor)	FPGA Area
9symml	16956	82	7778	9	219	15
C1355	16533	78	5556	74	290	79
C17	12122	2	2222	2	15	2
C1908	21667	129	8889	103	865	110
C2670	27844	234	12222	132	1677	171
C3540	37756	396	25556	323	17676	336
C432	16411	89	6667	73	400	71
C499	14756	78	5556	74	246	79
C5315	49133	477	32222	395	2746	456
C6288	82011	696	38889	507	1680	494
C7552	83000	494	38889	459	5250	477
C880	16322	109	10000	114	600	100
alu2	19411	157	21111	121	3815	151
alu4	30489	292	28889	252	7208	312
apex6	23056	322	23333	222	1071	241
apex7	17800	82	15556	77	319	79
b1	12189	2	7778	2	13	3
b9	14567	47	10000	36	133	40
c8	14200	52	12222	35	258	41
cc	13267	20	10000	17	38	19
cht	13178	46	11111	38	121	38
cm138a	12711	10	11111	9	18	9
cm150a	12900	14	12222	11	99	13
cm151a	12444	7	11111	5	38	8
cm152a	12433	6	12222	6	31	6
cm162a	12967	14	13333	14	29	12
cm163a	12567	11	13333	11	24	12
cm42a	12467	10	14444	10	19	10
cm82a	12289	6	13333	4	15	4
cm85a	12956	11	15556	12	52	14
cmb	13078	15	16667	16	39	16
comp	15656	30	16667	31	156	31
cordic	13711	21	16667	20	168	16
count	13589	43	16667	39	136	45
cu	13056	19	17778	16	55	18
dalu	46211	366	60000	406	2269	355
decod	12744	25	18889	18	18	18
des	81333	1524	112222	1156	9548	1137
example2	16611	115	31111	110	481	113
f51m	13333	25	28889	41	162	25
frg1	16478	43	30000	41	208	19
frg2	28922	339	58889	273	1738	290
i1	12844	16	33333	16	129	16
i10	81856	777	85556	683	5466	712
i2	15956	79	36667	69	4256	69
i3	13389	54	35556	46	208	46
i4	16233	75	37778	94	942	70
i5	14600	75	40000	110	201	67
i6	15578	144	41111	129	291	107
i7	16422	195	50000	167	440	169
i8	31733	371	76667	350	2833	367
i9	18556	212	55556	197	637	194
k2	50222	764	98889	437	9862	382
lal	14778	40	61111	28	202	32
majority	12222	2	57778	2	19	2
mux	12589	16	58889	11	98	13
my_adder	13178	32	60000	32	136	32
pair	34311	508	100000	507	2090	488
parity	12289	5	58889	5	124	5
pcle	13022	20	61111	19	31	20
pcler8	13522	29	62222	30	37	29
pm1	13433	18	65556	14	40	20
rot	24533	237	93333	208	979	222
sct	14633	39	78889	21	182	23
t	12400	2	80000	2	13	2
t481	46011	73	123333	357	15021	5
tcon	12378	8	77778	8	11	8
term1	21478	130	98889	82	1222	89
too_large	508156	277	152222	407	4540	507
ttt2	16856	77	106667	53	353	70
unreg	12956	48	91111	33	120	32
vda	30956	377	126667	253	1448	220
x1	21422	141	117778	135	808	133
x2	13156	17	122222	15	54	17
x3	25156	347	151111	215	853	217
x4	20933	192	150000	116	518	129
z4ml	13033	12	138889	9	26	6
Total	2171911	11947	3761111	10174	114133	10005
Norm	19.0X	1.194103	32.95376	1.016892	1X	100.0%
For SIS, script.rugged was used.
For BDS, BDS-pga and FBDD, default options were used.
Data is not reported for circuit runs that crashed or did not complete in less than 4 hours.
For both BDS and BDS-pga, 7.7% of circuits failed to synthesize.
Praetor was used for technology mapping to FPGA
SIS mapper and lib2.genlib were used for technology mapping to Standard Cell