Disclaimer:This note is based on my personal perception of silicon compilation and may be subject to error. For an authoritative, comprehensive treatment of the history of electronic design automation (EDA) in general, please refer to Sangiovanni-Vicentelli's ``The Tides of EDA'', a keynote address celebrating the 40th anniversary of the Design Automation Conference (DAC).
		The earliest computing device is the abacus, invented centuries ago in Asia. Although abacuses were routinely manufactured in white or green jade, therefore silicon, it was Kilby and Noyce's invention of integrated circuits (IC) that permanently linked silicon with computing. As circuit complexity approached the very large scale (VLSI), Mead and Conway established the structured design methodologies (1977), which led to the vision of silicon compilation, elegantly illustrated by the Gajski Y-Chart (1983). The Y-chart represents IC design in the orthogonal axises of behavioral, structural and physical domains at each circle of abstraction level, progressing from the circuit level, the logic level, the register transfer level (RTL) to the electronic system level (ESL). In its general sense, silicon compilation refers to the automatic generation of a low level chip representation from a high level representation. Time has seen the change of meaning for high level, accompanied by the rise and fall of major EDA companies.
		The first incarnation of silicon compiler operated in the physical domain at the circuit level, where designers used procedural languages to construct and assemble parameterized building blocks. This gave rise to Seattle Silicon, Silicon Compilers, and Silicon Design Labs. Despite pioneering visions and elegant products, these legendary companies unfortunately fell into extinction. Placement and routing tools emerged in 1980s to bridge the gap between the structural and physical domains at the logic level, which gave rise to Cadence, Compass and revived Mentor Graphics. After pioneering research at IBM ( Brayton et al's Yorktown Silicon Compiler) and Berkeley ( Sangiovanni-Vicentelli et al's Multilevel Interactive Synthesis) started in the 1980s, logic synthesis emerged in the 1990s to bridge the gap between the behavioral and structural domain at the logic level, which gave rise to Synopsys. The name of silicon compilation, which was then associated with the textual translation of layout languages, gradually gave way to synthesis, which emphasizes optimizations across large semantic gap. High level (behavioral) synthesis, pioneered by Thomas, Gajski and Parker in the 1980s, went one step further to bridge gap between the behavioral and structural domains at the register transfer level. Only half of high level synthesis was commercially successful: full behavioral synthesis that makes decisions on timing (scheduling) on designers' behalf found little acceptance, while the rest, combined with the revolution of Verilog/VHDL based design entry, became RTL synthesis, the industry standard today. The move to deep submicron fabrication process in the late 1990s signaled the return of the physical domain, as the signal integrity and timing closure problems called for the integration of RTL synthesis, placement and routing, and verification, a full circle on the Y-chart. This consolidation gave rise to Magma and Monterey. It is a consensus that to accommodate the functionality complexity of billion gate designs already on the horizon, one has to move above RTL. To cope with the physical effects of fabrication process in the nanometer regime, one has to bring them on early before RTL. Other than loosely naming the outer circle on the Y-chart electronic system level (ESL), it is still an open question in the community what exactly it entails in the behavioral, structural and physical domains, and what exactly can be and should be done by a silicon compiler at ESL.