From Quartus to VPR

Converting HDL to BLIF with the Titan Flow

This is a short demo on the inner workings of the Titan flow, showing how HDL can be synthesized with Altera's Quartus II design software and converted to the BLIF format commonly used by academic FPGA CAD tools like ABC and VPR. See the main Titan page for a higher level overview of the Titan flow.

The step-by-step tutorial is presented in our FPL 2013 Demo Paper.

Demo Paper

K. E. Murray, S. Whitty, S. Liu, J. Luu and V. Betz, "From Quartus To VPR: Converting HDL to BLIF with the Titan Flow", IEEE Int. Conf. on Field-Programmable Logic and Applications, 2013, 1-1. [Demo Night Paper] (pdf)

Demo Archive

The Titan demo archive includes:

The demo file is in tar.gz format, it can be extracted on a linux command line as follows: tar -xzvf filename.tar.gz


July 7, 2014

titan_hdl_to_blif_demo_1.0.1.tar.gz (2.3MB):

July 23, 2013

titan_hdl_to_blif_demo_1.0.0.tar.gz (1.6MB):

Previous Releases: