Additional information on how to interface devices to a CPU

This is meant to be an aid on top of the regular lecture notes. Let’s focus on the PIT example. As we have seen it supports three different operations.

1. Set the directionality of the external connections
2. Read the current values on the external connections
3. Write values to be output on the external connections

These are performed respectively by writing DDR, reading DIR, and writing DOR.

Examples for the corresponding instructions are:

1. move.b #$ff, DDR à This sets all external connections to be outputs
2. move.b DIR, d0 à this reads the current values from the external connections
3. move.b #$55, DOR à this sets the values for the external connections, however only those that were defined as outputs are affected.

Let’s assume that 68k uses the following wires for interfacing to memory

1. 32 ADDR wires for specifying the address
2. 8 DATA wires for communicating (reading/writing) data
3. 1 R/!W this is 1 when the CPU reads, otherwise it’s 0 (for write)
4. ME this is 1 when the CPU wants to either read or write, 0 means the CPU does not need anything

So, let’s assume that we want to set the lower four bits as outputs, set the lower two to 1 and the upper two to 0, and then read all 8 bits.

Here’s the code:

move.b #$0f, DDR

move.b #$03, DOR

move.b DIR, D0

In time the CPU does the following (time progresses from top to bottom):

Time 1 move.b #$0f, DDR

ADDR = $C10000, R/!W = 0, DATA = $0f, ME=1

…

Time 2 move.b #$03, DOR

ADDR = $C10002, R/!W = 0, DATA = $03, ME=1

…

Time 3 move.b DIR, D0

ADDR = $C10004, R/!W = 1, DATA = the device sets them, ME=1

The input signals to the device include DDRw, DORw, DIRr and DATA. Here are their values

Time 1 DDRw = 1, DORw = 0, DIRw = 0, DATA = $0f

… DDRw = 0, DORw = 0, DIRw = 0, DATA unspecified

Time 2 DDRw = 0, DORw = 1, DIRw = 0, DATA = $03

… DDRw = 0, DORw = 0, DIRw = 0, DATA unspecified

Time 3 DDRw = 0, DORw = 0, DIRw = 1, DATA = The device sets those

… DDRw = 0, DORw = 0, DIRw = 0, DATA unspecified

Notice that these signals are 1 only when the corresponding instructions execute and perform the memory access. This is why the device needs latches to remember their values. So, for example, we cannot connect the DDRw to the tri-state buffer that connects the output of the DOR to the external connection. If we were to do this, the ouput will be set only for the small time interval it takes for the CPU to perform the write that is part of move.b #$0f, DDR