Instruction Set Architectures: Characterization
Thus far we have seen two different instruction set architectures: the 68000 and the simple instruction set we used in the lectures where we explained how a CPU can be designed.
There is a variety of instruction sets out there. In this lecture we will discuss a few of the attributes that can be used to characterize these instruction sets in a meaningful way. In one way or another, virtually all instruction sets that exist today can be classified using these attributes.
Attribute #1: The number of operands
This attribute refers to the number of *explicit* operands that exist in instructions that perform calculations (i.e., an addition).
a. 0-operand architectures or stack-based architectures.
There are no explicit operands all are implicit and they refer to locations in a hardware supported stack.
For example, in these architectures A = B + C is implemented as:
Key advantage: code
Note that data movement instructions that refer to memory still use a single operand (A, B or C) which is the address where the data resides.
one operand is implicit AND it's the accumulator. The accumulator is a register inside the CPU. There are no other registers.
c. 2-operand (e.g., 68k, IA-32)
There are two explicit operands and instructions take the general form of:
Operation source/destination, source
One of the operands is both a source and destination.
A = B + C becomes:
load r1, B
load r2, C
add r1, r2
store r1, A
d. 3-operand (e.g., MIPS, SPARC, POWERpc)
Instructions take the form:
operation destination, source, source
There is one destination and two sources.
A = B + C:
load r2, C
add r3, r1, r2
store r3, A
Attribute #2: Whether the registers are general purpose
a) yes: can
use any register for any purpose
special uses are by convention (for example, register 28 is the stack pointer in MIPS).
Any register can be used like any other register.
b) no: some registers have specific uses
examples: a7 in 68k (it's used as a stack pointer by some instructions such as jsr, rts, link).
Attribute #3: Can an operand be a memory location?
i) Memory-to-Memory: do calculations directly from/to memory
ii) Memory-Register: one operand can be a memory location (e.g., 68k)
Called Load/Store Architectures
If you need to operate on memory values you have to first bring them into a register
Examples: MIPS, SPARC, PowerPC
Relationship of Instructions and Data Pairs being manipulated by the instruction
a. SISD: What we have been describing so far is an SISD or Single Instruction/Single Data instruction set.
Each instruction operates on a pair (at most) of values and produces a single result.
b. SIMD: An alternative is SIMD or Single
Instruction/Multiple Data. Examples of such instructions can be found in the “recent”
multimedia instruction set extensions such as MMX, SSE, 3DNow and Altivec (powerpc). Here an
instruction specifies that an operation should be performed on multiple pairs
of data. For example, a register in such an architecture
does not contain a single data quantity. Instead, if the register is say 256
bits wide it is assumed to contain eight 32 bit quantities. Adding two such
register amounts to performing eight independent additions, one per pair of 32
c. MIMD: finally, there is MIMD and for our discussion suffices to say that this is what parallel computers are.